JPH1056029A - Semiconductor device and its measuring method - Google Patents

Semiconductor device and its measuring method

Info

Publication number
JPH1056029A
JPH1056029A JP21251396A JP21251396A JPH1056029A JP H1056029 A JPH1056029 A JP H1056029A JP 21251396 A JP21251396 A JP 21251396A JP 21251396 A JP21251396 A JP 21251396A JP H1056029 A JPH1056029 A JP H1056029A
Authority
JP
Japan
Prior art keywords
conductor
electrode
semiconductor
semiconductor chips
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21251396A
Other languages
Japanese (ja)
Other versions
JP3311935B2 (en
Inventor
Tetsujiro Tsunoda
哲次郎 角田
Junichi Nakao
淳一 中尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21251396A priority Critical patent/JP3311935B2/en
Publication of JPH1056029A publication Critical patent/JPH1056029A/en
Application granted granted Critical
Publication of JP3311935B2 publication Critical patent/JP3311935B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with which the on-voltages of a plurality of semiconductor chips, which are parallel-connected can be made uniform, and to provide the manufacturing method of the semiconductor device. SOLUTION: A mounting substrate 13 is bonded on a metal base 11, and semiconductor chips 171 to 174 and diodes 201 to 204 are mounted on a base conductor 14 using the wiring pattern 122 on the mounting substrate 13. The first and the second conductor patterns 15 and 16 are formed along both edges of the base conductor 14, and the first conductor pattern 15 is divided into control electrode conductors 151 and 164. The emitter electrodes 181 to 184 of the semiconductor chips 171 to 174 are connected to the second conductor pattern 16 respectively, and the control electrodes 191 to 194 of the semiconductor chips 171 to 174 are connected to the control electrode conductors 151 to 154 respectively. Control voltage is applied to the control electrode conductor 151 of the semiconductor chip 171 to be measured, other control electrode conductors 152 to 154 are earthed, and the on-voltage of the semiconductor chip 171 is measured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、複数個の半導体
チップが並列接続して構成され、特に大電力の制御用に
好適な半導体装置およびその測定方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor chips connected in parallel and particularly suitable for controlling high power, and a measuring method therefor.

【0002】[0002]

【従来の技術】従来、大電力の制御用に用いることがで
き、複数個の半導体チップが並列接続されるようにした
半導体装置は、例えば図6の(A)に示すように構成さ
れる。すなわち、放熱機構を構成する金属ベース51上に
実装基板52が接合されているもので、この実装基板52は
セラミックス等の絶縁基板の両面に銅による導体パター
ン53を形成して構成される。この導体パターン53は、ベ
ース導体541 を中心に構成されるもので、実装基板の両
縁に沿ってそれぞれ細長い第1および第2の導体パター
ン542 および543 が形成される。
2. Description of the Related Art Conventionally, a semiconductor device which can be used for controlling a large amount of power and has a plurality of semiconductor chips connected in parallel is constituted, for example, as shown in FIG. That is, the mounting substrate 52 is joined to the metal base 51 constituting the heat radiation mechanism, and the mounting substrate 52 is formed by forming a conductor pattern 53 made of copper on both surfaces of an insulating substrate such as ceramics. The conductor pattern 53 is formed around the base conductor 541, and elongated first and second conductor patterns 542 and 543 are formed along both edges of the mounting board.

【0003】この半導体装置は、例えば4個の半導体チ
ップ551 〜554 および4個にダイオード561 〜564 によ
って構成され、これら半導体チップ551 〜554 およびダ
イオード561 〜564 は交互に配置されて、ベース導体54
1 の表面にはんだ付けによって取れ付けられる。
This semiconductor device comprises, for example, four semiconductor chips 551 to 554 and four diodes 561 to 564. These semiconductor chips 551 to 554 and diodes 561 to 564 are arranged alternately to form a base conductor 54.
It is attached to the surface of 1 by soldering.

【0004】ここで、半導体チップ551 〜554 がそれぞ
れトランジスタによって構成される場合、それぞれのチ
ップ551 〜554 ま裏面はそれぞれコレクタ電極で構成さ
れ、このコレクタ電極がベース導体541 に共通に接続さ
れる。そして、半導体チップ551 〜554 それぞれの表面
に形成されるゲート電極に相当する制御電極は、それぞ
れボンディングワイヤ57によって第1の導体パターン54
2 に接続され、同じくエミッタ電極はボンディングワイ
ヤ58によって第2の導体パターン543 に接続される。
Here, when the semiconductor chips 551 to 554 are each formed of a transistor, the back surface of each of the chips 551 to 554 is formed of a collector electrode, and the collector electrode is commonly connected to the base conductor 541. The control electrodes corresponding to the gate electrodes formed on the respective surfaces of the semiconductor chips 551 to 554 are respectively connected to the first conductor patterns 54 by the bonding wires 57.
2, and the emitter electrode is also connected to the second conductor pattern 543 by a bonding wire 58.

【0005】この半導体装置は、同図の(B)に示すよ
うに、エミッタとコレクタとの間にそれぞれダイオード
561 〜564 を接続した4個の半導体チップ551 〜554 を
並列接続した回路に構成される。そして、各半導体チッ
プ551 〜554 のそれぞれゲートはゲート端子Gに、コレ
クタはコレクタ端子Cに、さらにエミッタはエミッタ端
子Eにそれぞれ接続される。
In this semiconductor device, as shown in FIG. 1B, a diode is provided between an emitter and a collector.
It is configured as a circuit in which four semiconductor chips 551 to 554 connecting 561 to 564 are connected in parallel. The gate of each of the semiconductor chips 551 to 554 is connected to the gate terminal G, the collector is connected to the collector terminal C, and the emitter is connected to the emitter terminal E.

【0006】この様に複数個の半導体チップを並列接続
して構成される半導体装置の場合、この並列接続される
半導体チップそれぞれのオン電圧にばらつきがあると、
オン電圧の小さいチップに電流が集中する。すなわち、
図7においてAはオン電圧の小さいトランジスタの特性
を示し、Bはオン電圧の大きいトランジスタの特性を示
すもので、オン電圧の相違するトランジスタにおいて
は、同じコレクタ・エミッタ間の電圧(オン電圧)にお
けるコレクタ電流にaおよびbと大きな相違が生ずる。
すなわち、オン電圧の小さいトランジスタに電流が集中
し、オン電圧のばらつきの程度と動作条件によって、こ
の半導体装置の信頼性を著しく低下させ、ときによって
はその半導体チップの破壊につながる。
In the case of such a semiconductor device configured by connecting a plurality of semiconductor chips in parallel, if there is a variation in the on-voltage of each of the semiconductor chips connected in parallel,
Current concentrates on chips with low on-voltage. That is,
In FIG. 7, A shows the characteristics of a transistor with a low on-voltage, and B shows the characteristics of a transistor with a high on-voltage. A large difference occurs between the collector currents a and b.
That is, current concentrates on a transistor having a low on-voltage, and the reliability of the semiconductor device is significantly reduced depending on the degree of variation of the on-voltage and operating conditions, and in some cases, the semiconductor chip is broken.

【0007】しかし、この様な半導体チップの特性のば
らつきは、半導体装置として組み立てられた後の、製品
とされた後には判断できない。その対策としては、オン
電圧の揃った半導体チップを選別して、これを導体パタ
ーンに接続して並列接続されるようにすればよいが、大
電流を制御する半導体チップの場合に、チップの状態で
のオン電圧の測定は、このチップのエミッタ、コレクタ
さらにゲートに導線を接続する必要がある。このため、
この導線と電極部との接触抵抗等の問題が生じて、程度
の高い信頼性のある測定結果を得るのが困難であった。
However, such a variation in the characteristics of the semiconductor chip cannot be determined after the semiconductor chip has been assembled as a semiconductor device and after it has been manufactured. As a countermeasure, a semiconductor chip with a uniform on-voltage may be selected and connected to a conductor pattern so that the semiconductor chip is connected in parallel. In the measurement of the on-state voltage, it is necessary to connect a conductor to the emitter, the collector and the gate of the chip. For this reason,
Problems such as contact resistance between the conductive wire and the electrode portion occurred, and it was difficult to obtain a highly reliable measurement result.

【0008】接触抵抗の問題を解決するためには、導線
の電極に対する接触端を半導体チップの電極部に強く圧
接すればよいが、その圧接力を大きくすると、半導体チ
ップを破壊する虞が生じ、この接触抵抗の低減にも限界
がある。したがって、実質的に並列接続された複数個の
半導体チップの特性にばらつきが存在して、特にオン電
圧の大きく相違するものがあっても、これを検出するこ
とができない。
In order to solve the problem of the contact resistance, the contact end of the conductive wire to the electrode may be strongly pressed against the electrode portion of the semiconductor chip. However, if the pressing force is increased, the semiconductor chip may be broken. There is a limit in reducing this contact resistance. Therefore, even if there is a variation in the characteristics of a plurality of semiconductor chips connected in parallel substantially, and particularly there is a semiconductor chip having a greatly different on-voltage, it cannot be detected.

【0009】[0009]

【発明が解決しようとする課題】この発明は上記のよう
な点に鑑みなされたもので、並列接続された複数の半導
体チップの中のオン電圧のばらつきの存在を、半導体装
置として組み立てられた後において簡単且つ確実に検出
測定することができ、これを排除することが可能とされ
る半導体装置およびその測定方法を提供しようとするも
のである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has been made in consideration of the existence of variations in on-voltage in a plurality of semiconductor chips connected in parallel after assembly as a semiconductor device. It is an object of the present invention to provide a semiconductor device capable of easily and reliably detecting and measuring, and eliminating the same, and a measuring method thereof.

【0010】[0010]

【課題を解決するための手段】この発明に係る半導体装
置は、放熱用金属ベース上に絶縁基板に導体配線パター
ンの形成された実装基板を接合し、この実装基板の表面
に形成された配線パターンで構成されたベース導体パタ
ーン上に少なくとも1種類で構成される複数個の半導体
チップを搭載し、この複数個の半導体チップそれぞれの
ベース導体に接続された電極とは異なる他の電極がそれ
ぞれ配線パターンによって構成される導体パターンを分
割した複数の電極導体にそれぞれ接続する。ここで、半
導体チップがトランジスタによって構成された場合、そ
のそれぞれの制御電極は導体パターンによって構成され
た複数の電極導体それぞれに接続し、この電極導体を順
次接続することにより、複数の半導体チップが例えば並
列的に接続されるようにする。
According to the present invention, there is provided a semiconductor device in which a mounting substrate having a conductor wiring pattern formed on an insulating substrate is joined to a metal base for heat radiation, and a wiring pattern formed on a surface of the mounting substrate is provided. A plurality of semiconductor chips of at least one kind are mounted on a base conductor pattern composed of a plurality of semiconductor chips, and other electrodes different from the electrodes connected to the base conductor of each of the plurality of semiconductor chips are respectively connected to the wiring pattern. Is connected to a plurality of divided electrode conductors. Here, when the semiconductor chip is configured by a transistor, each control electrode is connected to each of a plurality of electrode conductors configured by a conductor pattern, and by sequentially connecting the electrode conductors, a plurality of semiconductor chips are connected, for example. Be connected in parallel.

【0011】また、半導体チップの測定方法は、前記複
数の半導体チップの中の1つの半導体チップに対応する
導体パターンによる1つの電極導体に制御電圧を印加
し、他の半導体チップそれぞれに対応する前記分割され
た他の電極導体は接地電位に設定して、前記1つの半導
体チップに接続された電極導体とベース導体との間の電
位が測定されるようにする。
The method for measuring a semiconductor chip includes applying a control voltage to one electrode conductor having a conductor pattern corresponding to one of the plurality of semiconductor chips, and applying a control voltage to each of the other semiconductor chips. The other divided electrode conductor is set to the ground potential, so that the potential between the electrode conductor connected to the one semiconductor chip and the base conductor is measured.

【0012】この様な半導体装置にあっては、複数の半
導体チップは例えば並列接続されて1つの装置として構
成されるものであるが、各半導体チップがトランジスタ
の場合、特に制御用の電極はそれぞれ分割して独立的に
構成された導体パターンの電極導体にそれぞれ接続され
ている。したがって、テスター等を用いてその電極導体
の1つを選択し、他の分割された電極導体を接地するこ
とにより、複数の半導体チップの1つずつの例えばオン
電圧が、組み立てられる過程において独立的に測定検出
できる。そして、その後分割された導体パターンを共通
に接続することにより、複数の半導体チップが例えば並
列に接続設定され、半導体装置が完成される。すなわ
ち、導体パターンに対してテスターの接触子を接触する
ことによって、金属ベース上に搭載され、所定の導体パ
ターンに接続された状態の半導体チップの例えばオン電
圧が個々に測定ができるもので、半導体チップに対して
不要な接触圧力を作用させることなくオン電圧の測定が
行え、並列接続された複数の半導体チップの中のオン電
圧のばらつきを検出でき、半導体装置の信頼性が効果的
に向上される。
In such a semiconductor device, a plurality of semiconductor chips are, for example, connected in parallel and configured as one device. When each semiconductor chip is a transistor, a control electrode is particularly provided. It is connected to the electrode conductor of the conductor pattern which is divided and independently formed. Therefore, by selecting one of the electrode conductors using a tester or the like and grounding the other divided electrode conductors, for example, the on-voltage of each of the plurality of semiconductor chips can be independently set in the process of assembling. Can be measured and detected. Then, by connecting the divided conductor patterns in common, a plurality of semiconductor chips are connected and set, for example, in parallel, and the semiconductor device is completed. That is, by contacting the contact of the tester with the conductor pattern, the on-voltage of the semiconductor chip mounted on the metal base and connected to the predetermined conductor pattern can be individually measured, for example. The on-voltage can be measured without applying unnecessary contact pressure to the chip, and the on-voltage variation among a plurality of semiconductor chips connected in parallel can be detected, thereby effectively improving the reliability of the semiconductor device. You.

【0013】[0013]

【発明の実施の形態】以下、図面を参照してこの発明の
一実施の形態を実施例に基づき説明する。図1の(A)
および(B)は第1の実施例の構成を示すもので、熱伝
導性の良好な金属材料によって構成された放熱用の金属
ベース11を備える。この金属ベース11の表面には、セラ
ミックスによって構成した絶縁基板121 の両面にそれぞ
れ銅による配線パターン122 および123 によって構成し
た実装基板13が、絶縁性の接着剤によって接合されてい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. (A) of FIG.
(B) and (B) show the configuration of the first embodiment, and include a heat dissipating metal base 11 made of a metal material having good heat conductivity. On the surface of the metal base 11, a mounting substrate 13 composed of wiring patterns 122 and 123 made of copper is bonded to both surfaces of an insulating substrate 121 composed of ceramics by an insulating adhesive.

【0014】ここで、(A)図で示すように実装基板13
の表面側の配線パターン122 は、例えば実装基板13が長
方形に構成された場合、その長手方向に延びるように長
方形状にしたベース導体14を有し、このベース導体14の
両側に沿って延びるようにして、第1および第2の導体
パターン15および16が形成される。そして、ベース導体
14の表面上には、それぞれトランジスタを構成する複数
個、例えば4個の同一種類の半導体チップ171 〜174 が
等間隔で配置されて、はんだ付け固定されている。
Here, as shown in FIG.
For example, when the mounting substrate 13 is formed in a rectangular shape, the wiring pattern 122 on the front side has a rectangular base conductor 14 so as to extend in the longitudinal direction, and extends along both sides of the base conductor 14. Thus, the first and second conductor patterns 15 and 16 are formed. And the base conductor
On the surface of 14, a plurality of, for example, four semiconductor chips 171 to 174 of the same type, each constituting a transistor, are arranged at equal intervals and fixed by soldering.

【0015】ここで、各半導体チップ171 〜174 それぞ
れの裏面にはコレクタ電極が形成されており、このコレ
クタ電極はベース導体14に接続され、したがってベース
導体14はコレクタ導体とされる。
Here, a collector electrode is formed on the back surface of each of the semiconductor chips 171 to 174, and this collector electrode is connected to the base conductor 14, so that the base conductor 14 is a collector conductor.

【0016】また、各半導体チップ171 〜174 それぞれ
の表面には、トランジスタのエミッタ電極181 〜184 が
形成され、さらにゲートとされる制御電極191 〜194 が
形成されている。そして、エミッタ電極181 〜184 は、
それぞれ2本のボンディングワイヤによって第2導体パ
ターン16に接続される。
On the surface of each of the semiconductor chips 171 to 174, transistor emitter electrodes 181 to 184 are formed, and further, control electrodes 191 to 194 serving as gates are formed. And, the emitter electrodes 181 to 184 are
Each is connected to the second conductor pattern 16 by two bonding wires.

【0017】また、制御電極191 〜194 はそれぞれ第1
の導体パターン15に接続されるもので、この第1の導体
パターン15は半導体チップ171 〜174 にそれぞれ対応す
るように4個に分割し、それぞれ独立した制御電極導体
151 〜154 が形成されるようにしているもので、これら
の制御電極導体151 〜154 それぞれに、半導体チップ17
1 〜174 それぞれの制御電極191 〜194 が、ボンディン
グワイヤを介して接続される。
The control electrodes 191 to 194 are respectively connected to the first
The first conductor pattern 15 is divided into four parts corresponding to the semiconductor chips 171 to 174, respectively, and independent control electrode conductors are provided.
151 to 154 are formed, and the semiconductor chip 17 is connected to each of these control electrode conductors 151 to 154.
The control electrodes 191 to 194 are connected via bonding wires.

【0018】ベース導体14の表面には、半導体チップ17
1 〜174 にそれぞれ隣接して、例えばフリーホイールダ
イオード(FWD)でなるダイオード201 〜204 が搭載
されるもので、このダイオード201 〜204 それぞれの、
例えばカソード電極がベース導体14の面にはんだ付け接
続される。そして、この各ダイオード201 〜204 のアノ
ード電極が、それぞれボンディングワイヤを介して第2
の導体パターン16に接続される。
A semiconductor chip 17 is provided on the surface of the base conductor 14.
Each of the diodes 201 to 204 includes, for example, a freewheel diode (FWD) adjacent to each of the diodes 201 to 174.
For example, a cathode electrode is connected to the surface of the base conductor 14 by soldering. The anode electrodes of the diodes 201 to 204 are respectively connected to the second electrodes via bonding wires.
Is connected to the conductor pattern 16 of FIG.

【0019】この様に構成されれば、半導体チップ171
〜174 それぞれのコレクタがベース導体14で共通に接続
され、また各半導体チップ171 〜174 それぞれのエミッ
タ電極181 〜184 が第2の導体パターン16に共通接続さ
れて、各半導体チップ171 〜174 のそれぞれ制御電極が
191 〜194 が、それぞれ第1の導体パターン15の分割さ
れた制御電極導体151 〜154 にそれぞれ独立的に接続設
定される。この様な接続状態であれば、複数の半導体チ
ップ171 〜1784それぞれのオン電圧の測定が可能とされ
る。
With this configuration, the semiconductor chip 171
The collectors of the semiconductor chips 171 to 174 are commonly connected to the second conductor pattern 16, and the emitter electrodes 181 to 184 of the semiconductor chips 171 to 174 are commonly connected to the second conductor pattern 16. Control electrode
191 to 194 are independently connected to the divided control electrode conductors 151 to 154 of the first conductor pattern 15, respectively. In such a connection state, it is possible to measure the on-voltage of each of the plurality of semiconductor chips 171-1784.

【0020】具体的には、実装基板13の所定の導体パタ
ーン部に接触端子を押し付けたり、あるいはクリップで
挟むようにして電極導出を行えるもので、例えば半導体
チップ171 のオン電圧を測定しようとする場合には、こ
の半導体チップ171 の制御電極191 の接続される制御電
極導体151 にゲート電圧を供給し、ベース導体14にコレ
クタ電圧を、さらに第2の導体パターン16にエミッタ電
圧を印加設定する。そして、他の制御電極導体152 〜15
4 は第2の導体パターン16に接続するもので、この第2
の導体パターン16は接地電位に保たれるようにする。そ
して、この様な状態でベース導体14と第2の導体パター
ン16との間の電圧を測定すれば、半導体チップ171 のオ
ン電圧が測定されることになる。IGBT等のノーマリ
ーオフ型のトランジスタの場合は、制御電極に対してバ
イアスを印加しなければオン電圧が極めて大きくなり、
各トランジスタのオン電圧が測定できる。
Specifically, the electrode can be led out by pressing a contact terminal against a predetermined conductor pattern portion of the mounting board 13 or sandwiching the terminal with a clip. For example, when the on-voltage of the semiconductor chip 171 is to be measured, Supplies a gate voltage to the control electrode conductor 151 to which the control electrode 191 of the semiconductor chip 171 is connected, and applies and sets a collector voltage to the base conductor 14 and an emitter voltage to the second conductor pattern 16. Then, the other control electrode conductors 152 to 15
4 is for connecting to the second conductor pattern 16;
Conductor pattern 16 is kept at the ground potential. When the voltage between the base conductor 14 and the second conductor pattern 16 is measured in such a state, the on-voltage of the semiconductor chip 171 is measured. In the case of a normally-off type transistor such as an IGBT, the on-state voltage becomes extremely large unless a bias is applied to the control electrode,
The on-voltage of each transistor can be measured.

【0021】この様な計測は半導体チップ171 〜174 そ
れぞれに対して独立的に行われるもので、半導体チップ
171 〜174 それぞれに対して直接的に圧接力を作用させ
ることなく、各半導体チップ171 〜174 のオン電圧測定
が実行できる。そして、このオン電圧測定のための測定
手段の端子導出は、実装基板13に形成された配線パター
ンに対する、例えばテスターの接触子の圧接、もしくは
クリップの挟み込みにより行えるので、特に複数の半導
体チップ171 〜174 を並列接続した半導体装置の組み立
て工程の途中において、半導体チップ171 〜174 に損傷
を与える虞を生ずることなく、各半導体チップ171 〜17
4 のオン電圧の測定が行える。
Such measurement is performed independently for each of the semiconductor chips 171 to 174.
The on-voltage measurement of each of the semiconductor chips 171 to 174 can be performed without directly applying a pressing force to each of the semiconductor chips 171 to 174. The terminal of the measuring means for measuring the on-voltage can be derived by, for example, pressing a contact of a tester or sandwiching a clip with respect to a wiring pattern formed on the mounting substrate 13, so that a plurality of semiconductor chips 171-1 to -17- During the process of assembling the semiconductor device in which the semiconductor chips 171 to 174 are connected in parallel, there is no possibility that the semiconductor chips 171 to 174 may be damaged.
4 can measure ON voltage.

【0022】この様な方法によれば、チップ状態におけ
る特性確認のためのオン電圧測定のための特性確認とは
異なり、測定手段の接触端をかなり強い圧力で導体パタ
ーンに接触でき、また電流通電と電圧センスを別接触端
から接続できるものであるため、高精度の測定が可能と
される。
According to such a method, the contact end of the measuring means can be brought into contact with the conductor pattern at a considerably high pressure, unlike the characteristic confirmation for measuring the on-voltage for confirming the characteristic in the chip state. And voltage sense can be connected from separate contact terminals, so that highly accurate measurement is possible.

【0023】したがって、例えばこの半導体装置を構成
する4個の半導体チップ171 〜174の中に、オン電圧の
大きく相違する半導体チップが存在した場合には、この
段階でその半導体チップの排除および交換をすることが
できる。
Therefore, for example, if there is a semiconductor chip having a significantly different on-voltage among the four semiconductor chips 171 to 174 constituting the semiconductor device, the semiconductor chip is removed and replaced at this stage. can do.

【0024】この様に搭載された各半導体チップ171 〜
174 のオン電圧の測定が終了したならば、第1の導体パ
ターン15を構成する分割された制御電極導体151 〜154
は、接続導体211 〜213 により一体的に接続されるもの
で、この接続導体211 〜213は、(B)図で示されるよ
うにアウターリード221 〜223 の接続工程において同時
に形成でき、この接続導体211 〜213 の形成によって半
導体チップ171 〜174が図6の(B)で示したような並
列接続されるようになる。
Each of the semiconductor chips 171 to 171 mounted as described above
When the measurement of the ON voltage at 174 is completed, the divided control electrode conductors 151 to 154 constituting the first conductor pattern 15 are divided.
Are integrally connected by connecting conductors 211 to 213. These connecting conductors 211 to 213 can be simultaneously formed in a connecting step of outer leads 221 to 223 as shown in FIG. With the formation of 211 to 213, the semiconductor chips 171 to 174 are connected in parallel as shown in FIG.

【0025】また、この様に構成される半導体装置にあ
っては、アウターリード221 〜213の製造工程におい
て、同時に半導体チップ161 〜174 が並列接続されるも
のであるため、従来と同様の組み立て工程によって、こ
の半導体装置を組み立てることができる。そして、この
様な接続工程の終了後に(B)図で鎖線で示す範囲を樹
脂によってモールドして、半導体装置が完成される。
In the semiconductor device having such a configuration, the semiconductor chips 161 to 174 are simultaneously connected in parallel in the manufacturing process of the outer leads 221 to 213. Thereby, the semiconductor device can be assembled. After completion of such a connection step, the area indicated by the chain line in FIG. 8B is molded with a resin to complete the semiconductor device.

【0026】この実施例にあっては、アウターリード22
1 〜223 により接続導体211 〜213が製造できるもので
あるが、図2の(A)で示すように第1の導体パターン
15の分割された電極導体151 〜154 それぞれに対してア
ウターリード231 〜234 を形成し、このアウターリード
231 〜234 のそれぞれの間をジャンパ線241 〜244 によ
って接続するように構成してもよい。また、図2の
(B)で示すように電極導体151 〜154 のそれぞれの間
を金属細線251 〜253 によって接続することもできる。
In this embodiment, the outer leads 22
1 to 223, the connection conductors 211 to 213 can be manufactured. However, as shown in FIG.
Outer leads 231 to 234 are formed for each of the fifteen divided electrode conductors 151 to 154, and the outer leads are formed.
Each of 231 to 234 may be connected by jumpers 241 to 244. Also, as shown in FIG. 2B, the electrode conductors 151 to 154 can be connected to each other by thin metal wires 251 to 253.

【0027】図3は第4の実施例を示すもので、第2の
導体パターン16を半導体チップ171〜174 それぞれに対
応して4個に分割し、エミッタ電極導体161 〜164 を構
成する。そして、半導体チップ171 〜174 それぞれのエ
ミッタ電極181 〜184 と、エミッタ電極導体161 〜164
の相互間をボンディングワイヤで接続する。またダイオ
ード201 〜204 それぞれとエミッタ電極導体161 〜164
それぞれとの間も、ボンデグワイヤによってそれぞれ接
続する。
FIG. 3 shows a fourth embodiment, in which the second conductor pattern 16 is divided into four corresponding to the semiconductor chips 171 to 174 to form emitter electrode conductors 161 to 164. The emitter electrodes 181 to 184 of the semiconductor chips 171 to 174 and the emitter electrode conductors 161 to 164
Are connected by bonding wires. Also, diodes 201 to 204 and emitter electrode conductors 161 to 164, respectively.
Each of them is also connected by a bond wire.

【0028】ここで、半導体チップがトランジスタに限
らずダイオードであっても同様な測定ができる。すなわ
ち、ダイオード201 〜204 のオン電圧も独立的にチップ
毎に測定できる。この半導体装置場合には、IGBTで
ある半導体チップ171 〜174とFWDであるダイオード2
01 〜204 は、それぞれ1個づつ並列接続されているも
のであるが、半導体チップ171 〜174 とダイオード201
〜204 それぞれの順方向の電流の向きが異なる。このた
め、簡単な切り換えスイッチによって半導体チップ171
〜174 それぞれとダイオード201 〜204 との電圧印加極
性を切り換え、それぞれのオン電圧を、個々に測定でき
るようになる。
Here, the same measurement can be performed even if the semiconductor chip is not limited to a transistor but is a diode. That is, the on-voltages of the diodes 201 to 204 can be measured independently for each chip. In the case of this semiconductor device, a semiconductor chip 171-174, which is an IGBT, and a diode 2 which is an FWD
01 to 204 are respectively connected one by one in parallel, and the semiconductor chips 171 to 174 and the diode 201 are connected.
204204 The forward current directions are different. For this reason, the semiconductor chip 171 is operated by a simple changeover switch.
By switching the polarity of the voltage applied to the diodes 201 to 204 and the diodes 201 to 204, the ON voltages of the respective diodes can be individually measured.

【0029】図4で示す第5の実施例にあっては、2枚
の実装基板131 および132 を用いて4個の半導体チップ
171 〜174 およびダイオード201 〜204 を搭載し、並列
回路が形成されるようにする。そして、実装基板131 お
よび132 にはそれぞれベース導体141 および142 が形成
され、さらに分割された制御電極導体151 〜154 および
エミッタ電極導体161 〜164 が実装基板131 および132
に分割設定され、接続導体261 、262 およびジャンパ線
で図3の例と同様に接続され、基板部の数が複数に構成
されるようにしてもよい。
In the fifth embodiment shown in FIG. 4, four semiconductor chips are formed by using two mounting substrates 131 and 132.
171 to 174 and diodes 201 to 204 are mounted so that a parallel circuit is formed. Base conductors 141 and 142 are formed on the mounting substrates 131 and 132, respectively, and the control electrode conductors 151 to 154 and the emitter electrode conductors 161 to 164 which are further divided are mounted on the mounting substrates 131 and 132.
3 and connected by the connection conductors 261 and 262 and the jumper wire in the same manner as in the example of FIG. 3, and the number of the substrate portions may be plural.

【0030】例えば図5で示す第6の実施例にあって
は、4枚の実装基板131 〜134 を用いるもので、各実装
基板131 〜134 それぞれに形成されるベース導体141 〜
144 上に半導体チップ171 〜174 およびダイオード201
〜204 をそれぞれはんだ付けにより取り付け搭載する。
また実装基板131 〜134 それぞれに制御電極導体151 〜
154 およびエミッタ電極導体161 〜164 を形成し、これ
らの制御電極導体151 〜154 およびエミッタ電極導体16
1 〜164 を接続導体263 、264 およびジャンパ線で接続
し、半導体チップ171 〜174 が並列接続されるようにす
る。この様にしても、接続導体263 、264 およびジャン
パ線により並列接続される前の段階で、半導体チップ17
1 〜174 それぞれのオン電圧の測定が可能とされる。
For example, in the sixth embodiment shown in FIG. 5, four mounting boards 131 to 134 are used, and the base conductors 141 to 134 formed on each of the mounting boards 131 to 134 are used.
144 Semiconductor chips 171-174 and diode 201
Are mounted by soldering.
Control electrode conductors 151 to 134 are mounted on the mounting substrates 131 to 134, respectively.
154 and emitter electrode conductors 161 to 164 are formed, and these control electrode conductors 151 to 154 and emitter electrode conductor 16 are formed.
1 to 164 are connected by connecting conductors 263 and 264 and a jumper wire so that the semiconductor chips 171 to 174 are connected in parallel. Even in this case, the semiconductor chip 17 is not connected in parallel by the connection conductors 263 and 264 and the jumper wire.
The measurement of the on-voltage of each of 1 to 174 is enabled.

【0031】この様に実装基板の数や各基板に搭載する
半導体チップの数は任意に設定できるものであり、基板
の数が複数枚ある場合には、測定されたオン電圧の同じ
ようなものを組み合わせて、最終的な半導体装置が構成
されるようにすることができる。
As described above, the number of mounting boards and the number of semiconductor chips mounted on each board can be arbitrarily set. When there are a plurality of boards, the same on-voltage as that of the measured on-voltage is used. Can be combined to form a final semiconductor device.

【0032】なお、これまでの実施例においては、トラ
ンジスタとダイオートの両方が搭載されるような例を示
したが、これらの第1ないし第6の実施例においてトラ
ンジスタのみ、または第4および第6の実施例において
はダイオードのみを搭載した構成としてもよい。また、
トランジスタに限らずサイリスタを搭載するものであっ
てもよい。
In the above embodiments, an example is shown in which both a transistor and a die transistor are mounted. However, in the first to sixth embodiments, only the transistor or the fourth and sixth transistors are mounted. In the embodiment, only the diode may be mounted. Also,
Not only transistors but also thyristors may be mounted.

【0033】[0033]

【発明の効果】以上のようにこの発明に係る半導体装置
にあっては、並列接続される半導体チップを実装基板に
搭載する状態で、大電流を取り扱うようになる半導体チ
ップの特性を個々に且つ高精度に測定できるようになる
ものであり、製品の組み立て段階において、オン電圧等
の特性のばらつきの大きいものを排除し交換することが
できる。また、複数の基板に分割して構成するようにし
た場合、同じような特性のチップの搭載された基板を選
択組み合わせることができ、半導体チップの特性の合っ
た組み合わせの半導体装置が確実に提供することがで
き、この種半導体装置の信頼性が向上される。
As described above, in the semiconductor device according to the present invention, when the semiconductor chips connected in parallel are mounted on the mounting board, the characteristics of the semiconductor chips that handle a large current are individually and individually determined. This makes it possible to measure with high accuracy, and in the stage of assembling a product, it is possible to eliminate and replace a product having a large variation in characteristics such as ON voltage. Further, when the semiconductor device is divided into a plurality of substrates, a substrate on which chips having similar characteristics are mounted can be selectively combined, and a semiconductor device having a combination of characteristics of semiconductor chips can be reliably provided. And the reliability of this type of semiconductor device is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)はこの発明の一実施の形態に係る半導体
装置の第1の実施例を説明する平面構成図、(B)は同
じく側面から見た構成図。
FIG. 1A is a plan view illustrating a first example of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a side view illustrating the same.

【図2】(A)および(B)はそれぞれ第2および第3
の実施例を説明する構成図。
FIGS. 2A and 2B are second and third views, respectively.
FIG.

【図3】同じく第4の実施例を説明する構成図。FIG. 3 is a configuration diagram illustrating a fourth embodiment.

【図4】同じく第5の実施例を説明する構成図。FIG. 4 is a configuration diagram illustrating a fifth embodiment.

【図5】同じく第6の実施例を説明する構成図。FIG. 5 is a configuration diagram illustrating a sixth embodiment.

【図6】(A)は従来の半導体装置を説明する平面構成
図、(B)はその回路図。
6A is a plan view illustrating a conventional semiconductor device, and FIG. 6B is a circuit diagram thereof.

【図7】半導体チップのオン電圧特性を説明する図。FIG. 7 illustrates an on-voltage characteristic of a semiconductor chip.

【符号の説明】[Explanation of symbols]

11…金属ベース、121 …絶縁基板、122 、123 …第1お
よび第2の配線パターン、13…実装基板、14…ベース導
体、15、16…第1および第2の導体パターン、151 〜15
4 …制御電極導体、171 〜174 …半導体チップ、181 〜
184 …エミッタ電極、191 〜194 …制御電極、201 〜20
4 …ダイオード、221 〜223 …アウターリード。
11 ... metal base, 121 ... insulating substrate, 122, 123 ... first and second wiring patterns, 13 ... mounting substrate, 14 ... base conductor, 15, 16 ... first and second conductor patterns, 151 to 15
4 ... control electrode conductors, 171 to 174 ... semiconductor chips, 181 to
184: Emitter electrode, 191-194 ... Control electrode, 201-20
4… Diode, 221-223… Outer lead.

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板に導体配線パターンの形成され
た実装基板と、 この実装基板の表面に形成された前記配線パターンで構
成されたベース導体パターン上に接続して搭載された少
なくとも1種類で構成される複数個の半導体チップと、 この複数個の半導体チップそれぞれの前記ベース導体に
接続された電極とは異なる他の電極がそれぞれ接続され
た、前記配線パターンによって構成される複数の電極導
体からなる導体パターンとを具備し、 前記複数の半導体チップが前記導体パターンによる複数
の電極導体を用いて相互に接続できるようにしたことを
特徴とする半導体装置。
1. A mounting board in which a conductor wiring pattern is formed on an insulating substrate, and at least one kind connected and mounted on a base conductor pattern formed by the wiring pattern formed on the surface of the mounting board. A plurality of semiconductor chips configured, and a plurality of electrode conductors configured by the wiring pattern, each of which is connected to another electrode different from the electrode connected to the base conductor of each of the plurality of semiconductor chips. A semiconductor pattern comprising: a plurality of semiconductor chips, wherein the plurality of semiconductor chips can be connected to each other by using a plurality of electrode conductors formed by the conductive pattern.
【請求項2】 前記複数の半導体チップはそれぞれトラ
ンジスタでなり、これら半導体チップそれぞれの共通す
る電極が前記導体パターンを構成する電極導体にそれぞ
れ接続されるようにした請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein each of said plurality of semiconductor chips comprises a transistor, and a common electrode of each of said semiconductor chips is connected to an electrode conductor constituting said conductor pattern.
【請求項3】 前記導体パターンを構成する複数の電極
導体は、それぞれ接続導体によって接続される請求項1
記載の半導体装置。
3. A plurality of electrode conductors constituting said conductor pattern are connected by connecting conductors, respectively.
13. The semiconductor device according to claim 1.
【請求項4】 前記接続導体は、外部に導出されるアウ
ターリードによって構成されるようにした請求項3記載
の半導体装置。
4. The semiconductor device according to claim 3, wherein said connection conductor is constituted by an outer lead led out.
【請求項5】 前記接続導体は、前記導体パターンを構
成する複数の電極導体それぞれに形成されたアウターリ
ードおよびこのアウターリードそれぞれを接続するジャ
ンパ線によって構成されるようにした請求項3記載の半
導体装置。
5. The semiconductor according to claim 3, wherein said connection conductor is constituted by an outer lead formed on each of a plurality of electrode conductors constituting said conductor pattern and a jumper wire connecting each of said outer leads. apparatus.
【請求項6】 前記接続導体は、前記導体パターンを構
成する複数の電極導体それぞれを接続するボンディング
ワイヤによって構成されるようにした請求項3記載の半
導体装置。
6. The semiconductor device according to claim 3, wherein said connection conductor is constituted by a bonding wire connecting each of a plurality of electrode conductors constituting said conductor pattern.
【請求項7】 前記複数の半導体チップはそれぞれトラ
ンジスタによって構成され、この各トランジスタの制御
電極は前記導体パターンを分割した電極導体にそれぞれ
接続するようにした請求項1記載の半導体装置。
7. The semiconductor device according to claim 1, wherein each of said plurality of semiconductor chips comprises a transistor, and a control electrode of each transistor is connected to an electrode conductor obtained by dividing said conductor pattern.
【請求項8】 前記複数の半導体チップはそれぞれトラ
ンジスタによって構成され、この各トランジスタの制御
電極はそれぞれ第1の導体パターンを分割した電極導体
にそれぞれ接続すると共に、さらに第2の導体パターン
を形成し、この第2の導体パターンに前記複数の半導体
チップそれぞれのエミッタ電極が共通に接続されるよう
にした請求項1記載の半導体装置。
8. The plurality of semiconductor chips are each constituted by a transistor, and control electrodes of the respective transistors are respectively connected to electrode conductors obtained by dividing the first conductor pattern, and further form a second conductor pattern. 2. The semiconductor device according to claim 1, wherein an emitter electrode of each of said plurality of semiconductor chips is commonly connected to said second conductor pattern.
【請求項9】 前記第2の導体パターンは前記複数の半
導体チップそれぞれに対応して複数に分割した電極導体
で構成され、この各電極導体には前記半導体チップのエ
ミッタ電極がそれぞれ接続されるようにした請求項8記
載の半導体装置。
9. The second conductor pattern is composed of a plurality of divided electrode conductors corresponding to the plurality of semiconductor chips, respectively, and each of the electrode conductors is connected to an emitter electrode of the semiconductor chip. 9. The semiconductor device according to claim 8, wherein:
【請求項10】 前記複数の少なくとも1種類の半導体
チップはダイオードで構成され、これら複数のタイオー
ドそれぞれのアノードもしくはカソードの少なくとも一
方が前記導体パターンの分割した電極導体にそれぞれ接
続されるようにした請求項1記載の半導体装置。
10. The plurality of at least one type of semiconductor chip is constituted by a diode, and at least one of an anode and a cathode of each of the plurality of diodes is connected to each of the divided electrode conductors of the conductor pattern. Item 2. The semiconductor device according to item 1.
【請求項11】 前記ベース導体は複数に分割して構成
され、この分割されたベース導体それぞれに1個もしく
は複数個の半導体チップが搭載されるようにした請求項
1記載の半導体装置。
11. The semiconductor device according to claim 1, wherein the base conductor is divided into a plurality of parts, and one or more semiconductor chips are mounted on each of the divided base conductors.
【請求項12】 前記分割されたベース導体は複数の実
装基板に分離して搭載されるようにした請求項10記載
の半導体装置。
12. The semiconductor device according to claim 10, wherein said divided base conductors are separately mounted on a plurality of mounting boards.
【請求項13】 絶縁基板に導体配線パターンの形成さ
れた実装基板の前記配線パターンで構成されたベース導
体パターン上に少なくとも1種類で構成される複数個の
半導体チップが搭載され、この複数個の半導体チップそ
れぞれの前記ベース導体に接続された電極とは異なる他
の電極が前記配線パターンによって構成される複数に分
割された電極導体からなる導体パターンのそれぞれに接
続される半導体装置において、 前記複数の半導体チップの中の1つの半導体チップに対
応する1つの分割された導体パターンの電極導体に制御
電圧を印加し、他の半導体チップそれぞれに対応する前
記分割された他のて電極導体は接地電位に設定し、前記
1つの半導体チップに対応する電極導体とベース導体と
の間の電位が独立的に測定されるようにしたことを特徴
とする半導体装置の計測方法。
13. A plurality of semiconductor chips of at least one kind are mounted on a base conductor pattern formed of the wiring pattern on a mounting substrate having a conductor wiring pattern formed on an insulating substrate. In a semiconductor device in which another electrode different from an electrode connected to the base conductor of each semiconductor chip is connected to each of conductor patterns formed of a plurality of divided electrode conductors formed by the wiring pattern, A control voltage is applied to the electrode conductor of one divided conductor pattern corresponding to one semiconductor chip among the semiconductor chips, and the other divided electrode conductors corresponding to each of the other semiconductor chips are set to the ground potential. So that the potential between the electrode conductor and the base conductor corresponding to the one semiconductor chip is measured independently. Measurement method of a semiconductor device, characterized in that.
【請求項14】 前記ベース導体および電極導体にはそ
れぞれテスターの接触子が圧接されるようにした請求項
13記載の半導体装置の計測方法。
14. The method according to claim 13, wherein a contact of a tester is pressed against each of the base conductor and the electrode conductor.
JP21251396A 1996-08-12 1996-08-12 Semiconductor device and measuring method thereof Expired - Fee Related JP3311935B2 (en)

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JP21251396A JP3311935B2 (en) 1996-08-12 1996-08-12 Semiconductor device and measuring method thereof

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JPH1056029A true JPH1056029A (en) 1998-02-24
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JP2009188346A (en) * 2008-02-08 2009-08-20 Denso Corp Semiconductor module
JP2014060417A (en) * 2008-09-19 2014-04-03 Renesas Electronics Corp Semiconductor device
JP2017162866A (en) * 2016-03-07 2017-09-14 株式会社東芝 Semiconductor device

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JPH053229A (en) * 1991-06-25 1993-01-08 Nec Corp Semiconductor device
JPH05206449A (en) * 1992-01-29 1993-08-13 Hitachi Ltd Semiconductor module and power converter employing the same
JPH0729933A (en) * 1993-07-12 1995-01-31 Origin Electric Co Ltd Power semiconductor device
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JP2009188346A (en) * 2008-02-08 2009-08-20 Denso Corp Semiconductor module
JP4506848B2 (en) * 2008-02-08 2010-07-21 株式会社デンソー Semiconductor module
US7957135B2 (en) 2008-02-08 2011-06-07 Denso Corporation Semiconductor module
JP2014060417A (en) * 2008-09-19 2014-04-03 Renesas Electronics Corp Semiconductor device
US9000574B2 (en) 2008-09-19 2015-04-07 Renesas Electronics Corporation Semiconductor device for battery power voltage control
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JP2017162866A (en) * 2016-03-07 2017-09-14 株式会社東芝 Semiconductor device

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