JP2021132134A - Silicon carbide semiconductor device and method for manufacturing the same - Google Patents

Abstract

To improve the controllability of the injection depth and make it easy to manufacture high-performance silicon carbide semiconductor devices.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes a step of ion implantation into a 4H-SiC crystal layer to form an ion implantation layer. The ion implantation is performed at an ion implantation angle of +10° or -10° from [0001] with respect to the {1-100} plane, at an ion implantation angle of +3° or -3° from [0001] with respect to the {1-210} plane, or at an ion implantation angle of +4° or -4° from [0001] with respect to a plane intermediate between the {1-100} and {1-210} planes.SELECTED DRAWING: Figure 9

Description

The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the same.

Semiconductor devices are used for various purposes. In recent years, there has been a demand for semiconductor devices that can operate even in a high temperature environment of 200 ° C. or higher or in an environment where the absorbed dose is several thousand Gy to tens of thousands Gy. However, it is difficult to use conventional silicon (Si) semiconductors in such an environment, and new semiconductor materials are being studied. Among them, silicon carbide (SiC) semiconductors are expected as semiconductor materials having excellent heat resistance and radiation resistance.

Ion implantation technology is indispensable for manufacturing semiconductor devices. In the case of a silicon carbide semiconductor, there is a problem peculiar to a silicon carbide semiconductor, such as recovery of crystallinity after ion implantation is not as easy as that of a silicon semiconductor. For this reason, attempts have been made to optimize ion implantation for silicon carbide semiconductors. For example, in Patent Document 1, it is studied to reduce damage to the crystal lattice of silicon carbide by changing the plane orientation at the time of ion injection.

Japanese Unexamined Patent Publication No. 2002-261041

Ion implantation into a silicon carbide semiconductor has not only the problem of damage to crystals but also the problem of poor controllability of the implantation depth. An object of the present disclosure is to improve the controllability of the implantation depth of ion implantation into a silicon carbide semiconductor so that a high-performance silicon carbide semiconductor device can be easily manufactured.

One aspect of the method for manufacturing a silicon carbide semiconductor device of the present disclosure includes a step of forming an ion implantation layer by implanting ions into a 4H-SiC crystal layer, and the ion implantation is performed with respect to the {1-100} plane [0001]. ] To an ion implantation angle tilted + 10 ° or -10 °, an ion implantation angle tilted + 3 ° or -3 ° from [0001] to the {1-210} plane, or a {1-100} plane and {1-1 The ion implantation angle is tilted by + 4 ° or -4 ° from [0001] with respect to the surface intermediate with the 210} surface.

One aspect of the method for manufacturing a silicon carbide semiconductor device is a step of forming a trench penetrating the ion-implanted layer to make the ion-implanted layer a source region and a drain region separated from each other, and forming a gate insulating film in the trench. A step of forming a gate electrode on the gate insulating film, and a step of forming an ohmic electrode in ohmic contact with each of the source region and the drain region may be further provided.

One aspect of the silicon carbide semiconductor device of the present disclosure includes a 4H-SiC crystal layer and at least one impurity-injecting layer formed in the 4H-SiC crystal layer, and the impurity-injecting layer is 2.14 more than the design depth. The impurity concentration at the double depth position is less than 1/20 of the highest impurity concentration in the design depth range.

In one aspect of the silicon carbide semiconductor device, a trench provided in the 4H-SiC crystal layer, a gate electrode provided in the trench via a gate insulating film, and an ohmic electrode in ohmic contact with the impurity injection layer are further provided. The impurity injection layer may be provided on both sides of the trench.

According to the method for manufacturing a semiconductor device of the present disclosure, the controllability of the injection depth is improved, and a high-performance silicon carbide semiconductor device can be easily manufactured.

It is sectional drawing which shows the trench MOSFET which concerns on one Embodiment. (A) to (h) are cross-sectional views showing the manufacturing method of the trench MOSFET according to one embodiment in the order of processes. It is sectional drawing which shows the vertical MOSFET which concerns on one Embodiment. It is sectional drawing which shows the IGBT which concerns on one Embodiment. It is sectional drawing which shows the PN diode which concerns on one Embodiment. It is sectional drawing which shows the Schottky barrier diode which concerns on one Embodiment. It is sectional drawing which shows the modification of the Schottky barrier diode which has a junction barrier structure. It is a top view which shows the relationship between the ion implantation angle and the plane orientation. It is a graph which shows the measurement result of the backscattering yield by the Rutherford scattering method. It is a graph which shows the change of the impurity concentration in the depth direction.

In the symbol of the lattice plane, the negative exponent is crystallographically represented by adding a "-" (bar) above the number, but in the present disclosure, for the convenience of preparing the specification, the number is indicated. It may be represented by prefixing it with a negative number.

The method for manufacturing a silicon carbide (SiC) semiconductor device of the present disclosure includes a step of forming an ion-implanted layer by implanting ions into a 4H-SiC crystal layer. In the step of forming the ion implantation layer, the ion implantation is performed from the ion implantation angle [0001] tilted by + 10 ° or -10 ° with respect to the {1-100} plane, and from [0001] with respect to the {1-210} plane. At an ion implantation angle tilted + 3 ° or -3 °, or at an ion implantation angle tilted + 4 ° or -4 ° from [0001] with respect to the intermediate plane between the {1-100} plane and the {1-210} plane. conduct. It should be noted that this angle allows a deviation of about ± 1 °.

It is preferable that impurities are present in the ion-implanted layer in the region of the design depth range at the designed concentration, and the impurity concentration is rapidly attenuated outside the range. In order to form an ideal ion implantation layer, simulations using parameters such as the implantation ion concentration, injection energy, and substrate material are performed to determine the ion implantation conditions. However, the concentration profile in the depth direction of the actual impurities may deviate significantly from the simulation result, and the characteristics of the semiconductor device may be greatly disturbed. The inventors of the present application can bring the concentration profile in the depth direction of impurities closer to the simulation result by performing ion implantation in an angle range in which the number of backscattered ions in the Rutherford backscattering method does not decrease sharply (dip). I found what I could do.

Specifically, in the case of the direction parallel to the {0-100} plane, there is a range in which a dip of about ± 1 ° hardly occurs from [0001] to + 10 ° or −10 °. Therefore, by performing ion implantation at an ion implantation angle inclined by + 10 ° or -10 ° from [0001] to the {1-100} plane, the controllability of the ion implantation depth is improved and the design value is obtained. Ion implantation layers with close ideal concentration profiles can be formed.

The range where similar dips rarely occur is from [0001] to + 3 ° or -3 ° in the direction parallel to the {1-210} plane, and between the {1-100} plane and the {1-210} plane. It is also present at + 4 ° or -4 ° from [0001] in the direction parallel to the plane. Therefore, the ion implantation angle is tilted by + 3 ° or -3 ° from [0001] with respect to the {1-210} plane, or the plane between the {1-100} plane and the {1-210} plane. It can also be an angle tilted by + 4 ° or -4 ° with respect to [0001].

By setting the ion implantation angle to such a value, the impurity concentration at a position 2.14 times deeper than the design implantation depth can be increased from [0001] to + 4 ° or -4 ° with respect to the conventional {1-100} plane. It can be reduced to 1/6 or less as compared with the case of a tilted implantation angle. For example, when the design injection depth is 70 nm, the impurity concentration at the position where the depth is 150 nm, which is 2.14 times deeper, can be reduced to 1/6 or less of the conventional concentration.

Further, the impurity concentration at a position 2.14 times deeper than the design value injection depth may be preferably 1/20 or less, more preferably 1/50 or less of the highest impurity concentration within the design depth range. can. For example, when an ion implantation layer is formed with a design implantation depth of 70 nm, the impurity concentration at a depth of 150 nm is preferably 1/20 or less, more preferably 1/20 or less of the highest impurity concentration in the range from the surface to 70 nm. Can be 1/50 or less.

In the method for forming the ion-implanted layer of the present embodiment, the impurity concentration is greatly attenuated in the depth direction and an ideal impurity profile can be easily realized. Therefore, a trench MOSFET (Metal-Oxide-Semiconductor Field Effect) as shown in FIG. 1 can be easily realized. It is useful in the manufacture of Transistor).

The trench MOSFET shown in FIG. 1 has a source region 112 and a drain region 111, which are ion implantation layers formed by ion implantation on a substrate 101 made of a 4H-SiC single crystal. A trench is provided between the source region 112 and the drain region 111. An insulating film 116 having an opening for exposing the source region 112, the drain region 111, and the trench is formed on the substrate 101.

A gate electrode 123 is formed in the trench via a gate insulating film 115 which is a dry oxide film. The VDD layer 125 is formed on the source region 112 and the drain region 111 so as to make ohmic contact with each other, and the metal layer 126 is formed on the VDD layer 125. The silicide layer 125 and the metal layer 126 formed on the source region 112 function as the source electrode 122, and the silicide layer 125 and the metal layer 126 formed on the drain region 111 function as the drain electrode 121.

For example, as shown in FIG. 2, the trench MOSFET forms an insulating film 117 serving as an implantation mask on the substrate 101 and then implants ions to form an ion implantation layer 113 serving as a source region 112 and a drain region 111. Ion implantation is performed at an ion implantation angle tilted by + 10 ° or −10 ° from [0001] with respect to the {1-100} plane. Further, in order to reduce damage, for example, high temperature ion implantation at 500 ° C. is preferable. After that, the carbon cap layer 118 is formed and annealed to activate impurities and restore crystallinity. Annealing can be, for example, at 1700 ° C. for 5 minutes.

Next, after forming the insulating film 116 having an opening that exposes the ion-implanted layer 113, a trench is formed using the insulating film 116 as a mask to separate the ion-implanted layer 113 into a source region 112 and a drain region 111. After that, dry oxidation is performed at, for example, 1150 ° C. to form a gate insulating film 115 in the trench portion. After that, an opening for exposing the source region 112 and the drain region 111 is formed in the insulating film 116, and a silicide layer 125 is formed in the source region 112 and the drain region 111. After that, an aluminum layer is formed and patterned to form a source electrode 122, a drain electrode 121, and a gate electrode 123.

In the trench MOSFET, the impurity profile in the depth direction of the ion implantation layer 113 which becomes the source region 112 and the drain region 111 is very important. If impurities are injected deeper than the design position, the source region 112 and the drain region 111 will not be sufficiently separated even if a trench is formed, and a leak will occur under the gate electrode 123. The threshold voltage rises above the design value. If the trench is made deeper, the threshold voltage can be lowered, but if the trench is made deeper than the design value, the parasitic capacitance increases and the operating speed decreases. Further, if the ion-implanted layer 113 expands to a position deeper than the design value, there is also a problem that the impurity concentration in the ion-implanted layer 113 decreases.

By using the method for forming the ion-implanted layer of the present embodiment, it is possible to suppress the ion-implanted layer 113 from expanding to a position deeper than the design value and realize a concentration profile close to the design value. As a result, in the trench MOSFT, leakage is less likely to occur on the lower side of the gate electrode 123, and deviation of the threshold voltage is less likely to occur. It should be noted that the ion implantation angle tilted by + 3 ° or -3 ° from [0001] with respect to the {1-210} plane, or with respect to the plane intermediate between the {1-100} plane and the {1-210} plane [ Ion implantation of the ion implantation layer 113 can also be performed at an ion implantation angle tilted by + 4 ° or -4 ° from [0001].

In principle, the method for forming the ion-implanted layer of the present embodiment can bring the impurity profile closer to the ideal type for any of the p-type impurities aluminum and boron and the n-type impurities nitrogen and phosphorus. Therefore, it is useful for forming both the p-type ion-implanted layer and the n-type ion-implanted layer. Further, even if the ion of the atom is implanted instead of the ion of the molecular cluster, the impurity profile can be easily controlled, and the ion implantation with less damage to the silicon carbide crystal can be performed.

The method for forming the ion-implanted layer of the present embodiment is not limited to the trench MOSFET, and can be used for manufacturing various semiconductor devices having an ion-implanted layer. For example, it can also be used for manufacturing a vertical MOSFET as shown in FIG. In the vertical MOSFET shown in FIG. 3, an ^n- type drift layer 132 is formed by epitaxial growth on the surface of a substrate 131 made of ^{n + type 4H-SiC. A p-type well 133 and an n +} -type source region 134 are provided on the surface side of the drift layer 132 by ion implantation, and a source electrode 141 is formed on the source region 134. The gate electrode 143 is formed via the gate insulating film 135 so as to straddle the source region 134. A drain electrode 142, which is an ohmic electrode, is formed on the back surface of the substrate 131.

The method for forming the ion-implanted layer of the present embodiment can be used for forming the p-type well 133 and the source region 134, which are the ion-implanted layers. In particular, by using the method for forming the ion implantation method of the present embodiment for forming the source region 134, it is possible to easily control the source region 134 so as not to become too deep.

The method for forming the ion-implanted layer of the present embodiment can also be used for manufacturing an insulated gate bipolar transistor (IGBT) as shown in FIG. In the IGBT shown in FIG. 4, for example ^{, an n-} type drift layer 152 is formed by epitaxial growth on the surface of a substrate 151 made of ^{p +} type 4H-SiC, and a p-type well is formed on the surface side of the drift layer 152. 153 is formed by ion implantation. In the p-type well 153, an n ⁺ type emitter region 154 is formed by ion implantation, and an emitter electrode 161 is formed on the emitter region 154. The gate electrode 163 is formed via the gate insulating film 155 so as to straddle the emitter region 154. A collector electrode 162 is formed on the back surface of the substrate 151.

The method for forming the ion-implanted layer of the present embodiment can be used for forming the p-type well 153 and the emitter region 154, which are the ion-implanted layers. In particular, by using the method of forming the ion implantation method of the present embodiment for forming the emitter region 154, it is possible to easily control the emitter region 154 so that it does not become too deep.

The method for forming the ion-implanted layer of the present embodiment can also be used for manufacturing a PN diode as shown in FIG. 5, on a substrate 171 made of n ⁺ -type 4H-SiC of, n ^- -type epitaxial layer 172 is formed of, the top of the epitaxial layer 172 p ⁺ -type layer 173 is formed by ion implantation There is. A silicon oxide film 175 having an opening for exposing the ^{p +} type layer is formed on the epitaxial layer 172, and an anode electrode 178 is formed in the opening. A cathode electrode 179 is formed on the back surface of the substrate 171. the formation of the p ⁺ -type layer 173, by using the method of forming the ion implantation in this embodiment, can easily be p ⁺ -type layer 173 is controlled not to become too deeply.

The method for forming the ion-implanted layer of the present embodiment can also be used for manufacturing a Schottky barrier diode as shown in FIG. 6, on a substrate 181 made of n ⁺ -type 4H-SiC of, n ^- -type epitaxial layer 182 is formed of, the top of the epitaxial layer 182 p ⁺ -type layer 183 is formed by ion implantation There is. A silicon oxide film 185 having an opening for exposing the ^{p +} type layer is formed on the epitaxial layer 182, and a Schottky electrode 188 is formed in the opening. An ohmic electrode 189 is formed on the back surface of the substrate 181. Instead of the p ⁺ type layer 183, a junction barrier structure 184 as shown in FIG. 7 can be formed. By using the method for forming the ion implantation method of the present embodiment, ^{it is possible to easily control the p +} type layer 183 or the junction barrier structure 184 so as not to be too deep.

Not limited to these, the method for forming the ion-implanted layer of the present embodiment can be used in all cases where the ion-implanted layer is formed in the 4H-SiC crystal layer. The 4H-SiC crystal layer into which ions are injected may be a substrate or an epitaxial growth layer formed on the substrate.

The method for forming the ion-implanted layer of the present disclosure will be described in more detail with reference to Examples. The following examples are examples and are not intended to limit the scope of rights.

<Channeling measurement by Rutherford backscattering method>
Helium was injected at an injection angle tilted from [0001], and channeling was measured by the Rutherford backscattering method. With the injection acceleration voltage set to 2 MeV, the scattering intensity was measured at an angle along the lines 1, 2 and 3 in FIG.

As shown in FIG. 9, in the case of line 1 in the direction parallel to the {1-100} plane, a dip in which the number of backscattered ions sharply decreases is observed near -4 ° used in normal ion implantation. Be done. At the position where the dip is recognized, channeling occurs during ion implantation, and there is a high possibility that impurities will spread to a deep position. On the other hand, no dip is observed in the range of -10 ± 1 °, and it is predicted that channeling can be less likely to occur even if the injection angle is deviated.

In the case of line 2, which is the direction parallel to the {1-210} plane, the direction parallel to the intermediate plane between the {1-100} plane and the {1-210} plane within the range of -3 ± 1 °. In the case of line 3, since a sharp decrease in the number of backscattered ions is not observed in the range of -4 ± 1 °, it is predicted that channeling can be less likely to occur in this range as well.

Further, since the profile of the number of backscattered ions is symmetrical, it is predicted that channeling can be similarly less likely to occur at + 10 ° on line 1, + 3 ° on line 2, and + 4 ° on line 3.

<Measurement of impurity concentration profile>
Ion implantation was performed on a 4H-SiC single crystal substrate, and the impurity concentration in the depth direction was measured by the secondary ion mass spectrometry (SIMS) method. The conditions for ion implantation were determined by simulation so that the design implantation depth was 70 nm. The simulation of the condition determination was performed using SRIMM2008 as the simulation software. Specific injection conditions are multi-stage injection with an aluminum atom as an ion species, an injection depth of 70 nm, and an injection concentration of 4 × 10 ²⁰ (atoms / cm ³ ). The conditions for multi-stage injection are acceleration energy of 55 keV. The injection amount is 2.40 × 10 ¹⁵ / cm ² , the injection amount is 7.00 × 10 ¹⁴ / cm ² with the acceleration energy of 25 keV, and the injection amount is 3.20 × 10 ¹³ / cm ² with the acceleration energy of 12 keV. The SIMS was measured using a secondary ion mass spectrometer SIMS6650 manufactured by ULVAC-PHI, and an O2 duoplasmatron ion gun was used as the primary ion gun.

As shown in FIG. 10, when ion implantation is performed at an angle of -4 ° from [0001] to the {1-100} plane corresponding to -4 ° of line 1, the impurity concentration starts from about 80 nm. However, the deviation from the ideal profile by simulation begins to increase, and the impurity concentration at the position of 150 nm, which is 2.14 times the design implantation depth, is about ^{6 × 10 19} cm ^-3.

On the other hand, when ion implantation is performed at an angle of -10 ° from [0001] to the {1-100} plane corresponding to -10 ° of line 1, the impurity concentration up to a depth of about 100 nm is ideal by simulation. It is not very different from the typical profile. The deviation gradually increased at a position deeper than the design injection depth of 70 nm, but the impurity concentration at 150 nm was ^{about 1 × 10 19} cm ^-3 , which was about 1/6 of that at -4 °.

At -10 °, the maximum impurity concentration in the range up to the design injection depth of 70 nm is ^{about 6 × 10 20} cm ^-3, which is 2.14 times the design injection depth of impurities at 150 nm. The concentration was 1/50 or less of the maximum value. On the other hand, in the case of -4 °, the impurity concentration at 150 nm is about 1/10 of the maximum value, and the impurity concentration is not sufficiently attenuated.

<Comparison of threshold voltage>
When the p-type trench MOSFET shown in FIG. 1 was created, the threshold voltage became -4V when ion implantation was performed at an angle of -10 ° from [0001] to the {1-100} plane, resulting in normal off. I was able to realize it. On the other hand, when ion implantation was performed with the {1-100} plane tilted by -4 ° from [0001], the threshold voltage became + 9V, and normal off could not be realized. The threshold voltage was measured by changing the gate voltage with the drain voltage set to −100 mV and the source voltage set to 0 V.

The trench depth was 160 nm, the gate insulating film was 20 nm, the gate length was 5 μm, and the gate width was 10 μm. The ion implantation layer was formed by multi-stage implantation in which aluminum atoms were formed as ion species, the design implantation depth was 70 nm, and the implantation concentration was 4 × 10 ²⁰ atoms / cm ^3. The conditions for multi-stage injection are: injection amount 2.40 × 10 ¹⁵ / cm ² with acceleration energy 55 keV, injection amount 7.00 × 10 ¹⁴ / cm ² with acceleration energy 25 keV, injection amount 3.20 × 10 ^{13 with acceleration energy 12 keV.} / Cm ² .

The method for manufacturing a silicon carbide semiconductor device of the present disclosure is useful in the field of semiconductor devices because it has high controllability of injection depth and can easily manufacture a high-performance silicon carbide semiconductor device.

101 Substrate 111 Drain region 112 Source region 113 Ion injection layer 115 Gate insulation film 116 Insulation film 117 Insulation film 118 Carbon cap layer 121 Drain electrode 122 Source electrode 123 Gate electrode 125 VDD layer 126 Metal layer 131 Substrate 132 Drift layer 133 p-type well 134 Source region 135 Gate insulating film 141 Source electrode 142 Drain electrode 143 Gate electrode 151 Substrate 152 Drift layer 153 p-type well 154 Emitter region 155 Gate insulating film 161 Emitter electrode 162 Collector electrode 163 Gate electrode 171 Substrate 172 Epitential layer 173 p ⁺ type Layer 175 Silicon oxide film 178 Anode electrode 179 Cathode electrode 181 Substrate 182 Epitional layer 183 type layer 184 Junction barrier structure 185 Silicon oxide film 188 Schottky electrode 189 Ohmic electrode

Claims (4)

A step of forming an ion-implanted layer by implanting ions into a 4H-SiC crystal layer is provided.
The ion implantation angle is + 10 ° or -10 ° tilted from [0001] with respect to the {1-100} plane, and + 3 ° or -3 ° tilted from [0001] with respect to the {1-210} plane. Ion implantation angle, or an ion implantation angle tilted by + 4 ° or -4 ° from [0001] with respect to the intermediate surface between the {1-100} plane and the {1-210} plane. Production method. A step of forming a trench penetrating the ion-implanted layer to make the ion-implanted layer a source region and a drain region separated from each other.
The process of forming a gate insulating film in the trench and
The process of forming the gate electrode on the gate insulating film and
The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of forming ohmic electrodes in ohmic contact with the source region and the drain region, respectively. 4H-SiC crystal layer and
It is provided with at least one impurity injection layer formed on the 4H-SiC crystal layer.
The impurity injection layer is a silicon carbide semiconductor device in which the impurity concentration at a position 2.14 times deeper than the design injection depth is 1/20 or less of the highest impurity concentration in the design depth range. The trench provided in the 4H-SiC crystal layer and
A gate electrode provided in the trench via a gate insulating film and
Further provided with the impurity injection layer and an ohmic electrode in ohmic contact,
The silicon carbide semiconductor device according to claim 3, wherein the impurity injection layer is provided on both sides of the trench.

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