JP2021097171A - Semiconductor device - Google Patents

Abstract

To provide a technique of suppressing the occurrence of a crack in an interlayer insulating film.SOLUTION: A semiconductor device includes a semiconductor substrate, a trench provided on an upper surface of the semiconductor substrate, a gate insulating film covering an inner surface of the trench, a gate electrode disposed in the trench, an interlayer insulating film covering an upper surface of the gate electrode and having a contact hole on an upper part of the upper surface of the semiconductor substrate, and an upper electrode covering the range from an upper surface of the interlayer insulating film to an inner surface of the contact hole and being in contact with the upper surface of the semiconductor substrate in the contact hole. The upper electrode includes a tungsten-containing metal layer disposed on an upper part of the interlayer insulating film, an aluminum-containing metal layer extending from the upper part of the interlayer insulating film to the upper part of the contact hole and covering an upper surface of the tungsten-containing metal layer, and a nickel-containing metal layer covering an upper surface of the aluminum-containing metal layer.SELECTED DRAWING: Figure 1

Description

The techniques disclosed herein relate to semiconductor devices.

Patent Document 1 discloses a semiconductor device having a trench, a gate insulating film, a gate electrode, an interlayer insulating film, an aluminum-containing metal layer, and a nickel-containing metal layer. The trench is provided on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of the trench. The gate electrode is arranged in the trench. The interlayer insulating film covers the upper surface of the gate electrode and has a contact hole on the upper surface of the semiconductor substrate. A plug electrode is provided in the contact hole. The aluminum-containing metal layer covers the range straddling the upper surface of the interlayer insulating film and the upper surface of the plug electrode. The nickel-containing metal layer covers the upper surface of the aluminum-containing metal layer.

International Publication No. 2018/056233

When the semiconductor device operates and generates heat, each component thermally expands. In the semiconductor device of Patent Document 1, since the linear expansion coefficient of the semiconductor substrate and the nickel-containing metal layer are different, a high thermal stress is applied to the nickel-containing metal layer when the semiconductor device generates heat. When the semiconductor device repeatedly generates heat, stress is repeatedly applied to the nickel-containing metal layer, and the nickel-containing metal layer is deformed. As a result, the nickel-containing metal layer may be elongated and invade the inside of the aluminum-containing metal layer. When the nickel-containing metal layer exceeds the aluminum-containing metal layer and reaches the interlayer insulating film, cracks occur in the interlayer insulating film, causing problems such as a gate leak current flowing. The present specification provides a technique for suppressing the occurrence of cracks in the interlayer insulating film.

The semiconductor device disclosed in the present specification includes a semiconductor substrate, a trench, a gate insulating film, a gate electrode, an interlayer insulating film, and an upper electrode. The trench is provided on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of the trench. The gate electrode is arranged in the trench. The interlayer insulating film covers the upper surface of the gate electrode and has a contact hole on the upper surface of the semiconductor substrate. The upper electrode covers a range straddling the upper surface of the interlayer insulating film and the inner surface of the contact hole, and is in contact with the upper surface of the semiconductor substrate in the contact hole. The upper electrode includes a tungsten-containing metal layer, an aluminum-containing metal layer, and a nickel-containing metal layer. The tungsten-containing metal layer is arranged above the interlayer insulating film. The aluminum-containing metal layer extends from the upper part of the tungsten-containing metal layer to the upper part of the contact hole and covers the upper surface of the tungsten-containing metal layer. The nickel-containing metal layer covers the upper surface of the aluminum-containing metal layer.

In this semiconductor device, a tungsten-containing metal layer is arranged on the interlayer insulating film. That is, the tungsten-containing metal layer is arranged between the interlayer insulating film and the nickel-containing metal layer. The tungsten-containing metal layer is harder than the nickel-containing metal layer (Vickers hardness is higher). Therefore, even when the nickel-containing metal layer invades the inside of the aluminum-containing metal layer when the semiconductor device generates heat, the tungsten-containing metal layer prevents the nickel-containing metal layer from advancing. Therefore, the nickel-containing metal layer is prevented from reaching the interlayer insulating film. Therefore, in this semiconductor device, cracks are unlikely to occur in the interlayer insulating film, and the reliability of the semiconductor device is high.

FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view showing a state in which the Ni layer is elongated in the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view of the semiconductor device according to the second embodiment. Top view of the semiconductor device according to the third embodiment. FIG. 4 is a cross-sectional view taken along the line VV of FIG. FIG. 4 is a cross-sectional view taken along the line VI-VI of FIG. FIG. 3 is a cross-sectional view of a semiconductor device according to a modified example.

(Example 1)
The semiconductor device 10 of the first embodiment shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field effect transistor). The semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of a semiconductor material such as SiC (silicon carbide) or Si (silicon). In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends long in the y direction. The trenches 22 extend parallel to each other at intervals in the x direction. The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is arranged in each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

The upper surface of the gate electrode 26 and the upper surface 12a of the semiconductor substrate 12 are covered with an interlayer insulating film 28. A plurality of contact holes 28a are formed in the interlayer insulating film 28. Each contact hole 28a is provided in a range between two adjacent trenches 22 respectively. That is, the contact hole 28a is arranged in a range in which the gate electrode 26 is not provided in the x direction. Each contact hole 28a penetrates from the upper surface to the lower surface of the interlayer insulating film 28. The upper surface 12a of the semiconductor substrate 12 is exposed at the bottom of the contact hole 28a.

A W layer 40 is provided inside each contact hole 28a. The W layer 40 is made of tungsten. The W layer 40 is in contact with the upper surface 12a of the semiconductor substrate 12 at the bottom of each contact hole 28a. The W layer 40 extends from the inside of the contact hole 28a to a range straddling the upper surface of the interlayer insulating film 28. The W layer 40 is formed so that its upper surface is substantially flat. The W layer 40 is insulated from the gate electrode 26 by an interlayer insulating film 28.

An AlSi layer 42 is provided on the upper surface of the W layer 40. The AlSi layer 42 is made of an alloy of aluminum and silicon. The AlSi layer 42 covers substantially the entire upper surface of the W layer 40. That is, the AlSi layer 42 extends from the upper part of the interlayer insulating film 28 to the upper part of the contact hole 28a.

A Ni layer 44 is provided on a part of the upper surface of the AlSi layer 42. The Ni layer 44 is made of nickel. The Ni layer 44 covers the upper surface of the AlSi layer 42 on the center side (left side in FIG. 1) of the semiconductor substrate 12. A polyimide film 46 is provided on the upper surface of the AlSi layer 42 on the outer peripheral side (right side in FIG. 1) of the semiconductor substrate 12. The polyimide film 46 is in contact with the outer peripheral end surface of the Ni layer 44 and the upper surface of the AlSi layer 42.

The upper electrode 50 is composed of the W layer 40, the AlSi layer 42, and the Ni layer 44. A solder layer 48 is provided on the upper surface of the Ni layer 44. The solder layer 48 is not provided on the upper surface of the polyimide film 46. The upper electrode 50 is soldered to an external terminal (not shown) by the solder layer 48. The Ni layer 44 is provided for soldering the upper electrode 50 to the external terminal. A lower electrode 52 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 52 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

A source region 30, a body region 32, a drift region 34, and a drain region 35 are provided inside the semiconductor substrate 12.

The source region 30 is n-shaped and is exposed on the upper surface 12a of the semiconductor substrate 12 and is in contact with the gate insulating film 24. A part of the source region 30 is in contact with the W layer 40. The body region 32 is p-shaped and is in contact with the source region 30. The body region 32 extends from the range sandwiched between the two source regions 30 to the lower side of each source region 30. The body region 32 has a contact region 32a and a main body region 32b. The contact region 32a has a higher p-type impurity concentration than the main body region 32b. The contact region 32a is arranged in a range sandwiched between the two source regions 30. The contact region 32a is in contact with the W layer 40. The main body region 32b is in contact with the gate insulating film 24 on the lower side of the source region 30.

The drift region 34 is n-shaped and is arranged below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is in contact with the gate insulating film 24 on the lower side of the body region 32. The drain region 35 is n-type and has an n-type impurity concentration higher than that of the drift region 34. The drain region 35 is arranged below the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in contact with the lower electrode 52.

When the semiconductor device 10 is used, the semiconductor device 10, a load (for example, a motor), and a power supply are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 10 and the load. The power supply voltage is applied in a direction in which the drain side (lower electrode 52) of the semiconductor device 10 has a higher potential than the source side (upper electrode 50). When a gate-on potential (potential higher than the gate threshold value) is applied to the gate electrode 26, a channel is formed in the main body region 32b in the range in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When a gate-off potential (potential equal to or lower than the gate threshold value) is applied to the gate electrode 26, the channel disappears and the semiconductor device 10 is turned off.

When the semiconductor device 10 operates and generates heat, each component thermally expands. Since the linear expansion coefficients of the semiconductor substrate 12 and the Ni layer 44 are different, a high thermal stress is applied to the Ni layer 44 when the semiconductor device 10 generates heat. When the semiconductor device 10 repeatedly generates heat, stress is repeatedly applied to the Ni layer 44, and the Ni layer 44 is deformed. As a result, as shown in FIG. 2, the Ni layer 44 may extend and invade the inside of the AlSi layer 42. In this embodiment, the interlayer insulating film 28 is covered with the W layer 40. The Vickers hardness (about 3430 MPa) of tungsten constituting the W layer 40 is larger than the Vickers hardness (about 638 MPa) of nickel constituting the Ni layer 44. That is, the W layer 40 has higher strength than the Ni layer 44. Further, the W layer 40 is provided so that its upper surface is substantially flat. Therefore, even if the Ni layer 44 invades the inside of the AlSi layer 42 when the semiconductor device 10 generates heat, the W layer 40 prevents the Ni layer 44 from advancing. Therefore, it is prevented that the Ni layer 44 reaches the interlayer insulating film 28. Therefore, the semiconductor device 10 of this embodiment has high reliability because the interlayer insulating film 28 is less likely to be cracked.

(Example 2)
Subsequently, the semiconductor device 100 of the second embodiment will be described. As shown in FIG. 3, in the semiconductor device 100 of the second embodiment, the configuration of the upper electrode 150 is different from that of the upper electrode 50 of the first embodiment.

As shown in FIG. 3, in the second embodiment, the W layer 40 covers a part of the upper surface 12a of the semiconductor substrate 12 and a part of the plurality of interlayer insulating films 28. Specifically, the W layer 40 is arranged in a range including the lower part of the boundary portion A between the Ni layer 44 and the polyimide film 46. The interlayer insulating film 28 located immediately below the boundary portion A and the two interlayer insulating films 28 adjacent to both sides of the interlayer insulating film 28 are covered with the W layer 40. The W layer 40 is in contact with the upper surface 12a of the semiconductor substrate 12 in the contact hole 28a. In the range where the W layer 40 is not provided, the AlSi layer 42 is arranged in the contact hole 28a. In the range where the W layer 40 is not provided, the AlSi layer 42 is in contact with the upper surface 12a of the semiconductor substrate 12 in the contact hole 28a.

When the semiconductor device 100 repeatedly generates heat, in the triple contact portion where the AlSi layer 42, the Ni layer 44, and the polyimide film 46 are in contact with each other, three types of layers having different coefficients of linear expansion are in contact with each other, so that high stress is achieved. Occurs. Therefore, when the semiconductor device 100 repeatedly generates heat, a high stress is repeatedly applied to the Ni layer 44, and the Ni layer 44 tends to stretch. That is, the Ni layer 44 easily penetrates into the AlSi layer 42 located below the boundary A between the Ni layer 44 and the polyimide film 46. In this embodiment, the interlayer insulating film 28 located below the boundary portion A is covered with the W layer 40. Therefore, the interlayer insulating film 28 can be suitably protected. On the other hand, in this embodiment, the W layer 40 is not provided at a position relatively distant from the boundary portion A. That is, the AlSi layer 42 is in contact with the upper surface 12a of the semiconductor substrate 12. The AlSi layer 42 has a lower electrical resistance than the W layer 40. Therefore, a large current can be passed through the semiconductor device 100 by bringing the AlSi layer 42 into contact with the upper surface 12a of the semiconductor substrate 12 without passing through the W layer 40, except for the portion where the interlayer insulating film 28 is particularly required to be protected. .. As described above, in the semiconductor device 100 of this embodiment, both the protection of the interlayer insulating film 28 and the high energization performance can be achieved at the same time.

(Example 3)
Subsequently, the semiconductor device 200 of the third embodiment will be described. In the semiconductor device 200 of the third embodiment, the configuration of the upper electrode 250 (see FIGS. 5 and 6) is different from that of the upper electrode 50 of the first embodiment.

FIG. 4 is a top view of the semiconductor device 200. When the semiconductor device 200 is operated, the central portion 210 of the semiconductor substrate 12 becomes hotter than the outer peripheral portion 220 in the region where the upper electrode 250 is formed (that is, the region where the semiconductor element is formed). That is, in the central portion 210, the temperature change of the semiconductor substrate 12 is large and the stress applied to the Ni layer 44 is large, so that the Ni layer 44 is easily elongated. In this embodiment, as shown in FIGS. 5 and 6, the interlayer insulating film 28 is covered with the W layer 40 in the central portion 210, and the W layer 40 is not provided in the outer peripheral portion 220. That is, in the outer peripheral portion 220, the AlSi layer 42 covers the range extending from the upper surface 12a of the semiconductor substrate 12 to the inside of the contact hole 28a. As described above, in this embodiment, the interlayer insulating film 28 can be suitably protected by arranging the W layer 40 in the central portion 210 where the elongation of the Ni layer 44 is particularly remarkable. Further, at the outer peripheral portion 220 where the Ni layer 44 does not extend so much (that is, the Ni layer 44 does not easily penetrate into the AlSi layer 42), the AlSi layer 42 is brought into contact with the upper surface 12a of the semiconductor substrate 12 without passing through the W layer 40. As a result, a large current can be passed through the semiconductor device 100. As described above, also in the semiconductor device 200 of this embodiment, both the protection of the interlayer insulating film 28 and the high energization performance can be achieved at the same time.

In the technique disclosed in the present specification, as shown in FIG. 7, it is sufficient that the W layer 40 is provided at least above the interlayer insulating film 28, and the inside of the contact hole 28a is made of a material other than tungsten. The metal layer 60 may be arranged. The material of the metal layer 60 is not particularly limited, and may be, for example, an alloy of aluminum and silicon.

Further, in each of the above-described embodiments, a barrier metal layer composed of Ti (titanium), TiN (titanium nitride) or the like may be interposed in a range extending from the upper surface of the interlayer insulating film 28 to the inner surface of the contact hole 28a. ..

Further, in each of the above-described embodiments, the case where the semiconductor device is a MOSFET has been described. However, the semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor).

(Correspondence)
The W layer 40 is an example of the "tungsten-containing metal layer", the AlSi layer 42 is an example of the "aluminum-containing metal layer", and the Ni layer 44 is an example of the "nickel-containing metal layer".

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor device 12: Semiconductor substrate 12a: Upper surface 12b: Lower surface 22: Trench 24: Gate insulating film 26: Gate electrode 28: Interlayer insulating film 28a: Contact hole 30: Source region 32: Body region 32a: Contact region 32b: Main Body region 34: Drift region 35: Drain region 40: W layer 42: AlSi layer 44: Ni layer 46: Polyimide film 48: Solder layer 50: Upper electrode 52: Lower electrode

Claims (1)

With a semiconductor substrate
The trench provided on the upper surface of the semiconductor substrate and
The gate insulating film covering the inner surface of the trench and
With the gate electrode arranged in the trench,
An interlayer insulating film that covers the upper surface of the gate electrode and has a contact hole on the upper surface of the semiconductor substrate.
An upper electrode that covers a range that straddles the upper surface of the interlayer insulating film and the inner surface of the contact hole and is in contact with the upper surface of the semiconductor substrate in the contact hole.
Is equipped with
The upper electrode
A tungsten-containing metal layer arranged on the interlayer insulating film and
An aluminum-containing metal layer extending from the upper part of the interlayer insulating film to the upper part of the contact hole and covering the upper surface of the tungsten-containing metal layer.
A nickel-containing metal layer covering the upper surface of the aluminum-containing metal layer,
A semiconductor device.

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