JP2019110248A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2019110248A
JP2019110248A JP2017243149A JP2017243149A JP2019110248A JP 2019110248 A JP2019110248 A JP 2019110248A JP 2017243149 A JP2017243149 A JP 2017243149A JP 2017243149 A JP2017243149 A JP 2017243149A JP 2019110248 A JP2019110248 A JP 2019110248A
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metal film
linear expansion
semiconductor device
surface electrode
expansion coefficient
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JP7102723B2 (en
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橋本　直樹
Naoki Hashimoto
直樹 橋本
明高 添野
Akitaka Soeno
明高 添野
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Toyota Motor Corp
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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Abstract

To provide a technique capable of reducing a cavity generated in a front surface electrode of a semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate; and a front surface electrode covering a front surface of the semiconductor substrate. The front surface electrode includes: a first metal film; a second metal film; and a third metal film. The first metal film covers the front surface of the semiconductor substrate. The second metal film covers the front surface of the first metal film, includes a penetration hole achieved to the front surface of the first metal film, and includes a linear expansion coefficient lower than that of the first metal film. The third metal film covers the front surfaces of the second metal film and the first metal film in the penetration hole, and includes the linear expansion coefficient larger than that of the second metal film. A difference of linear expansion coefficient between the first metal film and the third metal film, is smaller than the difference of the linear expansion coefficient between the first and second metal films and the difference of the linear expansion coefficient between the second and third metal films.SELECTED DRAWING: Figure 1

Description

本明細書に開示の技術は、半導体装置に関する。   The technology disclosed herein relates to a semiconductor device.

特許文献１には、半導体基板の表面を覆う表面電極を備える半導体装置が開示されている。この表面電極は、下部金属膜と、下部金属膜の表面を覆う高強度金属膜と、高強度金属膜の表面を覆う上部金属膜を有する。この構成によれば、ワイヤーボンディングによる半導体基板へのダメージを抑制することができる。   Patent Document 1 discloses a semiconductor device provided with a surface electrode covering the surface of a semiconductor substrate. The surface electrode has a lower metal film, a high strength metal film covering the surface of the lower metal film, and an upper metal film covering the surface of the high strength metal film. According to this configuration, damage to the semiconductor substrate due to the wire bonding can be suppressed.

特開２０１１−２４９４９１号公報JP, 2011-249491, A

特許文献１の構造では、半導体装置が温度変化する際に、表面電極を構成する各金属膜の線膨張係数の差によって、各金属膜に高い応力が加わる。その結果、金属膜の内部に空洞が生じる場合がある。このような状態で表面電極にクラックが生じると、空洞を通じてクラックが進展し易くなり、クラックが半導体基板まで達する虞がある。本明細書では、表面電極に生じる空洞を低減することができる技術を提供する。   In the structure of Patent Document 1, when the temperature of the semiconductor device changes, high stress is applied to each metal film due to the difference in the linear expansion coefficient of each metal film constituting the surface electrode. As a result, a cavity may be generated inside the metal film. If a crack is generated in the surface electrode in such a state, the crack is likely to progress through the cavity, and the crack may reach the semiconductor substrate. The present specification provides a technique capable of reducing the cavities generated in the surface electrode.

本明細書が開示する半導体装置は、半導体基板と、前記半導体基板の表面を覆う表面電極、を有する。前記表面電極が、第１金属膜と、第２金属膜と、第３金属膜を有する。前記第１金属膜は、前記半導体基板の前記表面を覆っている。前記第２金属膜は、前記第１金属膜の表面を覆っており、前記第１金属膜の前記表面に達する貫通孔を有しており、前記第１金属膜よりも低い線膨張係数を有する。前記第３金属膜は、前記第２金属膜の表面と前記貫通孔内の前記第１金属膜の前記表面を覆っており、前記第２金属膜よりも高い線膨張係数を有する。前記第１金属膜と前記第３金属膜の線膨張係数の差は、前記第１金属膜と前記第２金属膜の線膨張係数の差及び前記第２金属膜と前記第３金属膜の線膨張係数の差よりも小さい。   A semiconductor device disclosed in the present specification includes a semiconductor substrate and a surface electrode covering a surface of the semiconductor substrate. The surface electrode includes a first metal film, a second metal film, and a third metal film. The first metal film covers the surface of the semiconductor substrate. The second metal film covers the surface of the first metal film, has a through hole reaching the surface of the first metal film, and has a linear expansion coefficient lower than that of the first metal film. . The third metal film covers the surface of the second metal film and the surface of the first metal film in the through hole, and has a linear expansion coefficient higher than that of the second metal film. The difference between the linear expansion coefficients of the first metal film and the third metal film is the difference between the linear expansion coefficients of the first metal film and the second metal film, and the line of the second metal film and the third metal film. Less than the difference in expansion coefficients.

上記の半導体装置では、第２金属膜が第１金属膜の表面に達する貫通孔を有している。そして、貫通孔内では、線膨張係数の差が比較的小さい第１金属膜と第３金属膜が接している。したがって、貫通孔内では、第１金属膜と第３金属膜に加わる応力が低減される。また、第２金属膜の一部に貫通孔（すなわち、高い応力が生じない部分）が設けられていることで、第２金属膜全体で応力が緩和される。このため、この半導体装置では、温度変化が生じても、表面電極の内部に空洞が生じ難い。   In the above semiconductor device, the second metal film has a through hole reaching the surface of the first metal film. In the through hole, the first metal film and the third metal film are in contact with each other with a relatively small difference in linear expansion coefficient. Therefore, in the through hole, stress applied to the first metal film and the third metal film is reduced. In addition, since the through holes (that is, portions where high stress does not occur) are provided in a part of the second metal film, stress is relaxed in the entire second metal film. For this reason, in this semiconductor device, even if a temperature change occurs, a cavity is less likely to be generated inside the surface electrode.

半導体装置１０の断面図。FIG. 2 is a cross-sectional view of the semiconductor device 10; 半導体装置１０の上面図。FIG. 2 is a top view of the semiconductor device 10;

図１に示す実施例の半導体装置１０は、半導体基板１２を有している。半導体基板１２の表面１２ａには、トレンチ４０が設けられている。各トレンチ４０内に、ゲート電極３０とゲート絶縁膜３２が配置されている。ゲート電極３０の表面は、層間絶縁膜６２に覆われている。半導体基板１２内には、ｎ型のエミッタ領域２２、ｐ型のボディコンタクト領域２４、ｐ型のボディ領域２５、ｎ型のドリフト領域２６及びｐ型のコレクタ領域２７が設けられている。半導体基板１２の表面１２ａには、表面電極５０が配置されている。半導体基板１２の裏面１２ｂには、裏面電極６４が配置されている。エミッタ領域２２、ボディコンタクト領域２４、ボディ領域２５、ドリフト領域２６、コレクタ領域２７、ゲート電極３０等によって、ＩＧＢＴ（Insulated Gate Bipolar Transistor）が構成されている。表面電極５０は、ＩＧＢＴのエミッタ電極として機能する。裏面電極６４は、ＩＧＢＴのコレクタ電極として機能する。   The semiconductor device 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. Trenches 40 are provided on the surface 12 a of the semiconductor substrate 12. In each trench 40, a gate electrode 30 and a gate insulating film 32 are disposed. The surface of the gate electrode 30 is covered with an interlayer insulating film 62. In the semiconductor substrate 12, an n-type emitter region 22, a p-type body contact region 24, a p-type body region 25, an n-type drift region 26, and a p-type collector region 27 are provided. A surface electrode 50 is disposed on the surface 12 a of the semiconductor substrate 12. A back electrode 64 is disposed on the back surface 12 b of the semiconductor substrate 12. The emitter region 22, the body contact region 24, the body region 25, the drift region 26, the collector region 27, the gate electrode 30, and the like constitute an IGBT (insulated gate bipolar transistor). The surface electrode 50 functions as an emitter electrode of the IGBT. The back surface electrode 64 functions as a collector electrode of the IGBT.

表面電極５０は、第１金属膜５１、第２金属膜５２及び第３金属膜５３を有している。   The surface electrode 50 has a first metal film 51, a second metal film 52, and a third metal film 53.

第１金属膜５１は、半導体基板１２の表面１２ａに配置されている。第１金属膜５１は、層間絶縁膜６２によってゲート電極３０から絶縁されている。第１金属膜５１は、層間絶縁膜６２が存在しない範囲で、半導体基板１２の表面１２ａに接している。第１金属膜５１は、例えば、ＡｌＳｉ（アルミニウムとシリコンの合金）を主成分とする金属膜である。第１金属膜５１は、エミッタ領域２２及びボディコンタクト領域２４に対してオーミック接触している。   The first metal film 51 is disposed on the surface 12 a of the semiconductor substrate 12. The first metal film 51 is insulated from the gate electrode 30 by the interlayer insulating film 62. The first metal film 51 is in contact with the surface 12 a of the semiconductor substrate 12 in the range where the interlayer insulating film 62 does not exist. The first metal film 51 is, for example, a metal film containing AlSi (an alloy of aluminum and silicon) as a main component. The first metal film 51 is in ohmic contact with the emitter region 22 and the body contact region 24.

第２金属膜５２は、第１金属膜５１の表面に配置されている。図２は、半導体装置１０の上面図を示している。図２では、図の見易さのため、第２金属膜５２より上側の構成の図示を省略している。また、図２では、第２金属膜５２が分布している範囲をハッチングにより示している。図２に示すように、第２金属膜５２は、第１金属膜５１の表面に達する複数の貫通孔７０を有している。複数の貫通孔７０は、ｘ方向及びｙ方向に等間隔で設けられている。また、ｘ方向に沿って設けられている貫通孔７０を１つの列としたときに、ｙ方向に沿って隣接する各列の貫通孔７０のｘ方向の位置が互い違いになるように各貫通孔７０が設けられている。各貫通孔７０は、平面視において、矩形状に形成されている。貫通孔７０の幅Ｌ（すなわち、長手方向の幅）は、例えば、２．６μｍ以下である。第２金属膜５２は、例えば、Ｔｉ（チタン）またはＴｉＮ（窒化チタン）を主成分とする金属膜である。第２金属膜５２の線膨張係数は、第１金属膜５１の線膨張係数よりも低い。また、第２金属膜５２の引張強度は、第１金属膜５１の引張強度よりも高い。なお、図２では、理解を容易にするために、図１に比較して貫通孔７０の縮尺が大きくなっている。このために、図１及び図２における貫通孔７０の数や幅等が異なっていることに留意されたい。   The second metal film 52 is disposed on the surface of the first metal film 51. FIG. 2 shows a top view of the semiconductor device 10. In FIG. 2, the upper side of the second metal film 52 is not shown for easy viewing. Further, in FIG. 2, the range in which the second metal film 52 is distributed is indicated by hatching. As shown in FIG. 2, the second metal film 52 has a plurality of through holes 70 reaching the surface of the first metal film 51. The plurality of through holes 70 are provided at equal intervals in the x direction and the y direction. In addition, when the through holes 70 provided along the x direction are one row, the through holes 70 in each row adjacent to each other along the y direction are alternately arranged in the x direction. 70 are provided. Each through hole 70 is formed in a rectangular shape in plan view. The width L (that is, the width in the longitudinal direction) of the through hole 70 is, for example, 2.6 μm or less. The second metal film 52 is, for example, a metal film containing Ti (titanium) or TiN (titanium nitride) as a main component. The linear expansion coefficient of the second metal film 52 is lower than the linear expansion coefficient of the first metal film 51. In addition, the tensile strength of the second metal film 52 is higher than the tensile strength of the first metal film 51. Note that, in FIG. 2, the scale of the through hole 70 is larger than that in FIG. 1 in order to facilitate understanding. For this purpose, it should be noted that the number, width, etc. of the through holes 70 in FIGS. 1 and 2 are different.

第３金属膜５３は、第２金属膜５２の表面に配置されている。また、第３金属膜５３は、貫通孔７０の内部において、第１金属膜５１に接している。第３金属膜５３は、第２金属膜５２の表面から貫通孔７０の内部に跨る範囲を覆っている。第３金属膜５３は、ＡｌＳｉを主成分とする金属膜である。第３金属膜５３の線膨張係数は、第２金属膜５２の線膨張係数よりも高い。第３金属膜５３の線膨張係数は、第１金属膜５１の線膨張係数と略等しい。したがって、第１金属膜５１と第３金属膜５３の線膨張係数の差は、第１金属膜５１と第２金属膜５２の線膨張係数の差よりも小さい。また、第１金属膜５１と第３金属膜５３の線膨張係数の差は、第２金属膜５２と第３金属膜５３の線膨張係数の差よりも小さい。また、第３金属膜５３の引張強度は、第２金属膜５２の引張強度よりも低い。第３金属膜５３の引張強度は、第１金属膜５１の引張強度と略等しい。   The third metal film 53 is disposed on the surface of the second metal film 52. In addition, the third metal film 53 is in contact with the first metal film 51 inside the through hole 70. The third metal film 53 covers a range extending from the surface of the second metal film 52 to the inside of the through hole 70. The third metal film 53 is a metal film containing AlSi as a main component. The linear expansion coefficient of the third metal film 53 is higher than the linear expansion coefficient of the second metal film 52. The linear expansion coefficient of the third metal film 53 is substantially equal to the linear expansion coefficient of the first metal film 51. Therefore, the difference between the linear expansion coefficients of the first metal film 51 and the third metal film 53 is smaller than the difference between the linear expansion coefficients of the first metal film 51 and the second metal film 52. Further, the difference between the linear expansion coefficients of the first metal film 51 and the third metal film 53 is smaller than the difference between the linear expansion coefficients of the second metal film 52 and the third metal film 53. Also, the tensile strength of the third metal film 53 is lower than the tensile strength of the second metal film 52. The tensile strength of the third metal film 53 is substantially equal to the tensile strength of the first metal film 51.

表面電極５０の外周部は、保護膜５６によって覆われている。保護膜５６は、例えば、ポリイミドによって構成されている。保護膜５６は、表面電極５０（すなわち、第３金属膜５３）に接している。表面電極５０の表面の中央部は、保護膜５６に覆われていない。   The outer peripheral portion of the surface electrode 50 is covered by a protective film 56. The protective film 56 is made of, for example, polyimide. The protective film 56 is in contact with the surface electrode 50 (that is, the third metal film 53). The central portion of the surface of the surface electrode 50 is not covered by the protective film 56.

保護膜５６の表面と表面電極５０の表面に跨る範囲は、はんだ接合用金属膜５８に覆われている。はんだ接合用金属膜５８は、はんだ濡れ性を有する金属により構成されている。はんだ接合用金属膜５８は、例えば、ニッケルを主成分とする金属膜である。はんだ接合用金属膜５８は、保護膜５６に覆われていない範囲の表面電極５０の表面全域を覆っている。はんだ接合用金属膜５８の表面は、はんだ層６０によって覆われている。はんだ接合用金属膜５８は、はんだ層６０によって、図示しない端子に接続されている。   A range extending over the surface of the protective film 56 and the surface of the surface electrode 50 is covered with the metal film 58 for solder bonding. The solder bonding metal film 58 is made of a metal having solder wettability. The solder bonding metal film 58 is, for example, a metal film containing nickel as a main component. The solder bonding metal film 58 covers the entire surface of the surface electrode 50 in a range not covered by the protective film 56. The surface of the solder bonding metal film 58 is covered by the solder layer 60. The solder bonding metal film 58 is connected to a terminal (not shown) by the solder layer 60.

半導体装置１０の動作中には、半導体装置１０の発熱や周囲の温度変化等によって、半導体装置１０全体の温度が繰り返し変化する。半導体装置１０を構成する各材料の線膨張係数が異なるので、温度変化時に各材料の膨張率が異なる。このため、半導体装置１０の内部に熱応力が加わる。表面電極５０を構成する各金属膜５１、５２、５３においては、第２金属膜５２の線膨張係数が相対的に低いため、第１金属膜５１及び第３金属膜５３に高い熱応力が加わる。特に、第２金属膜５２の引張強度が高いので、第２金属膜５２が変形し難く、第１金属膜５１及び第３金属膜５３に高い熱応力が加わる。表面電極５０として従来の構造（すなわち、貫通孔が形成されていない第２金属膜が設けられている構造）を採用すると、第１金属膜５１及び第３金属膜５３に繰り返し高い熱応力が加わることで、各金属膜５１、５３の内部に空洞が生じ易い。このような状態で表面電極５０にクラックが生じると、空洞を通じてクラックが進展しやすく、クラックが半導体基板１２まで達する場合がある。   During the operation of the semiconductor device 10, the temperature of the entire semiconductor device 10 changes repeatedly due to the heat generation of the semiconductor device 10, the temperature change of the surroundings, and the like. Since the coefficients of linear expansion of the respective materials constituting the semiconductor device 10 are different, the coefficients of expansion of the respective materials are different when the temperature changes. Therefore, thermal stress is applied to the inside of the semiconductor device 10. In each of the metal films 51, 52, and 53 constituting the surface electrode 50, high thermal stress is applied to the first metal film 51 and the third metal film 53 because the linear expansion coefficient of the second metal film 52 is relatively low. . In particular, since the tensile strength of the second metal film 52 is high, the second metal film 52 is not easily deformed, and high thermal stress is applied to the first metal film 51 and the third metal film 53. When a conventional structure (that is, a structure in which a second metal film without a through hole is provided) is adopted as the surface electrode 50, high thermal stress is repeatedly applied to the first metal film 51 and the third metal film 53. Thus, a cavity is likely to be generated inside each of the metal films 51, 53. When a crack is generated in the surface electrode 50 in such a state, the crack may easily progress through the cavity, and the crack may reach the semiconductor substrate 12.

これに対し、本実施例の半導体装置１０では、第２金属膜５２に貫通孔７０が設けられており、貫通孔７０内では、第１金属膜５１と第３金属膜５３が接している。第１金属膜５１と第３金属膜５３の線膨張係数の差は比較的小さい。このため、貫通孔７０の内部では、半導体装置１０の温度変化により第１金属膜５１及び第３金属膜５３に加わる熱応力が低減される。また、第２金属膜５２の一部に貫通孔７０が設けられているため、第２金属膜５２全体で熱応力が緩和される。したがって、表面電極５０に加わる熱応力が全体として低減される。このように、半導体装置１０では、温度変化が生じても、表面電極５０の内部に空洞が生じ難い。例えば、半導体装置１０では、表面電極５０（第３金属膜５３）と、保護膜５６と、はんだ接合用金属膜５８とが互いに接する三重接触部９０において高い熱応力が生じ易く、その位置を起点としてクラックが生じる場合がある。しかしながら、半導体装置１０によれば、表面電極５０の内部に空洞が生じることを抑制することができる。このため、仮に表面電極５０にクラックが生じたとしても、クラックが進展し難い。半導体装置１０によれば、表面電極５０のクラックによる特性劣化を抑制することができる。   On the other hand, in the semiconductor device 10 of the present embodiment, the through hole 70 is provided in the second metal film 52, and in the through hole 70, the first metal film 51 and the third metal film 53 are in contact. The difference between the linear expansion coefficients of the first metal film 51 and the third metal film 53 is relatively small. Therefore, the thermal stress applied to the first metal film 51 and the third metal film 53 due to the temperature change of the semiconductor device 10 is reduced inside the through hole 70. Further, since the through holes 70 are provided in a part of the second metal film 52, the thermal stress is relieved in the entire second metal film 52. Therefore, the thermal stress applied to the surface electrode 50 is reduced as a whole. As described above, in the semiconductor device 10, even if a temperature change occurs, a cavity is unlikely to be generated inside the surface electrode 50. For example, in the semiconductor device 10, high thermal stress is likely to occur at the triple contact portion 90 where the surface electrode 50 (third metal film 53), the protective film 56, and the solder bonding metal film 58 contact each other. As a crack may occur. However, according to the semiconductor device 10, the occurrence of a cavity in the surface electrode 50 can be suppressed. For this reason, even if the surface electrode 50 is cracked, the crack is unlikely to progress. According to the semiconductor device 10, the characteristic deterioration due to the crack of the surface electrode 50 can be suppressed.

なお、第３金属膜５３を成膜する際には、下地の材料によって第３金属膜５３（すなわち、ＡｌＳｉ）の結晶粒径が変化する。例えば、ＡｌＳｉを主成分とする第１金属膜５１上に第３金属膜５３を成膜したときの第３金属膜５３の結晶粒径は、ＴｉまたはＴｉＮを主成分とする第２金属膜５２上に第３金属膜５３を成膜したときの第３金属膜５３の結晶粒径よりも大きくなる。一般的に、結晶粒径が小さいほど、金属の強度は高くなる。本実施例の半導体装置１０では、貫通孔７０の幅Ｌが２．６μｍ以下となっている。このため、貫通孔７０内に配置される（すなわち、第１金属膜５１上に成膜される）第３金属膜５３の結晶粒径を２．６μｍ以下とすることができる。第３金属膜５３の結晶粒径が２．６μｍ以下であれば、半導体装置１０の温度変化による応力に対して、十分な０．２％耐力を得ることができる。   When the third metal film 53 is formed, the crystal grain size of the third metal film 53 (that is, AlSi) changes depending on the material of the base. For example, when the third metal film 53 is formed on the first metal film 51 containing AlSi as a main component, the crystal grain size of the third metal film 53 is the second metal film 52 containing Ti or TiN as a main component. The crystal grain size of the third metal film 53 when the third metal film 53 is formed thereon is larger than that of the third metal film 53. In general, the smaller the grain size, the higher the strength of the metal. In the semiconductor device 10 of the present embodiment, the width L of the through hole 70 is 2.6 μm or less. Therefore, the crystal grain size of the third metal film 53 disposed in the through hole 70 (that is, formed on the first metal film 51) can be set to 2.6 μm or less. When the crystal grain size of the third metal film 53 is 2.6 μm or less, a sufficient 0.2% proof stress can be obtained against the stress due to the temperature change of the semiconductor device 10.

上述した実施例の半導体装置１０では、図２に示すように、貫通孔７０が矩形状に形成されていた。しかしながら、貫通孔７０は、他の多角形状に形成されてもよいし、円形状に形成されてもよい。また、実施例の半導体装置１０では、複数の貫通孔７０のｘ方向の位置がｙ方向に沿って互い違いに設けられていた。しかしながら、貫通孔７０の位置は特に限定されず、例えば、第２金属膜５２が格子状となるように複数の貫通孔７０が設けられてもよい。   In the semiconductor device 10 of the embodiment described above, as shown in FIG. 2, the through hole 70 is formed in a rectangular shape. However, the through holes 70 may be formed in another polygonal shape or may be formed in a circular shape. In the semiconductor device 10 of the embodiment, the positions in the x direction of the plurality of through holes 70 are alternately provided along the y direction. However, the position of the through hole 70 is not particularly limited. For example, the plurality of through holes 70 may be provided such that the second metal film 52 has a lattice shape.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   As mentioned above, although the specific example of this invention was described in detail, these are only an illustration and do not limit a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the techniques illustrated in the present specification or the drawings simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

１０：半導体装置
１２：半導体基板
１２ａ：表面
１２ｂ：裏面
２２：エミッタ領域
２４：ボディコンタクト領域
２５：ボディ領域
２６：ドリフト領域
２７：コレクタ領域
３０：ゲート電極
３２：ゲート絶縁膜
５０：表面電極
５１：第１金属膜
５２：第２金属膜
５３：第３金属膜
５６：保護膜
５８：はんだ接合用金属膜
６０：はんだ層
６２：層間絶縁膜
６４：裏面電極
７０：貫通孔


10: semiconductor device 12: semiconductor substrate 12a: front surface 12b: back surface 22: emitter region 24: body contact region 25: body region 26: drift region 27: collector region 30: gate electrode 32: gate insulating film 50: surface electrode 51: First metal film 52: second metal film 53: third metal film 56: protective film 58: metal film for solder bonding 60: solder layer 62: interlayer insulating film 64: back surface electrode 70: through hole


Claims (1)

半導体装置であって、
半導体基板と、
前記半導体基板の表面を覆う表面電極、
を有し、
前記表面電極が、
前記半導体基板の前記表面を覆っている第１金属膜と、
前記第１金属膜の表面を覆っており、前記第１金属膜の前記表面に達する貫通孔を有しており、前記第１金属膜よりも低い線膨張係数を有する第２金属膜と、
前記第２金属膜の表面と前記貫通孔内の前記第１金属膜の前記表面を覆っており、前記第２金属膜よりも高い線膨張係数を有する第３金属膜、
を有しており、
前記第１金属膜と前記第３金属膜の線膨張係数の差は、前記第１金属膜と前記第２金属膜の線膨張係数の差及び前記第２金属膜と前記第３金属膜の線膨張係数の差よりも小さい、
半導体装置。

A semiconductor device,
A semiconductor substrate,
A surface electrode covering the surface of the semiconductor substrate,
Have
The surface electrode is
A first metal film covering the surface of the semiconductor substrate;
A second metal film covering a surface of the first metal film, having a through hole reaching the surface of the first metal film, and having a linear expansion coefficient lower than that of the first metal film;
A third metal film covering the surface of the second metal film and the surface of the first metal film in the through hole and having a linear expansion coefficient higher than that of the second metal film;
And have
The difference between the linear expansion coefficients of the first metal film and the third metal film is the difference between the linear expansion coefficients of the first metal film and the second metal film, and the line of the second metal film and the third metal film. Less than the difference in expansion coefficients,
Semiconductor device.

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7470070B2 (en) 2021-02-18 2024-04-17 株式会社東芝 Semiconductor Device

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JP2008028079A (en) * 2006-07-20 2008-02-07 Denso Corp Semiconductor device, and its manufacturing method
JP2014222742A (en) * 2013-05-14 2014-11-27 トヨタ自動車株式会社 Semiconductor device
JP2017152486A (en) * 2016-02-23 2017-08-31 株式会社デンソー Semiconductor device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
JP2008028079A (en) * 2006-07-20 2008-02-07 Denso Corp Semiconductor device, and its manufacturing method
JP2014222742A (en) * 2013-05-14 2014-11-27 トヨタ自動車株式会社 Semiconductor device
JP2017152486A (en) * 2016-02-23 2017-08-31 株式会社デンソー Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7470070B2 (en) 2021-02-18 2024-04-17 株式会社東芝 Semiconductor Device

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