JP2021093034A - Data processing apparatus, image reading device, image forming apparatus, and data processing method - Google Patents

Abstract

To provide a data processing control device that, when performing data processing based on a signal received from the outside, can prevent an adverse effect on the data processing even if noise is superimposed on the received data.SOLUTION: A data processing apparatus receives processing target data and an external clock from the outside and executes predetermined data processing on the processing target data, and comprises data processing control means that controls execution of data processing with an operation in accordance with a clock in a different line from the external clock, the clock being lower in impedance than the external clock. The data processing control means includes a clock state detection unit that notifies a result of detection of the state of the external clock, and an abnormality correction unit that, when the notification is one indicating an abnormality in the external clock, corrects an abnormality related to the processing target data occurring due to the abnormality in the external clock.SELECTED DRAWING: Figure 2

Description

The present invention relates to a data processing device, an image reading device, an image forming device, and a data processing method.

A data processing device that executes predetermined data processing on data to be processed received from an external device via a transmission line is known. The data processing device is mounted on various devices. For example, an image reading device such as a printer scanner is also equipped with the above data processing device, and receives data read by an image reading unit including an image sensor or the like via a transmission path and outputs the data as image data. Performs predetermined data processing for the purpose.

The data processing device receives, for example, a clock signal and a synchronization signal indicating a processing unit together with data from an image reading unit via a serial transmission line. If an abnormality occurs in the synchronization signal due to the influence of noise such as static electricity during transmission, normal data processing cannot be performed. Therefore, in the conventional data processing device, when an abnormality occurs in the synchronization signal due to an external factor during transmission, the data of the processing unit in which the abnormality occurs is discarded, and the remaining normal data is output to the subsequent device as a processing target. However, the processing in the subsequent device was stabilized (see Patent Document 1).

The technique disclosed in Patent Document 1 is based on the premise that the clock received via the serial transmission line is stable. Therefore, in the case of line synchronization when an abnormality occurs in the synchronization signal, the line in which the abnormality has occurred is discarded. Therefore, when the serial transmission clock is abnormal due to the influence of noise (when the PLL lock signal is released), the clock (post-stage clock) used for data processing cannot be generated. If the subsequent clock cannot be generated, the operation of discarding the line where the abnormality has occurred cannot be performed normally due to the malfunction of the abnormality detection circuit that detects the abnormality in the data processing, and the adverse effect on the output data cannot be suppressed. There is a problem.

An object of the present invention is to provide a data processing apparatus capable of suppressing an adverse effect on data processing even if data on which noise is superimposed is received when data processing is performed based on a signal received from the outside.

In order to solve the above technical problem, one aspect of the present invention is a data processing apparatus that receives processing target data and an external clock from the outside and executes predetermined data processing on the processing target data, and is the external. It is a clock of a system different from the clock, and includes data processing control means for controlling the execution of the data processing by operating with a clock having a lower impedance than the external clock, and the data processing control means is a state of the external clock. The clock state detection unit that notifies the result of detecting the above, and when the notification indicates an abnormality of the external clock, corrects the abnormality related to the data to be processed caused by the abnormality of the external clock. It is characterized by including an abnormality correction unit.

According to the present invention, when performing data processing based on a signal received from the outside, it is possible to suppress an adverse effect on the data processing even if the data on which noise is superimposed is received.

The block diagram which shows the example of the data processing system including the data processing apparatus which concerns on this invention. The block diagram which shows the embodiment of the data processing apparatus which concerns on this invention. The block diagram which shows another embodiment of the data processing apparatus which concerns on this invention. The block diagram which shows still another embodiment of the data processing apparatus which concerns on this invention. The block diagram which shows still another embodiment of the data processing apparatus which concerns on this invention. A timing chart showing an example of normal writing and reading operations of data to be processed in the embodiment of the above data processing apparatus. The timing chart which shows the example at the time of abnormality of the write operation and read operation of the data to be processed in the embodiment of the said data processing apparatus. The figure which shows typically the state of the data after processing by the said write operation and read operation. The block diagram which shows still another embodiment of the data processing apparatus which concerns on this invention. A timing chart showing an example of normal writing and reading operations of data to be processed in the embodiment of the above data processing apparatus. The timing chart which shows the example at the time of abnormality of the write operation and read operation of the data to be processed in the embodiment of the said data processing apparatus. The block diagram which shows the embodiment of the image reading apparatus which concerns on this invention. The block diagram which shows the embodiment of the image forming apparatus which concerns on this invention.

[Embodiment of Data Processing Device]
The data processing apparatus according to the present invention is mounted on an apparatus that performs predetermined data processing on data to be processed. For example, when it is mounted on an image reading device such as a scanner that optically reads an image formed on a storage medium and generates image data, it is arranged between an image reading unit and an image processing unit. When mounted on an image forming apparatus that forms an image on a recording medium, it is arranged between a data input unit that receives image data to be formed from an external device and an image forming unit or the like.

[Overall configuration of data processing system]
A schematic configuration of a data processing system 1 to which the data processing control device 10 according to the embodiment of the data processing device according to the present invention can be applied will be described. As shown in FIG. 1, the data processing system 1 is a system including a data processing control device 10, a data acquisition device 20, a data output device 30, and a transmission line 40.

The data acquisition device 20 includes a data acquisition unit 21 and a signal transmission unit 22, and for example, in the case of a scanner, the signal transmission unit 22 transmits the processing target data acquired by the data acquisition unit 21 corresponding to the image reading unit. It is converted into a data signal and transmitted to the data processing control device 10. The data processing control device 10 converts the data to be processed into a predetermined format and passes it to the data output device 30. The data output device 30 generates and outputs image data from the data to be processed.

For example, if the data processing system 1 is an image forming apparatus, the data output apparatus 30 corresponds to an image forming unit that executes an image forming process to form an image on a recording medium and discharge the image.

The transmission line 40 is composed of a cable (also referred to as a harness) in which a plurality of signal lines for transmitting a data signal or a clock signal from the data acquisition device 20 to the data processing control device 10 are bundled. The transmission impedance in the transmission line 40 is generally likely to be high, and noise is likely to be superimposed on a data signal or the like during transmission. Therefore, although the cable may be devised to suppress the influence of external noise, it is difficult to completely eliminate the influence of noise generated by sudden static electricity or the like. Therefore, the data processing control device 10 has decided to take noise countermeasures for the received data signal. The probability that the data signal will be affected by noise in the transmission line 40 increases as the signal line constituting the transmission line 40 becomes longer.

The data processing control device 10 includes a configuration for detecting an abnormality in a clock signal (external clock) transmitted together with data to be processed from an external device (data acquisition device 20 in FIG. 1). Then, when an abnormality in the external clock is detected, predetermined data processing is executed so that the data to be processed to be output to the subsequent device (data output device 30 in FIG. 1) can be output in the normal manner as much as possible. It has a configuration. For example, it is possible to perform a process (also referred to as a correction process) for complementing the abnormal data with the normal data, and control the data output device 30 to output the processing target data composed of the normal data. ..

The data processing control device 10 detects an abnormality in the external clock by using a clock generated by an OSC (electronic oscillator) 120 mounted on the same circuit board as the circuit board having a function of executing predetermined data processing. It is configured in. The OSC 120 is located on the same substrate as the circuit board on which the circuit constituting the data processing control means (data processing control unit) included in the data processing control device 10 is formed, and is arranged in the vicinity of the data processing control unit. ..

Therefore, since the transmission line length of the signal line for supplying the internal clock from the OSC 120 to the data processing control unit is shorter than that of the transmission line 40, the clock supplied from the OSC 120 is a clock obtained from the outside (external clock). It is a clock with a lower impedance than. Therefore, since the clock (internal clock) used by the data processing control unit for operation has a lower impedance than the external clock, it is less susceptible to noise such as static electricity than the external clock. That is, it can be said that the internal clock (OSC supply clock) in the data processing control device 10 is a clock of another system that does not become abnormal even if the external clock becomes abnormal.

When a low-impedance OSC supply clock is used as the operating clock of the data processing control means that detects an abnormality in the external clock and controls predetermined data processing, such as the data processing control device 10, the abnormal processing target data is processed. The operation of the correction circuit can be continued. That is, even if the data signal transmitted from the data acquisition device 20 is affected by noise, the data processing control device 10 can correct the data (abnormal data) in the noise-affected section and output it to the subsequent device. The adverse effect of noise on the output data can be suppressed.

[First Embodiment of Data Processing Control Device 10]
Next, the configuration of the data processing control device 10 which is the first embodiment of the data processing device according to the present invention will be described with reference to FIG. As shown in FIG. 2, the data processing control device 10 includes a receiving unit 101 for receiving a data signal from the data acquisition device 20, a data receiving processing unit 102, a data writing unit 103, a data storage unit 104, and data. It includes a reading unit 105, an unlocked detection unit 106, and a data reading signal generation unit 107.

The receiving unit 101 is a data receiving unit including a data processing unit 111 and a clock processing unit 112. The data processing unit 111 delivers the processing target data included in the data signal transmitted from the data acquisition device 20 to the subsequent circuit. Further, the clock processing unit 112 delivers the clock signal (external clock) included in the data signal transmitted from the data acquisition device 20 to the subsequent circuit. The "second-stage circuit" is a data reception processing unit 102 and a data writing unit 103, which constitute a data processing means for executing predetermined data processing on the data to be processed.

The data reception processing unit 102 uses the subsequent clock passed from the clock processing unit 112 to perform a process of dividing the data passed from the data processing unit 111 into predetermined units, and passes this to the data writing unit 103. I do. Here, the "predetermined unit" is formed based on a pixel-based unit such as a certain "pixel unit" or "line unit" when the processing target data is image data, or based on the data. A unit based on the length of the image to be created, and so on. Further, the data divided into predetermined units means that when the data to be processed is image data and the predetermined unit is "line unit", the data is divided into a plurality of line images constituting one image (plane). Line data ".

The data writing unit 103 generates a data writing side synchronization signal at predetermined unit intervals based on the subsequent clock from the clock processing unit 112, and based on this data writing side synchronization signal, the data writing side synchronization signal is used from the data receiving processing unit 102. The passed data to be processed is sequentially written to the data storage unit 104. Further, the data writing unit 103 passes the generated data writing side synchronization signal to the data reading signal generation unit 107.

The data storage unit 104 sequentially stores the passed data to be processed. Then, the processing target data stored in the data storage unit 104 is handed over to the data reading unit 105 based on the data reading side synchronization signal and output to the data output device 30.

The data reading unit 105 reads data from the data storage unit 104 based on the data reading side synchronization signal, and passes the read data to the data output device 30.

The unlock detection unit 106 operates based on the "OSC supply clock" supplied from the OSC 120, and detects the "unlock" of the lock signal related to the external clock passed from the clock processing unit 112. The unlock detection unit 106 passes the detection result (unlock detection signal) to the data read signal generation unit 107. The unlock detection unit 106 corresponds to a clock state detection unit.

The data read signal generation unit 107 generates a data read side synchronization signal and passes it to the data read unit 105. The data reading side synchronization signal is a synchronization signal generated by synchronizing the data writing side synchronization signal passed from the data writing unit 103 with the output clock (OSC supply clock) of the low impedance crystal oscillator (OSC120). .. The period during which the data read signal generation unit 107 passes the data read side synchronization signal to the data read unit 105 is a period that does not correspond to the "unlock period" in the unlock detection signal passed from the unlock detection unit 106.

As shown in FIG. 2, the unlock detection unit 106, the data read signal generation unit 107, and the data read unit 105, which constitute the data processing control means for detecting an abnormality in the external clock and executing predetermined data processing, are all included. It is a circuit that operates with a low-impedance OSC supply clock. Therefore, that is, the data processing control means according to the present embodiment can operate without being affected by noise due to static electricity or the like.

When the unlock detection unit 106 determines that the external clock is unlocked, the unlock detection signal is output so as to notify it. Further, the data read signal generation unit 107 generates a mask signal of the line memory: read side synchronization signal based on the unlock detection signal. At the timing when the "unlocked period" is set in this mask signal, the external clock is affected by noise. That is, the processing target data corresponding to this period may be abnormal data. Therefore, in order to prevent the data output device 30 from outputting the data to be processed that may be abnormal data, processing is performed so that the data is not read from the data storage unit 104.

As a result, if the data to be processed is, for example, image data, the image in which the abnormality has occurred can be discarded, and the influence of noise on the output image can be suppressed.

The OSC120 is exemplified by a crystal oscillator, but the OSC120 is not limited to this. For example, a combination of a crystal oscillator and an oscillating cell, a configuration such as a clock buffer, or the like may be used.

As described above, the data processing control device 10 according to the present embodiment outputs an unlock detection signal from the unlock detection unit 106 that operates using a clock having a lower impedance than the external clock. Further, the data read signal generation unit 107 generates a mask signal of the line memory: read side synchronization signal based on the unlock detection signal. When this mask signal indicates that the external clock is locked (the data to be processed is not affected by noise), the data read synchronization for reading the data to be processed from the data storage unit 104 Turn on the signal.

On the other hand, when the mask signal indicates that the external clock is not locked (the data to be processed may be abnormal due to the influence of noise), the data to be processed is stored as data. The data read synchronization signal for reading from unit 104 is turned off. By controlling the data reading process from the data storage unit 104 in this way, it is possible to suppress the output of abnormal data.

[Second Embodiment of Data Processing Control Device 10]
Next, the configuration of the data processing control device 10a, which is the second embodiment of the data processing device according to the present invention, will be described with reference to FIG. As shown in FIG. 3, the data processing control device 10a has many configurations similar to those of the data processing control device 10 already described. Hereinafter, the same configurations as those of the data processing control device 10 are designated by the same reference numerals, and detailed description thereof will be omitted. Since the data processing control device 10a includes a receiving unit 101a and a PLL unlock detection unit 106a as a configuration different from the data processing control device 10, these will be mainly described.

The receiving unit 101a includes an S / P processing unit 111a and a PLL unit 112a. Similar to the data processing control device 10 described above, the S / P processing unit 111a delivers the data included in the data signal transmitted from the signal transmission unit 22 to the subsequent circuit. Further, the PLL unit 112a generates an internal clock from the clock (external clock) included in the data signal transmitted from the signal transmission unit 22 as in the clock processing unit 112 already described, and uses this as the subsequent stage clock for the subsequent stage. Hand over to the circuit. Therefore, the PLL unit 112a constitutes an internal clock generation means.

When the data acquisition unit 21 (see FIG. 1) included in the data acquisition device 20 is an image sensor and is a data acquisition means for outputting multi-bit data, for example, when outputting 10-bit data for each of RGB, transmission is performed. The data transmitted on the road 40 is a 30-bit data signal. It is necessary to transmit this to the data processing control device 10a, and the receiving unit 101a needs to receive a 30-bit data signal.

When a 30-bit data signal is transmitted by a parallel transmission method, the number of signal line cables (harnesses) in the transmission line 40 increases, resulting in an increase in cost. In order to suppress this, a serial transmission method is used for the transmission of multi-bit data. In the case of the serial transmission method, the signal transmission unit 22 converts the data from parallel to serial and transmits the data. Therefore, in the reception unit 101a, the S / P processing unit 111a converts the serial data into parallel data, and the data is converted into parallel data in the subsequent stage. Hand over to the circuit of.

Further, the PLL unit 112a generates a latter-stage clock by using the clock included in the serial data and transmitted, and passes it to the subsequent-stage circuit. That is, the subsequent clock is generated by the PLL unit 112a based on the external clock from the data acquisition device 20. Further, when the external clock received from the signal transmission unit 22 is locked, the PLL unit 112a passes the lock signal to the PLL unlock detection unit 106a.

The unlock detection unit 106a detects the “unlock” of the PLL lock signal based on the PLL lock signal from the PLL unit 112a and the “OSC supply clock” supplied from the OSC 120. The unlock detection unit 106 passes the “unlock detection signal” indicating the detection result to the data read signal generation unit 107. The unlock detection unit 106a corresponds to a clock state detection unit.

The data read signal generation unit 107 generates a mask signal of the line memory: read side synchronization signal based on the “unlocked detection signal”. The mask signal indicates that the lock is released, and is a signal for controlling the data read-side synchronization signal.

The unlock detection unit 106a operates based on the OSC supply clock, which has a lower impedance than the external clock. Therefore, the operation of determining the PLL lock signal in the PLL lock release detection unit 106a is performed regardless of the influence of noise on the external clock. The same applies to the data read signal generation unit 107. Therefore, it is controlled so that only the normal data is output without outputting the portion where the data transmitted together with the external clock may contain abnormal data to the data output device 30. As a result, if the data to be processed is image data, the influence of noise on the output image can be reduced.

[Third Embodiment of the data processing control device 10]
Next, the configuration of the data processing control device 10b, which is the third embodiment of the data processing device according to the present invention, will be described with reference to FIG. In the description of the data processing control device 10b, detailed description of the same configurations as the data processing control device 10 and the data processing control device 10a already described will be omitted. Then, the data writing unit 103b, the data storage unit 104b, the line data reading unit 105b, and the data reading signal generating unit 107b, which have different configurations, will be mainly described.

The data writing unit 103b writes the divided data divided into line units by the data receiving processing unit 102 to the first line memory 1041 or the second line memory 1042 included in the data storage unit 104b.

The data storage unit 104b includes a first line memory 1041 and a second line memory 1042. The data storage unit 104b alternately stores the divided data passed from the data writing unit 103b in the first line memory 1041 and the second line memory 1042.

The line data reading unit 105b reads data from the first line memory 1041 and the second line memory 1042 based on the data reading side synchronization signal (line data reading side synchronization signal) from the data reading signal generation unit 107b, and obtains data. The read data is passed to the output device 30.

The data read signal generation unit 107b passes the line data read side synchronization signal, which is a synchronization signal obtained by synchronizing the data write side synchronization signal with the OSC supply clock, to the line data read unit 105b. The period during which the data read signal generation unit 107b passes the line data read side synchronization signal to the line data read side 105b is the "unlock period" in the mask signal of the line memory: read side synchronization signal generated by the data read signal generation unit 107b. It is a period that does not correspond to.

As described above, in the data processing control device 10b, the data reception processing unit 102 divides the data in "line units", and the data writing unit 103 writes and stores the "line data" in the data storage unit 104b. The line data reading unit 105b reads the line data. If the operation is simply to write / read the line data, it can be realized by delaying the timing of reading the line data from the start of writing the line data.

However, if the line data being written is affected by noise and contains abnormal data, the abnormal data written in the first line memory 1041 or the second line memory 1042 is read out, which causes this. Can no longer be avoided.

Therefore, in order to avoid reading data from the line memory in which abnormal data is generated, the line memory is configured to have a two-line configuration (first line memory 1041 and second line memory 1042). Then, the line for which the writing is completed is read out at a timing delayed by one line. Then, if there is an abnormality in the already written data, the process of reading is not performed and the line data in which the abnormality has occurred is discarded.

The data processing control device 10b detects an abnormality in the external clock using a low impedance clock, and sets the holding unit (division unit) of the data to be processed as a line unit. As a result, when there is a high possibility that an abnormality in the data transmitted from the signal transmission unit 22 is included, the data to be discarded can be set as a line unit. As a result, if the processing target data is image data, the processing for reducing the influence of noise on the output image can be simplified.

[Fourth Embodiment of Data Processing Control Device 10]
Next, the data processing control device 10c, which is the fourth embodiment of the data processing device according to the present invention, will be described with reference to FIG. The data processing control device 10c also has many configurations similar to those of the data processing control device 10, the data processing control device 10a, and the data processing control device 10b, which have already been described. An LVDS (Low voltage differential signaling) receiver 101c and a data writing unit 103c are provided as a configuration significantly different from the data processing control device 10b and the like. Hereinafter, these will be mainly described.

When the data acquisition unit 21 is an image sensor and a CCD (Charge Coupled Device) / AFE (Analog Front End) is used as the image reading element, the data included in the data signal transmitted from the signal transmission unit 22 includes the data included in the data signal. A synchronization signal indicating the start of one line is included. By using this synchronization signal, it is possible to execute the data writing operation of the data writing unit 103c and the line data reading operation of the line data reading unit 105b.

Further, the LVDS receiver 101c is a receiving circuit corresponding to data transmission by the LVDS method. The LVDS system is a differential signal system that uses two transmission lines 40, transmits two different voltages, and compares the two on the receiving side. By using the LVDS method, it is possible to reduce EMI (Electro-magnetic Interference).

[Flow of read operation and write operation during normal operation]
Next, the data writing unit 103 or the like included in the data processing control device 10 or the like writes the processing target data to the data storage unit 104 or the like, and the data reading unit 105 or the like writes the processing target data to the data storage unit 104 or the like. The operation of reading from is described. In the following description, the "writing operation" is referred to as a "write operation", and the "reading operation" is referred to as a "read operation". FIG. 3 is a timing chart showing the state of the write operation and the read operation in the normal state in which noise did not affect the transmission of the data to be processed.

Further, in the present specification, when the "predetermined data processing" (write operation and read operation) is described using the timing chart, the configuration of the data processing control device 10c is premised. Even with the configurations of the data processing control devices 10, 10a, and 10b already described, the operation flow is substantially the same. For example, there is a difference that the data storage unit 104b is a line memory and the data storage unit 104 does not limit the memory method, but in each case, the subsequent clock generated by the reception unit 101 (LVDS receiver 101c). The write operation is executed based on the data writing side synchronization signal generated based on. Further, by synchronizing with the clock from the OSC 120 (OSC supply clock), the read operation is executed based on the data read side synchronization signal generated from the data write side synchronization signal.

As described above, FIG. 6 is an example of a write operation and a read operation when noise is not superimposed on the data signal received from the data acquisition device 20.

FIG. 6A illustrates the data to be processed included in the data signal normally received continuously for a predetermined time in the LVDS receiver 101c.

FIG. 6B illustrates a data writing side synchronization signal generated by the data writing section 103c based on the subsequent clock output from the PLL section 112c of the LVDS receiver 101c.

FIG. 6C1 illustrates a PLL lock signal output from the PLL unit 112c of the LVDS receiver 101c. This PLL lock signal is output as "H" when the external clock is not unlocked (not affected by noise).

Further, FIG. 6 (c2) illustrates an unlock detection signal output from the PLL unlock detection unit 106a. This unlocked detection signal is a signal that detects the falling edge of the PLL lock signal and outputs "H". When the external clock is not unlocked (not affected by noise), it is output as "L".

FIG. 6D illustrates "line memory: mask signal of read-side synchronization signal" generated based on the unlock detection signal in the data read signal generation unit 107b. In the example of FIG. 6, since no abnormality has occurred in the received data signal, the unlock detection signal does not become “unlocked”. In this case, the "line memory: mask signal of the read side synchronization signal" is output as "L".

FIG. 6E illustrates a data read-side synchronization signal generated by synchronizing the data write-out side synchronization signal with the OSC supply clock in the data read-out signal generation unit 107b and passed to the line data read-out unit 105b. ..

FIG. 6F illustrates the timing of the write operation to the data storage unit 104b by the data writing synchronization signal. Here, since the data to be processed is divided by the data reception processing unit 102 at predetermined intervals, the writing operation is performed in this division unit. The data in the section where the data writing side synchronization signal corresponds to "A" is written to the first line memory 1041 as "data A". The data in the section where the data writing side synchronization signal corresponds to "B" is written as "data B" in the second line memory 1042. This light operation is performed alternately.

FIG. 6 (g) illustrates a line memory switching signal generated by the data read signal generation unit 107b. The line memory switching signal is composed of a write selection signal and a read selection signal that are inverted in synchronization with the data read side synchronization signal generated from the data write side synchronization signal synchronized with the OSC supply clock. The line data reading unit 105b alternately switches the read operation for the first line memory 1041 and the second line memory 1042 based on the line memory switching signal.

When in the unlocked state, the PLL lock signal negates. In the example of FIG. 6, since the unlocked state has not occurred, the PLL lock signal remains asserted. In this case, the unlock detection signal (FIG. 6 (c2)) output from the PLL unlock detection unit 106a remains negated. Further, the mask signal (FIG. 6D) of the line memory: read side synchronization signal generated by the data read signal generation unit 107b indicates “no unlocking”.

The data writing unit 103c first writes "data A" to the first line memory 1041 with reference to the data writing side synchronization signal. Subsequently, the line data reading unit 105b reads "data A" from the first line memory 1041 by the data reading signal in which the data reading signal generation unit 107b synchronizes the data writing side synchronization signal with the OSC supply clock. At the same time, the data writing unit 103 writes "data B" to the second line memory 1042 with reference to the data writing side synchronization signal. Subsequently, the data writing unit 103c writes "data C" to the first line memory 1041 with reference to the data writing side synchronization signal, and at the same time, the line data reading unit 105b writes "data B" from the second line memory 1042. Is read.

As described above, the external input data divided into predetermined units is alternately written to the first line memory 1041 and the second line memory 1042 by the write operation, and is read by the alternate read operation by the line data reading unit 105b. Then, the data is output to the data output device 30 in the subsequent stage in the normal order.

[Flow of read operation and write operation at the time of abnormality]
Next, with respect to the "write operation" and the "read operation" according to the present embodiment, a case where an abnormal process occurs due to the influence of noise on the data received from the outside will be illustrated.

In FIG. 7, it is assumed that the synchronization signal that distinguishes the section B and the section C of the data to be processed included in the data signal received from the data acquisition device 20 becomes abnormal due to the influence of noise. In this case, there is a possibility that both the "data B" in the section B and the "data C" in the section C are abnormal data.

In this case, a part of the PLL lock signal (PLL: lock signal) becomes "L", and the line data corresponding to the data B and the data C is unlocked in the PLL section 112a. In this case (abnormal data). It is necessary to correct the data to be processed in the range). Therefore, in the present embodiment, in order to correct the image data in the abnormal image range, the data writing side synchronization signal (line memory: write side synchronization signal) is internally inserted in the line where the lock of the PLL unit 112a is unlocked. Generate with. Then, the mask signal of the data read side synchronization signal (line memory: the mask signal of the read side synchronization signal) is asserted.

Then, the logical product (result of AND operation) of the mask signal inversion signal of the data read side write synchronization signal and the data read side signal (line memory: read side synchronization signal) is set to "line memory: read side synchronization signal (line memory). (For switching) ”.

In the present embodiment, by not switching the "line memory: read side synchronization signal (for line memory switching)", the normal data of the previous line is continuously read during the period when the PLL lock is released.

Here, the "normal data of the previous line" refers to the normal data corresponding to the processing unit at the previous timing in the division processing target data divided into the processing units that are continuous in chronological order. means.

In the present embodiment, "line memory: mask signal of read side synchronization signal" is asserted by falling edge detection from the PLL lock signal, and "line memory: read side synchronization signal (for line memory switching)" is asserted. The signal in which the PLL lock signal is synchronized with the clock on the memory writing side is monitored, and the PLL lock signal is negated with the signal synchronized with the clock on the memory writing side.

By executing the predetermined data processing as described above, the data processing control device 10 or the like according to the present embodiment corrects the data for the processing unit in which the processing target data (line data) is affected by noise. The process can be executed. The correction process here is a process of replacing the abnormal section by using the normal processing target data one line before.

That is, in the data processing control device 10d according to the present embodiment, the abnormality correction unit is configured by the data writing unit 103b, the data storage unit 104b, the line data reading unit 105b, the unlock detection unit 106a, and the data reading signal generation unit 107b. Will be done.

That is, in the data processing control device 10 or the like according to the present embodiment, even when the synchronization signal from the outside overlaps with the unlocking timing and disappears, it is possible to prevent the data processing control device 10 and the like from being unable to write to and read from the line memory. As an example, correction data is generated so that the processing target data in the abnormal section can be complemented with the normal processing target data. By setting the operating clock of the circuit that executes this generation process to be an internal clock that has a lower impedance than the external clock and is less susceptible to noise, correction data can be generated even if the influence of noise occurs.

[Example of image data processing when the PLL lock is released]
FIG. 8 schematically shows a state of data (image data) output as a result of the write operation and the read operation illustrated in FIG. 7.

The processing unit of the image data is a line unit, and a case where an abnormal image is included in a plurality of lines will be described. FIG. 8A shows the input data of the line memory, but since the data in the section B and the section C is in the unlocked period of the PLL signal, it is abnormal data.

An example of image data output by the read operation illustrated in the timing chart of FIG. 7 is illustrated in FIG. 8 (b). As shown in FIG. 8B, the section B that becomes the abnormal image is next to the normal data of the section A. In this case, the normal data (data A) of the previous section (section A) is used. , Complement section B. In this way, the data in the unlocked period is lost and cannot be restored, but the data to be processed can be corrected so that the total number of lines does not change, so that the adverse effect on the quality of the output data can be suppressed.

[Fifth Embodiment of Data Processing Control Device 10]
Next, the data processing control device 10d, which is the fifth embodiment of the data processing device according to the present invention, will be described with reference to FIG. The data processing control device 10d also has many configurations similar to those of the data processing control device 10, the data processing control device 10a, the data processing control device 10b, and the data processing control device 10c that have already been described. As a configuration significantly different from the data processing control device 10c and the like, there is a point that the line memory is increased to 4 lines in the data storage unit 104d. Further, the data processing control device 10d further includes an image data generation unit 108.

The data processing control device 10d can generate correction data from the line data before and after the abnormal line data in which the PLL lock is released.

The data processing control device 10d uses the data of the line memory (data storage unit 104d) as it is when indicating that the detection signal is locked in the detection signal output by the PLL unlock detection unit 106a.

When the detection result of the PLL unlock detection unit 106a indicates that the lock is unlocked, the image data generation unit 108 is controlled to generate and replace the line data in which the abnormality has occurred from the normal line data before and after. I do.

The line data corresponding to the section in which the abnormality has occurred is defined as "processing target data corresponding to the abnormality processing unit". In addition, the line data corresponding to the (normal) section in which no abnormality has occurred is defined as "processing target data corresponding to the normal processing unit". And "before and after line data" means one past processing unit and one future processing unit when a certain processing unit (a certain section) is the starting point in the processing units that are continuous in chronological order. means.

[Flow of normal read operation and write operation according to the fifth embodiment]
Next, the "write operation" and the "read operation" in the data processing control device 10d according to the fifth embodiment will be described with reference to FIGS. 10 and 11. The timing chart illustrated in FIG. 10 illustrates a case where normal processing is performed without the influence of noise on the data received from the outside.

As shown in FIG. 10, when the “PLL: lock signal” (PLL lock signal) does not come off, the processing target data (for example, image data) input from the outside is normal. In this case, the line memory of the line data is written with reference to the "line memory: sync signal on the write side" (synchronous signal on the data writing side).

Further, the selection (write selection) of the writing destination of the line memory is switched by the "line memory: write side synchronization signal", and the write operation is executed in order to the line memory having four lines.

Further, the line memory is read with reference to the "line memory: read-side synchronization signal" (data read-side synchronization signal). As a result, the line data is read out.

Further, the selection (read selection) of the read source of the line memory is switched by the "line memory: read side synchronization signal", and the read operation is sequentially performed on the line memory having four lines.

After the line memory write (write operation) is performed and two lines are delayed, the line memory read (read operation) is executed to output the processing target data (for example, image data).

[Flow of read operation and write operation at the time of abnormality according to the fifth embodiment]
Next, the "write operation" and the "read operation" at the time of abnormality in the data processing control device 10d according to the fifth embodiment will be described with reference to FIG. The timing chart illustrated in FIG. 11 illustrates a case where an abnormality process occurs due to the influence of noise or the like on the data received from the outside.

In FIG. 11, even if the “PLL: lock signal” is a part, the PLL unit 112a including the PLL circuit is unlocked at the timing of the data C section (line data C) in which the “L” is set. Indicates the state. In this case, the image corresponding to the line data C may become an abnormal image.

In this case, in order to correct the image data in the abnormal image range, the data processing control device 10 transmits "line memory: write side synchronization signal" on the line (line C) where the lock of the PLL unit 112a is unlocked. Generated internally. Then, "line memory: mask signal of read-side synchronization signal" is asserted. Then, the logical product (result of AND operation) of the inverted signal of "line memory: mask signal of read side synchronization signal" and "line memory: synchronization signal of read side" is converted into "line memory: read side synchronization signal (for line memory switching). ) ”.

Further, by not switching the "line memory: read side synchronization signal (for switching the line memory)", the normal data of the previous line is continuously read during the period when the PLL lock is released.

Then, "line memory: mask signal of read side synchronization signal" is asserted at the edge detection of the falling edge of "PLL: lock signal", and at the time of asserting "line memory: read side synchronization signal (for line memory switching)". Monitor the signal in which the "PLL: lock signal" is synchronized with the clock on the line memory read side. Further, the "PLL: lock signal" is negated by a signal synchronized with the clock on the line memory read side.

The "image data error flag" is a flag indicating that the data to be read is abnormal data, and is used by the image data generation unit 108. Since the data read after the output after the delay of 2 lines from the release of the PLL lock is an abnormal image, the image data error flag is also output at the same timing.

When the "image data error flag" is asserted, control is performed to switch to the output of the image data generation unit 108.

As shown in FIG. 10, the data processing control device 10d according to the present embodiment replaces the data before and after the abnormality occurrence line with the averaged data as a method of correcting the line data. FIG. 10 describes the case where an abnormality occurs within one line (within a period of one processing unit), but when an abnormality occurs within a plurality of lines (within a period spanning a plurality of processing units), the line It is possible to deal with this by increasing the memory.

By performing the read operation and the write operation as described above, the data processing control device 10d can reduce the influence of abnormal data by a simple correction method.

The above description of the write operation and the read operation is based on the data processing control device 10d provided with four line memories. As described above, substantially the same operation is possible in other embodiments (data processing control devices 10, 10a, 10b, 10c).

[Embodiment of image reader]
Next, an embodiment of the image reading device according to the present invention will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view showing a configuration example of the scanner device 200 according to the present embodiment. The scanner device 200 is a device mounted on an image forming device such as a digital copier, a digital multifunction device, or a facsimile device, or a single device, and is the above-mentioned data acquisition device 20, transmission path 40, and data processing control device 10. And, at least.

The scanner device 200 includes a contact glass 203 on which a document is placed on the upper surface. Further, the scanner device 200 includes a first carriage 211 including a light source 214 for exposing a document and a first reflection mirror 209, and a second carriage 206 including a second reflection mirror 207 and a third reflection mirror 208. Further, the scanner device 200 includes a lens unit 212 for forming an image of the light reflected by the third reflection mirror 208 on the light receiving region of the image sensor 213.

Further, the scanner device 200 also includes a reference member 204 having a reference density such as a reference white plate used for correcting various distortions due to a reading optical system and the like, and a sheet-through reading slit 205. The reference member 204 can be illuminated by the light source 214, and is provided at a position different from the contact glass 203 and the sheet-through reading slit 205, which are the document illumination positions.

The image sensor 213 can use the reflected light from either the document placed on the contact glass 203 or the document passing through the sheet-through reading slit 205 and the reference member 204 as incident light.

An ADF 200 is mounted on the upper portion of the scanner device 200, and the ADF 215 is connected to the contact glass 203 via a hinge or the like so that the contact glass 203 can be opened and closed. The ADF 215 includes a document tray 201 as a document mounting table on which a document bundle 210 composed of a plurality of documents can be placed. Further, the ADF 215 separates and feeds the originals one by one from the original bundle 210 placed on the original tray 201, and automatically feeds the originals toward the sheet-through reading slit 205, including the feeding roller 202. It also has a means of transportation.

Here, the operation of the scan mode in which the image surface of the document placed on the contact glass 203 is scanned (scanned) in the scanner device 200 having the above configuration to read the image of the document will be described.

In the scan mode, the first carriage 211 and the second carriage 206 are moved in the arrow A direction (secondary scanning direction) by the stepping motor to scan the document. At this time, the second carriage 206 moves at half the speed of the first carriage 211 in order to keep the optical path length from the contact glass 203 to the light receiving region of the image sensor 213 constant.

At the same time, the image surface, which is the lower surface of the document set on the contact glass 203, is illuminated (exposed) by the light source 214 of the first carriage 211. Then, the reflected light from the image plane is sequentially reflected by the first reflection mirror 209 of the first carriage 211, the second reflection mirror 207 of the second carriage 206, and the third reflection mirror 208. Then, the luminous flux reflected by the third reflection mirror 208 is focused by the lens unit 212 and imaged on the light receiving region of the image sensor 213.

The image sensor 213 outputs an analog electric signal obtained by photoelectrically converting the amount of light received by each pixel for each line. The electric signal is converted into a digital signal, the gain is adjusted, and the image data obtained by reading the image of the original is output. The image data is transmitted via the cable harness 216 to the substrate 217 including the data processing control device 10 and the like already described. When the cable harness 216 is long, the transmission impedance becomes high, so that it is easily affected by noise.

Next, the operation of the sheet-through mode in which the document is automatically fed by the ADF 215 and the image of the moving document is read will be described.

In this seat-through mode, the first carriage 211 and the second carriage 206 move to the lower side of the seat-through reading slit 205 and stop. After that, the lowermost document of the document bundle 210 placed on the document tray 201 is automatically fed by the feeding roller 202 in the arrow B direction (sub-scanning direction), and the position of the sheet-through reading slit 205 is adjusted. As it passes, the document is scanned.

At this time, the lower surface (image surface) of the automatically fed document is illuminated by the light source 214 of the first carriage 211. Then, the reflected light from the image plane is sequentially reflected by the first reflection mirror 209 of the first carriage 211, the second reflection mirror 207 of the second carriage 206, and the third reflection mirror 208. Then, the luminous flux reflected by the third reflection mirror 208 is focused by the lens unit 212 and imaged on the image sensor 213.

The image sensor 213 outputs an analog electric signal obtained by photoelectrically converting the amount of light received by each pixel for each line. The electric signal is converted into a digital signal, the gain is adjusted, and the image data obtained by reading the image of the original is output. The image data is transmitted via the cable harness 216 to the substrate 217 including the data processing control device 10 and the like already described. The original whose image has been read in this way is discharged to the discharge port.

Before reading the image in the scan mode or the sheet-through mode, the image sensor 213 reads the image by the reflected light from the reference member 204 illuminated by the lit light source 214. Then, shading correction data is generated and stored in the image sensor 213 so that the level of each pixel of the image data for one line becomes a uniform predetermined level. After that, when the image of the original is read, the image data read by the image sensor 213 is subjected to shading correction based on the shading correction data previously stored. Further, when the ADF 215 is provided with a transport belt, the ADF 215 can automatically feed the original to the reading position on the contact glass 203 and read the image of the original even in the scan mode.

[Embodiment of image forming apparatus]
Next, an embodiment of the image forming apparatus according to the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing a configuration example of the MFP (Multi-Function Peripheral) 300 according to the present embodiment. The MFP 300 includes at least the above-mentioned data acquisition device 20, the transmission line 40, and the data processing control device 10.

The MFP 300 includes a scanner device 200 described above, a paper feeding unit 302, and an image forming unit 303. The paper feed unit 302 is provided from a paper feed cassette 321 and 322 for storing recording papers having different paper sizes and various rollers for transporting the recording paper stored in the paper feed cassettes 321 and 322 to the image formation position of the image forming unit 303. It has a paper feeding means 323 and the like. The image forming unit 303 includes an exposure device 331, a photoconductor drum 332, a developing device 333, a transfer belt 334, and a fixing device 335.

The image forming unit 303 exposes the photoconductor drum 332 with the exposure device 331 to form a latent image on the photoconductor drum 332 based on the image data of the document read by the image reading unit inside the ADF 215, and forms a latent image on the photoconductor drum 332. Therefore, toners of different colors are supplied to the photoconductor drum 332 for development.

Then, the image forming unit 303 transfers the image developed on the photoconductor drum 332 by the transfer belt 334 to the recording paper supplied from the paper feeding unit 302, and then transfers the toner image transferred to the recording paper by the fixing device 335. The toner is melted to fix the color image on the recording paper.

The MFP 300 has a function of processing the image data read by the scanner device 200 in the image forming unit 303, forming an image on a recording medium, and discharging the image data. Therefore, the data processing control device 10 described above can be applied to the MFP 300, whereby a good image can be obtained.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical gist thereof, and the technical concept included in the claims is included in the technical concept. All of the matters are the subject of the present invention. Although the above embodiment shows a suitable example, those skilled in the art can realize various modified examples from the disclosed contents. Such modifications are also included in the technical scope described in the claims.

1: Data processing system 10, 10a, 10b, 10c, 10d: Data processing control device 20: Data acquisition device 21: Data acquisition unit 22: Signal transmission unit 30: Data output device 40: Transmission path 101, 101a: Reception unit 101c : LVDS receiver 102: Data reception processing unit 103, 103b, 103c: Data writing unit 104, 104b, 104d: Data storage unit 105, 105b: Line data reading unit 106, 106a: Detection unit 107, 107b: Data reading signal generation Unit 108: Image data generation unit 111: Data processing unit 111a: S / P processing unit 112: Clock processing unit 112a, 112c: PLL unit 200: Scanner device 201: Document tray 202: Feeding roller 203: Contact glass 204: Reference Member 205: Sheet-through reading slit 206: Second carriage 207: Second reflection mirror 208: Third reflection mirror 209: First reflection mirror 210: Document bundle 211: First carriage 212: Lens unit 213: Image pickup element 214: Light source 216: Cable harness 217: Board 300: MFP
302: Paper feed unit 303: Image forming unit 321 and 322: Paper feed cassette 323: Paper feed means 331: Exposure device 332: Photoreceptor drum 333: Developing device 334: Transfer belt 335: Fixing device 1041: First line memory 1042 : Second line memory

Patent No. 6049554

Claims (13)

A data processing device that receives processing target data and an external clock from the outside and executes predetermined data processing on the processing target data.
It is provided with a data processing control means that controls the execution of the data processing by operating with a clock having a lower impedance than the external clock, which is a clock of a system different from the external clock.
The data processing control means
A clock state detection unit that notifies the result of detecting the state of the external clock, and
When the notification indicates an abnormality of the external clock, the abnormality correction unit for correcting the abnormality related to the data to be processed caused by the abnormality of the external clock is included.
A data processing device characterized by the fact that. The low impedance clock is generated on the same circuit board as the circuit board on which the circuit constituting the data processing control means is formed.
The data processing device according to claim 1. It has an internal clock generating means including a PLL circuit that generates an internal clock used for the operation of the data processing control means from the external clock.
The clock state detection unit detects an abnormality in the external clock based on the PLL lock signal output by the PLL circuit.
The data processing apparatus according to claim 1 or 2. The processing unit of the data to be processed is a line unit.
The abnormality correction unit corrects the processing target data on a line-by-line basis.
The data processing device according to any one of claims 1 to 3. The processing target data includes a synchronization signal that defines the processing unit.
The data processing device according to claim 4. The LVDS receiver for receiving the processing target data transmitted by the LVDS method is provided.
Performs predetermined data processing on the processing target data received by the LVDS receiver.
The data processing device according to any one of claims 1 to 5. The abnormality correction unit is a processing unit that is continuous with the processing unit when the external clock is abnormal with respect to the processing target data corresponding to the abnormality processing unit which is the processing unit when the external clock is abnormal. Based on the processing target data corresponding to the normal processing unit which is the processing unit when the external clock is normal, the correction data for correcting the processing target data corresponding to the abnormal processing unit is generated.
The data processing device according to any one of claims 1 to 6. The abnormality correction unit corrects the processing target data corresponding to the abnormality processing unit based on the normal processing target data corresponding to the past processing units that are continuous in time series with the abnormality processing unit. Generate,
The data processing device according to claim 7. The abnormality correction unit includes normal processing target data corresponding to past processing units that are time-series continuous with the abnormality processing unit, and normal processing units that correspond to future processing units that are time-series continuous with the abnormality processing unit. To generate correction data that corrects the processing target data corresponding to the abnormal processing unit, based on the averaged data of the processing target data.
The data processing device according to claim 7. The processing target data is image data.
The data processing device according to any one of claims 1 to 9. Data processing in a data processing apparatus including a data processing means for executing predetermined data processing on the processing target data by using the external clock included in the data signal for the processing target data included in the data signal received from the outside. It ’s a method,
A data processing control means provided in the data processing apparatus and operating with a clock having a lower impedance than the external clock is provided.
Detects the state of the external clock and
When an abnormality of the external clock is detected, the processing target data received during the period when the abnormality of the external clock is detected is discarded.
A data processing method characterized by that. A data acquisition device that transmits optically read image data together with a clock signal, receives the image data and the clock signal from the data acquisition device, and uses the clock signal to perform predetermined data processing on the image data. An image reader having a data processing device to execute,
The image reading device according to any one of claims 1 to 10, wherein the data processing device is the data processing device. An image forming apparatus that forms an image on a recording medium and outputs it using the data processed by a data processing apparatus that executes predetermined data processing on the processing target data input from the outside.
The image forming apparatus according to any one of claims 1 to 10, wherein the data processing apparatus is the data processing apparatus.

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