JP2021092394A - A/d conversion circuit - Google Patents

Abstract

To provide an A/D conversion circuit that performs accurate temperature measurement in all temperature bands.SOLUTION: An A/D conversion circuit includes a plurality of first inverters, a clock circuit that generates a clock signal, a plurality of second inverters and a delay signal generation circuit that generates a delay signal having a change amount depending on a change in physical quantity to be measured. A gate length of a transistor provided by the plurality of second inverters is longer than a gate length of a transistor provided by the plurality of first inverters. The A/D conversion circuit includes a delay time measurement circuit to which the clock signal and the delay signal are input and which measures the change amount in the delay signal based on the number of clocks in the clock signal. The A/D conversion circuit includes a first timing control circuit that controls a start-timing of the clock circuit so that a measured value of the number of clocks is proportional to the change in the physical quantity, or controls a transmission timing of the delay signal output by the delay signal generation circuit to the delay time measurement circuit.SELECTED DRAWING: Figure 1

Description

The techniques disclosed herein relate to A / D conversion circuits.

A temperature sensor circuit including a clock circuit that generates a clock signal and a delay circuit that generates a delay signal that changes depending on the temperature is known. In such a temperature sensor circuit, the temperature dependence of the delay signal is set higher than the temperature dependence of the clock signal. That is, the ratio of the amount of change in the delay time of the signal when the temperature changes is larger in the delay signal than in the clock signal. Temperature information can be obtained by measuring the fluctuation of the pulse width of the delay signal using the clock signal. In addition, an example of a related technique is disclosed in Patent Documents 1 and 2.

Japanese Unexamined Patent Publication No. 2007-187695 JP-A-2009-236603

The temperature sensor circuit is required to have a proportional relationship (that is, high linearity) in the measured values of the number of clocks with respect to the temperature change. However, there may be a temperature zone (eg, high temperature region, low temperature region) in which non-linearity is remarkably generated. It becomes difficult to perform accurate temperature measurement in all temperature bands.

The A / D conversion circuit disclosed in the present specification includes a ring oscillator in which a plurality of first inverters are connected in a ring shape, and includes a clock circuit that generates a clock signal. The A / D conversion circuit includes an inverter chain in which a plurality of second inverters are connected in series, and includes a delay signal generation circuit that generates a delay signal having a change amount depending on a change in a physical quantity to be measured. The gate length of the transistor included in the plurality of second inverters is larger than the gate length of the transistor included in the plurality of first inverters. The A / D conversion circuit includes a delay time measuring circuit in which a clock signal and a delay signal are input and the amount of change in the delay signal is measured based on the number of clocks of the clock signal. The A / D conversion circuit controls the start timing of the clock circuit so that the measured values of the number of clocks are proportional to the change in the physical quantity, or the delay signal output by the delay signal generation circuit is transferred to the delay time measurement circuit. A first timing control circuit for controlling the transmission timing is provided.

As long as there is a non-linearity in which the measured value of the number of clocks is smaller (or larger) than the theoretical value of the number of clocks corresponding to the actual physical quantity, the first timing control circuit accelerates the start timing of the clock circuit ( Or slower) can be controlled. Alternatively, the first timing control circuit can control the transmission timing of the delay signal to the delay time measurement circuit later (or earlier). As a result, the measured value of the number of clocks can be increased (or decreased), so that the measured value of the number of clocks can be brought closer to the theoretical value. It is possible to put the measured value of the number of clocks in a proportional relationship with the change of the physical quantity (a state of high linearity).

The first timing control circuit may be a circuit that controls the start timing of the clock circuit. The first timing control circuit includes a first delay circuit in which a first predetermined number of first inverters are connected in series and a second delay circuit in which a second predetermined number of second inverters are connected in series. You may have it. The first delay circuit may output a first start signal having a delay time that increases proportionally with a positive first slope with respect to an increase in the physical quantity. The second delay circuit may output a second start signal having a delay time that increases proportionally with a positive second slope with respect to an increase in the physical quantity. The first start signal and the second start signal may be signals for instructing the start of generation of the clock signal and the delay signal. The second slope may be larger than the first slope. The first start signal may be input to the delay signal generation circuit. Either one of the first start signal and the second start signal may be input to the clock circuit. Details of the effect will be described in Examples.

In the first region where the physical quantity is smaller than the first threshold value, which is the intersection of the straight line having the first slope and the straight line having the second slope, the second start signal has a delay time longer than the first start signal. May be small. In the second region where the physical quantity is larger than the first threshold value, the delay time of the first start signal may be smaller than that of the second start signal. In the first region, when the measured value of the number of clocks is smaller than the value corresponding to the actual physical quantity, the second start signal is input to the clock circuit in the first region, and the first start signal is clocked in the second region. It may be input to the circuit. When the measured value of the number of clocks is larger than the value corresponding to the actual physical quantity in the first region, the first start signal may be input to the clock circuit in the first region. Details of the effect will be described in Examples.

A second timing control circuit that controls the start timing of the clock circuit may be further provided. The second timing control circuit includes a third delay circuit in which a third predetermined number of first inverters are connected in series and a fourth delay circuit in which a fourth predetermined number of second inverters are connected in series. You may have it. The third delay circuit may output a third start signal having a delay time that increases proportionally with a positive third slope with respect to an increase in the physical quantity. The fourth delay circuit may output a fourth start signal having a delay time that increases proportionally with a positive fourth slope with respect to an increase in the physical quantity. The third start signal and the fourth start signal may be signals for instructing the start of generation of the clock signal and the delay signal. The fourth slope may be larger than the third slope. The second threshold value, which is the intersection of the straight line having the third inclination and the straight line having the fourth inclination, may be larger than the first threshold value. The second region may be a region in which the physical quantity is larger than the first threshold value and the physical quantity is smaller than the second threshold value. In the second region, the fourth start signal may have a smaller delay time than the third start signal. In the third region where the physical quantity is larger than the second threshold value, the delay time of the third start signal may be smaller than that of the fourth start signal. In the third region, when the measured value of the number of clocks is smaller than the value corresponding to the actual physical quantity, the first start signal or the fourth start signal is input to the clock circuit in the second region, and the third region is the third. 3 The start signal may be input to the clock circuit. In the third region, when the measured value of the number of clocks is larger than the value corresponding to the actual physical quantity, the second start signal or the third start signal is input to the clock circuit in the second region, and the third region is the third. 4 The start signal may be input to the clock circuit. Details of the effect will be described in Examples.

The first threshold value may be set by the ratio of the first predetermined number to the second predetermined number. The first inclination may increase as the value of the first predetermined number increases. The second slope may become larger as the value of the second predetermined number is increased.

The first delay circuit counts the ring oscillator provided with a plurality of first inverters and the output pulses of the ring oscillator, and outputs a first start signal according to the count value becoming a predetermined first predetermined value. The first counter may be provided. The second delay circuit counts the ring oscillator provided with a plurality of second inverters and the output pulses of the ring oscillator, and outputs a second start signal according to the count value becoming a predetermined second predetermined value. A second counter may be provided. Details of the effect will be described in Examples.

The first timing control circuit may be a circuit that controls the transmission timing of the delay signal to the delay time measurement circuit. The first timing control circuit includes a first delay circuit in which a first predetermined number of first inverters are connected in series and a second delay circuit in which a second predetermined number of second inverters are connected in series. You may have it. A delay signal output from the delay signal generation circuit may be input to the first delay circuit and the second delay circuit. The first delay circuit may output a first specific delay signal in which a delay time that increases proportionally with a positive first slope with respect to an increase in physical quantity is added to the delay signal. The second delay circuit may output a second specific delay signal in which a delay time that increases proportionally with a positive second slope with respect to an increase in the physical quantity is added to the delay signal. The second slope may be larger than the first slope. Either one of the first specific delay signal and the second specific delay signal may be input to the delay time measurement circuit. Details of the effect will be described in Examples.

It is a block diagram which shows the outline of a temperature sensor circuit. It is a figure which shows the circuit structure of the compensation circuit 20. It is a waveform diagram explaining the operation of a temperature sensor circuit. It is a graph explaining the non-linearity of temperature measurement. It is a graph which shows the relationship between the delay time generated by the 1st timing control circuit 21 and temperature. It is a graph which shows the relationship between the delay time generated by the 2nd timing control circuit 22 and the temperature. It is a waveform diagram of various signals output from a 1st timing control circuit 21 and a compensation circuit 20. FIG. 5 is a waveform diagram of various signals output from the second timing control circuit 22 and the compensation circuit 20. It is a graph explaining the non-linearity of the temperature measurement which concerns on Example 2. FIG. It is a figure which shows the temperature sensor circuit 1b which concerns on Example 3. FIG. It is a figure which shows the circuit structure of the 1st delay circuit DC1c which concerns on Example 5. It is a figure which shows the circuit structure of the temperature sensor circuit 1d which concerns on Example 6.

(Structure of temperature sensor circuit 1)
FIG. 1 shows a temperature sensor circuit 1 according to this embodiment. The temperature sensor circuit 1 is an example of an A / D conversion circuit that converts a temperature, which is a physical quantity, into a digital value. The temperature sensor circuit 1 is a one-chip circuit, and includes a compensation circuit 20, a clock circuit 30, a delay signal generation circuit 40, and a delay time measurement circuit 50.

The compensation circuit 20 receives a start signal SS and outputs drive start signals DS1 and DS2. The drive start signal DS1 is a signal instructing the delay signal generation circuit 40 to start generating the delay signal DLS. The drive start signal DS2 is a signal instructing the clock circuit 30 to start generating the clock signal CLK. The details of the compensation circuit 20 will be described later.

The clock circuit 30 is a circuit that generates a clock signal CLK. The clock signal CLK is, for example, a rectangular wave having a duty ratio of 50%. The clock circuit 30 is composed of a ring oscillator in which an odd number of first inverters INV1 are connected in a ring shape.

The delay signal generation circuit 40 includes a pulse generation circuit 41 and a delay circuit 42. The drive start signal DS2 is input to the pulse generation circuit 41. The pulse generation circuit 41 is a circuit that generates a low frequency signal LS. The low frequency signal LS is a signal having a sufficiently lower frequency than the clock signal CLK. The low frequency signal LS may be generated, for example, by reducing the frequency of the clock signal CLK to 1/1024 times or 2048 times.

The delay circuit 42 is a circuit that generates a delay signal DLS that delays the low frequency signal LS. The delay signal DLS is a signal that changes depending on the temperature, which is a physical quantity to be measured. The delay circuit 42 is composed of an inverter chain in which even-numbered second inverters INV2 are connected in series. The gate length of the transistor included in the second inverter INV2 of the delay signal generation circuit 40 is larger than the gate length of the transistor included in the first inverter of the clock circuit 30.

The delay time measurement circuit 50 is a circuit that measures the time difference between the low frequency signal LS and the delay signal DLS (corresponding to the delay time of the delay signal DLS) based on the number of clocks of the clock signal CLK. Further, the delay time measurement circuit 50 is configured to convert the measured number of clocks into digital temperature information Dout and output it.

(Circuit configuration of compensation circuit 20)
FIG. 2 shows the circuit configuration of the compensation circuit 20. The compensation circuit 20 includes a first timing control circuit 21, a second timing control circuit 22, and an output selection circuit 23. The first timing control circuit 21 includes a first delay circuit DC1, a second delay circuit DC2, and an or circuit OR1. The first delay circuit DC1 has a configuration in which a first inverter INV1 having a first predetermined number K1 (K1 is a natural number of 2 or more) is connected in series. That is, the first delay circuit DC1 is composed of transistors having the same gate length as the clock circuit 30. The start signal SS is input to the first delay circuit DC1, and the first start signal SSD1 is output. The first start signal SSD1 is a signal in which the delay time DT1 is added to the start signal SS. The first start signal SSD1 is input to the D terminal of the flip-flop FF of the output selection circuit 23 and the or circuit OR1.

The second delay circuit DC2 has a configuration in which a second inverter INV2 having a second predetermined number K2 (K2 is a natural number of 2 or more) is connected in series. That is, the second delay circuit DC2 is composed of transistors having the same gate length as the delay circuit 42. The start signal SS is input to the second delay circuit DC2, and the second start signal SSD2 is output. The second start signal SSD2 is a signal in which the delay time DT2 is added to the start signal SS. The second start signal SSD2 is input to the or circuit OR1.

From the or circuit OR1, the signal of the first input signal SSD1 and the second start signal SSD2 (that is, the one having the faster rising edge) is output. The output of the or circuit OR1 is input to the CLK terminal of the flip-flop FF of the output selection circuit 23.

The second timing control circuit 22 includes a third delay circuit DC3, a fourth delay circuit DC4, and an or circuit OR2. The third delay circuit DC3 has a configuration in which the first inverter INV1 of the third predetermined number K3 (K3 is a natural number of 2 or more) is connected in series. The start signal SS is input to the third delay circuit DC3, and the third start signal SSD3 is output. The third start signal SSD3 is a signal in which the delay time DT3 is added to the start signal SS. The third start signal SSD3 is input to the or circuit OR2. The fourth delay circuit DC4 has a configuration in which a second inverter INV2 having a fourth predetermined number K4 (K4 is a natural number of 2 or more) is connected in series. The start signal SS is input to the fourth delay circuit DC4, and the fourth start signal SSD4 is output. The fourth start signal SSD4 is a signal in which the delay time DT4 is added to the start signal SS. The fourth start signal SSD4 is input to the output selection circuit 23 and the or circuit OR2. From the or circuit OR2, of the third start signal SSD3 and the fourth start signal SSD4, whichever is input earlier is output. The output of the or circuit OR2 is input to the output selection circuit 23.

The output selection circuit 23 includes a flip-flop FF, AND circuits AD1 to AD4, or circuits OR3 and OR4. The output terminal nQ is connected to the AND circuits AD1 and AD3. The output terminal Q is connected to the AND circuits AD2 and AD4. The output signal of the or circuit OR1 and the first start signal SSD1 are input to each of the AND circuits AD1 and AD3. The output signal of the or circuit OR2 and the fourth start signal SSD4 are input to each of the AND circuits AD2 and AD4. The output signals of the AND circuits AD1 and AD2 are input to the or circuit OR3, and the drive start signal DS2 is output. The output signals of the AND circuits AD3 and AD4 are input to the or circuit OR4, and the drive start signal DS1 is output.

The flip-flop FF is a circuit that switches at the first threshold temperature T1. In a region lower than the first threshold temperature T1 described later in FIG. 5, the output of the output terminal Q becomes a low level, and the output of the output terminal nQ becomes a high level. Therefore, the AND circuits AD1 and AD3 become active, and the first timing control circuit 21 is selected. As a result, the output signal of the or circuit OR1 is selected as the drive start signal DS2, and the first start signal SSD1 is selected as the drive start signal DS1. On the other hand, in a region higher than the first threshold temperature T1, the output of the output terminal Q becomes a high level and the output of the output terminal nQ becomes a low level. Therefore, the AND circuits AD2 and AD4 become active, and the second timing control circuit 22 is selected. As a result, the output signal of the or circuit OR2 is selected as the drive start signal DS2, and the fourth start signal SSD4 is selected as the drive start signal DS1.

(Explanation of temperature measurement principle and non-linearity)
The operation of the temperature sensor circuit 1 will be specifically described with reference to the waveform diagrams of FIGS. 3 (A) and 3 (B). 3A and 3B are waveform diagrams of various signals input to the delay time measurement circuit 50. When the rising edge of the low frequency signal LS is detected at time tt1, the count of the clock signal CLK is started. When the rising edge of the delay signal DLS is detected at time tt2, the counting of the clock signal CLK ends. As described above, the gate length of the transistor of the second inverter INV2 of the delay circuit 42 is larger than the gate length of the transistor of the first inverter INV1 of the clock circuit 30. Therefore, the amount of change in the signal delay time when the temperature changes is larger in the delay signal DLS than in the clock signal CLK.

Therefore, as shown in FIG. 3A, at a relatively low temperature, the number of clocks of the clock signal CLK measured by the delay time DD1 of the delay signal DLS is “6”. On the other hand, as shown in FIG. 3B, at a relatively high temperature, the number of clocks of the clock signal CLK measured by the delay time DD2 of the delay signal DLS is “9”. If the temperature-dependent characteristics of the clock signal CLK and the temperature-dependent characteristics of the delay signal DLS are different in this way, the number of clocks measured by the delay time measuring circuit 5 fluctuates with respect to the temperature. As a result, the temperature information Dout of the digital value can be obtained.

The non-linearity of temperature measurement will be described with reference to FIG. In FIG. 4, the horizontal axis is the temperature and the vertical axis is the temperature information Dout (that is, the number of clock counts). The temperature information Dout is an arbitrary unit (a.u.). As shown in the ideal straight line IL (dotted line) in FIG. 4, it is required that the measured values of the number of clocks for the entire temperature range from the minimum temperature Tmin to the maximum temperature Tmax are in a proportional relationship (that is, high linearity). To. However, in reality, non-linearity may occur due to the difference in temperature characteristics between the clock circuit 30 and the delay circuit 42 described above. As an example of non-linearity, a characteristic graph CG (solid line) is shown. In the example of the characteristic graph CG, the measured value of the number of clocks becomes smaller than the value corresponding to the actual temperature in the low temperature region RL on the lower temperature side than the boundary temperature TL and the high temperature region RH on the higher temperature side than the boundary temperature TH. There is. In FIG. 4, the low temperature region RL and the high temperature region RH are shaded for clarity. The region between the low temperature region RL and the high temperature region RH is defined as the intermediate temperature region RM.

(Setting of the first timing control circuit 21)
FIG. 5 shows the relationship between the delay time generated by the first timing control circuit 21 and the temperature. The horizontal axis is the temperature and the vertical axis is the delay time. Let DT1 be the delay time generated by the first delay circuit DC1. Let DT2 be the delay time generated by the second delay circuit DC2. Each of the delay times DT1 and DT2 increases proportionally with the increase in temperature with a positive first slope SL1 and a second slope SL2. The second inclination SL2 is larger than the first inclination SL1. That is, the delay time DT2 changes more significantly than the delay time DT1 with respect to the temperature change. This is a phenomenon that occurs because the gate length of the first inverter INV1 of the first delay circuit DC1 is smaller than the gate length of the second inverter INV2 of the second delay circuit DC2.

The temperature at the intersection of the straight line having the first slope SL1 and the straight line having the second slope SL2 is defined as the first threshold temperature T1. In the first temperature region R1 where the temperature is lower than the first threshold temperature T1, the delay time DT2 is smaller than the delay time DT1. On the other hand, in the second temperature region R2 where the temperature is higher than the first threshold temperature T1, the delay time DT1 is smaller than the delay time DT2.

The value of the first threshold temperature T1 can be set by the ratio of the first predetermined number K1 (the number of the first inverter INV1) and the second predetermined number K2 (the number of the second inverter INV2). In the present embodiment, the first threshold temperature T1 is set in the vicinity of the boundary temperature TL (FIG. 4) by appropriately determining the ratio of the first predetermined number K1 and the second predetermined number K2. Further, the first temperature region R1 is set so as to substantially overlap the low temperature region RL.

The first inclination SL1 can be increased as the value of the first predetermined number K1 is increased. The second inclination SL2 can be increased as the value of the second predetermined number K2 is increased. Therefore, by increasing (or decreasing) the values of the first predetermined number K1 and the second predetermined number K2 while maintaining the ratio of the number of inverters, the amount of compensation for non-linearity is increased (or decreased). Can be adjusted.

(Setting of the second timing control circuit 22)
FIG. 6 shows the relationship between the delay time generated by the second timing control circuit 22 and the temperature. Let DT3 be the delay time generated by the third delay circuit DC3. Let DT4 be the delay time generated by the fourth delay circuit DC4. Each of the delay times DT3 and DT4 increases proportionally with the increase in temperature with a positive third slope SL3 and a fourth slope SL4. The fourth inclination SL4 is larger than the third inclination SL3.

The temperature at the intersection of the straight line having the third slope SL3 and the straight line having the fourth slope SL4 is defined as the second threshold temperature T2. A region having a temperature higher than the first threshold temperature T1 and lower than the second threshold temperature T2 is defined as a second temperature region R2. A region having a temperature higher than the second threshold temperature T2 is defined as a third temperature region R3. The value of the second threshold temperature T2 can be set by the ratio of the third predetermined number K3 and the fourth predetermined number K4. In the present embodiment, the second threshold temperature T2 is set in the vicinity of the boundary temperature TH (FIG. 4) by appropriately determining the ratio between the third predetermined number K3 and the fourth predetermined number K4. Further, the third temperature region R3 is set so as to substantially overlap with the high temperature region RH.

(Operation of the first timing control circuit 21)
FIG. 7 shows a waveform diagram of various signals output from the first timing control circuit 21 and the compensation circuit 20. A case where the first timing control circuit 21 is operated in the first temperature region R1 (the temperature region lower than the first threshold temperature T1) will be described with reference to FIG. 7A. At time t1, a high-level start signal SS is input to the first timing control circuit 21. At the time t3 when the delay time DT1 has elapsed from the time t1, the high-level first start signal SSD1 is output. At the time t2 when the delay time DT2 has elapsed from the time t1, the high-level second start signal SSD2 is output. As described above, in the first temperature region R1, the delay time DT1 is larger than the delay time DT2, so that the second start signal SSD2 is output earlier than the first start signal SSD1 by the time TT1.

From the or circuit OR1 of the first timing control circuit 21, the second start signal SSD2, which is the signal with the earlier input, is output. Since the output signal of the or circuit OR1 becomes higher level than the first start signal SSD1, the output selection circuit 23 outputs the second start signal SSD2 as the drive start signal DS2 (arrow Y11). Further, the first start signal SSD1 is output as the drive start signal DS1 (arrow Y12).

Using FIG. 7B, the case where the first timing control circuit 21 is operated in the second temperature region R2 (the temperature region higher than the first threshold temperature T1 and lower than the second threshold temperature T2) is used. explain. At the time t4 when the delay time DT1 has elapsed from the time t1, the high-level first start signal SSD1 is output. At the time t5 when the delay time DT2 has elapsed from the time t1, the high-level second start signal SSD2 is output. As described above, in the second temperature region R2, the delay time DT2 is larger than the delay time DT1, so that the first start signal SSD1 is output earlier than the second start signal SSD2. The first start signal SSD1 is output from the or circuit OR1 of the first timing control circuit 21. Since the first start signal SSD1 becomes higher level than the output signal of the or circuit OR1, the output selection circuit 23 outputs the first start signal SSD1 as the drive start signal DS2 (arrow Y21) and drives the circuit. It is output as a start signal DS1 (arrow Y22).

(Operation of the second timing control circuit 22)
FIG. 8 shows a waveform diagram of various signals output from the second timing control circuit 22 and the compensation circuit 20. Using FIG. 8A, a case where the second timing control circuit 22 is operated in the second temperature region R2 (the temperature region higher than the first threshold temperature T1 and lower than the second threshold temperature T2) is used. explain. In the second temperature region R2, the delay time DT3 is larger than the delay time DT4, so that the fourth start signal SSD4 (time t12) is output earlier than the third start signal SSD3 (time t13) by the time TT11. Will be done. The fourth start signal SSD4 is output from the or circuit OR2. Therefore, the output selection circuit 23 outputs the fourth start signal SSD4 as the drive start signal DS2 (arrow Y31) and the drive start signal DS1 (arrow Y32).

A case where the second timing control circuit 22 is operated in the third temperature region R3 (the temperature region higher than the second threshold temperature T2) will be described with reference to FIG. 8B. In the third temperature region R3, the delay time DT4 is larger than the delay time DT3, so that the third start signal SSD3 (time t14) is output earlier than the fourth start signal SSD4 (time t15) by the time TT12. Will be done. From the or circuit OR2, the third start signal SSD3, which is the signal with the earlier input, is output. Therefore, the output selection circuit 23 outputs the third start signal SSD3 as the drive start signal DS2 (arrow Y41). Further, the fourth start signal SSD4 is output as the drive start signal DS1 (arrow Y42).

(Effects of the first timing control circuit 21 and the second timing control circuit 22)
In the first temperature region R1 (temperature region lower than the first threshold temperature T1), the output selection circuit 23 selects the first timing control circuit 21. In the first timing control circuit 21, the delay time of the drive start signal DS2 for starting the clock circuit 30 can be generated in the first temperature region R1 according to the second slope SL2 (FIG. 5, region A11). That is, the drive start signal DS2 can be output earlier than the drive start signal DS1 for the time TT1 according to the second inclination SL2 (FIG. 7A). Therefore, in the first temperature region R1, the clock circuit 30 can be started to operate earlier than the delay signal generation circuit 40 by the time TT1. As a result, as shown in the example of FIG. 3A, the clock count start time can be advanced from the time tt1 to the time tt0, so that the measured value of the number of clocks in the first temperature region R1 can be increased. .. Therefore, in the first temperature region R1 (that is, the low temperature region RL (FIG. 4) in which the measured value of the clock number is smaller than the ideal straight line IL), the measured value of the clock number can be increased and corrected so as to approach the ideal value. ..

On the other hand, in the second temperature region R2 and the third temperature region R3, which are temperature regions higher than the first threshold temperature T1, the output selection circuit 23 selects the second timing control circuit 22. In the second temperature region R2, the second timing control circuit 22 can generate the delay time of the drive start signal DS2 for starting the clock circuit 30 according to the fourth inclination SL4 (FIG. 6, region A21). That is, the drive start signal DS2 can be output at the same timing as the drive start signal DS1 (FIG. 8 (A)). Therefore, in the second temperature region R2, the clock circuit 30 can be started to operate at the same timing as the delay signal generation circuit 40. Therefore, in the second temperature region R2 (that is, the intermediate temperature region RM (FIG. 4) in which the measured value of the clock number is close to the ideal straight line IL), the measured value of the clock number is not corrected.

The second timing control circuit 22 can generate the delay time of the drive start signal DS2 for starting the clock circuit 30 in the third temperature region R3 according to the third inclination SL3 (FIG. 6, region A22). That is, the drive start signal DS2 can be output earlier than the drive start signal DS1 only for the time TT12 according to the third inclination SL3 (FIG. 8B). Therefore, in the third temperature region R3, the clock circuit 30 can be started to operate earlier than the delay signal generation circuit 40 by the time TT12, so that the measured value of the number of clocks in the third temperature region R3 can be increased. .. Therefore, in the third temperature region R3 (that is, the high temperature region RH (FIG. 4) in which the measured value of the clock number is smaller than the ideal straight line IL), the measured value of the clock number can be increased and corrected so as to approach the ideal value. .. From the above, in all the temperature bands from the first temperature region R1 to the third temperature region R3, it is possible to realize a state in which the measured values of the number of clocks with respect to the temperature change are in a proportional relationship (a state in which the linearity is high).

The temperature sensor circuit 1 has two important characteristics: the linearity described above and the power supply voltage fluctuation characteristic (the fluctuation characteristic of the temperature information Dout when the power supply voltage fluctuates). Then, it is preferable that these two characteristics can be corrected individually. However, for example, when correcting circuit characteristics (eg, power supply voltage VDD supplied to an inverter) in order to correct linearity (that is, when performing analog correction), the power supply voltage fluctuation characteristics are affected. It may get lost. On the other hand, in the technique of the present embodiment, the linearity can be corrected (that is, digital correction can be performed) by controlling the timing of the signal, so that the circuit characteristics are not affected. It is possible to correct the linearity without affecting the power supply voltage fluctuation characteristics.

The second embodiment is a method of compensating for the temperature information Dout when the non-linearity is opposite to that of the first embodiment. FIG. 9 shows the non-linearity of the temperature measurement according to the second embodiment in the characteristic graph CGa. In the second embodiment, the measured value of the number of clocks is larger than the value corresponding to the actual temperature in the low temperature region RL and the high temperature region RH. In order to compensate for such non-linearity, in the temperature sensor circuit 1 of the second embodiment, the output destination of the drive start signal DS1 is changed from the delay signal generation circuit 40 to the clock circuit 30, and the output destination of the drive start signal DS2 is changed. May be changed from the clock circuit 30 to the delay signal generation circuit 40. Since the other circuit configurations in the second embodiment are the same as those in the first embodiment, the description thereof will be omitted.

As described with reference to FIG. 7A, in the first temperature region R1, the second start signal SSD2 is output earlier than the first start signal SSD1 by the time TT1. In the first embodiment, the earlier second start signal SSD2 is output as the drive start signal DS2 for starting the clock circuit 30. On the other hand, in the second embodiment, the slower first start signal SSD1 is output as the drive start signal DS2. As a result, the clock count start time can be delayed, so that the measured value of the number of clocks in the first temperature region R1 can be reduced. Therefore, in the first temperature region R1 (that is, the low temperature region RL (FIG. 9) in which the measured value of the clock number is larger than the ideal straight line IL), the measured value of the clock number can be reduced and corrected so as to approach the ideal value. ..

Further, as described with reference to FIG. 8B, in the third temperature region R3, the third start signal SSD3 is output earlier than the fourth start signal SSD4 by the time TT12. In the second embodiment, the slower fourth start signal SSD4 is output as the drive start signal DS2. As a result, the clock count start time can be delayed, so that the measured value of the number of clocks in the third temperature region R3 can be reduced. Therefore, in the third temperature region R3 (that is, the low temperature region RH (FIG. 9) in which the measured value of the clock number is larger than the ideal straight line IL), the measured value of the clock number can be reduced and corrected so as to approach the ideal value. ..

FIG. 10 shows the temperature sensor circuit 1b according to the third embodiment. In the first embodiment, the compensation circuit 20 is provided in front of the clock circuit 30 and the delay signal generation circuit 40. In the third embodiment, the compensation circuit 20b is provided after the delay signal generation circuit 40. The common reference numerals are given to the parts common to the first and third embodiments, and the description thereof will be omitted. Further, the parts peculiar to Example 3 are distinguished by adding "b" at the end.

The first timing control circuit 21b and the second timing control circuit 22b are circuits that control the transmission timing of the delay signal DLS to the delay time measurement circuit 50. The delay signal DLS output from the delay signal generation circuit 40 is input to each of the first delay circuit DC1 to the fourth delay circuit DC4. The first specific delay signal DLSD1 is output from the first delay circuit DC1. The first specific delay signal DLSD1 is a signal in which a delay time DT1 is added to the delay signal DLS. The second specific delay signal DLSD2 is output from the second delay circuit DC2. The second specific delay signal DLSD2 is a signal in which the delay time DT2 is added to the delay signal DLS. From the AND circuit AD11b, of the first specific delay signal DLSD1 and the second specific delay signal DLSD2, the signal that is input later (that is, the signal with the slower rising edge) is output. Similarly, the third delay circuit DC3 outputs the third specific delay signal DLSD3 in which the delay time DT1 is added to the delay signal DLS. From the fourth delay circuit DC4, the fourth specific delay signal DLSD4 in which the delay time DT2 is added to the delay signal DLS is output. From the AND circuit AD12b, of the third specific delay signal DLSD3 and the fourth specific delay signal DLSD4, whichever is input later is output.

The output signals of the output terminal nQ and the AND circuit AD11b are input to the AND circuit AD1. The output signals of the output terminal Q and the AND circuit AD12b are input to the AND circuit AD2. A specific delay signal DLSD is output from the or circuit OR3. In the region lower than the first threshold temperature T1 in FIG. 5, the AND circuit AD1 becomes active, and the output signal of the first timing control circuit 21b becomes the specific delay signal DLSD. On the other hand, in a region higher than the first threshold temperature T1, the AND circuit AD2 becomes active, and the output signal of the second timing control circuit 22b becomes the specific delay signal DLSD.

(Effects of the first timing control circuit 21b and the second timing control circuit 22b)
In the first temperature region R1, the output selection circuit 23b selects the first timing control circuit 21b. In the first timing control circuit 21b, in the first temperature region R1 (see FIG. 5), the second specific delay signal DLSD2 is output earlier than the first specific delay signal DLSD1. Therefore, the slower first specific delay signal DLSD1 is output to the delay time measurement circuit 50 as the specific delay signal DLSD. Thereby, the delay time of the specific delay signal DLSD can be generated according to the first slope SL1 (FIG. 5, region B11).

On the other hand, in the second temperature region R2 and the third temperature region R3, which are temperature regions higher than the first threshold temperature T1, the second timing control circuit 22b is selected by the output selection circuit 23b. The second timing control circuit 22b can generate the delay time of the specific delay signal DLSD in the second temperature region R2 according to the third slope SL3 (FIG. 6, region B21). Further, in the third temperature region R3, the delay time of the specific delay signal DLSD can be generated according to the fourth slope SL4 (FIG. 6, region B22).

As can be seen from FIG. 5, the delay time in the first temperature region R1 can be increased from the region A11 to the region B11. As a result, as shown in the example of FIG. 3A, the input time of the delay signal DLS can be delayed from the time tt2 to the time tt3, so that the measured value of the number of clocks in the first temperature region R1 can be increased. it can. Therefore, in the first temperature region R1 (that is, the low temperature region RL (FIG. 4) in which the measured value of the clock number is smaller than the ideal straight line IL), the measured value of the clock number can be increased and corrected so as to approach the ideal value. .. Similarly, as can be seen from FIG. 6, the delay time in the third temperature region R3 can be increased from region A22 to region B22. Therefore, in the third temperature region R3 (that is, the high temperature region RH (FIG. 4) in which the measured value of the clock number is smaller than the ideal straight line IL), the measured value of the clock number can be increased and corrected so as to approach the ideal value. ..

The fourth embodiment is a method of compensating for the temperature information Dout when the non-linearity is opposite to that of the third embodiment. FIG. 9 shows the non-linearity of the temperature measurement according to the fourth embodiment in the characteristic graph CGa. In Example 4, in the low temperature region RL and the high temperature region RH, the measured value of the number of clocks is larger than the value corresponding to the actual temperature. In order to compensate for such non-linearity, in the temperature sensor circuit 1b (see FIG. 10) of the fourth embodiment, the AND circuits AD11b and AD12b may be changed to an or circuit. Since the other circuit configurations in the fourth embodiment are the same as those in the third embodiment, the description thereof will be omitted.

In the first timing control circuit 21b, in the first temperature region R1 (see FIG. 5), the earlier second specific delay signal DLSD2 is output to the delay time measurement circuit 50 as the specific delay signal DLSD. Thereby, the delay time of the specific delay signal DLSD can be generated according to the second slope SL2 (FIG. 5, region A11). Similar to the contents described in the first timing control circuit 21b, the second timing control circuit 22b can generate the delay time of the specific delay signal DLSD in the second temperature region R2 according to the fourth slope SL4 (in the second temperature region R2). FIG. 6, region A21). Further, the second timing control circuit 22b can generate the delay time of the specific delay signal DLSD in the third temperature region R3 according to the third slope SL3 (FIG. 6, region A22).

As can be seen from FIG. 5, the delay time in the first temperature region R1 can be reduced from the region B11 to the region A11. Therefore, in the first temperature region R1 (that is, the low temperature region RL (FIG. 9) in which the measured value of the clock number is larger than the ideal straight line IL), the measured value of the clock number can be reduced and corrected so as to approach the ideal value. .. Similarly, as can be seen from FIG. 6, the delay time in the third temperature region R3 can be reduced from region B22 to region A22. Therefore, in the third temperature region R3 (that is, the high temperature region RH (FIG. 9) in which the measured value of the clock number is larger than the ideal straight line IL), the measured value of the clock number can be reduced and corrected so as to approach the ideal value. ..

The fifth embodiment is an example of another configuration of the first delay circuit DC1 to the fourth delay circuit DC4 of the first to fourth embodiments. The contents peculiar to the fifth embodiment will be described below. FIG. 11 shows the first delay circuit DC1c. The first delay circuit DC1c of FIG. 11 is a circuit corresponding to the first delay circuit DC1 of the first embodiment. The first delay circuit DC1c includes a ring oscillator 61, a counter 62, a latch 63, and an inverter chain 64, which are connected in series. The ring oscillator 61 includes a plurality of first inverters INV1. The counter 62 includes N-stage flip-flops connected in series. The output of the flip-flop at the final stage of the counter 62 is input to the latch 63. The inverter chain 64 includes a plurality of inverters connected in series. The number of stages of the inverter chain 64 and the gate length of the inverter can be freely set according to a desired delay time.

The circuit configuration of the third delay circuit DC3c corresponding to the third delay circuit DC3 (FIG. 2) may be the same as that of the first delay circuit DC1c (FIG. 11). The circuit configuration of the second delay circuit DC2c corresponding to the second delay circuit DC2 (FIG. 2) and the circuit configuration of the fourth delay circuit DC4c corresponding to the fourth delay circuit DC4 are the first delay circuit DC1c (FIG. 11). In, the ring oscillator 61 may be configured by the second inverter INV2.

The operation of the first delay circuit DC1c will be described. When the high-level start signal SS is input, the clock signal CLK is output from the ring oscillator 61. The counter 62 multiplies the frequency of the clock signal CLK by 2 ^N times. The latch 63 latches the output of the multiplied clock signal CLKM multiplied by ^2N. The inverter chain 64 outputs the first start signal SSD1 in which a desired delay time is added to the multiplication clock signal CLKM. Similarly, the second start signal SSD2 to the fourth start signal SSD4 are output from each of the second delay circuit DC2c to the fourth delay circuit DC4c (not shown).

The delay time generated by the first delay circuit DC1c and the third delay circuit DC3c has a smaller change slope with respect to temperature than the delay time generated by the second delay circuit DC2c and the fourth delay circuit DC4c. This is because the gate length of the first inverter INV1 of the first delay circuit DC1c and the third delay circuit DC3c is smaller than the gate length of the second inverter INV2 of the second delay circuit DC2c and the fourth delay circuit DC4c.

(effect)
By configuring the first delay circuit DC1 to the fourth delay circuit DC4 with the ring oscillator 61 and the counter 62, the number of inverter stages required to generate the same delay time is reduced as compared with the case where the first delay circuit DC1 to the counter 62 are configured. can do. This configuration is useful, especially on the high temperature side, because the number of inverter stages required increases. Further, the inverter chain 64 makes it possible to finely adjust the output timing of the multiplied clock signal CLKM, which is output at ^{2 N times the clock signal CLK.}

The sixth embodiment is an embodiment of a configuration in which a part of the counter inside the delay time measurement circuit 50d is diverted to the compensation circuit 20d. The contents peculiar to the sixth embodiment will be described below. The parts common to Examples 1 and 6 are designated by a common reference numeral, and the description thereof will be omitted. Further, the part peculiar to Example 6 is distinguished by adding "d" at the end.

FIG. 12 shows the temperature sensor circuit 1d according to the sixth embodiment. The delay time measuring circuit 50d includes a counter 51d. The counter 51d includes N-stage (N is a natural number of 2 or more) flip-flops (not shown) connected in series. The N-stage flip-flop is composed of transistors having the same gate length as the clock circuit 30. _{Timing signals PS J} and PS _K are output from the flip-flops of the Jth and Kth stages, and are latched by the latches LA1 and LA2. J is a natural number greater than or equal to 2 and less than N. K is a natural number greater than J and less than or equal to N. The timing signals PS _J and PS _K are signals obtained by multiplying the frequency of the clock signal CLK by 2 ^J times and 2 ^{K times.}

The compensation circuit 20d includes a first delay circuit DC1d and a third delay circuit DC3d. The number of stages of one inverter INV1 of the first delay circuit DC1d is smaller than that of the first delay circuit DC1 (FIG. 2) of the first embodiment. The number of stages of one inverter INV1 of the third delay circuit DC3d is smaller than that of the third delay circuit DC3 of the first embodiment. _{Timing signals PS J} and PS _K are input to the first delay circuit DC1d and the third delay circuit DC3d. A start signal SS is input to the clock circuit 30.

The operation of the temperature sensor circuit 1d will be described. When the start signal SS transitions to a high level, the clock circuit 30 starts generating the clock signal CLK. The clock signal CLK is counted by the counter 51d. When the clock signal CLK is multiplied to ^{2 J} times, along with the rising edge of the timing signal PS _J is latched by the latch LA1, the timing signal PS _J of a high level is input to the first delay circuit DC1d. Then, as the clock signal CLK is multiplied to ^{2 K} times, with the rising edge of the timing signal PS _K is latched by the latch LA2, timing signal PS _K of a high level is input to the third delay circuit DC3d.

(effect)
The gate length of the inverter of the counter 51d and the gate length of the inverters of the first delay circuit DC1d and the third delay circuit DC3d are the same. Therefore, the timing signal PS _J obtained by multiplying the clock signal CLK by the counter 51d has an inverter chain equivalent delay time J stage of the first delay circuit DC1d. Therefore, by inputting the timing signal PS _J to the first delay circuit DC1d, it is possible to reduce the J stage component of the inverter from the first delay circuit DC1d. Similarly, the timing signal PS _K by inputting to the third delay circuit DC3d, it is possible to reduce the K stages fraction of the inverter from the third delay circuit DC3d. It is possible to suppress the circuit scale of the temperature sensor circuit 1d. Further, since the timing signals PS _J and PS _K are multiplied signals and have low frequencies, it is difficult to generate a desired delay time. Therefore by providing a first delay circuit DC1d and third delay circuit DC3d, by finely adjusting the delay time of the timing signal PS _J and PS _K, it is possible to generate a desired delay time.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

(Modification example)
The temperature sensor according to the present specification is an example of an A / D conversion circuit. The techniques herein are applicable to circuits that convert various analog values into digital values.

The configuration of the output selection circuit 23 is an example. The selection of the first timing control circuit 21 and the second timing control circuit 22 is not limited to the temperature, and may be performed based on the output timings of various signals. Switching between the first timing control circuit 21 and the second timing control circuit 22 by the flip-flop FF may take various forms. For example, it may be switched in a predetermined temperature range by a temperature sensor (not shown).

Temperature is an example of a physical quantity. The delay signal DLS is an example of a delay signal. The threshold temperature T1 is an example of the first threshold. The threshold temperature T2 is an example of the second threshold.

1: Temperature sensor circuit 20: Compensation circuit 21: First timing control circuit 22: Second timing control circuit 23: Output selection circuit 30: Clock circuit 40: Delay signal generation circuit 41: Pulse generation circuit 42: Delay circuit 50: Delay Time measurement circuit SS: Start signal SSD1 to SSD4: 1st to 4th start signals DS1, DS2: Drive start signal LS: Low frequency signal CLK: Clock signal

Claims (10)

A clock circuit that generates a clock signal and has a ring oscillator in which a plurality of first inverters are connected in a ring shape.
A delay signal generation circuit that includes an inverter chain in which a plurality of second inverters are connected in series and generates a delay signal having a change amount depending on a change in a physical quantity to be measured.
The delay signal generation circuit in which the gate length of the transistor included in the plurality of second inverters is larger than the gate length of the transistor included in the plurality of first inverters.
A delay time measuring circuit in which the clock signal and the delay signal are input and the amount of change in the delay signal is measured based on the number of clocks of the clock signal.
The start timing of the clock circuit is controlled so that the measured value of the number of clocks is proportional to the change of the physical quantity, or the delay signal output by the delay signal generation circuit is transmitted to the delay time measurement circuit. The first timing control circuit that controls the timing,
A / D conversion circuit. The first timing control circuit is a circuit that controls the start timing of the clock circuit.
The first timing control circuit is
A first delay circuit in which a first predetermined number of the first inverters are connected in series, and
A second delay circuit in which a second predetermined number of the second inverters are connected in series is provided.
From the first delay circuit, a first start signal having a delay time that increases proportionally with a positive first slope with respect to the increase in the physical quantity is output.
From the second delay circuit, a second start signal having a delay time that increases proportionally with a positive second slope with respect to the increase in the physical quantity is output.
The first start signal and the second start signal are signals for instructing the start of generation of the clock signal and the delay signal.
The second slope is larger than the first slope,
The first start signal is input to the delay signal generation circuit, and the first start signal is input to the delay signal generation circuit.
The A / D conversion circuit according to claim 1, wherein either one of the first start signal and the second start signal is input to the clock circuit. In the first region where the physical quantity is smaller than the first threshold value, which is the intersection of the straight line having the first inclination and the straight line having the second inclination, the second start signal is the first start. The delay time is smaller than the signal,
In the second region where the physical quantity is larger than the first threshold value, the delay time of the first start signal is smaller than that of the second start signal.
In the first region, when the measured value of the number of clocks is smaller than the value corresponding to the actual physical quantity,
In the first region, the second start signal is input to the clock circuit.
In the second region, the first start signal is input to the clock circuit.
In the first region, when the measured value of the number of clocks is larger than the value corresponding to the actual physical quantity,
The A / D conversion circuit according to claim 2, wherein in the first region, the first start signal is input to the clock circuit. A second timing control circuit for controlling the start timing of the clock circuit is further provided.
The second timing control circuit
A third delay circuit in which a third predetermined number of the first inverters are connected in series, and
A fourth delay circuit in which a fourth predetermined number of the second inverters are connected in series is provided.
From the third delay circuit, a third start signal having a delay time that increases proportionally with a positive third slope with respect to the increase in the physical quantity is output.
From the fourth delay circuit, a fourth start signal having a delay time that increases proportionally with a positive fourth slope with respect to the increase in the physical quantity is output.
The third start signal and the fourth start signal are signals for instructing the start of generation of the clock signal and the delay signal.
The fourth slope is larger than the third slope,
The second threshold value, which is the intersection of the straight line having the third inclination and the straight line having the fourth inclination, is larger than the first threshold value.
The second region is a region in which the physical quantity is larger than the first threshold value and the physical quantity is smaller than the second threshold value.
In the second region, the fourth start signal has a smaller delay time than the third start signal.
In the third region where the physical quantity is larger than the second threshold value, the delay time of the third start signal is smaller than that of the fourth start signal.
In the third region, when the measured value of the number of clocks is smaller than the value corresponding to the actual physical quantity,
In the second region, the first start signal or the fourth start signal is input to the clock circuit.
In the third region, the third start signal is input to the clock circuit.
In the third region, when the measured value of the number of clocks is larger than the value corresponding to the actual physical quantity,
In the second region, the second start signal or the third start signal is input to the clock circuit.
The A / D conversion circuit according to claim 3, wherein in the third region, the fourth start signal is input to the clock circuit. The first threshold value can be set by the ratio of the first predetermined number to the second predetermined number.
The first inclination increases as the value of the first predetermined number increases.
The A / D conversion circuit according to claim 3 or 4, wherein the second inclination increases as the value of the second predetermined number increases. The first delay circuit is
A ring oscillator equipped with a plurality of the first inverters,
A first counter that counts the output pulse of the ring oscillator and outputs the first start signal according to the count value becoming a predetermined first predetermined value.
With
The second delay circuit is
A ring oscillator equipped with a plurality of the second inverters,
A second counter that counts the output pulse of the ring oscillator and outputs the second start signal according to the count value becoming a predetermined second predetermined value.
The A / D conversion circuit according to any one of claims 2 to 5, wherein the A / D conversion circuit comprises. The first timing control circuit is a circuit that controls the transmission timing of the delay signal to the delay time measurement circuit.
The first timing control circuit is
A first delay circuit in which a first predetermined number of the first inverters are connected in series, and
A second delay circuit in which a second predetermined number of the second inverters are connected in series is provided.
The delay signal output from the delay signal generation circuit is input to the first delay circuit and the second delay circuit.
From the first delay circuit, a first specific delay signal in which a delay time proportionally increasing with a positive first slope with respect to an increase in the physical quantity is added to the delay signal is output.
From the second delay circuit, a second specific delay signal in which a delay time proportionally increasing with a positive second slope with respect to an increase in the physical quantity is added to the delay signal is output.
The second slope is larger than the first slope,
The A / D conversion circuit according to claim 1, wherein either the first specific delay signal or the second specific delay signal is input to the delay time measurement circuit. In the first region where the physical quantity is smaller than the first threshold value, which is the intersection of the straight line having the first slope and the straight line having the second slope, the second specific delay signal is the first. The added delay time is smaller than the specific delay signal,
In the second region where the physical quantity is larger than the first threshold value, the delay time added to the first specific delay signal is smaller than that of the second specific delay signal.
In the first region, when the measured value of the number of clocks is smaller than the value corresponding to the actual physical quantity,
In the first region, the second specific delay signal is input to the delay time measurement circuit, and the delay time measurement circuit is input.
In the second region, the first specific delay signal is input to the delay time measurement circuit, and the delay time measurement circuit is input.
In the first region, when the measured value of the number of clocks is larger than the value corresponding to the actual physical quantity,
In the first region, the first specific delay signal is input to the delay time measurement circuit, and the delay time measurement circuit is input.
The A / D conversion circuit according to claim 7, wherein in the second region, the second specific delay signal is input to the delay time measurement circuit. The first threshold value can be set by the ratio of the first predetermined number to the second predetermined number.
The first inclination increases as the value of the first predetermined number increases.
The A / D conversion circuit according to claim 8, wherein the second inclination increases as the value of the second predetermined number increases. The first delay circuit is
A ring oscillator equipped with a plurality of the first inverters,
A first counter that counts the output pulse of the ring oscillator and outputs the first specific delay signal according to the count value becoming a predetermined first predetermined value.
With
The second delay circuit is
A ring oscillator equipped with a plurality of the second inverters,
A second counter that counts the output pulse of the ring oscillator and outputs the second specific delay signal according to the count value becoming a predetermined second predetermined value.
The A / D conversion circuit according to any one of claims 7 to 9, further comprising.

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