JP2021086612A5 - - Google Patents
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- JP2021086612A5 JP2021086612A5 JP2020150869A JP2020150869A JP2021086612A5 JP 2021086612 A5 JP2021086612 A5 JP 2021086612A5 JP 2020150869 A JP2020150869 A JP 2020150869A JP 2020150869 A JP2020150869 A JP 2020150869A JP 2021086612 A5 JP2021086612 A5 JP 2021086612A5
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- JP
- Japan
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- lru
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025080815A JP2025118847A (ja) | 2019-11-26 | 2025-05-13 | フレキシブルなキャッシュ割り当て技術の優先度ベースのキャッシュラインエビクションアルゴリズム |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/696,548 US11656997B2 (en) | 2019-11-26 | 2019-11-26 | Flexible cache allocation technology priority-based cache line eviction algorithm |
| US16/696,548 | 2019-11-26 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025080815A Division JP2025118847A (ja) | 2019-11-26 | 2025-05-13 | フレキシブルなキャッシュ割り当て技術の優先度ベースのキャッシュラインエビクションアルゴリズム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021086612A JP2021086612A (ja) | 2021-06-03 |
| JP2021086612A5 true JP2021086612A5 (https=) | 2025-01-23 |
| JP7682613B2 JP7682613B2 (ja) | 2025-05-26 |
Family
ID=72659026
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020150869A Active JP7682613B2 (ja) | 2019-11-26 | 2020-09-08 | フレキシブルなキャッシュ割り当て技術の優先度ベースのキャッシュラインエビクションアルゴリズム |
| JP2025080815A Pending JP2025118847A (ja) | 2019-11-26 | 2025-05-13 | フレキシブルなキャッシュ割り当て技術の優先度ベースのキャッシュラインエビクションアルゴリズム |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025080815A Pending JP2025118847A (ja) | 2019-11-26 | 2025-05-13 | フレキシブルなキャッシュ割り当て技術の優先度ベースのキャッシュラインエビクションアルゴリズム |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US11656997B2 (https=) |
| EP (2) | EP3828714B1 (https=) |
| JP (2) | JP7682613B2 (https=) |
| CN (2) | CN117609109A (https=) |
| BR (1) | BR102020019663A2 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821324B (zh) * | 2021-09-17 | 2022-08-09 | 海光信息技术股份有限公司 | 处理器的高速缓存系统、方法、设备和计算机介质 |
| US12099444B2 (en) * | 2022-01-21 | 2024-09-24 | Centaur Technology, Inc. | Cat aware loads and software prefetches |
| US11947462B1 (en) | 2022-03-03 | 2024-04-02 | Apple Inc. | Cache footprint management |
| CN115098040B (zh) * | 2022-07-22 | 2024-10-29 | 北京天融信网络安全技术有限公司 | 基于fpga的数据处理方法、装置、设备及存储介质 |
| US20240311151A1 (en) * | 2023-03-13 | 2024-09-19 | Intel Corporation | Device, method and system for prioritizing entries of an instruction fetch resource |
| US12541455B2 (en) * | 2024-06-07 | 2026-02-03 | SanDisk Technologies, Inc. | Data storage device and method for defining caching layers based on cache attributes |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09101916A (ja) | 1995-10-06 | 1997-04-15 | Fujitsu Ltd | マルチプロセス処理装置 |
| US7899994B2 (en) | 2006-08-14 | 2011-03-01 | Intel Corporation | Providing quality of service (QoS) for cache architectures using priority information |
| US7725657B2 (en) | 2007-03-21 | 2010-05-25 | Intel Corporation | Dynamic quality of service (QoS) for a shared cache |
| US7802057B2 (en) | 2007-12-27 | 2010-09-21 | Intel Corporation | Priority aware selective cache allocation |
| JP5217432B2 (ja) | 2007-12-28 | 2013-06-19 | 富士通株式会社 | セクタ機能付きキャッシュメモリ |
| JP5413001B2 (ja) | 2009-07-09 | 2014-02-12 | 富士通株式会社 | キャッシュメモリ |
| US8677071B2 (en) * | 2010-03-26 | 2014-03-18 | Virtualmetrix, Inc. | Control of processor cache memory occupancy |
| WO2012095957A1 (ja) | 2011-01-12 | 2012-07-19 | 富士通株式会社 | キャッシュメモリ装置，キャッシュメモリの制御装置，情報処理装置，キャッシュメモリの制御方法，及びキャッシュメモリ装置の閾値決定プログラム |
| US9378153B2 (en) | 2013-08-27 | 2016-06-28 | Advanced Micro Devices, Inc. | Early write-back of modified data in a cache memory |
| US9582430B2 (en) * | 2015-03-27 | 2017-02-28 | Intel Corporation | Asymmetric set combined cache |
| US9734070B2 (en) | 2015-10-23 | 2017-08-15 | Qualcomm Incorporated | System and method for a shared cache with adaptive partitioning |
-
2019
- 2019-11-26 US US16/696,548 patent/US11656997B2/en active Active
-
2020
- 2020-09-08 JP JP2020150869A patent/JP7682613B2/ja active Active
- 2020-09-09 CN CN202311713977.3A patent/CN117609109A/zh active Pending
- 2020-09-09 CN CN202010940678.3A patent/CN112948285A/zh active Pending
- 2020-09-24 EP EP20198156.0A patent/EP3828714B1/en active Active
- 2020-09-24 EP EP23211531.1A patent/EP4307130A3/en active Pending
- 2020-09-26 BR BR102020019663-4A patent/BR102020019663A2/pt unknown
-
2023
- 2023-05-22 US US18/321,603 patent/US12182025B2/en active Active
-
2025
- 2025-05-13 JP JP2025080815A patent/JP2025118847A/ja active Pending
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