CN117609109A - 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法 - Google Patents

灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法 Download PDF

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Publication number
CN117609109A
CN117609109A CN202311713977.3A CN202311713977A CN117609109A CN 117609109 A CN117609109 A CN 117609109A CN 202311713977 A CN202311713977 A CN 202311713977A CN 117609109 A CN117609109 A CN 117609109A
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China
Prior art keywords
cache
processor
priority
field
instruction
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CN202311713977.3A
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English (en)
Chinese (zh)
Inventor
N·侯卡尔
A·库马
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Intel Corp
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Intel Corp
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Publication of CN117609109A publication Critical patent/CN117609109A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN202311713977.3A 2019-11-26 2020-09-09 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法 Pending CN117609109A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/696,548 US11656997B2 (en) 2019-11-26 2019-11-26 Flexible cache allocation technology priority-based cache line eviction algorithm
US16/696,548 2019-11-26
CN202010940678.3A CN112948285A (zh) 2019-11-26 2020-09-09 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法

Related Parent Applications (1)

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CN202010940678.3A Division CN112948285A (zh) 2019-11-26 2020-09-09 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法

Publications (1)

Publication Number Publication Date
CN117609109A true CN117609109A (zh) 2024-02-27

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CN202311713977.3A Pending CN117609109A (zh) 2019-11-26 2020-09-09 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法
CN202010940678.3A Pending CN112948285A (zh) 2019-11-26 2020-09-09 灵活高速缓存分配技术的基于优先级的高速缓存行驱逐算法

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Country Status (5)

Country Link
US (2) US11656997B2 (https=)
EP (2) EP3828714B1 (https=)
JP (2) JP7682613B2 (https=)
CN (2) CN117609109A (https=)
BR (1) BR102020019663A2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113821324B (zh) * 2021-09-17 2022-08-09 海光信息技术股份有限公司 处理器的高速缓存系统、方法、设备和计算机介质
US12099444B2 (en) * 2022-01-21 2024-09-24 Centaur Technology, Inc. Cat aware loads and software prefetches
US11947462B1 (en) 2022-03-03 2024-04-02 Apple Inc. Cache footprint management
CN115098040B (zh) * 2022-07-22 2024-10-29 北京天融信网络安全技术有限公司 基于fpga的数据处理方法、装置、设备及存储介质
US20240311151A1 (en) * 2023-03-13 2024-09-19 Intel Corporation Device, method and system for prioritizing entries of an instruction fetch resource
US12541455B2 (en) * 2024-06-07 2026-02-03 SanDisk Technologies, Inc. Data storage device and method for defining caching layers based on cache attributes

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09101916A (ja) 1995-10-06 1997-04-15 Fujitsu Ltd マルチプロセス処理装置
US7899994B2 (en) 2006-08-14 2011-03-01 Intel Corporation Providing quality of service (QoS) for cache architectures using priority information
US7725657B2 (en) 2007-03-21 2010-05-25 Intel Corporation Dynamic quality of service (QoS) for a shared cache
US7802057B2 (en) 2007-12-27 2010-09-21 Intel Corporation Priority aware selective cache allocation
JP5217432B2 (ja) 2007-12-28 2013-06-19 富士通株式会社 セクタ機能付きキャッシュメモリ
JP5413001B2 (ja) 2009-07-09 2014-02-12 富士通株式会社 キャッシュメモリ
US8677071B2 (en) * 2010-03-26 2014-03-18 Virtualmetrix, Inc. Control of processor cache memory occupancy
WO2012095957A1 (ja) 2011-01-12 2012-07-19 富士通株式会社 キャッシュメモリ装置，キャッシュメモリの制御装置，情報処理装置，キャッシュメモリの制御方法，及びキャッシュメモリ装置の閾値決定プログラム
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
US9582430B2 (en) * 2015-03-27 2017-02-28 Intel Corporation Asymmetric set combined cache
US9734070B2 (en) 2015-10-23 2017-08-15 Qualcomm Incorporated System and method for a shared cache with adaptive partitioning

Also Published As

Publication number Publication date
US20230409485A1 (en) 2023-12-21
US20210157739A1 (en) 2021-05-27
US12182025B2 (en) 2024-12-31
EP4307130A3 (en) 2024-05-01
EP3828714B1 (en) 2024-04-03
US11656997B2 (en) 2023-05-23
CN112948285A (zh) 2021-06-11
JP7682613B2 (ja) 2025-05-26
JP2021086612A (ja) 2021-06-03
EP3828714A1 (en) 2021-06-02
EP4307130A2 (en) 2024-01-17
BR102020019663A2 (pt) 2021-06-08
JP2025118847A (ja) 2025-08-13

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