JP2021083192A - Shutdown device of inverter - Google Patents

Abstract

To provide a shutdown device that continues operation of an inverter in a case where one controller is normal even when abnormality occurs in one of two controllers.SOLUTION: Output terminals of first/second controllers are connected to an input terminal of an OR circuit via a first/a second switches, respectively. The first/second controllers output a first/a second pulse signals when a shutdown state of an inverter is detected, respectively. The first controller turns off the second switch when a state is detected in which the second controller is abnormal and the first controller is normal. The second controller executes processing to turn off the first switch when a state is detected in which the first controller is abnormal and the second controller is normal. A determination unit performs processing to shut down the inverter when the number of pulses within a predetermined time of the pulse signal from the OR circuit is within a predetermined range. A frequency of the first pulse signal is differentiated from that of the second pulse signal.SELECTED DRAWING: Figure 1

Description

This specification discloses an inverter operation stop device.

High reliability is required to control inverters installed in electric vehicles and the like. Therefore, a controller has been developed that monitors whether or not a state in which the operation of the inverter should be stopped has occurred, and stops the inverter when the occurrence of that state is detected. In order to improve reliability, Patent Document 1 discloses a technique in which two controllers (referred to as a microprocessor in Patent Document 1) are used in duplicate (redundantly). In Patent Document 1, the outputs of the two controllers are compared and collated, and if the outputs of the two controllers are different, it is determined that an abnormality has occurred in one of the controllers, and the output to the inverter is stopped. .. According to the technique of Patent Document 1, when a state in which the operation of the inverter should be stopped occurs, the inverter can be stopped even if either controller is abnormal.

JP-A-2009-140213

In the technique of Patent Document 1, when a state in which the operation of the inverter should be stopped occurs, the safety is improved by stopping the inverter even if one of the controllers is abnormal. Even if it is not necessary to stop the inverter, if an abnormality occurs in one controller, the inverter will be stopped even if the other controller is normal.
In the present specification, when the inverter should be stopped, the inverter is stopped even if one of the controllers is abnormal, and when it is not necessary to stop the operation of the inverter, an abnormality occurs in one of the controllers. Also discloses a technique that does not stop the inverter as long as the other controller is normal.

The inverter operation stop device disclosed in the present specification includes a first controller, a first switch, a second controller, a second switch, an OR circuit, and a determination unit.
The output terminal of the first controller is connected to one input terminal of the OR circuit via the first switch, and the output terminal of the second controller is connected to the other input terminal of the OR circuit via the second switch. It is connected to the. The output terminal of the OR circuit is connected to the determination unit.
The first controller outputs a first pulse signal when it detects a state in which the operation of the inverter is stopped, and turns off the second switch when the first controller is normal and the second controller detects an abnormal state. To execute. The second controller outputs a second pulse signal when it detects a state in which the operation of the inverter is stopped, and turns off the first switch when the first controller detects an abnormal state and the second controller detects a normal state. Execute. The frequency of the first pulse signal and the frequency of the second pulse signal are different. The determination unit executes a process of stopping the operation of the inverter when the number of pulses of the pulse signal output by the OR circuit within a predetermined time is within a predetermined range. Each of the first pulse signal and the second pulse signal has a predetermined number of pulses within a predetermined time.

The above-mentioned operation stop device executes the following processing.
(1) When the first controller and the second controller detect the state in which the operation of the inverter is stopped and both the first controller and the second controller are normal. In this case, the first controller outputs the first pulse signal. The output is output and input to the OR circuit, and the second controller outputs the second pulse signal and inputs it to the OR circuit. The OR results of the first pulse signal and the second pulse signal are input to the determination unit. In this case, as will be described in detail later, in the OR result, the number of pulses within the predetermined time is within the predetermined range, and the inverter stops.
(2) Processing when the first controller and the second controller detect the state in which the operation of the inverter is stopped and either the first controller or the second controller is abnormal. In this case, the abnormal controller gives an abnormal signal. Is output, but the corresponding switch is turned off, so that the abnormal signal is not input to the OR circuit. A normal controller outputs a predetermined pulse signal, which is input to the OR circuit. As for the OR result, the inverter stops because the number of pulses within the predetermined time is within the predetermined range.
(3) Processing when the state of stopping the operation of the inverter is not detected and the first controller and the second controller are normal In this case, neither the first controller nor the second controller outputs a pulse signal. The determination unit does not determine that the number of pulses within the predetermined time is within the predetermined range, and the inverter does not stop.
(4) Processing when the state of stopping the operation of the inverter is not detected and either the first controller or the second controller is abnormal In this case, the abnormal controller may output an abnormal signal. However, since the corresponding switch is turned off, the abnormal signal is not input to the OR circuit. Also, a normal controller does not output a predetermined pulse signal. The determination unit does not determine that the number of pulses within the predetermined time is within the predetermined range, and the inverter does not stop.
As described above, according to the operation stop device disclosed in the present specification, when the inverter should be stopped, it is necessary to stop the operation of the inverter while stopping the inverter even if either controller is abnormal. If not, the inverter will not be stopped as long as the other controller is normal even if one controller malfunctions. While reliably stopping the inverter when necessary, the inverter is not stopped unnecessarily.

Details of the techniques disclosed herein and further improvements will be described in the "Modes for Carrying Out the Invention" below.

It is a block diagram of the operation stop device of an Example. It is a waveform diagram of the 1st pulse signal, the 2nd pulse signal, and the synthetic pulse signal when they are in phase. It is a waveform diagram of the 1st pulse signal, the 2nd pulse signal, and the synthetic pulse signal in the case where the phase is out of phase. It is a timing chart when the 1st controller and the 2nd controller are normal. It is a timing chart when an abnormality occurs in the 2nd controller when the operation of an inverter is continued. It is a timing chart when an abnormality occurs in the 2nd controller when the operation of an inverter is stopped.

The operation stop device of the embodiment will be described with reference to the drawings. FIG. 1 shows the configuration of the operation stop device 10. The operation stop device 10 includes a first controller 1, a first switch 16, a second controller 2, a second switch 26, an OR circuit 4, a determination unit 6, and the like, and operates the inverter 8 when necessary. To stop. The operation stop device 10 is connected to the microcomputer 8a included in the inverter 8.
Information ES1 is input to the first controller 1 from the microcomputer 8a. Similarly, the information ES2 is input to the second controller 2 from the microcomputer 8a. Information ES1 and ES2 are information that changes depending on the operating state of the inverter 8, such as the voltage and temperature of the inverter 8. The operation stop device 10 sequentially determines whether or not it is necessary to stop the operation of the inverter 8 based on the information ES1 and ES2 received from the microcomputer 8a.

The first controller 1 includes a first output unit 11, a first cut unit 12, and a first monitoring unit 13. Similarly, the second controller 2 includes a second output unit 21, a second cut unit 22, and a second monitoring unit 23. Although not shown, both the first controller 1 and the second controller 2 include a central control unit (CPU). The first controller 1 analyzes the information ES1 received from the microcomputer 8a, and when it detects that a state in which the operation of the inverter 8 should be stopped has occurred based on the analysis result, the first output unit 11 to the first controller 1. Output a pulse signal. Similarly, the second controller 2 also analyzes the information ES2 received from the microcomputer 8a, and when it is detected that a state in which the operation of the inverter 8 should be stopped has occurred based on the analysis result, the second output unit 21 starts. Outputs the second pulse signal.

The first pulse signal output from the first output unit 11 is transmitted to one input terminal of the OR circuit 4 via the first resistor 14 and the first switch 16. One end of the first transistor is connected between the first resistor 14 and the OR circuit 4, and the other end of the first transistor is grounded. The second cut portion 22 is connected to the gate of the first transistor. The first transistor is normally off, and is turned on only when the second cut portion 22 outputs a high signal. When the second cut portion 22 applies a high voltage to the gate of the first transistor, the first transistor is turned on. When the first transistor is turned on, the voltage of one input terminal of the OR circuit 4 drops to the ground voltage (low voltage). When the first transistor is turned off, the voltage at the input terminal of the OR circuit 4 corresponds to the first pulse signal. In the present specification, it is said that the first switch 16 is off when the first transistor is on, and the first switch 16 is on when the first transistor is off.

Similarly, the second pulse signal output from the second output unit 21 is transmitted to the other input terminal of the OR circuit 4 via the second resistor 24 and the second switch 26. One end of the second transistor is connected between the second resistor 24 and the OR circuit 4, and the other end of the second transistor is grounded. The first cut portion 12 is connected to the gate of the second transistor. The second transistor is normally off, and is turned on only when the first cut portion 12 outputs a high signal. When the first cut portion 12 applies a high voltage to the gate of the second transistor, the second transistor is turned on. When the first transistor is turned on, the voltage of the other input terminal of the OR circuit 4 drops to the ground voltage (low voltage). When the second transistor is turned off, the voltage at the input terminal of the OR circuit 4 corresponds to the second pulse signal. In the present specification, it is said that the second switch 26 is off when the second transistor is on, and the second switch 26 is on when the second transistor is off.

The first monitoring unit 13 of the first controller 1 communicates with the second monitoring unit 23 of the second controller 2. The first monitoring unit 13 transmits a survival notification of the first controller 1 to the second monitoring unit 23 at predetermined time intervals. Similarly, the second monitoring unit 23 transmits a survival notification of the second controller 2 to the first monitoring unit 13 at predetermined time intervals. When the first monitoring unit 13 does not receive the survival notification from the second monitoring unit 23 even after the lapse of a predetermined time, the first monitoring unit 13 determines that an abnormality has occurred in the second controller 2. Similarly, the second monitoring unit 23 determines that an abnormality has occurred in the first controller 1 when the survival notification from the first monitoring unit 13 is not received even after the lapse of a predetermined time. In this way, the first monitoring unit 13 of the first controller 1 monitors the second controller 2, and the second monitoring unit 23 of the second controller 2 monitors the first controller 1. The method in which the first monitoring unit 13 monitors the second controller 2 is not limited to this, and may be another method (for example, data monitoring). Similarly, the method in which the second monitoring unit 23 monitors the first controller 1 may be another method.
The first monitoring unit 13 also monitors whether or not an abnormality has occurred in the first controller 1, and the second monitoring unit 23 also monitors whether or not an abnormality has occurred in the second controller 2.

When the first monitoring unit 13 determines that the first controller 1 is normal and an abnormality has occurred in the second controller 2, the first monitoring unit 13 transmits an abnormality detection flag to the second monitoring unit 23 and cuts the first. An abnormality determination is transmitted to unit 12. Upon receiving the abnormality determination, the first cut unit 12 applies a high voltage to the gate of the second switch 26 to turn off the second switch 26. Even if the second controller 2 outputs a second pulse signal or an abnormal signal, the output signal is not input to the OR circuit 4. The first controller 1 prevents the output voltage of the second controller 2 in which the abnormality has occurred from reaching the OR circuit 4 when the first cut unit 12 turns off the second switch 26.

When the second monitoring unit 23 determines that the second controller 2 is normal and an abnormality has occurred in the first controller 1, the second monitoring unit 23 transmits an abnormality detection flag to the first monitoring unit 13 and cuts the second. An abnormality determination is transmitted to unit 22. Upon receiving the abnormality determination, the second cut unit 22 applies a high voltage to the gate of the first switch 16 to turn off the first switch 16. Even if the first controller 1 outputs the first pulse signal or the abnormal signal, the output signal is not input to the OR circuit. The second controller 2 prevents the output voltage of the first controller 1 in which the abnormality has occurred from reaching the OR circuit 4 when the second cut unit 22 turns off the first switch 16.

The OR circuit 4 includes a first diode 18, a second diode 28, an input side switch 4a, a circuit resistor 4b, an output side switch 4c, and a circuit power supply 4d. The OR circuit 4 is a diode OR circuit. Details will be described later with reference to FIGS. 2 and 3, but when a high potential is applied to either or both of the first diode 18 and the second diode 28, a current is applied to the gate of the input side switch 4a. The input side switch 4a and the output side switch 4c are turned on, and the input voltage of the determination unit 6 becomes high (12V described later). When a low voltage is applied to the input side of both the first diode 18 and the second diode 28, no current flows through the gate of the input side switch 4a, and the input side switch 4a and the output side switch 4c are turned off. The input voltage of the determination unit 6 becomes low.

The determination unit 6 measures the number of pulses of the pulse signal output by the OR circuit 4 at predetermined time intervals by the pulse counter 6a. The determination unit 6 transmits an operation or stop instruction to the microcomputer 8a of the inverter 8 according to the measured number of pulses. When the number of pulses is within a predetermined range, a signal for stopping the operation of the inverter 8 is output to the microcomputer 8a, and when the number of pulses is outside the above range, a signal for stopping the operation of the inverter 8 is output to the microcomputer 8a. Is not output.

With reference to FIG. 2, the period and duty ratio of the first pulse signal output by the first output unit 11 and the second pulse signal output by the second output unit 21 will be described. FIG. 2A shows the waveform of the first pulse signal PS1 output by the first output unit 11 when the first controller 1 detects a state in which the operation of the inverter 8 needs to be stopped. FIG. 2B shows the waveform of the second pulse signal PS2 output by the second output unit 21 when the second controller 2 detects a state in which the operation of the inverter 8 needs to be stopped. The first pulse signal PS1 changes between the high potential H1 and the low potential L2. The second pulse signal PS2 changes between the high potential H2 and the low potential L2. The high potentials H1 and H2 are higher potentials than the gate threshold value of the input side switch 4a, and the low potentials L1 and L2 are lower potentials than the gate threshold value of the input side switch 4a.

As shown in FIGS. 2A and 2B, the duty ratios of the first pulse signal PS1 and the second pulse signal PS2 are both 50%. In one example, the frequency of the first pulse signal PS1 is 500 Hz, and the frequency of the second pulse signal PS2 is 1000 Hz. Therefore, the period T1 of the first pulse signal PS1 is twice the period T2 of the second pulse signal PS2. While the first pulse signal PS1 changes from the high potential H1 to the low potential L1 once, the second pulse signal PS2 changes twice from the high potential H2 to the low potential L2.

FIG. 2C shows the waveform of the synthetic pulse signal PSm1 generated by the OR circuit 4 (see FIG. 1). As described above, the OR circuit 4 (see FIG. 1) generates a high potential Hm1 when at least one of the first pulse signal PS1 and the second pulse signal PS2 has a high potential, and the first pulse signal. When both PS1 and the second pulse signal PS2 have a low potential, a low potential Lm1 is generated. The high potential Hm1 becomes 12V by the circuit power supply 4d.

The combined pulse signal PSm1 is transmitted to the pulse counter 6a of the determination unit 6. The pulse counter 6a of the determination unit 6 measures the number of pulses of the combined pulse signal PSm1 per predetermined time Dt. The predetermined time Dt is changed by the ability of the OR circuit 4 and the like, and is, for example, 6.4 ms. As shown in FIG. 2 (C), the number of pulses per predetermined time Dt of the combined pulse signal PSm1 obtained by combining the first pulse signal PS1 of FIG. 2 (A) and the second pulse signal PS2 of FIG. 2 (B) is There are four. The determination unit 6 (see FIG. 1) transmits a stop instruction to the microcomputer 8a of the inverter 8 when the number of pulses per predetermined time Dt is 2 or more and 9 or less. Therefore, when the determination unit 6 receives the first pulse signal PS1, the second pulse signal PS2, and the combined pulse signal PSm1 shown in FIGS. 2A to 2C, the operation of the inverter 8 is stopped. .. As described above, when the second controller 2 is normal and an abnormality occurs in the first controller 1, the second cut portion 22 of the second controller is the first in which the abnormality occurs by turning off the first switch. It prevents the output of the controller 1 from reaching the OR circuit 4. In that case, since the output of the first controller 1 drops to a low voltage, a combined pulse signal having the same number of pulses as the second pulse signal PS2 shown in FIG. 2B is transmitted to the OR circuit 4. Therefore, even if the second controller 2 is normal and an abnormality occurs in the first controller 1, the normal second controller 2 stops the operation of the inverter 8. Similarly, when the first controller 1 is normal and an abnormality occurs in the second controller 2, a combined pulse signal having the same number of pulses as the first pulse signal PS1 shown in FIG. 2 (A) is transmitted to the OR circuit 4. To. Therefore, even if the first controller 1 is normal and an abnormality occurs in the second controller 2, the normal first controller 1 stops the operation of the inverter 8.

The number of pulses of the first pulse signal PS1 is 4, and the number of pulses of the second pulse signal PS2 is 7. The operation stop device 10 of the embodiment stops the operation of the inverter 8 when the number of pulses of the combined pulse signal is 2 or more and 9 or less in order to cope with the variation in the measurement timing of the pulse counter 6a. .. By expanding the range of the number of pulses for stopping the operation of the inverter 8 in this way, the operation stop device 10 stops the operation of the inverter 8 even when an abnormality occurs in the first controller 1 or the second controller 2. It's easy to do.

The number of pulses of the combined pulse signal PSm2 generated by the OR circuit 4 (see FIG. 1) will be described with reference to FIG. In FIG. 2, the first pulse signal PS1 and the second pulse signal PS2 are expressed in synchronization with each other, but the first pulse signal PS1 and the second pulse signal PS2 of the operation stop device 10 of the embodiment are not synchronized. Therefore, the timings of the high potential H2 and the low potential L2 of the second pulse signal PS2 may be deviated from the high potential H1 and the low potential L1 of the first pulse signal PS1. In FIG. 3B, the timings of the high potential H2 and the low potential L2 of the second pulse signal PS2 are expressed differently from those in FIG. 2B.

In FIG. 3, the timing of the high potential H2 of the second pulse signal PS2 matches the timing of the low potential L1 of the first pulse signal PS1. As described above, since the OR circuit 4 (see FIG. 1) generates a high potential Hm2 when at least one of the first pulse signal PS1 and the second pulse signal PS2 has a high potential, it is a combined pulse signal. PSm2 has the waveform shown in FIG. 3 (C). The number of pulses per predetermined time Dt of the combined pulse signal PSm2 is 7. In this way, even when the timing of the second pulse signal PS2 is deviated from that of the first pulse signal PS1, the number of pulses per predetermined time Dt of the combined pulse signal PSm2 is the same as that of the second pulse signal PS2. It is an individual. That is, even when the timing of the second pulse signal PS2 deviates from that of the first pulse signal PS1, the determination unit 6 (see FIG. 1) may stop the operation of the inverter 8 (see FIG. 1). it can.

Further, as described above, the first pulse signal PS1 and the second pulse signal PS2 are not synchronized. Therefore, if the same period is set for the first pulse signal PS1 and the second pulse signal PS2, the timing of the high potential H1 of the first pulse signal PS1 and the timing of the low potential L2 of the second pulse signal PS2 are completely aligned. In the case of duplication, the combined pulse signal PSm can always be a high potential Hm. In that case, the number of pulses of the combined pulse signal PSm becomes zero. When the number of pulses of the combined pulse signal PSm is zero, the determination unit 6 continues the operation of the inverter 8. In this way, when the cycles of the first pulse signal PS1 and the second pulse signal PS2 are the same, even when the first controller 1 and the second controller 2 determine that the operation of the inverter 8 should be stopped. There is a possibility that the determination unit 6 continues the operation of the inverter 8 due to the unintended combined pulse signal PSm. In the operation stop device 10 of the embodiment, the operation of the inverter 8 is stopped by the number of pulses of the combined pulse signal obtained by combining the first pulse signal PS1 and the second pulse signal PS2 having different cycles, so that the number of pulses of the combined pulse signal is increased. Prevent it from becoming unintended.

The timing of each pulse signal when the first controller 1 and the second controller 2 are normal will be described with reference to FIG. “OK” in FIG. 4A indicates that the determination of the first monitoring unit 13 of the first controller 1 is in a normal state. That is, "OK" in FIG. 4A indicates that the second controller 2 is normal. “NG” in FIG. 4A indicates that the determination of the first monitoring unit 13 of the first controller 1 is abnormal. That is, "NG" in FIG. 4A indicates that an abnormality has occurred in the second controller 2. Similarly, FIG. 4B shows the monitoring status of the second monitoring unit 23 of the second controller 2. That is, FIG. 4B shows the state of the first controller 1. In FIGS. 4A and 4B, both the first controller 1 and the second controller 2 are normal.

4 (C) and 4 (D) show the on / off states of the first switch 16 and the second switch 26. In FIGS. 4C and 4D, since the first controller 1 and the second controller 2 are normal, both the first switch 16 and the second switch 26 are “on”.

A case where an abnormality occurs in the inverter 8 at time t1 and the voltage measurement value of the microcomputer 8a exceeds the threshold value will be described. As described with reference to FIG. 1, the first controller 1 acquires information ES1 such as the voltage value of the inverter 8 from the microcomputer 8a. The second controller 2 also acquires the information ES2 in the same manner. When the voltage value included in the information ES1 exceeds the threshold value, the first controller 1 outputs the first pulse signal PS1 having the period T1 in order to stop the operation of the inverter 8 (see FIG. 4E). Note that in FIGS. 4 and 5, the individual waveforms of each pulse signal are not represented, the period during which each pulse signal is output is represented by H, and the period during which each pulse signal is not output is represented by L. ing. The second controller 2 also outputs the second pulse signal PS2 having a period T2 when the voltage value included in the information ES2 exceeds the threshold value (see FIG. 4F). As shown in FIG. 4 (G), the OR circuit 4 generates a combined pulse signal PSm in which the first pulse signal PS1 and the second pulse signal PS2 are combined. The combined pulse signal PSm has a period Tm in which the period T1 and the period T2 are combined.

As described above, the determination unit 6 (see FIG. 1) that has received the combined pulse signal PSm from the OR circuit 4 (see FIG. 1) measures the number of pulses of the combined pulse signal PSm. As described with reference to FIGS. 2 and 3, the number of pulses of the combined pulse signal PSm is 4 or 7. That is, the number of pulses of the combined pulse signal PSm is 2 or more and 9 or less. Therefore, the determination unit 6 stops the operation of the inverter 8 based on the number of pulses of the combined pulse signal PSm.

FIG. 4 shows a case where the voltage values included in the information ES1 and ES2 are equal to or less than the threshold value at time t2. In this case, at time t2, the first controller 1 stops the output of the first pulse signal, and the second controller 2 stops the output of the second pulse signal. As a result, the number of pulses of the combined pulse signal PSm becomes zero. When the number of pulses of the combined pulse signal PSm is zero, the number of pulses is 2 or less, so that the determination unit 6 restarts the operation of the inverter 8.

In FIG. 4, for easy understanding, the output start time of the first pulse signal PS1, the output start time of the second pulse signal PS2, the output start time of the combined pulse signal PSm, and the operation stop time of the inverter 8 are all set. It is expressed according to the time t1. However, depending on the time required for the determination unit 6 to determine the number of pulses of the combined pulse signal PSm, the timing at which the inverter 8 in FIG. 4 (H) is turned off may be later than the time t1. Similarly, the timing for restarting the operation of the inverter 8 may be later than the time t2.

With reference to FIGS. 5 and 6, the timing of each pulse signal when the first controller 1 is normal and an abnormality occurs in the second controller 2 will be described. FIG. 5 shows a case where the voltages included in the information ES1 and ES2 from the microcomputer 8a of the inverter 8 are within the threshold value. In FIG. 5, since it is not necessary to stop the operation of the inverter 8 (see FIG. 1), the first controller 1 does not output the first pulse signal, and the second controller 2 does not output the second pulse signal. However, if an abnormality occurs in the second controller 2 at time t3, the abnormal pulse signal WP may be output thereafter as shown in FIG. 5 (F). The anomalous pulse signal has a period Tw different from the period T1 and the period T2. When the abnormal pulse signal WP is transmitted to the OR circuit 4, the OR circuit 4 generates a combined pulse signal PSm in which the low potential L output by the first output unit 11 and the abnormal pulse signal WP are combined. Since the first output unit 11 is fixed at the low potential L, the combined pulse signal PSm has the same period Tw as the abnormal pulse signal WP. The combined pulse signal PSm is transmitted to the pulse counter 6a of the determination unit 6 (see FIG. 1). When the number of pulses of the combined pulse signal PSm measured by the pulse counter 6a is 2 or more and 9 or less, the determination unit 6 stops the operation of the inverter 8. When the number of pulses of the combined pulse signal is 2 or less or 9 or more, the determination unit 6 continues the operation of the inverter 8. As can be understood from the above explanation, according to the technique of simply using the first pulse signal, the second pulse signal, and the OR circuit, when one of the controllers becomes abnormal, the other controller is normal. Moreover, the inverter will be stopped until it is not necessary to stop the inverter.

As described above, the first monitoring unit 13 determines that an abnormality has occurred in the second controller 2 when the survival notification from the second monitoring unit 23 of the second controller 2 is not received. FIG. 5 shows a case where the first monitoring unit 13 determines the occurrence of an abnormality in the second controller at time t4. When the first monitoring unit 13 determines that an abnormality has occurred in the second controller 2, the first monitoring unit transmits an abnormality determination to the first cut unit 12. When the first cut unit 12 receives the abnormality determination, the second switch 26 is turned off so that the abnormality pulse signal WP output by the second output unit 21 is not input to the OR circuit 4. As mentioned earlier, the second switch 26 is off unless it is turned on. As a result, after the time t4, as shown in FIG. 5 (G), the calculation result of the OR circuit 4 is fixed at the low potential L. When the calculation result of the OR circuit 4 is fixed to the low potential L, the number of pulses becomes zero, so that the determination unit 6 restarts the operation of the inverter 8. As described above, the operation stop device 10 of the embodiment is prevented from unnecessarily stopping the operation of the inverter even if an abnormality occurs in the second controller 2.

With reference to FIG. 6, the timing of each pulse signal when an abnormality occurs in the second controller 2 at time t6 while the operation of the inverter 8 is stopped will be described. FIG. 5 shows a case where the voltages included in the information ES1 and ES2 from the microcomputer 8a of the inverter 8 exceed the threshold value at the time t5, and as shown in FIG. 6 (E), the first output unit 11 , The first pulse signal PS1 of the period T1 is output in order to stop the operation of the inverter 8. Similarly, at time t5, the second output unit 21 outputs the second pulse signal PS2 having the period T2. The OR circuit 4 synthesizes the first pulse signal PS1 and the second pulse signal PS2 to generate a combined pulse signal PSm, and transmits the combined pulse signal PSm to the pulse counter 6a (see FIG. 1) of the determination unit 6. As described with reference to FIGS. 2 and 3, the number of pulses of the combined pulse signal PSm obtained by combining the first pulse signal PS1 and the second pulse signal PS2 is 2 or more and 9 or less. Stop the operation of the inverter 8.

If an abnormality occurs in the second controller 2 at time t6, the second output unit 21 of the second controller 2 may output an abnormal pulse signal WP. For easy understanding, in FIG. 6, the height of the abnormal pulse signal WP is expressed by being offset from the first pulse signal PS1 and the second pulse signal PS2. The period Tw of the abnormal pulse signal WP cannot be controlled. Therefore, the period Tw1 of the combined pulse signal PSm, which is a combination of the first pulse signal PS1 and the abnormal pulse signal WP, cannot be controlled. However, as described above, the determination unit 6 stops the operation of the inverter 8 when the number of pulses of the combined pulse signal is 2 or more and 9 or less. Therefore, when the number of pulses of the combined pulse signal PSm is 2 or more and 9 or less, the determination unit 6 normally stops the operation of the inverter 8 even if an abnormality occurs in the second controller 2. .. Further, although not shown, the second output unit 21 of the second controller 2 in which an abnormality has occurred may output nothing. Even in that case, since the combined pulse signal PSm obtained by combining the first pulse signal PS1 and the low potential L is transmitted to the OR circuit 4, the determination unit 6 stops the operation of the inverter 8.

At time t7, when the first monitoring unit 13 (see FIG. 1) determines the abnormality of the second controller 2, the first cut unit 12 turns off the second switch 26 and the second switch 26 is turned off, as described above. The output of the abnormal pulse signal WP of the second output unit 21 of the controller 2 is cut. As a result, the first cut portion 12 prevents the abnormal pulse signal WP from reaching the OR circuit 4. As a result, the first pulse signal PS1 and the low potential L are transmitted to the OR circuit 4. The OR circuit 4 generates a combined pulse signal PSm that combines the first pulse signal PS1 and the low potential L. This combined pulse signal PSm has the same waveform as the first pulse signal PS1, and as described in FIG. 2A, the number of pulses per predetermined time Dt is 4, so that the determination unit 6 determines the time t7. In, the operation of the inverter 8 is stopped. After that, when the voltage of the inverter 8 falls within the threshold value, the first output unit 11 stops the output of the first pulse signal PS1 at time t8. As a result, the determination unit 6 restarts the operation of the inverter 8.

The points to be noted in the examples are described below. As described above, the first controller 1 acquires the information ES1 from the microcomputer 8a of the inverter 8 and outputs the first pulse signal PS1 when the operation of the inverter 8 should be stopped. In the operation stop device 10 of the embodiment, the second controller 2 acquires the same information ES2 as the information ES1 from the microcomputer 8a of the inverter 8, and outputs the second pulse signal PS2 when the operation of the inverter 8 should be stopped. To do. However, the information ES1 and the information ES2 may be different information. In this case, the first controller 1 outputs the first pulse signal PS1 based on the information ES1, but the second controller 2 does not output the second pulse signal PS2 based on the information ES2.

Further, in the operation stop device 10 of the embodiment, the first switch 16 and the second switch 26 are composed of transistor switches, but the present invention is not limited to this, and the first switch 16 and the second switch 26 are general-purpose bus switches. It may be configured by a circuit. Further, the first switch 16 may be provided by the first controller 1, and the second switch 26 may be provided by the second controller 2. Further, the OR circuit 4 converts the 5V signal voltage of the calculation result into 12V by the circuit power supply 4d and transmits it to the pulse counter 6a of the determination unit 6. However, the techniques disclosed herein are not limited to this, and the signal voltage need not be converted to 12V.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: 1st controller 2: 2nd controller 4: OR circuit 4a: Input side switch 4b: Circuit resistance 4c: Output side switch 4d: Circuit power supply 6: Judgment unit 6a: Pulse counter 8: Inverter 8a: Microcomputer 10: Stop operation Device 11: 1st output unit 12: 1st cut unit 13: 1st monitoring unit 14: 1st resistance 16: 1st switch 18: 1st diode 21: 2nd output unit 22: 2nd cut unit 23: 2nd Monitoring unit 24: 2nd resistor 26: 2nd switch 28: 2nd diode

Claims (1)

An inverter operation stop device including a first controller, a first switch, a second controller, a second switch, an OR circuit, and a determination unit.
The output terminal of the first controller is connected to one input terminal of the OR circuit via the first switch.
The output terminal of the second controller is connected to the other input terminal of the OR circuit via the second switch.
The output terminal of the OR circuit is connected to the determination unit, and is connected to the determination unit.
The first controller outputs a first pulse signal when it detects a state in which the operation of the inverter is stopped, and when the first controller is normal and the second controller detects an abnormal state, the second switch is turned on. Execute the process to turn off,
The second controller outputs a second pulse signal when it detects a state in which the operation of the inverter is stopped, and when the first controller detects an abnormality and the second controller detects a normal state, the first switch is turned on. Execute the process to turn off,
The determination unit executes a process of stopping the operation of the inverter when the number of pulses of the pulse signal output by the OR circuit within a predetermined time is within a predetermined range.
The frequency of the first pulse signal is different from the frequency of the second pulse signal.
Each of the first pulse signal and the second pulse signal is an inverter operation stop device, wherein the number of pulses within the predetermined time is within the predetermined range.

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