JP2021065079A - Switching control circuit and power source circuit - Google Patents

Abstract

To provide a switching control circuit that can operate a switching power source circuit in a suitable operation mode.SOLUTION: A switching power source circuit includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, and a transistor controlling the current of the primary coil. The switching power source circuit operates based on the power source voltage according to the voltage from the auxiliary coil of the power source circuit, and controls the switching of the transistor. A control IC 40 includes a driving signal output circuit that outputs a driving signal according to the operation mode of the power source circuit, a driving circuit that switches the transistor on the basis of the output from the driving signal output circuit, and a control circuit that includes a first transition condition including time in a condition and a second transition condition not including time in the condition, and when the first transition condition or the second transition condition is satisfied, causes the driving signal output circuit to output the driving signal that operates the power source circuit in a first burst mode.SELECTED DRAWING: Figure 2

Description

The present invention relates to a switching control circuit and a power supply circuit.

The switching power supply circuit includes a circuit that operates in a burst mode in which the switching operation is intermittently stopped in order to increase the efficiency at the time of a light load (for example, Patent Document 1).

JP-A-2017-147854

By the way, when the power supply voltage to the control circuit of the switching power supply circuit is generated based on the switching operation, the power supply voltage must be changed from the normal mode to the burst mode at an appropriate timing. May decrease and the control circuit may not operate normally.

Further, for example, if the switching power supply circuit continues to operate in the burst mode when the load changes transiently, the output voltage may deviate significantly from the target level.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a switching control circuit capable of operating a switching power supply circuit in an appropriate operation mode.

The first aspect of the present invention for solving the above-mentioned problems is that the primary coil provided on the primary side, the secondary coil provided on the secondary side, and electromagnetic waves are applied to the primary coil or the secondary coil. A power supply corresponding to the voltage from the auxiliary coil of the power supply circuit that includes a transformer including a coupled auxiliary coil and a transistor that controls the current of the primary coil and generates an output voltage of a target level on the secondary side. A switching control circuit that operates based on a voltage and controls switching of the transistor, and is based on a drive signal output circuit that outputs a drive signal according to an operation mode of the power supply circuit and an output of the drive signal output circuit. When the drive circuit for switching the transistor, the first transition condition including time and the second transition condition not including time are satisfied, and the first transition condition or the second transition condition is satisfied. A control circuit for outputting the drive signal for operating the power supply circuit in the first burst mode to the drive signal output circuit.

A second aspect of the present invention includes a primary coil provided on the primary side, a secondary coil provided on the secondary side, and an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil. Operates based on the power supply voltage corresponding to the voltage from the auxiliary coil of the power supply circuit including the transformer including the above and the transistor for controlling the current of the primary coil and generating the output voltage of the target level on the secondary side. , A switching control circuit that controls switching of the transistor, the drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and the transistor are switched based on the output of the drive signal output circuit. When the power consumption of the load decreases while the drive circuit and the power supply circuit are operating in the normal mode, the power supply circuit is operated in the operation mode corresponding to the power consumption of the load among the plurality of burst modes. The drive signal is output to the drive signal output circuit, and the power consumption of the load is consumed when the power supply circuit is operating in an operation mode corresponding to the load, which consumes the least power among the plurality of burst modes. When the number increases, a control circuit for outputting the drive signal for operating the power supply circuit in the normal mode to the drive signal output circuit is provided.

A third aspect of the present invention includes a primary coil provided on the primary side, a secondary coil provided on the secondary side, and an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil. A target level including a transformer including, a transistor for controlling the current of the primary coil, and a switching control circuit which operates based on a power supply voltage corresponding to a voltage from the auxiliary coil and controls switching of the transistor. It is a power supply circuit that generates the output voltage of the above on the secondary side, and the switching control circuit is a drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and the output of the drive signal output circuit. Based on this, it has a drive circuit that switches the transistor, a first transition condition that includes time as a condition, and a second transition condition that does not include time, and satisfies the first transition condition or the second transition condition. A control circuit for outputting the drive signal for operating the power supply circuit in the first burst mode to the drive signal output circuit.

A fourth aspect of the present invention includes a primary coil provided on the primary side, a secondary coil provided on the secondary side, and an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil. A target level including a transformer including, a transistor for controlling the current of the primary coil, and a switching control circuit which operates based on a power supply voltage corresponding to a voltage from the auxiliary coil and controls switching of the transistor. It is a power supply circuit that generates the output voltage of the above on the secondary side, and the switching control circuit is a drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and the output of the drive signal output circuit. Based on this, when the power consumption of the load is reduced while the drive circuit for switching the transistor and the power supply circuit are operating in the normal mode, an operation mode corresponding to the power consumption of the load is selected among the plurality of burst modes. The drive signal for operating the power supply circuit is output to the drive signal output circuit, and the power supply circuit operates in an operation mode corresponding to the load, which consumes the least power among the plurality of burst modes. When the power consumption of the load increases, a control circuit for outputting the drive signal for operating the power supply circuit in the normal mode to the drive signal output circuit is provided.

According to the present invention, it is possible to provide a switching control circuit capable of operating a switching power supply circuit in an appropriate operation mode.

It is a figure which shows an example of a switching power supply circuit 10. It is a figure which shows an example of the control IC 40. It is a figure which shows an example of the drive signal output circuit 75. It is a figure for demonstrating the signals Va1 and Va2. It is a figure for demonstrating the relationship between a gain and a switching frequency. It is a figure for demonstrating the generation timing of signals Vb1 and Vb2. It is a figure for demonstrating the pulse signals Vp1 and Vp2. It is a figure for demonstrating the efficiency of a switching power supply circuit 10. It is a figure for demonstrating the transition condition of the operation mode. It is a state transition diagram of the operation mode. It is a state transition table of the operation mode. It is a figure for demonstrating operation of a switching power supply circuit 10.

The description of this specification and the accompanying drawings will clarify at least the following matters.

===== This embodiment =====
<<< Outline of switching power supply circuit 10 >>>
FIG. 1 is a diagram showing a configuration of a switching power supply circuit 10 according to an embodiment of the present invention. The switching power supply circuit 10 is an LLC current resonance type converter that generates an output voltage Vout of a target level on the load 11 from a predetermined input voltage Vin.

The switching power supply circuit 10 includes capacitors 20, 21, 32, NMOS transistors 22, 23, a transformer 24, a control block 25, diodes 30, 31, a constant voltage circuit 33, and a light emitting diode 34.

The capacitor 20 stabilizes the voltage between the power supply line to which the input voltage Vin is applied and the ground line on the ground side, and removes noise and the like. The input voltage Vin is a DC voltage of a predetermined level. The capacitor 21 is a so-called resonance capacitor that constitutes a resonance circuit with a leakage inductance (leakage inductance) between the primary coils L1 and the secondary coils L2 and L3.

The NMOS transistor 22 is a power transistor on the high side, and the NMOS transistor 23 is a power transistor on the low side. In this embodiment, the NMOS transistors 22 and 23 are used as the switching element, but they may be, for example, a MIMO transistor or a bipolar transistor.

The transformer 24 includes a primary coil L1, a secondary coil L2 and L3, and an auxiliary coil L4, and the primary coil L1, the secondary coils L2 and L3, and the auxiliary coil L4 are insulated from each other. In the transformer 24, a voltage is generated in the secondary coils L2 and L3 on the secondary side according to the change in the voltage across the primary coil L1 on the primary side. Similarly, the voltage of the auxiliary coil L4 on the primary side is generated according to the change in the voltage across the primary coil L1 on the primary side and the change in the voltage of the secondary coils L2 and L3.

Further, in the primary coil L1, the source of the NMOS transistor 22 and the drain of the NMOS transistor 23 are connected to one end, and the source of the NMOS transistor 23 is connected to the other end via the capacitor 21.

Therefore, when the switching of the NMOS transistors 22 and 23 is started, the voltages of the secondary coils L2 and L3 and the auxiliary coils L4 change. The primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with the same polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are also electromagnetically coupled with the same polarity.

The control block 25 is a circuit block for controlling the switching of the NMOS transistors 22 and 23, and the details will be described later.

The diodes 30 and 31 rectify the voltage of the secondary coils L2 and L3, and the capacitor 32 smoothes the rectified voltage. As a result, a smoothed output voltage Vout is generated in the capacitor 32. The output voltage Vout is a DC voltage of a target level.

The constant voltage circuit 33 is a circuit that generates a constant DC voltage, and is configured by using, for example, a shunt regulator.

The light emitting diode 34 is an element that emits light having an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 33, and constitutes a photocoupler together with the phototransistor 59 described later. In the present embodiment, the higher the level of the output voltage Vout, the stronger the intensity of the light from the light emitting diode 34.

<<< Control block 25 >>
The control block 25 includes a control IC 40, capacitors 50 to 54, resistors 55 to 57, a diode 58, and a phototransistor 59.

The control IC 40 is an integrated circuit that controls switching of the NMOS transistors 22 and 23, and has terminals VCS, GND, FB, IS, CA, HO, and LO. The control IC 40 corresponds to a "switching control circuit".

The terminal VCS is a terminal to which a power supply voltage Vcc for operating the control IC 40 is applied. A capacitor 52 whose one end is grounded and a cathode of a diode 58 are connected to the terminal VCS. Therefore, the capacitor 52 is charged by the current from the diode 58, and the charging voltage of the capacitor 52 becomes the power supply voltage Vcc for operating the control IC 40. The control IC 40 is started by applying a voltage dividing voltage of an input voltage Vin that rectifies an AC input via a terminal (not shown), and after being started, operates based on a power supply voltage Vcc.

The terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, a housing of a device provided with a switching power supply circuit 10.

The terminal FB is a terminal where a feedback voltage Vfb corresponding to the output voltage Vout is generated, and a capacitor 53 and a phototransistor 59 are connected to the terminal FB. The capacitor 53 is provided to remove noise between the terminal FB and the ground, and the phototransistor 59 grounds a bias current I1 having a magnitude corresponding to the intensity of the light from the light emitting diode 34 from the terminal FB. Flush to. Therefore, the phototransistor 59 operates as a transistor that generates a sink current.

The terminal IS is a terminal for detecting the current value of the resonance current of the primary coil L1. Here, a voltage corresponding to the current value of the resonance current of the primary coil L1 is generated at the node to which the capacitor 50 and the resistor 55 are connected. The resistor 56 and the capacitor 51 form a low-pass filter. Therefore, a voltage from which noise components have been removed is applied to the terminal IS according to the current value of the resonance current of the primary coil L1.

The terminal CA is a terminal that is generated based on the resonance current of the primary coil L1 and to which a voltage Vca corresponding to the input power of the switching power supply circuit 10 is applied. Although the details will be described later, the capacitor 54 and the resistor 57 are connected to the terminal CA.

The terminal HO is a terminal to which the signal Vo1 for driving the NMOS transistor 22 is output, and the gate of the NMOS transistor 22 is connected to the terminal HO.

The terminal LO is a terminal to which the signal Vo2 for driving the NMOS transistor 23 is output, and the gate of the NMOS transistor 23 is connected to the terminal LO.

<<< Details of control IC40 >>>
FIG. 2 is a diagram showing the configuration of the control IC 40. The control IC 40 includes a resistor 70, AD converters 71 and 73, a load detection circuit 72, a comparator 74, a drive signal output circuit 75, a control circuit 76, and a drive circuit 77. Note that the terminals VCS, GND, and IS are omitted here. Further, although the details will be described later, the drive signal output circuit 75 and the control circuit 76 are digital control circuits 78.

The resistor 70 generates a feedback voltage Vfb based on the bias current I1 from the phototransistor 59. A predetermined voltage Vdd is applied to one end of the resistor 70, and the other end is connected to the terminal FB. Therefore, assuming that the resistance value of the resistor 70 is “R”, the feedback voltage Vfb generated at the terminal FB is represented by the equation (1).

Vfb = Vdd-R × I1 ... (1)
As described above, in the present embodiment, the current value of the bias current I1 increases as the output voltage Vout increases. Therefore, when the output voltage Vout rises, the feedback voltage Vfb decreases.

The AD converter 71 converts the feedback voltage Vfb of the terminal FB into a digital value and outputs it. The load detection circuit 72 smoothes the voltage corresponding to the resonance current of the primary coil L1 detected by the terminal IS by the capacitor 54 and the resistor 57 connected to the terminal CA, and outputs the voltage as Vca.

Here, the current value of the resonance current of the primary coil L1 increases according to the input power of the switching power supply circuit 10, and the input power of the switching power supply circuit 10 increases according to the power consumed by the load 11. Therefore, the voltage Vca applied to the terminal CA shows a value that increases as the power consumption of the load 11 increases.

The AD converter 73 converts the voltage Vca output by the load detection circuit 72 into a digital value and outputs it. The comparator 74 detects a decrease in the power supply voltage Vcc.

The comparator 74 is a hysteresis comparator that compares the voltage V1 which is a high threshold voltage and the power supply voltage Vcc, and also compares the voltage V2 (<V1) which is a low threshold voltage and the power supply voltage Vcc.

When the power supply voltage Vcc decreases and becomes lower than the "voltage V2", the comparator 74 changes the voltage Vc indicating the comparison result to a low level (hereinafter referred to as "L level"). Further, when the power supply voltage Vcc rises and becomes higher than the "voltage V1", the comparator 74 changes the voltage Vc to a high level (hereinafter referred to as "H level").

The digital control circuit 78 is a circuit that outputs drive voltages Vdr1 and Vdr2 based on the feedback voltage Vfb, voltage Vca, and voltage Vc, and includes a drive signal output circuit 75 and a control circuit 76.

The drive signal output circuit 75 is a circuit that outputs drive signals Vdr1 and Vdr2 according to the operation mode of the switching power supply circuit 10 based on the control signal CONT from the control circuit 76.

Although details will be described later, the "operating mode" of the switching power supply circuit 10 of the present embodiment includes three modes: "normal mode", "high frequency burst mode", and "low frequency burst mode". is there.

The "normal mode" is, for example, a mode in which the switching operation is continuously performed and the switching operation is not stopped intermittently, and the "burst mode" is, for example, the switching operation is intermittently stopped. The mode.

Further, among the "burst modes", the "high frequency burst mode" is a mode in which the switching operation is intermittently stopped for a shorter period than the "low frequency burst mode". Therefore, when the "high frequency burst mode" and the "low frequency burst mode" are compared, the "low frequency burst mode" is preferable as the operation mode when the load 11 is a lighter load.

The control circuit 76 controls various operations of the drive signal output circuit 75 based on the control signal CONT. For example, the control circuit 76 has, for example, three “operation modes” with respect to the drive signal output circuit 75 based on the feedback voltage Vfd and the voltage Vca and the power supply voltage Vcc that change according to the power consumption of the load 11. Of these, the drive signals Vdr1 and Vdr2 corresponding to any of the modes are output. The details of the control circuit 76 will be described later.

The drive circuit 77 is a buffer that switches the NMOS transistors 22 and 23 based on the input drive signals Vdr1 and Vdr2. Specifically, the drive circuit 77 drives the NMOS transistor 22 with the signal Vo1 having the same logic level as the drive signal Vdr1, and drives the NMOS transistor 23 with the signal Vo2 having the same logic level as the drive signal Vdr2.

<< Details of drive signal output circuit 75 >>
FIG. 3 is a diagram showing an example of the configuration of the drive signal output circuit 75. The drive signal output circuit 75 includes an oscillation circuit 90, a buffer 91, an inverter 92, a low frequency burst control circuit 93, a timer 94, a pulse circuit 95, and a selector 96. Although not shown here for convenience, the control signal CONT is input to circuits other than the buffer 91 and the inverter 92 among the circuits of the drive signal output circuit 75.

== "Normal mode" signals Va1, Va2 ==
The oscillation circuit 90, the buffer 91, and the inverter 92 are blocks that output signals Va1 and Va2 for operating the switching power supply circuit 10 in the "normal mode" when the control signal CONT indicating the "normal mode" is input. Is.

The oscillation circuit 90 is a voltage control oscillation circuit that outputs an oscillation signal Vosc having a duty ratio of, for example, "H" level of 50% based on the input feedback voltage Vfb. The oscillation circuit 90 outputs a high frequency oscillation signal Vosc when the level of the feedback voltage Vfb becomes low. Further, the oscillation circuit 90 outputs an oscillation signal Vosc corresponding to the feedback voltage Vfb when a control signal CONT indicating "operation" is input, and an oscillation signal when a control signal CONT indicating "stop" is input. Stop the output of Vosc.

The buffer 91 outputs a signal having the same logic level as the oscillation signal Vosc, and the inverter 92 inverts the logic level of the oscillation signal Vosc and outputs the signal. As a result, the signals Va1 and Va for operating the switching power supply circuit 10 in the "normal mode" become signals having opposite phases to each other, for example, as shown in FIG.

Further, when the control signal CONT indicating the "normal mode" is input, the selector 96 selects the signals Va1 and Va2 which are the outputs of the buffer 91 and the inverter 92, and outputs them as the drive signals Vdr1 and Vdr2. As a result, the NMOS transistors 22 and 23 are driven based on the signals Va1 and Va2 in the "normal mode".

When the switching power supply circuit 10 is operating in the "normal mode" and the level of the output voltage Vout rises above the target level, the feedback voltage Vfb drops, so that the frequency of the oscillation signal Vosc becomes high.

Here, for example, the relationship shown in FIG. 5 is established between the gain (= Vout / Vin) of the switching power supply circuit 10 which is an LLC current resonance type converter and the switching frequency. Then, in this embodiment, the frequency of the oscillation signal Vosc is designed to be higher than the resonance frequency of the switching power supply circuit 10. As a result, when the feedback voltage Vfb decreases and the frequency of the oscillation signal Vosc increases, the output voltage Vout decreases.

On the other hand, when the level of the output voltage Vout is lower than the target level, the feedback voltage Vfb rises, so that the frequency of the oscillation signal Vosc becomes lower. As a result, the output voltage Vout of the switching power supply circuit 10 rises. Therefore, when the switching power supply circuit 10 is operating in the "normal mode", the switching power supply circuit 10 can generate an output voltage Vout of a target level.

== "Low frequency burst mode" signals Vb1, Vb2 ==
The oscillation circuit 90, the buffer 91, the inverter 92, and the low frequency burst control circuit 93 operate the switching power supply circuit 10 in the "low frequency burst mode" when the control signal CONT indicating the "low frequency burst mode" is input. This is a block that outputs signals Vb1 and Vb2 for causing the oscillation.

The low frequency burst control circuit 93 is a circuit that controls the operation of the oscillation circuit 90 so that the switching cycle is intermittently stopped. When the feedback voltage Vfb rises and becomes higher than the “voltage V3”, the low-frequency burst control circuit 93 operates the oscillation circuit 90 to generate an oscillation signal Vosc according to the feedback voltage Vfb.

On the other hand, the low frequency burst control circuit 93 stops the operation of the oscillation circuit 90 when the feedback voltage Vfb drops and becomes lower than the “voltage V4”.

FIG. 6 is a diagram for explaining the timing at which the signals Vb1 and Vb2 in the “low frequency burst mode” are generated.

For example, at time t10, when the feedback voltage Vfb rises to “voltage V3”, the oscillation signal Vosc is generated. Then, the buffer 91 outputs a signal Vb1 having the same logic level as the oscillation signal Vosc, and the inverter 92 outputs a signal Vb2 in which the logic level of the oscillation signal Vosc is inverted. As a result, the signals Vb1 and Vb2 in the "low frequency burst mode" have the same waveforms as the signals Va1 and Va2 shown in FIG.

Further, when the control signal CONT indicating "low frequency burst mode" is input, the selector 96 selects the signals Vb1 and Vb2 which are the outputs of the buffer 91 and the inverter 92, and outputs them as the drive signals Vdr1 and Vdr2. As a result, the NMOS transistors 22 and 23 are driven based on the signals Vb1 and Vb2 in the "low frequency burst mode".

When the NMOS transistors 22 and 23 are driven at the time t10, the output voltage Vout rises, so that the feedback voltage Vfb falls slightly later than the time t10. Then, for example, when the feedback voltage Vfb drops to “voltage V4” at time t11, the generation of the oscillation signal Vosc is stopped.

As a result, the switching of the NMOS transistors 22 and 23 is also stopped, so that the output voltage Vout drops. Then, the feedback voltage Vfb rises slightly after the time t11. For example, when the feedback voltage Vfb becomes the “voltage V3” at the time t12, the oscillation signal Vosc is generated. As a result, the NMOS transistors 22 and 23 are driven based on the signals Vb1 and Vb2. The operation from time t12 to time t10 to time 12 is repeated.

In this way, the low-frequency burst control circuit 93 operates the switching power supply circuit 10 in the "low-frequency burst mode" by controlling the oscillation circuit 90 based on the control signal CONT indicating the "low-frequency burst mode". Can be made to.

The period from time t10 to t12 in FIG. 6 is the period Ta indicating one cycle of the “low frequency burst mode”. Then, in the present embodiment, the resistances of the voltage V3 and the voltage V4 and the resistor 70 that generates the feedback voltage Vfb so that the "stop period" in which the switching is stopped is sufficiently longer than the "switching period" in the period Ta. The value R (see FIG. 2) and is set.

== "High frequency burst mode" pulse signals Vp1, Vp2 ==
The timer 94 and the pulse circuit 95 are blocks that output pulse signals Vp1 and Vp2 for operating the switching power supply circuit 10 in the "high frequency burst mode" when the control signal CONT indicating the "high frequency burst mode" is input. Is.

The timer 94 repeatedly measures the period Tb of one cycle of the “high frequency burst mode”, for example, and the pulse circuit 95 repeatedly measures a total of three pulse signals Vp1 at predetermined timings within the period Tb based on the measurement time of the timer 94. , Vp2 is output.

FIG. 7 is a diagram for explaining the timing at which the pulse signals Vp1 and Vp2 in the “high frequency burst mode” are generated.

For example, when the timer 94 starts measuring the time at the time t20, the pulse circuit 95 outputs the “H” level pulse signal Vp2 until the timing at the time t21.

Here, when the control signal CONT indicating the "high frequency burst mode" is input, the selector 96 selects the pulse signals Vp1 and Vp2 and outputs them as the drive signals Vdr1 and Vdr2. Therefore, when the “H” level pulse signal Vp2 is output from time t20 to t21, the drive signal Vdr2 becomes the “H” level and the NMOS transistor 23 is turned on.

Further, based on the output of the timer 94, at the time t21, the pulse circuit 95 outputs the “H” level pulse signal Vp1 until the timing at the time t22. As a result, during the period from time t21 to t22, the drive signal Vdr1 becomes "H" level, and the NMOS transistor 22 is turned on.

Further, based on the output of the timer 94, at the time t22, the pulse circuit 95 outputs the “H” level pulse signal Vp2 until the timing at the time t23. As a result, during the period from time t21 to t22, the drive signal Vdr2 becomes “H” level, and the NMOS transistor 23 is turned on.

Then, based on the measurement time of the timer 94, the pulse circuit 95 stops the generation of the pulse signals Vp1 and Vp2 during the period from time t23 to t24. Further, when the time t20 becomes the time t24 when the period Tb has elapsed, the measurement time of the timer 94 is reset, so that the operations from the time t20 to t24 are repeated.

In this way, the timer 94 and the pulse circuit 95 generate the pulse signals Vp1 and Vp2 based on the control signal CONT indicating the "high frequency burst mode", thereby setting the switching power supply circuit 10 in the "high frequency burst mode". Can be operated.

In this embodiment, the "switching period" per unit time of the "high frequency burst mode" is designed to be sufficiently longer than the "switching period" per unit time of the "low frequency burst mode".

Therefore, in the present embodiment, among the above-mentioned three operation modes, each time the "normal mode" is shifted to the "high frequency burst mode" and the "high frequency burst mode" is shifted to the "low frequency burst mode", the unit is The "switching period" per hour is shortened. When the switching period is shortened, for example, the power consumption of the NMOS transistors 22 and 23 having a large gate capacitance and the drive circuit 77 becomes small.

As a result, for example, as shown in FIG. 8, as the power consumption of the load 11 decreases, the "operation mode" of the switching power supply circuit 10 is changed from the "normal mode" to the "high frequency burst mode" via the "low frequency". By shifting to the burst mode, the efficiency of the switching power supply circuit 10 can be improved in a wide range.

<< About control circuit 76 >>
The control circuit 76 of FIG. 2 is a state machine that controls various operations of the drive signal output circuit 75 based on the feedback voltage Vfb, the voltage Vca, and the voltage Vc. For example, the control circuit 76 generates a control signal CONT for switching the "operation mode" of the switching power supply circuit 10 according to the power consumption of the load 11. The "state machine" is, for example, a logic circuit that is logically synthesized so as to change the output state according to an input condition.

FIG. 9 is a diagram showing the relationship between the feedback voltage Vfb and the voltage Vca, which change according to the power consumption of the load 11, and the transition condition of the “operation mode”. Here, when the power consumption of the load 11 decreases, the output voltage Vout increases, so that the feedback voltage Vfb decreases. Further, the voltage Vca decreases as the power consumption of the load 11 decreases. In FIG. 9, only the relationship between the levels of the feedback voltage Vfb and the voltage Vca and the transition condition will be described. Therefore, the “transition time” when transitioning the “operation mode” will be described later.

In the present embodiment, for example, when the power consumption of the load 11 is large and the feedback voltage Vfb is higher than the voltage V5 or the voltage Vca is higher than the voltage V7, the "operation mode" is set to the "normal mode". Hereinafter, the case where the feedback voltage Vfb is higher than the voltage V5 or the voltage Vca is higher than the voltage V7 is defined as “condition 1”.

Further, when the power consumption of the load 11 becomes small, the feedback voltage Vfb becomes lower than the voltage V6 (<voltage V5), and the voltage Vca becomes lower than the voltage V8 (<voltage V7), the “operation mode” is changed to “high frequency”. Set to "burst mode". Hereinafter, the case where the feedback voltage Vfb is lower than the voltage V6 and the voltage Vca is lower than the voltage V8 is referred to as “condition 2”.

Further, when the power consumption of the load 11 becomes very small, the feedback voltage Vfb becomes lower than the voltage V6, and the voltage Vca becomes lower than the voltage V10 (<voltage V8), the "operation mode" is changed to the "low frequency burst mode". ". Hereinafter, the case where the feedback voltage Vfb is lower than the voltage V6 and the voltage Vca is lower than the voltage V10 is referred to as “condition 3”.

Further, the "operation mode" is the "low frequency burst mode", the power consumption of the load 11 becomes large, the feedback voltage Vfb becomes higher than the voltage V5 (> voltage V6), or the voltage Vca becomes the voltage V9 ( When it becomes higher than V8 <V9 <V10), the "operation mode" is set to the "normal mode". Hereinafter, the case where the feedback voltage Vfb is higher than the voltage V5 or the voltage Vca is higher than the voltage V8 is referred to as “condition 4”.

<< About state transition >>
FIG. 10 is a state transition diagram for explaining the relationship between the input condition to the control circuit 76 and the control signal CONT, and FIG. 11 is a state transition table.

<< Transition within "normal mode">>
Here, it is assumed that the input condition to the control circuit 76 satisfies "condition 1 (Vfb> V5 or Vca>V7)", and the "operation mode" is the "normal mode".

By the way, as described above, the voltage Vca input to the control circuit 76 is generated by smoothing the voltage corresponding to the resonance current of the primary coil L1 by the capacitor 54 and the resistor 57, so that the load 11 state. Does not change immediately even if is changed.

On the other hand, since the feedback voltage Vfb is a voltage generated by the current I1 from the phototransistor 59 and the resistor 70, when the state of the load 11 changes, it changes in a time shorter than the voltage Vca. Therefore, in the present embodiment, in the "normal mode", for example, when the load 11 becomes a light load, only the feedback voltage Vfb drops, and the voltage V20 falls below a predetermined level, a process of temporarily stopping the switching operation is executed. To. The "predetermined level" at which the switching operation is stopped corresponds to the "second level".

Specifically, in the "normal mode", when the feedback voltage Vfb drops below the voltage V20 of a predetermined level, the control circuit 76 outputs a control signal CONT indicating "stop" (process S10). As a result, since the operation of the oscillation circuit 90 of FIG. 3 is stopped, the switching operation is stopped and the overshoot of the output voltage Vout is suppressed.

Further, in the "normal mode", when the feedback voltage Vfb rises above the voltage V21 (> voltage V20) of a predetermined level, the control circuit 76 outputs a control signal CONT indicating "operation" (process S11). As a result, since the oscillation circuit 90 generates the oscillation signal Vosc, the switching operation is executed and the output voltage Vout of the target level is generated. In the present embodiment, the voltage V21 is a voltage lower than the voltage V6, and the relationship of V5> V6> V21> V20 is established between the voltages V5, V6, V20, and V21.

<< Transition from "normal mode" to "high frequency burst mode">>
By the way, for example, when the load 11 changes transiently and the "operating mode" of the switching power supply circuit 10 is immediately changed to another mode, the output voltage Vout may deviate significantly from the target level. is there.

Therefore, in the present embodiment, the control circuit 76 is made to determine whether or not the time when the load 11 becomes a light load becomes the "predetermined time Tx".

Therefore, in the control circuit 76, the load 11 becomes a light load, and the period in which the input condition to the control circuit 76 satisfies "condition 2 (Vfb <V6 and Vca <V8)" continues for "predetermined time Tx". Then, the control circuit 76 outputs a control signal CONT indicating "high frequency burst mode" (process S20).

As a result, the "operation mode" of the switching power supply circuit 10 shifts to the "high frequency burst mode".

<< Transition from "normal mode" to "low frequency burst mode">>
For example, the load 11 becomes a lighter load (or no load), the input condition to the control circuit 76 satisfies "condition 3 (Vfb <V6, and Vca <V10)", and "condition 3". When "" continues for "Tx for a predetermined time", the control circuit 76 outputs a control signal CONT indicating "low frequency burst mode" (process S21).

As a result, the "operation mode" of the switching power supply circuit 10 shifts to the "low frequency burst mode".

By the way, when the feedback voltage Vfb is lower than the voltage V20 of a predetermined level, the process S10 may be executed and the switching may be stopped. Then, when "condition 3 (Vfb <voltage V6 and Vca <voltage V10)" is satisfied, in the process S21, the operation of the "low frequency burst mode" does not start until the "predetermined time Tx" elapses, so that the power supply is supplied. The voltage Vcc may drop more than necessary and the control IC 40 may not operate properly.

Therefore, in the present embodiment, the feedback voltage Vfb is lower than the predetermined level voltage V20 even when the input condition to the control circuit 76 does not satisfy "Condition 3 (Vfb <V6 and Vca <V10)". When the process S10 is executed and the voltage Vc reaches the “L” level, that is, when the power supply voltage Vcc becomes lower than the “voltage V2”, the control circuit 76 outputs a control signal CONT indicating “low frequency burst mode” ( Process S22). The conditions under which the process S22 is executed (hereinafter referred to as "condition 5") are a feedback voltage Vfb <V20 and a power supply voltage Vcc <V2.

As a result, since the switching power supply circuit 10 operates in the "low frequency burst mode" before the "condition 3" is satisfied and the "predetermined time Tx" elapses, it is possible to prevent the power supply voltage Vcc from dropping more than necessary. Can be done.

In the present embodiment, for example, a state satisfying "condition 3 (Vfb <V6 and Vca <V10)" corresponds to a "light load state". Further, the process S21 corresponds to the "first transition condition" including the time, and the process S22 corresponds to the "second transition condition" not including the time. Further, the voltage V2 corresponds to the "first level", and the "low frequency burst mode" corresponds to the "first burst mode".

<<< Transition from "High Frequency Burst">>
When the switching power supply circuit 10 is operating in the "high frequency burst", the input condition to the control circuit 76 satisfies "condition 3 (Vfb <V6 and Vca <V10)" and "condition 3". When "" continues for "Tx for a predetermined time", the control circuit 76 outputs a control signal CONT indicating "low frequency burst mode" (process S30). As a result, the "operation mode" of the switching power supply circuit 10 shifts to the "low frequency burst mode".

Further, when the switching power supply circuit 10 is operating in the "high frequency burst", the time is not included in the "condition 5 (Vfb <V20 and Vcc)" as in the case of operating in the "low frequency burst". When "<V2)" is satisfied, the control circuit 76 outputs a control signal CONT indicating "low frequency burst mode" (process S31).

On the other hand, when the input condition to the control circuit 76 satisfies "condition 1 (Vfb> V5 or Vca> V7)", the control circuit 76 outputs a control signal CONT indicating "normal mode" (process S32). ). As a result, the "operation mode" of the switching power supply circuit 10 shifts to the "normal mode".

<<< Transition from "low frequency burst">>
When the switching power supply circuit 10 is operating in "low frequency burst" and the input condition to the control circuit 76 satisfies "condition 4 (Vfb> V5 or Vca>V9)", the control circuit 76 Outputs a control signal CONT indicating a "normal mode" (process S40). As a result, the "operation mode" of the switching power supply circuit 10 shifts to the "normal mode".

Although details will be described later, in the present embodiment, when the power consumption of the load 11 increases while the switching power supply circuit 10 is operating in the “low frequency burst mode”, the “operating mode” is changed to the “high frequency burst mode”. Transition to "normal mode" instead of "mode". When the switching power supply circuit 10 is operating in the "normal mode", the output voltage Vout can be stabilized in a short time. Therefore, in the present embodiment, when the power consumption of the load 11 increases, the transition from the “low frequency burst mode” to the “normal mode” is performed without shifting to the “high frequency burst mode”.

<< Waiting time after transition of "operation mode">>
As described above, when the input to the control circuit 76 satisfies a predetermined condition, the "operation mode" transitions, but the waiting time after the transition may be set. Specifically, the control circuit 76 prohibits input reception, that is, transition of the operation mode, until a predetermined "standby time T1 (first period)" elapses after the transition of the "operation mode". As a result, the control signal CONT indicating the "operation mode" continues to be output for at least the "standby time T1 (first period)". As a result, it is possible to prevent the "operation mode" from being switched more than necessary and the operation of the switching power supply circuit 10 from becoming unstable.

In the present embodiment, this "standby time T1" is set at the time of transition from the operation mode corresponding to the load with the lowest power consumption, that is, from the "normal mode" to the "low frequency burst mode" or the "high frequency burst mode". doing. Even if the "standby time T1" is set only at the time of transition from "normal mode" to "low frequency burst mode" or at the time of transition from "normal mode" to "high frequency burst mode". good.

=== Operation of switching power supply circuit 10 ===
FIG. 12 is a diagram for explaining the operation of the switching power supply circuit 10 when the state of the load 11 becomes a light load. Here, it is assumed that the switching power supply circuit 10 is operating in the "normal mode" before the time t30.

First, at time t30, when the state of the load 11 becomes a light load, the output voltage Vout rises, so that the feedback voltage Vfb decreases and the voltage Vca decreases.

Then, when the feedback voltage Vfb drops to "voltage V20" at time t31, the control circuit 76 outputs a control signal CONT indicating "stop" (process S10 in FIG. 10). As a result, the switching operation is stopped, and the rise in the output voltage Vout is stopped.

Further, when the "condition 3 (Vfb <V6 and Vca <V10)" is satisfied at the time t32, the control circuit 76 measures the "predetermined time Tx" in order to shift to the "low frequency burst mode". Start.

However, since the switching operation is stopped at time t31, the power supply voltage Vcc drops significantly. Since this timing is the timing before the "predetermined time Tx" elapses in order to shift to the "low frequency burst mode", the switching power supply circuit 10 does not operate.

At time t33, the power supply voltage Vcc drops, and at voltage V2, the control circuit 76 outputs a control signal CONT indicating "low frequency burst mode" (process S22 in FIG. 10). That is, the process S22 is executed before the condition 3 is satisfied and the predetermined time Tx elapses. As a result, the "operation mode" of the switching power supply circuit 10 transitions to the "low frequency burst mode".

Then, when the feedback voltage Vfb rises in response to the decrease in the output voltage Vout and reaches the voltage V3 at the time t34, the switching operation is performed. As a result, the power supply voltage Vcc rises, so that it is possible to prevent the power supply voltage Vcc of the control IC 40 from dropping more than necessary.

Further, when the switching operation is performed at the time t34, the output voltage Vout increases, so that the feedback voltage Vfb decreases. Further, as the output voltage Vout increases, the power consumption at the load 11 increases, so that the voltage Vca increases.

Then, when the feedback voltage Vfb drops at time t35 and reaches the voltage V4, the switching operation stops. As described above, when the load 11 is lightly loaded, the switching power supply circuit 10 operates in the "low frequency burst mode" because the switching is intermittently stopped, so that the output of the target level is output while increasing the efficiency. A voltage Vout can be generated.

Although not shown in FIG. 12, for example, when the power consumption of the load 11 increases after the time t36 when the standby time T1 elapses from the time t33, the output voltage Vout decreases and the feedback voltage Vfb increases. .. Then, when "condition 4 (Vfb> V5 or Vca> V9)" is satisfied, the control circuit 76 outputs a control signal CONT indicating "normal mode" (process S40 in FIG. 10). As a result, the switching power supply circuit 10 operates in the "normal mode".

Further, after t36, when Vca is high (Vca> V9), the control circuit 76 outputs a control signal CONT indicating "normal mode" (process S40 in FIG. 10). As a result, the switching power supply circuit 10 operates in the "normal mode".

When the switching power supply circuit 10 is operating in the "normal mode", the switching period is longer than when the switching power supply circuit 10 is operating in the "high frequency burst mode". Therefore, by changing the "operation mode" of the switching power supply circuit 10 from the "low frequency burst mode" to the "normal mode", the output voltage Vout can be increased even when the power consumption of the load 11 increases significantly. The decrease can be suppressed.

=== Others ===
For example, when the switching power supply circuit 10 is operating in the "normal mode" and the switching frequency becomes very high, the power consumption of the NMOS transistors 22, 23 and the like increases, so that the power supply voltage Vcc drops significantly. It may end up. Therefore, for example, the control circuit 76 may output a control signal CONT indicating a "low frequency burst mode" when the power supply voltage Vcc becomes lower than the "voltage V2".

That is, in the process S22 of FIG. 10, when the condition 5 (Vfb <V20 and Vcc <V2) "is satisfied, the transition to the" low frequency burst mode "is determined, but only the power supply voltage Vcc is lower than the voltage V2. In this case, the transition to the "low frequency burst mode" may be performed. With such a configuration, it is possible to prevent the power supply voltage Vcc of the control IC 40 from dropping more than necessary.

Further, the control IC 40 of the present embodiment is used in the switching power supply circuit 10 which is an LLC current resonance type converter, but the present invention is not limited to this, and may be used in, for example, a flyback type switching power supply circuit. In the switching power supply circuit 10, the NMOS transistors 22 and 23 that control the current of the primary coil L1 correspond to the first and second transistors.

Further, the control circuit 76 is a logic circuit that changes the control signal CONT according to the input condition, but the present invention is not limited to this, and for example, a microcomputer (control) that executes a program stored in a memory (not shown). Department) may be. Further, the drive signal output circuit 75 can also be realized by the functional block of the microcomputer (for example, the drive signal output unit). Even when such a microcomputer is used, the same functions as those in the present embodiment can be realized.

Further, in the present embodiment, the AD converters 71 and 73 convert the feedback voltage Vfb and the voltage Vca as digital values, and the digital control circuit 78 outputs the drive signals Vdr1 and Vdr2, but the present invention is limited to this. Absent. For example, the control IC 40 may include various analog circuits and digital circuits so as to output the same drive signals Vdr1 and Vdr2 as in the present embodiment based on the analog value feedback voltage Vfb and voltage Vca. Even in such a case, the same effect as that of the present embodiment can be obtained.

=== Summary ===
The switching power supply circuit 10 of the present embodiment has been described above. When the switching power supply circuit 10 is operating in the "normal mode", the "first transition condition" in which the condition 3 continues for the "predetermined time Tx" is satisfied, or corresponds to the "second transition condition". When the time-free condition 5 (Vfb <V20 and Vcc <V2) is satisfied, the switching power supply circuit 10 operates in the "low frequency burst mode". As a result, the efficiency of the switching power supply circuit 10 can be increased while suppressing a decrease in the power supply voltage Vcc, so that the switching power supply circuit 10 can be operated in an appropriate "operation mode".

Further, if the state in which the load 11 becomes a light load continues, as a result, for example, the condition 3 continues for "a predetermined time Tx", and the "first transition condition" is satisfied. Therefore, the switching power supply circuit 10 can surely shift to the "low frequency burst mode" when the load 11 continues to be in a light load state.

Further, for example, when the switching power supply circuit 10 is operating in the "normal mode", if the switching frequency becomes very high, the power supply voltage Vcc may drop significantly. For example, when the power supply voltage Vcc becomes lower than the “voltage V2 (first level)”, the transition to the “low frequency burst mode” can prevent the power supply voltage Vcc of the control IC 40 from dropping more than necessary. Therefore, with such a configuration, the switching power supply circuit 10 can be operated in an appropriate "operation mode".

Further, for example, when the power supply voltage Vcc becomes lower than the "voltage V2" in a state where the load 11 is a light load, the control circuit 76 shifts the "operation mode" to the "low frequency burst mode". Therefore, the efficiency of the switching power supply circuit 10 can be increased.

Further, in the present embodiment, whether or not the load 11 is a light load is determined based on, for example, whether or not "Condition 3 (Vfb <V6 and Vca <V10)" is satisfied, but this is limited to this. I can't. For example, the control circuit 76 may determine whether or not the load 11 is a light load based on either a state in which the feedback voltage Vfb is lower than the voltage V6 or a state in which the voltage Vca is lower than the voltage V10. good. Even in such a case, it can be accurately determined whether or not the load 11 is a light load.

Further, the control circuit 76 stops the switching operation when the output voltage Vout rises when the load 11 becomes a light load and the feedback voltage Vfb reaches a predetermined level voltage V20 (for example, the process of FIG. 10). S10). As a result, overshoot of the output voltage Vout can be suppressed. Further, when such a process S10 is executed, the power supply voltage Vcc drops significantly. In the present embodiment, when the power supply voltage Vcc becomes "voltage V2" before the light load state continues for "predetermined time Tx", the transition to "low frequency burst mode" is immediately performed. Therefore, it is possible to prevent the power supply voltage Vcc from dropping significantly.

Further, when the switching power supply circuit 10 is operating in the "normal mode", the control circuit 76 sets the "operating mode" to the "high frequency burst mode" or the "low frequency burst" according to the power consumption of the load 11. Change to "mode". On the other hand, when the switching power supply circuit 10 is operating in the "low frequency mode", the control circuit 76 always changes the "operating mode" to the "normal mode" when the power consumption of the load 11 increases. As a result, the power consumption of the load 11 increases, and the output voltage Vout when the load becomes heavy can be further stabilized.

Further, the control circuit 76 does not change the "operation mode" at the time of transition from the "normal mode" to the "high frequency burst mode or low frequency burst mode" until at least a predetermined "standby time T1" elapses. Therefore, it is possible to prevent the operation mode of the switching power supply circuit 10 from being switched more than necessary and the operation of the switching power supply circuit 10 from becoming unstable.

As described above, in the present embodiment, the "operation mode" of the switching power supply circuit 10 is directly "normally" from the "low frequency burst mode" when the power consumption of the load 11 is the smallest among the plurality of "burst modes". It has been changed to "mode". Therefore, in particular, when the load 11 becomes a heavy load, it is not necessary to sequentially use all the "burst modes" in order to stabilize the output voltage Vout.

In the present embodiment, there are two "burst modes", a "low frequency burst mode" and a "high frequency burst mode", but for example, even if there are three or more "burst modes". good. Even in such a case, the present embodiment is obtained by directly transitioning from the "burst mode" when the power consumption of the load 11 is the smallest to the "normal mode" without going through another "burst mode". The same effect as

Further, the signals generated when the "low frequency burst mode" and the "high frequency burst mode" are selected are shown in FIGS. 4, 5 and 7, for example, but the present invention is not limited to this, and for example, intermittently. Any signal may be used as long as the switching operation can be stopped.

The above embodiment is for facilitating the understanding of the present invention, and is not for limiting the interpretation of the present invention. Further, it is needless to say that the present invention can be changed or improved without departing from the spirit thereof, and the present invention includes an equivalent thereof.

10 Switching power supply circuit 11 Load 20, 21, 32, 50 to 54 Capacitor 22, 23 NMOS Transistor 24 Transformer 25 Control block 30, 31, 58 Diode 33 Constant voltage circuit 34 Light emitting diode 40 Control IC
55-57,70 Resistance 59 Phototransistor 71,73 AD converter 72 Load detection circuit 74 Comparator 75 Drive signal output circuit 76 Control circuit 77 Drive circuit 78 Digital control circuit 90 Oscillation circuit 91 Buffer 92 Inverter 93 Low frequency burst control circuit 94 Timer 95 pulse circuit 96 selector

Claims (12)

A transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side, an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil, and the primary coil. Switching that controls the switching of the transistor by operating based on the power supply voltage corresponding to the voltage from the auxiliary coil of the power supply circuit that includes the transistor that controls the current and the output voltage of the target level on the secondary side. It ’s a control circuit,
A drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and a drive signal output circuit.
A drive circuit that switches the transistor based on the output of the drive signal output circuit, and
It has a first transition condition that includes time as a condition and a second transition condition that does not include time, and when the first transition condition or the second transition condition is satisfied, the power supply circuit operates in the first burst mode. A control circuit for outputting the drive signal to be output to the drive signal output circuit, and
A switching control circuit. The switching control circuit according to claim 1.
The first transition condition is that the light load state in which the load is light continues for a predetermined time.
Switching control circuit. The switching control circuit according to claim 1 or 2.
The second transition condition is that the power supply voltage drops to the first level.
Switching control circuit. The switching control circuit according to claim 3.
The second transition condition is that the load state is a light load state and the power supply voltage drops to the first level.
Switching control circuit. The switching control circuit according to any one of claims 1 to 4.
The control circuit
It is determined whether or not the load state is a light load state based on at least one of the feedback voltage corresponding to the output voltage and the voltage corresponding to the input power on the primary side.
Switching control circuit. The switching control circuit according to any one of claims 1 to 5.
The control circuit
When the output voltage rises above the target level and the feedback voltage corresponding to the output voltage reaches the second level, the drive circuit stops driving the transistor.
Switching control circuit. The switching control circuit according to any one of claims 1 to 6.
The control circuit
When the power consumption of the load decreases while the power supply circuit is operating in the normal mode, the power supply circuit is operated in the operation mode corresponding to the power consumption of the load among the plurality of burst modes including the first burst mode. The drive signal to be operated is output to the drive signal output circuit to be output.
When the power consumption of the load increases while the power supply circuit is operating in the operation mode corresponding to the load having the smallest power consumption among the plurality of burst modes, the power supply circuit is operated in the normal mode. The drive signal is output to the drive signal output circuit.
Switching control circuit. The switching control circuit according to claim 7.
The control circuit
At the time of transition from the operation mode corresponding to the load having the lowest power consumption to the normal mode, the drive signal output circuit is made to output the drive signal for operating the power supply circuit in the normal mode for at least the first period.
Switching control circuit. A transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side, an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil, and the primary coil. Switching that controls the switching of the transistor by operating based on the power supply voltage corresponding to the voltage from the auxiliary coil of the power supply circuit that includes the transistor that controls the current and the output voltage of the target level on the secondary side. It ’s a control circuit,
A drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and a drive signal output circuit.
A drive circuit that switches the transistor based on the output of the drive signal output circuit, and
When the power consumption of the load decreases while the power supply circuit is operating in the normal mode, the drive signal for operating the power supply circuit in the operation mode corresponding to the power consumption of the load among the plurality of burst modes is transmitted. Output to the drive signal output circuit
When the power consumption of the load increases while the power supply circuit is operating in the operation mode corresponding to the load having the smallest power consumption among the plurality of burst modes, the power supply circuit is operated in the normal mode. A control circuit that outputs the drive signal to the drive signal output circuit, and
A switching control circuit. The switching control circuit according to claim 9.
The control circuit
At the time of transition from the operation mode corresponding to the load having the lowest power consumption to the normal mode, the drive signal output circuit is made to output the drive signal for operating the power supply circuit in the normal mode for at least the first period.
Switching control circuit. A transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side, and an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil.
The transistor that controls the current of the primary coil and
A switching control circuit that operates based on the power supply voltage corresponding to the voltage from the auxiliary coil and controls the switching of the transistor.
It is a power supply circuit that generates the output voltage of the target level on the secondary side including
The switching control circuit
A drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and a drive signal output circuit.
A drive circuit that switches the transistor based on the output of the drive signal output circuit, and
It has a first transition condition that includes time as a condition and a second transition condition that does not include time, and when the first transition condition or the second transition condition is satisfied, the power supply circuit operates in the first burst mode. A control circuit for outputting the drive signal to be output to the drive signal output circuit, and
Power supply circuit with. A transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side, and an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil.
The transistor that controls the current of the primary coil and
A switching control circuit that operates based on the power supply voltage corresponding to the voltage from the auxiliary coil and controls the switching of the transistor.
It is a power supply circuit that generates the output voltage of the target level on the secondary side including
The switching control circuit
A drive signal output circuit that outputs a drive signal according to the operation mode of the power supply circuit, and a drive signal output circuit.
A drive circuit that switches the transistor based on the output of the drive signal output circuit, and
When the power consumption of the load decreases while the power supply circuit is operating in the normal mode, the drive signal for operating the power supply circuit in the operation mode corresponding to the power consumption of the load among the plurality of burst modes is transmitted. When the power consumption of the load increases when the power supply circuit is operated in the operation mode corresponding to the load, which consumes the least power among the plurality of burst modes, the drive signal output circuit is output. A control circuit that outputs the drive signal that operates the power supply circuit in the normal mode to the drive signal output circuit, and a control circuit that outputs the drive signal to the drive signal output circuit.
Power supply circuit with.

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