JP2024047998A - Switching control circuits, power supply circuits - Google Patents

Abstract

[Problem] To provide a switching control circuit that stably operates a power supply circuit when the load state changes. [Solution] A control IC (50) controls a DC-DC converter (10) that includes a transformer (33) including a primary coil (L1) and a secondary coil (L2), and transistors (31, 32) that control the current of the primary coil. The control IC (50) includes a drive signal output circuit that operates in a normal mode when the output voltage is lower than a first level and in a first burst mode when the output voltage is higher than a first level, and a drive circuit that switches the transistors (31, 32). In the normal mode, each transistor is switched continuously in a first cycle based on a feedback voltage according to the output voltage, and in the first burst mode, a first period in which each transistor is switched continuously in the first cycle and a second period in which switching of each transistor is stopped are repeated in a predetermined cycle. The drive signal output circuit shortens the first period of the predetermined cycle as the output voltage becomes higher than the first level. [Selected Figure] Figure 1

Description

The present invention relates to a switching control circuit and a power supply circuit.

Power supply circuits that generate a target level of output voltage from an input voltage have been disclosed (for example, Patent Documents 1 to 8).

Patent No. 6787505 International Publication No. 2019/155733 JP 2013-26079 A JP 2014-108004 A JP 2017-112798 A JP 2021-93813 A JP 2021-93814 A U.S. Pat. No. 1,006,9403

When the load state of the power supply circuit becomes light, the control circuit of the power supply circuit may switch the transistors from normal mode to burst mode. In this case, if the method of switching the transistors in normal mode differs from the method of switching the transistors in burst mode, the operation of the power supply circuit may become unstable.

The present invention was made in consideration of the above-mentioned problems in the conventional technology, and aims to provide a switching control circuit that can stably operate a power supply circuit when the load state changes.

The first aspect of the present invention, which is the main aspect of solving the above-mentioned problems, is a switching control circuit that controls the switching of the first and second transistors of a power supply circuit that generates an output voltage of a target level on the secondary side, the power supply circuit including a transformer including a primary coil and a secondary coil, and first and second transistors that control the current of the primary coil, and includes a drive signal output circuit that outputs a drive signal corresponding to a normal mode when the output voltage is lower than a first level, and outputs the drive signal corresponding to a first burst mode when the output voltage becomes higher than the first level, and a drive circuit that switches the first and second transistors based on the drive signal, the normal mode is a mode in which the first and second transistors are continuously switched in a first cycle based on a feedback voltage according to the output voltage, the first burst mode is a mode in which a first period in which the first and second transistors are continuously switched in the first cycle and a second period in which the switching of the first and second transistors is stopped are repeated in a predetermined cycle, and the drive signal output circuit shortens the first period of the predetermined cycle as the output voltage becomes higher than the first level.

The second aspect of the present invention, which is the main aspect of solving the above-mentioned problems, is a power supply circuit that generates an output voltage of a target level on the secondary side, comprising a transformer including a primary coil and a secondary coil, first and second transistors that control the current of the primary coil, and a switching control circuit that controls the switching of the first and second transistors, the switching control circuit including a drive signal output circuit that outputs a drive signal corresponding to a normal mode when the output voltage is lower than a first level, and outputs the drive signal corresponding to a first burst mode when the output voltage becomes higher than the first level, and a drive circuit that switches the first and second transistors based on the drive signal, the normal mode being a mode in which the first and second transistors are continuously switched in a first cycle based on a feedback voltage according to the output voltage, the first burst mode being a mode in which a first period in which the first and second transistors are continuously switched in the first cycle and a second period in which the switching of the first and second transistors is stopped are repeated in a predetermined cycle, and the drive signal output circuit shortens the first period of the predetermined cycle as the output voltage becomes higher than the first level.

The present invention provides a switching control circuit that can stably operate a power supply circuit when the load state changes.

FIG. 1 is a diagram illustrating an example of a DC-DC converter 10. FIG. 2 is a diagram illustrating an example of a control IC 50. FIG. 2 is a diagram illustrating an example of a detection circuit 140. FIG. 4 is a diagram showing an example of voltages Vwd, Vc1, and Vc2. 2 is a diagram for explaining the relationship between multiple operation modes of the digital control circuit 150 and various voltages. FIG. 4 is a diagram for explaining operation modes of the digital control circuit 150. FIG. FIG. 13 is a diagram showing an example of drive signals Vdr1, Vdr2 in normal mode M1. 10 is a diagram for explaining a switching period Tsw of drive signals Vdr1 and Vdr2; FIG. 2 is a diagram for explaining the relationship between the gain and the switching frequency of the DC-DC converter 10. FIG. FIG. 11 is a diagram for explaining a switching period T1 and a stop period T2 in a burst mode M2. FIG. 11 is a diagram for explaining a change in a switching period T1 in a burst mode M2. FIG. 11 is a diagram for explaining a switching period T1 and a stop period T2 in a burst mode M3. 1 is a diagram showing an example of a change in the operation mode of the DC-DC converter 10. FIG.

The following points become clear at least from the description in this specification and the accompanying drawings.

Here, identical or equivalent components, parts, etc. shown in each drawing are given the same reference numerals, and duplicate explanations are omitted as appropriate. Furthermore, in this embodiment, "connection" refers to a state in which two parts are electrically connected unless otherwise specified. For this reason, "connection" includes cases in which two parts are connected not only through wiring, but also through, for example, a resistor.

== ...
<<<Outline of DC-DC converter 10>>>
1 is a diagram showing an example of a DC-DC converter 10. The DC-DC converter 10 is an LLC current resonance type power supply circuit that generates an output voltage Vout (e.g., 12 V) of a target level from a predetermined input voltage Vin (e.g., 400 V).

The DC-DC converter 10 also applies the output voltage Vout to the load 11. Here, the load 11 is, for example, an LED of a lighting device (not shown), and the current flowing through the load 11 is the load current Iout.

The DC-DC converter 10 includes capacitors 30, 34, 35, and 42, NMOS transistors 31 and 32, a transformer 33, a resistor 36, a control block 37, diodes 40 and 41, a constant voltage circuit 43, and a light-emitting diode 44.

Capacitor 30 stabilizes the voltage between the power supply line to which the input voltage Vin is applied and the ground line on the ground side, and removes noise, etc.

NMOS transistor 31 is a high-side power transistor, and NMOS transistor 32 is a low-side power transistor. In this embodiment, NMOS transistors 31 and 32 are used as switching elements, but they may be PMOS transistors or bipolar transistors, for example.

The transformer 33 has a primary coil L1, secondary coils L2 and L3, and an auxiliary coil L4, and the primary coil L1 is insulated from the secondary coils L2 and L3, and the auxiliary coil L3. In the transformer 33, a voltage is generated in the secondary coils L2 and L3 on the secondary side in response to a change in the voltage across the primary coil L1 on the primary side, and a voltage is generated in the auxiliary coil L4 on the primary side in response to a change in the voltage across the secondary coils L2 and L3.

The primary coil L1 has one end connected to the source of NMOS transistor 31 and the drain of NMOS transistor 32, and the other end connected to the source of NMOS transistor 32 via capacitor 34. Therefore, when switching of NMOS transistors 31 and 32 begins, the voltages of the secondary coils L2 and L3 and the auxiliary coil L4 change.

In this embodiment, the primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with opposite polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are electromagnetically coupled with opposite polarity. The polarity of the electromagnetic coupling of the primary coil L1, the secondary coils L2 and L3, and the auxiliary coil L4 of the transformer 33 is not limited to this.

Capacitor 34 is a so-called resonant capacitor that forms a resonant circuit with the primary coil L1 of transformer 33 and leakage inductance (leakage inductance). Note that the leakage inductance is not shown in FIG. 1.

Capacitor 35 and resistor 36 connected in series to capacitor 35 are connected in parallel to capacitor 34 to form a circuit that shunts the resonant current of the resonant circuit. In this embodiment, a current Is that is a shunt of the resonant current flows through capacitor 35 and resistor 36, and a voltage Vs according to the resonant current is generated at the connection node between capacitor 35 and resistor 36.

In this embodiment, the direction of the current flowing from the primary coil L1 to the capacitor 34 is referred to as the "positive direction (or positive direction)." Also, the direction of the current flowing from the capacitor 34 to the primary coil L1 is referred to as the "negative direction (or negative direction)."

The control block 37 is a circuit block for controlling the switching of the NMOS transistors 31 and 32, and will be described in detail later.

Diodes 40 and 41 rectify the voltage of the secondary coils L2 and L3, and capacitor 42 smoothes the rectified voltage. As a result, a smoothed output voltage Vout is generated in capacitor 42. The output voltage Vout becomes a DC voltage of a desired level (e.g., 12 V).

The constant voltage circuit 43 is a circuit that generates a constant DC voltage and is configured using, for example, a shunt regulator.

The light-emitting diode 44 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 43, and together with the phototransistor 65 described below, constitutes a photocoupler. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light from the light-emitting diode 44 increases.

Control Block 37
The control block 37 includes a control IC 50 , a diode 60 , capacitors 61 , 62 , 66 , and 67 , resistors 63 and 64 , and a phototransistor 65 .

The control IC 50 is an integrated circuit that controls the switching of the NMOS transistors 31 and 32, and has terminals VCC, BO, VW, FB, IS, CA, HO, and LO. Note that the control IC 50 also has, for example, a ground terminal to which a ground voltage is applied, but this is omitted here for convenience.

The terminal VCC is a terminal to which a voltage Vcc is applied to operate the control IC 50. The terminal VCC is connected to the cathode of a diode 60 and a capacitor 61, one end of which is grounded. The anode of the diode 60 is connected to an auxiliary coil L4. In this embodiment, when the control IC 50 starts switching the NMOS transistors 31 and 32, a voltage corresponding to the load current Iout is generated in the auxiliary coil L4.

As a result, the capacitor 61 is charged by the current from the diode 60, and the charging voltage of the capacitor 61 becomes the power supply voltage Vcc that operates the control IC 50. The control IC 50 starts up based on a predetermined voltage (e.g., an AC voltage from a commercial power source) applied to a terminal not shown, and then operates based on the power supply voltage Vcc.

The terminal VW is a terminal for detecting the voltage of the auxiliary coil L4. In this embodiment, the series-connected capacitor 62 and resistors 63 and 64 are connected in parallel to the auxiliary coil L4. The capacitor 62 is an element that passes the AC component of the voltage from the auxiliary coil L4.

The resistors 63 and 64 form a voltage divider circuit that divides the voltage of the AC component generated by the auxiliary coil L4. In this embodiment, the node to which the resistors 63 and 64 are connected is connected to the terminal VW, and the voltage of the terminal VW is referred to as the voltage Vw.

Terminal BO is the terminal to which the input voltage Vin of the DC-DC converter 10 is applied.

Terminal FB is a terminal where a feedback voltage Vfb corresponding to the output voltage Vout is generated, and is connected to a phototransistor 65 and a capacitor 66. The phototransistor 65 passes a bias current I1, whose magnitude corresponds to the intensity of light from the light-emitting diode 44, from terminal FB to ground, and the capacitor 66 is provided to remove noise between terminal FB and ground. Therefore, the phototransistor 65 operates as a transistor that generates a sink current.

The terminal IS is a terminal to which a voltage corresponding to the resonant current of the DC-DC converter 10 is applied. As described above, a voltage Vs corresponding to the current Is resulting from the shunting of the resonant current is generated at the node to which the capacitor 35 and the resistor 36 are connected. In this embodiment, the node to which the capacitor 35 and the resistor 36 are connected is connected to the terminal IS, and therefore the voltage Vs is applied to the terminal IS.

The input voltage Vin is received from terminal BO and detected inside the control IC 50. This is because the resonant current and the power corresponding to the current Is (for example, the power of the load 11) are proportional to the input voltage Vin even if the resonant current and the current Is are the same magnitude.

Terminal CA changes according to the voltage Vs at terminal IS, and applies a voltage Vca to capacitor 67, which indicates the power consumed by load 11.

Terminal HO is a terminal from which signal Vo1 that drives NMOS transistor 31 is output, and is connected to the gate of NMOS transistor 31.

Terminal LO is a terminal from which signal Vo2 that drives NMOS transistor 32 is output, and is connected to the gate of NMOS transistor 32.

The control IC 50 corresponds to a "switching control circuit", the capacitor 34 corresponds to a "first capacitor", and the auxiliary coil L4 corresponds to an "auxiliary coil". The NMOS transistor 31 corresponds to a "first transistor", and the NMOS transistor 32 corresponds to a "second transistor". The terminal VW corresponds to a "first terminal", and the terminal BO corresponds to a "second terminal".

<<<<Details of Control IC 50>>>
2 is a diagram showing an example of the configuration of the control IC 50. The control IC 50 includes AD converters (ADCs) 100, 111, and 131, resistors 110, 120, and 121, a comparator 122, a load detection circuit 130, a detection circuit 140, a digital control circuit 150, and a drive circuit 151.

===AD Converter 100===
The AD converter 100 converts the input voltage Vin applied to the terminal BO into a digital value and outputs the digital value. In addition, in FIG. 2, the voltage converted into a digital value is shown in the same manner as the analog voltage before conversion.

===Resistor 110 and AD Converter 111===
The resistor 110 is an element that generates a feedback voltage Vfb at the terminal FB according to the bias current I1 in FIG. 1, and has one end to which the power supply voltage Vdd is applied and the other end connected to the terminal FB.

In this embodiment, when the output voltage Vout becomes higher than the target level, the light from the light-emitting diode 44 becomes stronger and the bias current I1 increases, so the feedback voltage Vfb decreases. On the other hand, when the output voltage Vout becomes lower than the target level, the light from the light-emitting diode 44 becomes weaker and the bias current I1 decreases, so the feedback voltage Vfb increases.

Furthermore, if the resistance value of the resistor 110 is R, the feedback voltage Vfb is expressed by the following equation (1).
Vfb=Vdd-R×I1 (1)

The AD converter 111 converts the feedback voltage Vfb generated at the terminal FB into a digital value and outputs it.

===Resistors 120, 121, and Comparator 122===
The resistors 120 and 121 are so-called level shift circuits that shift the center level of the voltage Vs that varies around the ground voltage (i.e., 0 V). In this embodiment, the resistors 120 and 121 have the same resistance value. Of the resistors 120 and 121 connected in series, a power supply voltage Vdd is applied to the resistor 120, and the resistor 121 is connected to the terminal IS.

Therefore, resistor 121 is connected to the connection node of capacitor 35 and resistor 36 in FIG. 1 via terminal IS. Here, when the current Is flowing through resistor 36 is zero, voltage Vs is zero. Therefore, in this case, the level of voltage Vsd at the node to which resistors 120 and 121 in FIG. 2 are connected is Vdd/2.

Furthermore, when the current Is flows in a positive direction, the voltage Vs also becomes positive, and the voltage Vsd rises from Vdd/2. On the other hand, when the current Is flows in a negative direction, the voltage Vs also becomes negative, and the voltage Vsd falls from Vdd/2. In this way, the voltage Vsd in this embodiment changes depending on the direction and magnitude of the current Is, with the level of Vdd/2 at the center.

The comparator 122 is a circuit that detects the direction of the current Is based on the voltage Vsd and a predetermined reference voltage Vref0. In this embodiment, the level of the reference voltage Vref0 is Vdd/2, so that the comparator 122 outputs a high-level (hereinafter, H-level) voltage Vc0 when the current Is is positive, and outputs a low-level (hereinafter, L-level) voltage Vc0 when the current Is is negative.

Therefore, in this embodiment, resistors 120 and 121 and comparator 122 operate as a circuit that detects the direction in which current Is flows.

Load Detection Circuit 130
The load detection circuit 130 is a circuit that detects the state of the load 11 (here, the power consumption of the load 11). Specifically, the load detection circuit 130 outputs a voltage Vca corresponding to the power of the load 11 to a terminal CA to which the capacitor 67 is connected, based on a voltage Vsd corresponding to a current Is (i.e., a resonant current).

The AD converter 131 converts the voltage Vca generated at the terminal CA into a digital value and outputs it. Note that the voltage Vca becomes larger, for example, when the power consumption of the load 11 increases and the current Is increases. Therefore, the digital control circuit 150 described later can determine the power consumption of the load 11 based on the voltage Vca. Note that the resonant current and the power corresponding to the current Is (for example, the power of the load 11) are proportional to the input voltage Vin as described above, so a process of correcting the voltage Vca may be performed using the AD-converted input voltage Vin.

Detection Circuit 140
The detection circuit 140 is a circuit that detects the timing for operating the DC-DC converter 10 in a predetermined burst mode (described later) based on the voltage Vw. Fig. 3 is a diagram showing an example of the detection circuit 140. The detection circuit 140 includes resistors 200 and 201, DA converters 210 and 211, and comparators 212 and 213.

The resistors 200 and 201 correspond to a level shift circuit that shifts the center level of the voltage Vw applied to the terminal VW in FIG. 1. In this embodiment, the level of the voltage Vw is shifted, and the voltage generated at the node to which the resistors 200 and 201 are connected is referred to as voltage Vwd.

When the NMOS transistors 31 and 32 are switched, the voltage at the node where the auxiliary coil L4 and the capacitor 62 are connected changes in the positive and negative directions with respect to 0 V. As a result, the voltage Vwd, which is the level-shifted version of the voltage Vw, has an AC waveform, for example, as shown in the upper part of Figure 4.

DA converter 210 outputs a reference voltage Vref1 whose level corresponds to data D1 from digital control circuit 150 described later, and DA converter 211 outputs a reference voltage Vref2 whose level corresponds to data D2.

The voltage across the auxiliary coil L4 changes according to the level of the input voltage Vin. Specifically, as the level of the input voltage Vin increases, the change in the voltage across the auxiliary coil L4 also increases. As a result, the amplitude of the voltage Vwd when the NMOS transistors 31 and 32 are switched also increases.

The digital control circuit 150 of this embodiment adjusts the levels of the reference voltages Vref1 and Vref2 according to the level of the input voltage Vin. Here, when the level of the input voltage Vin increases, the digital control circuit 150 outputs data D1 and D2 in which the level of the reference voltage Vref1 increases and the level of the reference voltage Vref2 decreases. As a result, the reference voltages Vref1 and Vref2 are adjusted so that the difference between the levels of the reference voltage Vref1 and the reference voltage Vref2 increases.

On the other hand, when the level of the input voltage Vin becomes low, the digital control circuit 150 outputs data D1 and D2 such that the level of the reference voltage Vref1 becomes low and the level of the reference voltage Vref2 becomes high. As a result, the reference voltages Vref1 and Vref2 are adjusted so that the difference between the levels of the reference voltage Vref1 and the reference voltage Vref2 becomes small.

The comparator 212 compares the voltage Vwd with the reference voltage Vref1 and outputs a voltage Vc1 indicating the comparison result. Specifically, when the voltage Vwd becomes higher than the reference voltage Vref1, the comparator 212 outputs an H-level voltage Vc1, and when the voltage Vwd becomes lower than the reference voltage Vref1, the comparator 212 outputs an L-level voltage Vc1.

The comparator 213 compares the voltage Vwd with the reference voltage Vref2 and outputs a voltage Vc2 indicating the comparison result. Specifically, when the voltage Vwd becomes higher than the reference voltage Vref2, the comparator 213 outputs an L-level voltage Vc2, and when the voltage Vwd becomes lower than the reference voltage Vref2, the comparator 213 outputs an H-level voltage Vc2.

As will be described in detail later, in a specified burst mode M3 (described later), when voltages Vc1 and Vc2 each become H level, the digital control circuit 150 outputs H-level drive signals Vdr1 and Vdr2 that turn on NMOS transistors 31 and 32.

Digital Control Circuit 150
2 outputs drive signals Vdr1, Vdr2 corresponding to the operation mode of the DC-DC converter 10 based on various input voltages. The digital control circuit 150 includes, for example, a digital signal processing circuit (DSP) and a storage circuit (for example, a memory), not shown.

As will be described in detail later, the digital control circuit 150 outputs drive signals Vdr1 and Vdr2 corresponding to three operating modes, normal mode M1, burst mode M2, and burst mode M3, as shown in FIG. 5, to operate the DC-DC converter 10.

Note that, hereafter, in this embodiment, the digital control circuit 150 outputting the drive signals Vdr1, Vdr2 corresponding to a predetermined operation mode may be referred to as "the digital control circuit 150 operating in a predetermined operation mode." Furthermore, when the digital control circuit 150 operates in a predetermined operation mode, the DC-DC converter 10 also operates in the predetermined operation mode.

Here, "normal mode" is an operating mode in which the control IC 50 continuously switches the NMOS transistors 31, 32. "Burst mode" is an operating mode in which the control IC 50 intermittently switches the NMOS transistors 31, 32. Therefore, in "burst mode", a switching period in which the NMOS transistors 31, 32 are switched (hereinafter referred to as switching period T1) and a stop period in which the switching of the NMOS transistors 31, 32 is stopped (hereinafter referred to as stop period T2) are repeated.

As shown in FIG. 5, when the digital control circuit 150 operates in normal mode M1 or burst mode M2, it uses the feedback voltage Vfb and the voltage Vc0 indicating the direction of the current Is. When the digital control circuit 150 operates in burst mode M3, it uses the feedback voltage Vfb, the voltage Vw, and the input voltage Vin. Details of the operation modes of the digital control circuit 150 will be described later.

The digital control circuit 150 that outputs the drive signals Vdr1 and Vdr2 corresponds to the "drive signal output circuit."

Drive Circuit 151
The drive circuit 151 is a buffer circuit that switches the NMOS transistors 31 and 32 based on the drive signals Vdr1 and Vdr2. Specifically, the drive circuit 151 drives the NMOS transistor 31 with a signal Vo1 having the same logical level as the drive signal Vdr1, and drives the NMOS transistor 32 with a signal Vo2 having the same logical level as the drive signal Vdr2.

<<<Operation of Digital Control Circuit 150>>>
6 is a diagram for explaining the operation of the digital control circuit 150. The horizontal axis of FIG. 6 indicates the voltage Vca corresponding to the power consumption of the load 11, and the vertical axis indicates the feedback voltage Vfb and the output voltage Vout. As described above, in this embodiment, when the output voltage Vout increases, the feedback voltage Vfb decreases. Therefore, on the vertical axis of FIG. 6, the direction in which the level of the feedback voltage Vfb increases (upward in FIG. 6) is opposite to the direction in which the output voltage Vout increases (downward in FIG. 6).

In FIG. 6, the voltages V0 to V4 on the axis of the output voltage Vout correspond to the voltages V10 to V14 on the axis of the feedback voltage Vfb. In other words, when the level of the output voltage Vout becomes the level of voltage V0, the level of the feedback voltage Vfb becomes the level of voltage V10. Note that the relationship between the other voltages V1 to V4 and voltages V11 to V14 is similar to the relationship between voltages V0 and V10, so a detailed explanation is omitted here. Also, the target level of the output voltage Vout corresponds to the level of the feedback voltage Vfb voltage V15.

First, here, a case where the power consumption of the load 11 is greater than 3% when the rated power consumption of the load 11 (hereinafter referred to as "rated power") is taken as 100% will be described. In this embodiment, a state in which the power consumption of the load 11 is 3% or less of the rated power is referred to as a "light load state of the load 11". In addition, the digital control circuit 150 determines whether the power consumption of the load 11 is greater than 3% based on the voltage Vca.

The level of voltage V1 corresponds to the "first level", the level of voltage V2 corresponds to the "second level", the level of voltage V3 corresponds to the "third level", and the level of voltage V4 corresponds to the "fourth level". Also, the "first value" corresponds to "3% of the rated power", burst mode M2 corresponds to the "first burst mode", and burst mode M3 corresponds to the "second burst mode".

===When load 11 is heavier than the light load state===
<<When the level of the output voltage Vout is lower than the voltage V0>>
First, the digital control circuit 150 when the level of the output voltage Vout is lower than the level of the voltage V0 will be described with reference to Fig. 6. The voltage V0 is a voltage sufficiently lower than the target level of the output voltage Vout (e.g., 12 V). For example, when the input voltage Vin is lower than a predetermined level, the level of the output voltage Vout may become lower than the level of the voltage V0.

Hereinafter, when the level of the output voltage Vout is lower than the level of voltage V0, it may be referred to as the output voltage Vout being lower than voltage V0. Also, as described above, when the level of the output voltage Vout becomes voltage V0, the feedback voltage Vfb becomes voltage V10.

When the output voltage Vout is lower than voltage V0 and the feedback voltage Vfb is higher than voltage V10, the digital control circuit 150 sets both drive signals Vdr1 and Vdr2 to the L level to stop the switching of NMOS transistors 31 and 32 based on the feedback voltage Vfb.

In this way, when the output voltage Vout becomes a voltage V0 that is sufficiently lower than the target level, the DC-DC converter 10 stops switching the NMOS transistors 31 and 32 so that the DC-DC converter 10 does not become unstable.

For example, when the DC-DC converter 10 starts up, the output voltage Vout rises from zero. In such a case, the digital control circuit 150 is designed so that the output voltage Vout does not stop the switching of the NMOS transistors 31 and 32.

<<When the output voltage Vout is higher than the voltage V0 and lower than the voltage V1>>
When the output voltage Vout becomes higher than the voltage V0, the digital control circuit 150 in FIG. 2 outputs the drive signals Vdr1, Vdr2 corresponding to the normal mode M1 based on the feedback voltage Vfb so as to set the output voltage Vout to a target level.

Figure 7 is a diagram showing an overview of the drive signals Vdr1 and Vdr2 corresponding to normal mode M1. In normal mode M1, the digital control circuit 150 changes the drive signals Vdr1 and Vdr2 complementarily. Specifically, when the drive signal Vdr1 goes to H level, the digital control circuit 150 sets the drive signal Vdr2 to L level, and when the drive signal Vdr1 goes to L level, the digital control circuit 150 sets the drive signal Vdr2 to H level.

Note that in FIG. 7, a period during which both drive signals Vdr1 and Vdr2 are at the L level (so-called dead time) is provided between drive signals Vdr1 and Vdr2, but this is omitted here for convenience.

As shown in FIG. 5, the digital control circuit 150 of this embodiment determines the switching period Tsw of the drive signals Vdr1 and Vdr2 based on the feedback voltage Vfb and the timing at which the direction of the current Is changes (i.e., the voltage Vc0). FIG. 8 is a diagram for explaining the details of the drive signals Vdr1 and Vdr2 in normal mode M1.

For example, at time t0, the digital control circuit 150 changes the drive signal Vdr1 to L level, so that the high-side NMOS transistor 31 in FIG. 1 is turned off. Then, at time t1, when the period Td1 corresponding to the dead time has elapsed, the digital control circuit 150 changes the drive signal Vdr2 to H level. As a result, the low-side NMOS transistor 32 is turned on.

After the NMOS transistor 32 turns on, the current Is gradually decreases and becomes zero at time t2. As a result, the comparator 122 in FIG. 2 outputs an L-level voltage Vc0, which indicates that the current Is is flowing in the negative direction.

Then, the digital control circuit 150 calculates the period Tah according to the product of the period Tbh from time t0 to time t2 and the feedback voltage Vfb, as shown in equation (2). Note that in equation (2), "k" is a predetermined constant.
Tah = k × Vfb × Thb (2)

When the time period Tah elapses from time t2 to time t3, the digital control circuit 150 changes the drive signal Vdr2 to the L level to turn off the NMOS transistor 32.

When the time t4 arrives, which is the time period Td2 corresponding to the dead time after the time t3, the digital control circuit 150 changes the drive signal Vdr1 to the H level. As a result, the high-side NMOS transistor 31 in FIG. 1 is turned on.

After the NMOS transistor 31 turns on, the current Is gradually increases and becomes zero at time t5. As a result, the comparator 122 in FIG. 2 outputs an H-level voltage Vc0, which indicates that the current Is is flowing in the positive direction.

Then, the digital control circuit 150 calculates the period Tal according to the product of the period Tbl from time t3 to time t5 and the feedback voltage Vfb, as shown in equation (3). Note that in equation (3), "k" is the above-mentioned predetermined constant.
Tal = k × Vfb × Tbl (3)

At time t6, which is the time period Tal after time t5, the digital control circuit 150 changes the drive signal Vdr1 to the L level. After time t6, the operation from time t0 to t6 is repeated. In this manner, the switching period Tsw in this embodiment is determined based on the period Tah and the period Tal. Therefore, the switching period Tsw becomes longer when the output voltage Vout decreases and the feedback voltage Vfb increases.

The relationship shown in FIG. 9, for example, exists between the gain (=Vout/Vin) of the LLC current resonant DC-DC converter 10 and the switching frequency of the NMOS transistors 31, 32. In this embodiment, the switching frequency of the NMOS transistors 31, 32 is designed to be higher than the resonant frequency of the resonant circuit including the primary coil L1 and capacitor 34 in FIG. 1. In other words, in this embodiment, the switching frequency of the NMOS transistors 31, 32 is designed to change in the "usage region" in FIG. 9.

If the output voltage Vout of the DC-DC converter 10 falls below the target level, the feedback voltage Vfb rises, and the switching period Tsw becomes longer. In this case, the switching frequency of the NMOS transistors 31 and 32 falls, and the gain (= Vout/Vin) increases, resulting in an increase in the output voltage Vout.

On the other hand, when the level of the output voltage Vout rises from the target level, the feedback voltage Vfb falls, and the switching period Tsw becomes shorter. In this case, the switching frequency of the NMOS transistors 31 and 32 rises and the gain (=Vout/Vin) falls, resulting in a fall in the output voltage Vout. Therefore, the DC-DC converter 10 can generate an output voltage Vout at the target level by outputting the drive signals Vdr1 and Vdr2 corresponding to the normal mode M1.

<<When the output voltage Vout is higher than the voltage V1>>
6, for example, when the power consumption of the load 11 decreases and the output voltage Vout becomes higher than the voltage V1, the digital control circuit 150 outputs the drive signals Vdr1 and Vdr2 corresponding to the burst mode M2. In this embodiment, when the level of the output voltage Vout becomes the voltage V1, the feedback voltage Vfb becomes the voltage V11.

The "burst mode M2" of this embodiment is an operation mode in which a switching period T1 during which the NMOS transistors 31 and 32 are continuously switched and a stop period T2 during which the switching of the NMOS transistors 31 and 32 is stopped are repeated at a predetermined cycle Tx.

Figure 10 is a diagram showing an example of drive signals Vdr1, Vdr2 corresponding to burst mode M2. In the switching period T1 of burst mode M2, the digital control circuit 150 of this embodiment outputs the same drive signals Vdr1, Vdr2 as in normal mode M1. Specifically, as shown in Figures 5 and 8, the digital control circuit 150 acquires the feedback voltage Vfb and the timing at which the direction of current Is changes (i.e., voltage Vc0). Then, the digital control circuit 150 outputs drive signals Vdr1, Vdr2 having a switching period Tsw obtained using equations (2) and (3).

Therefore, in the DC-DC converter 10, even if the power consumption of the load 11 decreases and the operation mode of the digital control circuit 150 changes from normal mode M1 to burst mode M2, the switching method of the NMOS transistors 31 and 32 does not change. As a result, in this embodiment, even if the operation mode of the digital control circuit 150 changes, it is possible to prevent the operation of the DC-DC converter 10 from becoming unstable.

Note that the "switching method" here is determined, for example, by the switching pattern and switching period Tsw of the NMOS transistors 31 and 32. In this embodiment, in both normal mode M1 and burst mode M2, when the dead time is ignored, the NMOS transistors 31 and 32 have a switching pattern in which they are complementarily turned on and off.

Furthermore, in each of the normal mode M1 and the burst mode M2, the switching period Tsw is determined based on, for example, the same formula (2) and formula (3). Therefore, in this embodiment, the switching method of the normal mode M1 and the switching method of the burst mode M2 are the same. Note that the switching period Tsw of the normal mode M1 and the switching period Tsw of the burst mode M2 each correspond to a "first period", and the switching period Tsw of the burst mode M3 corresponds to a "second period".

Figure 11 is a diagram for explaining the waveform of burst mode M2 when the output voltage Vout changes. Figure 11 (a) is an example of a waveform of burst mode M2 when the output voltage Vout is voltage V1 (i.e., the feedback voltage Vfb is voltage V11). In this case, the digital control circuit 150 sets the switching period T1 of the predetermined period Tx (e.g., 10 ms) to an initial value of period Ti (e.g., 6 ms), and sets the stop period T2 to a period obtained by subtracting period Ti from the predetermined period Tx (e.g., 4 ms). In other words, in this embodiment, the stop period T2 is Tx-T1 (=Tx-Ti).

For example, when the power consumption of the load 11 decreases and the output voltage Vout increases from voltage V1 (i.e., when the feedback voltage Vfb decreases from voltage V11), the digital control circuit 150 gradually shortens the switching period T1 from period Ti (see FIG. 11(b)).

In addition, in this embodiment, in burst mode M2, the cycle determined by the switching period T1 and the stop period T2 is a fixed predetermined cycle Tx. Therefore, when the switching period T1 becomes shorter, the power transmitted from the primary side to the secondary side of the DC-DC converter 10 also becomes smaller. As a result, it is possible to suppress the increase in the output voltage Vout.

If the power consumption of the load 11 is further reduced and the output voltage Vout becomes voltage V2 (i.e., the feedback voltage Vfb drops to voltage V12), the digital control circuit 150 stops gradually shortening the switching period T1, as shown in FIG. 6 and FIG. 11(c), for example. Specifically, when the output voltage Vout is in the range from voltage V2 to voltage V3 (i.e., the feedback voltage Vfb is in the range from voltage V12 to voltage V13), the digital control circuit 150 maintains the period Tf, which is the switching period T1 when the feedback voltage Vfb is voltage V12, as the switching period T1. Note that, out of the predetermined period Tx (e.g., 10 ms), the period Tf which is the switching period T1 is, for example, 2 ms, and therefore the stop period T2 is 8 ms.

Thus, in this embodiment, when the output voltage Vout becomes higher than the voltage V2, in burst mode M2, the switching period T1 is fixed to the period Tf. If the switching period T1 becomes zero and the switching of the NMOS transistors 31 and 32 is stopped for a long period of time, for example, each coil of the transformer 33 and the parasitic capacitance of the NMOS transistors 31 and 32 may be discharged. In such a case, when the DC-DC converter 10 resumes its switching operation, unnecessary noise may be generated, causing the operation of the DC-DC converter 10 to become unstable.

In this embodiment, the DC-DC converter 10 can stabilize the operation of the DC-DC converter 10 while suppressing noise generation because the switching period T1 does not become zero even when the output voltage Vout becomes higher than the voltage V2.

The switching period T1 corresponds to the "first period", the stop period T2 corresponds to the "second period", and the period Tf corresponds to the "predetermined period". The period Tf is the switching period T1 when the level of the output voltage Vout becomes the level of the voltage V2.

<<When the output voltage Vout is higher than the voltage V3>>
Furthermore, when the power consumption of the load 11 decreases and the output voltage Vout becomes higher than the voltage V3 (i.e., when the feedback voltage Vfb drops to the voltage V13), for example, as shown in FIG. 6 , the digital control circuit 150 outputs the drive signals Vdr1 and Vdr2 at the L level to stop the switching of the NMOS transistors 31 and 32.

===Load 11 is in a light load state===
Next, a case where the load 11 is in a light load state, that is, the power consumption of the load 11 is 3% or less in Fig. 6 will be described. The digital control circuit 150 determines that the power consumption of the load 11 is 3% or less based on the voltage Vca.

First, when the load 11 is in a light load state and certain conditions are satisfied, the digital control circuit 150 outputs the drive signals Vdr1 and Vdr2 at the L level so that the switching of the NMOS transistors 31 and 32 is stopped.

Here, "when a certain condition is satisfied" refers to when the output voltage Vout is higher than voltage V3 (i.e., when the feedback voltage Vfb is lower than voltage V13) and when the output voltage Vout is lower than voltage V0 (i.e., when the feedback voltage Vfb is higher than voltage V10).

In addition, when the load 11 is in a light load state and the output voltage Vout is higher than voltage V0 and lower than voltage V4 (i.e., when the feedback voltage Vfb is lower than voltage V10 and higher than voltage V14), the digital control circuit 150 outputs drive signals Vdr1 and Vdr2 corresponding to the normal mode M1 described above.

The level of voltage V4 in this embodiment is higher than the target level of the output voltage Vout and lower than the level of voltage V1 at which burst mode M2 is initiated. As a result, even if the load 11 is in a light load state, if the output voltage Vout does not become a relatively high voltage V4 (< V1), the DC-DC converter 10 will operate in normal mode M1.

On the other hand, when the load 11 is in a light load state and the output voltage Vout is higher than the voltage V4 and lower than the voltage V3 (i.e., when the feedback voltage Vfb is lower than the voltage V14 and higher than the voltage V13), the digital control circuit 150 outputs the drive signals Vdr1 and Vdr2 corresponding to the burst mode M3. Here, the burst mode M3 is an operation mode in which a switching period T1 during which the NMOS transistors 31 and 32 are continuously switched and a stop period T2 during which the switching of the NMOS transistors 31 and 32 is stopped are repeated.

In burst mode M3, unlike burst mode M2, as shown in FIG. 5, the switching period Tsw is determined based on the voltage Vw and the input voltage Vin. Specifically, in burst mode M3, the digital control circuit 150 in FIG. 2 outputs drive signals Vdr1 and Vdr2 based on the detection results (voltages Vc1 and Vc2) of the detection circuit 140 shown in FIG. 3. As a result, as described in FIG. 4, when voltage Vc1 becomes H level, the digital control circuit 150 outputs H level drive signal Vdr1, and when voltage Vc2 becomes H level, the digital control circuit 150 outputs H level drive signal Vdr2.

When the digital control circuit 150 operates in burst mode M3, as shown in FIG. 5, the digital control circuit 150 determines the switching period T1 based on the feedback voltage Vfb. FIG. 12 is a diagram for explaining the switching period T1 and the stop period T2 when the digital control circuit 150 operates in burst mode M3.

For example, at time t10, when the feedback voltage Vfb rises to a predetermined voltage level V20, the digital control circuit 150 generates drive signals Vdr1 and Vdr2 corresponding to burst mode M3. As a result, NMOS transistors 31 and 32 are switched.

When the NMOS transistors 31 and 32 are driven at time t10, the output voltage Vout rises, and the feedback voltage Vfb drops slightly after time t10. Then, for example, at time t11, when the feedback voltage Vfb drops to a predetermined level V21, the generation of the drive signals Vdr1 and Vdr2 is stopped. The period from time t10 to time t11 is the "switching period T1."

As a result, the switching of NMOS transistors 31 and 32 is also stopped, and the output voltage Vout drops. Then, with a slight delay from time t11, the feedback voltage Vfb rises, and when the feedback voltage Vfb reaches voltage V20 at time t12, for example, the drive signals Vdr1 and Vdr2 corresponding to burst mode M3 are generated. As a result, at this timing, the NMOS transistors 31 and 32 are driven again. The period from time t11 to time t12 is the "stop period T2."

After time t12, the operation from time t10 to time t12 is repeated. In this way, the digital control circuit 150 operates in burst mode M3 during the switching period T1 according to the feedback voltage Vfb. Therefore, in this embodiment, it is possible to suppress the increase in the output voltage Vout when the load 11 is in a light load state while suppressing the power consumption of the DC-DC converter 10. Note that voltage V20 is a predetermined voltage that is close to voltage V14 but lower than voltage V14, and voltage V21 is a predetermined voltage that is close to voltage V13 but higher than voltage V14.

===An Example of an Operation Mode When the Power Consumption of the Load 11 Has Decreased===
13 is a diagram showing an example of the operation mode of the digital control circuit 150 when the power consumption of the load 11 is reduced. Here, it is assumed that before time t30, the DC-DC converter 10 operates in normal mode M1 and generates the output voltage Vout at a target level.

At time t30, when the power consumption of the load 11 decreases, the output voltage Vout rises above the target level. Note that here, the load 11 is assumed to be a load heavier than a light load (i.e., 3% of the rated load). When the output voltage Vout rises, the feedback voltage Vfb falls from the voltage V15 corresponding to the target level.

Then, at time t31, when the feedback voltage Vfb becomes voltage V11, the operation mode of the digital control circuit 150 changes from normal mode M1 to burst mode M2. As a result, as shown in FIG. 11(a), the switching period T1 and the stop period T2 are repeated at a predetermined cycle Tx.

In addition, since the feedback voltage Vfb gradually decreases after time t31, the digital control circuit 150 gradually shortens the switching period T1 in the predetermined cycle Tx, as shown in FIG. 11(b). As a result, the power transmitted from the primary side to the secondary side of the DC-DC converter 10 decreases, suppressing the increase in the output voltage Vout, for example.

Furthermore, at time t32, when the feedback voltage Vfb becomes voltage V12, the digital control circuit 150 sets the switching period T1 to the minimum period Tf in the predetermined cycle Tx, as shown in FIG. 11(c). As a result, even if the feedback voltage Vfb drops from voltage V12 after time t32, the switching period T1 does not become shorter.

When the output voltage Vout subsequently drops, the feedback voltage Vfb rises and becomes voltage V12 at time t33. As a result, after time t33, the digital control circuit 150 lengthens the switching period T1 in response to the rise in the feedback voltage Vfb. Then, at time t34, when the feedback voltage Vfb becomes voltage V11, the operation mode of the digital control circuit 150 changes from burst mode M2 to normal mode M1.

As described above, in normal mode M1, when the output voltage Vout is higher than the target level, the digital control circuit 150 outputs drive signals Vdr1 and Vdr2 that set the output voltage Vout to the target level. As a result, the output voltage Vout of the DC-DC converter 10 becomes the target level.

====Summary====
The DC-DC converter 10 of this embodiment has been described above. When the output voltage Vout is lower than the voltage V1, the digital control circuit 150 of the control IC 50 outputs the drive signals Vdr1 and Vdr2 corresponding to the normal mode M1, and when the output voltage Vout becomes higher than the voltage V1, the digital control circuit 150 outputs the drive signals Vdr1 and Vdr2 corresponding to the burst mode M2 (see FIG. 6). For example, as shown in FIG. 5, the switching period Tsw of the drive signals Vdr1 and Vdr2 is generated in the same manner in each of the normal mode M1 and the burst mode M2. As the output voltage Vout becomes higher than the voltage V1, the digital control circuit 150 shortens the switching period T1, for example, as shown in FIG. 11(b). Therefore, in this embodiment, even if the state of the load 11 changes and the operation mode of the DC-DC converter 10 changes, the DC-DC converter 10 can be operated stably.

In addition, when the output voltage Vout becomes a voltage V2 higher than the voltage V1, the digital control circuit 150 stops shortening the switching period T1, for example, as shown in FIG. 11(c). Therefore, even if the output voltage Vout becomes higher than the voltage V2, the digital control circuit 150 fixes the switching period T1 of the burst mode M2 to the period Tf. As a result, in this embodiment, it is possible to prevent the switching of the NMOS transistors 31 and 32 from being stopped while suppressing the increase in the output voltage Vout.

In addition, when the output voltage Vout becomes voltage V3, the digital control circuit 150 outputs L-level drive signals Vdr1 and Vdr2 to stop the switching of the NMOS transistors 31 and 32. As a result, it is possible to prevent the output voltage Vout from becoming abnormally high.

In addition, for example, when the load 11 is in a light load state, the digital control circuit 150 may output drive signals Vdr1, Vdr2 corresponding to a burst mode M2 different from the burst mode M1. In such a case, different burst modes are used when the load 11 is in a light load state and when it is not in a light load state, so the DC-DC converter 10 can select the optimal burst mode depending on the state of the load 11.

In addition, when the load 11 is in a light load state and the output voltage Vout is higher than the voltage V4, the digital control circuit 150 operates in the burst mode M2. Therefore, even if the load 11 is in a light load state, if the output voltage Vout is low, the digital control circuit 150 operates in the normal mode M1, so that it is possible to prevent the operating mode from being switched more than necessary.

The digital control circuit 150 also operates in burst mode M2 when the power consumption of the load 11 is 5% or less of the rated power (here, for example, 3%). In this embodiment, it is possible to set conditions for using burst mode M2, which is different from burst mode M1, particularly when the load 11 is in a light load state, and therefore it is possible to particularly improve the conversion efficiency of the DC-DC converter 10 in a light load state.

In addition, when the digital control circuit 150 operates in burst mode M2, it determines the switching period Tsw based on the voltage Vw of the terminal VW.

When operating in burst mode M2, the digital control circuit 150 determines the switching period Tsw based on the voltage Vw and the input voltage Vin. For example, when the input voltage Vin of the DC-DC converter 10 increases, the voltage generated in the primary coil and the auxiliary coil L4 also increases, and the power transmitted to the secondary side also increases. Therefore, in this embodiment, in burst mode M2, power can be transmitted to the secondary side appropriately in accordance with the level of the input voltage Vin.

The above embodiment is intended to facilitate understanding of the present invention, and is not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents.

10 DC-DC converter 11 Load 30, 34, 35, 42, 61, 62, 66, 67 Capacitor 31, 32 NMOS transistor 33 Transformer 36, 63, 64, 110, 120, 121, 200, 201 Resistor 37 Control block 40, 41, 60 Diode 43 Constant voltage circuit 44 Light emitting diode 50 Control IC
65 Phototransistors 100, 111, 131 AD converters 122, 212, 213 Comparator 130 Load detection circuit 140 Detection circuit 150 Digital control circuit 151 Drive circuit 210, 211 DA converter VCC, BO, VW, FB, IS, CA, HO, LO terminals

Claims (9)

A switching control circuit for controlling switching of the first and second transistors of a power supply circuit that generates an output voltage of a target level on a secondary side, the power supply circuit comprising: a transformer including a primary coil and a secondary coil; and first and second transistors that control a current of the primary coil, the switching control circuit comprising:
a drive signal output circuit that outputs a drive signal corresponding to a normal mode when the output voltage is lower than a first level, and outputs the drive signal corresponding to a first burst mode when the output voltage is higher than the first level;
a drive circuit that switches the first and second transistors on the basis of the drive signal;
Equipped with
The normal mode is
a mode in which the first and second transistors are continuously switched in a first period based on a feedback voltage corresponding to the output voltage;
The first burst mode includes:
a mode in which a first period during which the first and second transistors are continuously switched on and a second period during which the switching of the first and second transistors is stopped are repeated at a predetermined period,
The drive signal output circuit includes:
shortening the first period of the predetermined cycle as the output voltage becomes higher than the first level;
Switching control circuit. 2. The switching control circuit according to claim 1,
The drive signal output circuit includes:
When the output voltage becomes a second level higher than the first level, the first period is set to a predetermined period regardless of an increase in the output voltage.
Switching control circuit. 3. A switching control circuit according to claim 2,
The drive signal output circuit includes:
when the output voltage reaches a third level higher than the second level, outputting the drive signal for stopping switching of the first and second transistors;
Switching control circuit. A switching control circuit according to any one of claims 1 to 3,
the power supply circuit includes a first capacitor connected in series to the primary coil;
The switching control circuit includes:
a load detection circuit that detects a state of a load of the power supply circuit based on a resonant current of a resonant circuit including the primary coil and the first capacitor;
The drive signal output circuit includes:
when the power consumed by the load becomes smaller than a first value, outputting the drive signal corresponding to a second burst mode different from the first burst mode.
Switching control circuit. 5. A switching control circuit according to claim 4,
The drive signal output circuit includes:
when the power consumed by the load becomes smaller than the first value and the output voltage becomes higher than a fourth level lower than the first level, outputting the drive signal corresponding to the second burst mode.
Switching control circuit. 5. A switching control circuit according to claim 4,
The first value is 5% or less of the rated power of the load.
Switching control circuit. 5. A switching control circuit according to claim 4,
The transformer includes an auxiliary coil,
the switching control circuit is an integrated circuit including a first terminal to which a voltage corresponding to a voltage of the auxiliary coil is applied,
The drive signal output circuit includes:
outputting the drive signal corresponding to the second burst mode and having a second period based on the voltage of the first terminal;
Switching control circuit. 8. A switching control circuit according to claim 7,
a second terminal to which an input voltage of the power supply circuit is applied;
The drive signal output circuit includes:
outputting the drive signal corresponding to the second burst mode and having the second period based on the voltage of the first terminal and the voltage of the second terminal;
Switching control circuit. a transformer including a primary coil and a secondary coil;
first and second transistors for controlling a current in the primary coil;
a switching control circuit for controlling switching of the first and second transistors;
A power supply circuit for generating an output voltage of a target level on a secondary side, comprising:
The switching control circuit includes:
a drive signal output circuit that outputs a drive signal corresponding to a normal mode when the output voltage is lower than a first level, and outputs the drive signal corresponding to a first burst mode when the output voltage is higher than the first level;
a drive circuit that switches the first and second transistors based on the drive signal;
Including,
The normal mode is
a mode in which the first and second transistors are continuously switched in a first period based on a feedback voltage corresponding to the output voltage;
The first burst mode includes:
a mode in which a first period during which the first and second transistors are continuously switched on and a second period during which the switching of the first and second transistors is stopped are repeated at a predetermined period, and the drive signal output circuit is
shortening the first period of the predetermined cycle as the output voltage becomes higher than the first level;
Power supply circuit.

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