JP2021049652A - Inkjet head and image forming device - Google Patents

Abstract

To provide an inkjet head that can prevent concentration of electric currents, and an image forming device.SOLUTION: An inkjet head according to an embodiment comprises a channel group and a driver IC. The channel group makes a nozzle discharge ink in response to a deformation of an actuator. The driver IC applies an output driving voltage to the actuator on the basis of a signal from a controller. Further, the driver IC, when receiving a circuit protection command supplied from the controller before receiving a reset command, gradually reduces the output driving voltage.SELECTED DRAWING: Figure 4

Description

Embodiments of the present invention relate to an inkjet head and an image forming apparatus.

An image forming apparatus (inkjet printer) that forms an image on a print medium according to print data has been put into practical use. The image forming apparatus includes, for example, an inkjet head and a head control circuit for controlling the inkjet head. The inkjet head includes a channel group for ejecting ink from a nozzle according to the deformation of the actuator, and a driver IC for applying an output drive voltage to the actuator based on a signal from the head control circuit.

The actuator has a plurality of grooves formed in the piezoelectric member and electrodes formed so as to sandwich the piezoelectric member forming the side wall of the groove. Ink flows into the groove of the actuator. The groove of the actuator is sealed by a nozzle plate in which a nozzle is formed for each groove. The actuator deforms according to the potential difference between the electrodes sandwiching the piezoelectric member. The driver IC deforms the actuator by applying an output drive voltage to the electrodes of the actuator, and ejects ink droplets (droplets) from the nozzles.

When the driver IC receives the reset signal from the head control circuit, the driver IC resets the actuator by grounding (connecting to GND) the electrodes of the actuator. However, when the output drive voltage of the inkjet head is a positive voltage in a steady state, there is a problem that current concentration occurs in which current flows from a plurality of actuators to the GND all at once when reset is executed.

Japanese Unexamined Patent Publication No. 11-291498

An object of the present invention is to provide an inkjet head and an image forming apparatus capable of preventing current concentration.

The inkjet head according to the embodiment includes a channel group and a driver IC. The channel group ejects ink from the nozzle according to the deformation of the actuator. The driver IC applies an output drive voltage to the actuator based on a signal from the controller. Further, when the driver IC receives the circuit protection command supplied from the controller before the reset command, the driver IC gradually lowers the output drive voltage.

FIG. 1 is an explanatory diagram of an example of a configuration of an image forming apparatus according to a first embodiment. FIG. 2 is an explanatory diagram of an example of the configuration of the inkjet head and the head control circuit according to the first embodiment. FIG. 3 is an explanatory diagram of an example of the configuration of the drive signal generation unit according to the first embodiment. FIG. 4 is an explanatory diagram of an example of a signal timing chart in the inkjet head and the head control circuit according to the first embodiment. FIG. 5 is an explanatory diagram of an example of the configuration of the inkjet head and the head control circuit according to the second embodiment. FIG. 6 is an explanatory diagram of an example of a signal timing chart in the inkjet head and the head control circuit according to the second embodiment.

Hereinafter, the inkjet head and the image forming apparatus according to the embodiment will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is an explanatory diagram showing a configuration example of the image forming apparatus 1 according to the first embodiment. The image forming apparatus 1 is an apparatus for forming an image on a medium by ejecting droplets from an inkjet head.

The image forming apparatus 1 includes a system controller 11, a communication interface 12, a head control circuit 13, an inkjet head 14, a conveying device 15, a pump 16, and a power supply circuit 17.

The system controller 11 controls the image forming apparatus 1. The system controller 11 includes, for example, a processor 21 and a memory 22.

The processor 21 is an arithmetic element (for example, a CPU) that executes arithmetic processing. The processor 21 is the main body of operation of the system controller 11. The processor 21 performs various processes based on data such as a program stored in the memory 22. The processor 21 functions as a control unit capable of executing various operations by executing a program stored in the memory 22.

The memory 22 is a storage device that stores a program and data used in the program. Further, the memory 22 temporarily stores data and the like being processed by the processor 21. The memory 22 is configured as a non-volatile memory.

The communication interface 12 is an interface for communicating with a client device or the like that supplies a print job via a network.

The head control circuit 13 is a head control circuit that controls the operation of the inkjet head 14. The head control circuit 13 operates the inkjet head 14 to eject droplets (ink droplets) from the inkjet head 14. The head control circuit 13 supplies a drive signal and a power supply voltage to the inkjet head 14.

The inkjet head 14 is configured to eject droplets. The inkjet head 14 ejects droplets from a nozzle by a drive signal from the head control circuit 13 and a power supply voltage. The image forming apparatus 1 may include a plurality of inkjet heads 14 corresponding to each color such as cyan, magenta, yellow, and black.

The transport device 15 is configured to transport the print medium. The transport device 15 transports the print medium in synchronization with the ejection of the droplets by the inkjet head 14.

The pump 16 is configured to supply ink to the inkjet head 14. The pump 16 supplies ink to the inkjet head 14 from an ink tank in which ink is held, based on the detection result of a sensor (not shown).

The power supply circuit 17 converts AC power supplied from a commercial power source into DC power. The power supply circuit 17 supplies DC power to each configuration in the image forming apparatus 1. The power supply circuit 17 supplies a DC voltage DCV to the head control circuit 13.

FIG. 2 is an explanatory diagram for explaining a detailed configuration of the head control circuit 13 and the inkjet head 14. The head control circuit 13 and the inkjet head 14 are connected via a flexible printed circuit (FPC) substrate for transmission (hereinafter, referred to as transmission FPC 31). As a result, the head control circuit 13 can supply the power supply voltage and the control signal to the inkjet head 14.

First, the head control circuit 13 will be described.
The head control circuit 13 includes a first communication interface 35, a second communication interface 36, a power supply voltage generator 32, a power supply sequence circuit 33, and a control IC 34.

The first communication interface 35 is an interface for connecting the system controller 11 and the control IC 34.

The second communication interface 36 is an interface that connects the inkjet head 14 and the head control circuit 13 via the transmission FPC 31. The second communication interface 36 includes various terminals to which the transmission FPC 31 is connected.

The power supply voltage generator 32 uses the DC voltage DCV supplied from the power supply circuit 17 to generate a plurality of power supply voltages required for the operation of the inkjet head 14 and a power supply voltage required for the operation of the control IC 34.

For example, the power supply voltage generator 32 uses the DC voltage DCV to generate the power supply voltage VAA-IN, the power supply voltage VCS-IN, the power supply voltage VDD-IN, and the power supply voltage VOL-LOG. The power supply voltage VAA-IN is a power supply voltage for generating the power supply voltage VAA used in the inkjet head 14. The power supply voltage VCS-IN is a power supply voltage for generating the power supply voltage VCS used in the inkjet head 14. The power supply voltage VDD-IN is a power supply voltage for generating the power supply voltage VDD used in the inkjet head 14. The power supply voltage VDD-LOG is a power supply voltage for operating the control IC 34.

The power supply voltage generator 32 supplies the power supply voltage VAA-IN, the power supply voltage VCS-IN, and the power supply voltage VDD-IN to the power supply sequence circuit 33. Further, the power supply voltage generator 32 supplies the power supply voltage VDD-LOG to the control IC 34.

The power supply sequence circuit 33 turns on and off each power supply voltage to the inkjet head 14 via the second communication interface 36 and the transmission FPC 31. The power supply sequence circuit 33 is based on the power supply voltage VAA-IN, the power supply voltage VCS-IN, and the power supply voltage VDD-IN supplied from the power supply voltage generator 32, and the power supply voltage VAA, the power supply voltage VCS, and the power supply voltage VCS with respect to the inkjet head 14. And the power supply voltage VDD is output.

The power supply sequence circuit 33 starts (turns on) the output of each power supply voltage based on a preset order (sequence). Further, the power supply sequence circuit 33 stops (cuts off) the output of each power supply voltage based on a preset order (sequence). When the power supply is turned on, the power supply sequence circuit 33 turns on the power supply voltage in the order of the power supply voltage VDD, the power supply voltage VCS, and the power supply voltage VAA. Further, the power supply sequence circuit 33 shuts off the power supply voltage in the order of the power supply voltage VAA, the power supply voltage VCS, and the power supply voltage VDD when the power supply is cut off.

The control IC 34 inputs a control signal to the inkjet head 14 via the second communication interface 36 and the transmission FPC 31. The control IC 34 operates by the power supply voltage VDD-LOG. The control IC 34 generates a control signal based on a print command input via the first communication interface 35. The control signal includes a clock signal CK, a reset signal RST, an initialization signal INIT, a print data SDI, and the like.

The control IC 34 inputs a clock signal CK, a reset signal RST, an initialization signal INIT, and the like to the inkjet head 14 in response to a command from the system controller 11. Further, the control IC 34 inputs the print data to the inkjet head 14 by the print data SDI. As a result, the head control circuit 13 causes the inkjet head 14 to form an image corresponding to the print data on the print medium.

Further, the control IC 34 inputs various commands to the inkjet head 14 by the print data SDI. For example, when the control IC 34 receives a command (end command) instructing the system controller 11 to end the operation, the control IC 34 inputs a circuit protection command to be described later to the inkjet head 14 by the print data SDI, and sends a reset signal RST. Input to the inkjet head 14 to stop the operation of the inkjet head 14.

Next, the inkjet head 14 will be described.
The inkjet head 14 includes a communication interface 44, a channel group 41, and a driver IC 42. The communication interface 44, the channel group 41, and the driver IC 42 are mounted on the head board 43.

The communication interface 44 is an interface that connects the inkjet head 14 and the head control circuit 13 via the transmission FPC 31. The communication interface 44 includes various terminals to which the transmission FPC 31 is connected.

The channel group 41 is a member that ejects ink. The channel group 41 is configured by arranging a plurality of channels for ejecting ink according to the applied voltage. The channel group 41 includes a first piezoelectric member bonded to the head substrate 43, a second piezoelectric member bonded to the first piezoelectric member, a plurality of electrodes, and a nozzle plate.

The first piezoelectric member and the second piezoelectric member are joined so that their polarization directions face each other. The first piezoelectric member and the second piezoelectric member are formed with a plurality of parallel grooves extending from the second piezoelectric member side to the first piezoelectric member. In addition, electrodes are formed for each groove. The first piezoelectric member and the second piezoelectric member sandwiched between the two electrodes formed in the two grooves are configured as an actuator that is deformed by the potential difference between the two electrodes.

The nozzle plate is a member that seals the groove. The nozzle plate is formed with a plurality of ejection nozzles for communicating the grooves with the outside of the inkjet head 14 for each groove. Further, the groove sealed by the nozzle plate functions as a pressure chamber filled with ink by the pump 16 and having a wall composed of a pair of actuators.

When the drive waveform (output drive voltage) is input from the driver IC 42 to the electrodes of the actuator forming the wall of the pressure chamber, the actuator is deformed and the volume of the pressure chamber changes. As a result, the pressure in the pressure chamber changes, and the ink in the pressure chamber is ejected from the ejection nozzle. In this example, the combination of the pressure chamber and the discharge nozzle is referred to as a channel. That is, the channel group 41 includes channels according to the number of grooves.

The driver IC 42 applies an output drive voltage to the actuator of the channel group 41 based on the signal from the head control circuit 13. As a result, the driver IC 42 deforms the actuator and ejects ink droplets (droplets) from the nozzles.

As shown in FIG. 2, the driver IC 42 includes a receiving unit 51, a command analysis unit 52, a print data buffer 53, a setting data buffer 54, and a drive signal generation unit 55.

The receiving unit 51 receives control signals such as the clock signal CK, the reset signal RST, the initialization signal INIT, and the print data SDI supplied from the head control circuit 13.

The command analysis unit 52 separates the control signals received by the reception unit 51 and stores them in the corresponding buffers. For example, the command analysis unit 52 stores the setting data supplied from the head control circuit 13 in the setting data buffer 54. Further, for example, the command analysis unit 52 stores the print data supplied from the head control circuit 13 in the print data buffer 53.

The print data buffer 53 supplies the stored print data to the drive signal generation unit 55. The print data buffer 53 temporarily stores the print data SDI supplied from the head control circuit 13 and supplies it to the drive signal generation unit 55.

The setting data buffer 54 supplies the stored setting data to the drive signal generation unit 55. The setting data buffer 54 temporarily stores setting data such as the clock signal CK, the reset signal RST, and the initialization signal INIT supplied from the head control circuit 13, and supplies the setting data to the drive signal generation unit 55. Further, the setting data buffer 54 may store a preset voltage pattern or the like. The setting data buffer 54 supplies a preset voltage pattern as a reference voltage to the drive signal generation unit 55.

Even if the command analysis unit 52 controls the timing of supplying the print data from the print data buffer 53 to the drive signal generation unit 55 and the timing of supplying the setting data from the setting data buffer 54 to the drive signal generation unit 55, respectively. Good.

The drive signal generation unit 55 uses the power supply voltage VDD, the power supply voltage VCS, the power supply voltage VAA, and the setting data and the print data supplied from the head control circuit 13 to set the output drive voltage for each channel of the channel group 41 ( Or it is generated for each electrode of the actuator). The drive signal generation unit 55 drives the actuator by inputting the generated output drive voltage to the channel group 41 at an arbitrary timing.

FIG. 3 is an explanatory diagram for explaining an example of the configuration of the drive signal generation unit 55.
The drive signal generation unit 55 includes a logic circuit 61, a level shifter 62, and a driver 63.

The logic circuit 61 operates by the power supply voltage VDD. The logic circuit 61 generates a drive signal for controlling the switching element of the driver 63 based on the clock signal CK, the reset signal RST, the initialization signal INIT, and the print data SDI input as control signals. The logic circuit 61 inputs a drive signal to the level shifter.

The level shifter 62 converts the voltage level of the drive signal input from the logic circuit 61 by using the power supply voltage VCS. The level shifter 62 converts the voltage level of the drive signal input from the logic circuit 61 according to the reference voltage supplied from the setting data buffer 54 by using the power supply voltage VCS. That is, the level shifter 62 converts the voltage level of the drive signal input from the logic circuit 61 into a value corresponding to the reference voltage supplied from the setting data buffer 54. The level shifter 62 inputs a drive signal whose voltage level has been converted to the driver 63.

The driver 63 includes two switching elements composed of, for example, a p-MOSFET and an n-MOSFET for each electrode configured in the channel group 41. The gate of the switching element (MOSFET) is connected to the output terminal of the level shifter 62. The p-MOSFET source is connected to the power supply voltage VAA and the n-MOSFET source is connected to the GND. Further, the electrodes of the channel group 41 are connected to the drains which are the connection points of the two switching elements. With such a configuration, the driver 63 outputs the power supply voltage VAA or GND level at a timing corresponding to the drive signal input from the level shifter 62. As a result, the driver 63 inputs the drive waveform (output drive voltage) to each electrode of the channel group 41. As a result, the driver 63 ejects ink from the ejection nozzle of the channel group 41.

According to the above configuration, the drive signal generation unit 55 can control the voltage applied to the gate terminal of the MOSFET of the driver 63 according to the reference voltage. As a result, the drive signal generation unit 55 can control the output drive voltage applied from the driver 63 to the actuator of the channel group 41.

Next, the signals at the start and end of the operation of the inkjet head 14 and the head control circuit 13 will be described.

FIG. 4 is an explanatory diagram of an example of a signal timing chart in the inkjet head 14 and the head control circuit 13. The horizontal axis represents time and the vertical axis represents voltage.

First, the time when the operation starts will be described.
When the power of the image forming apparatus 1 is turned on at the timing t1, the DC voltage DCV is supplied from the power supply circuit 17 to the head control circuit 13. When the DC voltage DCV is supplied, the power supply voltage generator 32 generates the power supply voltage VAA-IN, the power supply voltage VCS-IN, the power supply voltage VDD-IN, and the power supply voltage VDD-LOG. The power supply voltage generator 32 supplies the power supply voltage VAA-IN, the power supply voltage VCS-IN, and the power supply voltage VDD-IN to the power supply sequence circuit 33, and supplies the power supply voltage VDD-LOG to the control IC 34.

At the timing t2, the power supply sequence circuit 33 starts supplying the power supply voltage VDD.

Further, the control IC 34 is activated when the power supply voltage VDD-LOG is supplied from the power supply voltage generator 32, and sets the reset signal RST from the low level to the high level at the timing t3.

At the timing t4, the power supply sequence circuit 33 starts supplying the power supply voltage VCS. Further, the setting data buffer 54 of the driver IC 42 of the inkjet head 14 starts supplying the reference voltage to the drive signal generation unit 55.

At the timing t5, the power supply sequence circuit 33 starts supplying the power supply voltage VAA. As a result, the power supply voltage VAA is supplied to the driver 63 of the drive signal generation unit 55 of the driver IC 42 of the inkjet head 14, and the output drive voltage is applied to the actuator of the channel group 41.

Next, the time when the operation is completed will be described.
At the timing t6, when the end command is input from the system controller 11 of the image forming apparatus 1, the head control circuit 13 starts the process for stopping the operation of the inkjet head 14.

At the timing t7, the head control circuit 13 inputs a circuit protection command to the inkjet head 14. The head control circuit 13 inputs a circuit protection command to the inkjet head 14 via, for example, a control line of the print data SDI.

When the command analysis unit 52 of the driver IC 42 of the inkjet head 14 receives the circuit protection command, the command analysis unit 52 is set to input the circuit protection voltage pattern stored in the preset data buffer 54 to the drive signal generation unit 55 as a reference voltage. Controls the data buffer 54.

The circuit protection voltage pattern is a voltage pattern that gradually drops to GND as shown as a reference voltage at timings t7 to t8 in FIG. The circuit protection voltage pattern is a voltage pattern that drops from a high level value during normal operation to a value higher than GND once, and then drops to GND.

When the circuit protection voltage pattern shown in FIG. 4 is input to the drive signal generation unit 55, a voltage having a pattern similar to the circuit protection voltage pattern is applied to the gate terminal of the MOSFET of the driver 63. As a result, the output drive voltage output from the driver 63 also becomes a voltage pattern that gradually drops to GND as shown by timings t7 to t8 in FIG.

Further, at the timing t9, the power supply sequence circuit 33 ends the supply of the power supply voltage VAA, and at the timing t10, ends the supply of the power supply voltage VCS.

At the timing t111, the power supply sequence circuit 33 stops the output of the power supply voltage VDD. Further, the control IC 34 stops the output of the clock signal CK, the reset signal RST, the initialization signal INIT, and the like at the timing t11. When the driver IC 42 of the inkjet head 14 receives the reset signal from the head control circuit 13 (when the reset signal changes from high level to low level), the driver IC 42 resets by grounding the electrode of the actuator (connecting to GND). Do. As a result, the operation of the inkjet head 14 is completely stopped.

According to the above configuration, the inkjet head 14 performs a process of gradually reducing the output drive voltage supplied to the actuator before receiving the reset signal instructing that the electrodes of the actuator be grounded. As a result, when the inkjet head 14 receives the reset signal and the electrodes of the actuators are grounded, it is possible to prevent the current concentration in which the current flows from the plurality of actuators to the GND all at once.

(Second embodiment)
FIG. 5 is an explanatory diagram for explaining a configuration example of the head control circuit 13A and the inkjet head 14A according to the second embodiment. The inkjet head 14A according to the second embodiment is different from the inkjet head 14 of the first embodiment in that it does not perform a process of gradually reducing the output drive voltage supplied to the actuator. Further, the head control circuit 13A according to the second embodiment gradually reduces the power supply voltage for generating the output drive voltage supplied to the actuator before supplying the reset signal RST to the inkjet head 14A. It is different from the head control circuit 13 of the first embodiment. The same reference numerals are given to the same configurations as those of the first embodiment, and detailed description thereof will be omitted.

The head control circuit 13A and the inkjet head 14A are configurations for image formation provided in the image forming apparatus 1.

The inkjet head 14A includes a communication interface 44, a channel group 41, and a driver IC 42. The communication interface 44, the channel group 41, and the driver IC 42A are mounted on the head board 43.

The driver IC 42A applies an output drive voltage to the actuator of the channel group 41 based on the signal from the head control circuit 13A. As a result, the driver IC 42 deforms the actuator and ejects ink droplets (droplets) from the nozzles.

The head control circuit 13A includes a first communication interface 35, a second communication interface 36, a power supply voltage generator 32, a power supply sequence circuit 33, and a control IC 34A.

The control IC 34A inputs a control signal to the inkjet head 14A via the second communication interface 36 and the transmission FPC 31. The control IC 34A operates by the power supply voltage VDD-LOG. The control IC 34A generates a control signal based on a print command input via the first communication interface 35. The control signal includes a clock signal CK, a reset signal RST, an initialization signal INIT, a print data SDI, and the like.

The control IC 34A inputs a clock signal CK, a reset signal RST, an initialization signal INIT, and the like to the inkjet head 14A in response to a command from the system controller 11. Further, the control IC 34A inputs the print data to the inkjet head 14A by the print data SDI. As a result, the head control circuit 13A causes the inkjet head 14A to form an image corresponding to the print data on the print medium.

Next, signals at the end of operation of the inkjet head 14A and the head control circuit 13A will be described.

FIG. 6 is an explanatory diagram of an example of a signal timing chart in the inkjet head 14A and the head control circuit 13A. The horizontal axis represents time and the vertical axis represents voltage. Since the timings t11 to t15 are the same as the timings t1 to t5 of the first embodiment, the description thereof will be omitted.

At the timing t16, when the end command is input from the system controller 11 of the image forming apparatus 1, the head control circuit 13A starts the process for stopping the operation of the inkjet head 14A.

At timing t17 to timing t18, the control IC 34A of the head control circuit 13A controls the power supply sequence circuit 33 or the power supply voltage generator 32 so as to gradually reduce the power supply voltage VAA output from the power supply sequence circuit 33. .. The power supply voltage VAA is a power supply voltage used to generate the output drive voltage. That is, by gradually reducing the power supply voltage VAA, the output drive voltage applied to the actuator of the channel group 41 is also gradually reduced. For example, the control IC 34A controls the power supply sequence circuit 33 or the power supply voltage generator 32 so that the value of the power supply voltage VAA during normal operation is once lowered to a value higher than GND and then dropped to GND.

At the timing t19, the power supply sequence circuit 33 ends the supply of the power supply voltage VCS.

At the timing t20, the power supply sequence circuit 33 stops the output of the power supply voltage VDD. Further, the control IC 34A stops the output of the clock signal CK, the reset signal RST, the initialization signal INIT, and the like at the timing t20. As a result, the driver IC 42A of the inkjet head 14A brings the electrodes of the actuator to the ground (connected to GND). As a result, the operation of the inkjet head 14A is completely stopped.

As described above, the control IC 34A of the head control circuit 13A controls the power supply sequence circuit 33 or the power supply voltage generator 32 so as to gradually reduce the power supply voltage VAA before inputting the reset signal RST. With this configuration as well, the output drive voltage supplied to the actuator can be gradually reduced before the inkjet head 14 touches the electrodes of the actuator to the ground. As a result, it is possible to prevent current concentration in which current flows from the plurality of actuators to the GND all at once.

In the above example, the control IC 34A of the head control circuit 13A controls the power supply sequence circuit 33 or the power supply voltage generator 32 so as to gradually reduce the power supply voltage VAA before inputting the RST signal. Although it was explained that it is a configuration, it is not limited to this configuration. The control IC 34A of the head control circuit 13A may be configured to control the power supply sequence circuit 33 or the power supply voltage generator 32 so as to gradually reduce the power supply voltage VCS before inputting the RST signal.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... image forming device, 11 ... system controller, 12 ... communication interface, 13 ... head control circuit, 13A ... head control circuit, 14 ... inkjet head, 14A ... inkjet head, 15 ... transfer device, 16 ... pump, 17 ... power supply Circuit, 21 ... Processor, 22 ... Memory, 31 ... Transmission FPC, 32 ... Power supply voltage generator, 33 ... Power supply sequence circuit, 34 ... Control IC, 34A ... Control IC, 35 ... First communication interface, 36 ... Second Communication interface, 41 ... Channel group, 42 ... Driver IC, 42A ... Driver IC, 43 ... Head board, 44 ... Communication interface, 51 ... Receiver, 52 ... Command analysis unit, 53 ... Print data buffer, 54 ... Setting data Buffer, 55 ... drive signal generator, 61 ... logic circuit, 62 ... level shifter, 63 ... driver.

Claims (5)

A group of channels that eject ink from the nozzle according to the deformation of the actuator,
A driver IC that applies an output drive voltage to the actuator based on a signal from the controller,
Equipped with
The driver IC is an inkjet head that gradually reduces the output drive voltage when a circuit protection command supplied from the controller is received before the reset command. The inkjet head according to claim 1, wherein the driver IC sets the output drive voltage to a value higher than that of GND once, and then drops the output drive voltage to GND. The inkjet head according to claim 1 or 2, wherein the driver IC controls the voltage of the gate terminal of the MOSFET that applies the output drive voltage to the actuator to gradually reduce the output drive voltage applied to the actuator. .. An inkjet head including a channel group for ejecting ink from a nozzle according to the deformation of the actuator, and a driver IC for applying an output drive voltage to the actuator based on a signal from the controller.
A head control circuit including a power supply sequence circuit that supplies the output drive voltage to the inkjet head, and a control IC that controls the inkjet head and the power supply sequence circuit.
Equipped with
The control IC controls the power supply sequence circuit so as to gradually reduce the output drive voltage before resetting the inkjet head.
Image forming device. The image forming apparatus according to claim 4, wherein the control IC controls the power supply sequence circuit so that the output drive voltage is once set to a value higher than the GND and then dropped to the GND.

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