JP2021044456A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can secure the reliability by preventing the inclination of a semiconductor chip due to the wettability of solder.SOLUTION: A semiconductor device includes: an insulating circuit board 2; a chip connection member 3 disposed on a conductive layer 21 provided on an upper surface of the insulating circuit board 2; a semiconductor chip having a back surface bonded by the chip connection member 3 and including a first electrode pad 15 on one end side and a second electrode pad 16 on the other end side, the second electrode pad 16 allowing larger current to flow than the first electrode pad 15; a first connection pin 5 press-fitted in a first penetration hole 25 provided to a wiring board 7 opposite to the insulating circuit board 2 and having one end bonded to a first solder material 4a disposed on the first electrode pad 15; and a second connection pin 6 press-fitted in a second penetration hole 26 provided to the wiring board 7 and having one end bonded to a second solder material 4b disposed on the second electrode pad 16. A first plating layer of the first connection pin 5 has higher solder wettability than a second plating layer of the second connection pin.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a power semiconductor element.

Power semiconductor modules are widely applied in fields where efficient power conversion is required. Examples include renewable energy fields such as solar power generation and wind power generation, in-vehicle fields such as hybrid vehicles and electric vehicles, and railway fields such as vehicles, which have been attracting attention in recent years. Such a power semiconductor module contains a semiconductor chip having a power semiconductor element such as a switching element or a diode. Wide bandgap semiconductors such as silicon (Si) semiconductors and silicon carbide (SiC) semiconductors are used as power semiconductor elements. Compared to Si semiconductors, SiC semiconductors have features such as high withstand voltage, high heat resistance, and low loss, and by using them in power semiconductor modules, it is possible to reduce the size and loss of the device. In a power semiconductor module, a power semiconductor element is sealed with a sealing material containing an epoxy resin having excellent moisture resistance, heat resistance, mechanical properties, and the like.

In Patent Document 1, each of the lead terminals is connected to the source electrode and the gate electrode of the semiconductor chip via gold (Au) bumps, and the die terminal is connected to the back electrode of the semiconductor chip via silver (Ag) plating. It is stated that Au bumps are evenly arranged on the entire surface of each of the source electrode and the gate electrode by the ball bonding method. The die terminal is bonded to the back electrode by an ultrasonic bonding method while heating. In Patent Document 2, in a power semiconductor module, a connection pin such as an implant pin and a wiring board such as a printed wiring board (PCB) are used instead of a bonding wire or a lead frame for electrical wiring to a surface electrode of a semiconductor chip. The structure is disclosed. A source pad and a gate pad electrically connected to the source electrode and the gate electrode are arranged on the surface of the semiconductor chip. The connection pins inserted in the wiring board are electrically connected to each of the source pad and the gate pad by soldering.

The area of the source pad and the gate pad arranged on the surface of the semiconductor chip are different, and the number of connection pins to be soldered is also different. Therefore, when the connection pin is soldered to the source pad and the gate pad, the semiconductor chip is tilted and the reliability of the power semiconductor module is lowered.

Japanese Unexamined Patent Publication No. 2008-311685 Japanese Patent No. 5241177

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of preventing tilting of a semiconductor chip due to wettability of solder and ensuring reliability. To do.

In order to solve the above problems, one aspect of the present invention includes (a) an insulated circuit board, (b) a chip connecting member arranged on a conductive layer provided on the upper surface of the insulated circuit board, and (c). ) A semiconductor chip whose back surface is joined by a chip connecting member and which has a first electrode pad on one end side and a second electrode pad on the other end side where a larger current flows than the first electrode pad, and (d) an insulating circuit board. The first connection pin, which is press-fitted into the first through hole provided in the facing wiring board and one end is joined to the first solder material arranged on the first electrode pad, and (e) provided in the wiring board. The first plating layer provided on the surface of the first connection pin is provided with a second connection pin which is press-fitted into the second through hole and has one end bonded to the second solder material arranged on the second electrode pad. It is a gist that the solder is a semiconductor device having a higher solder wettability than the second plating layer provided on the surface of the second connection pin.

According to the present invention, it is possible to provide a semiconductor device capable of preventing tilting of a semiconductor chip due to wettability of solder and ensuring reliability.

It is sectional drawing which shows an example of the semiconductor device which concerns on the typical embodiment of this invention (hereinafter referred to as "representative embodiment"). It is a plan schematic diagram which shows an example of the arrangement of the connection pin with respect to the semiconductor chip which becomes a part of the semiconductor device of FIG. FIG. 3A is a schematic cross-sectional view showing an example of a first connection pin as a control electrode connection pin used in the semiconductor device according to the representative embodiment, and FIG. 3B is used for the semiconductor device according to the representative embodiment. It is sectional drawing which shows an example of the 2nd connection pin as a connection pin for a main electrode. It is an enlarged cross-sectional schematic view around the semiconductor chip seen from the line AA of FIG. FIG. 5A is a schematic cross-sectional view showing a control electrode connection pin used in a conventional semiconductor device, and FIG. 5B is a cross-sectional schematic view showing a main electrode connection pin of a conventional semiconductor device. It is an enlarged cross-sectional schematic diagram around a semiconductor chip which becomes a part of a conventional semiconductor device. It is sectional drawing explaining an example of the manufacturing method of the wiring board used for the semiconductor device which concerns on a typical embodiment. FIG. 5 is a schematic cross-sectional view following FIG. 7 for explaining an example of a method for manufacturing a wiring board used in a semiconductor device according to a representative embodiment. It is a table explaining an example of the thermal cycle test result with respect to the semiconductor device which concerns on a representative embodiment.

A representative embodiment will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the directions of "left and right" and "up and down" in the following description are merely definitions for convenience of explanation, and do not limit the technical idea of the present invention. Therefore, for example, if the paper surface is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper surface is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". Of course it will be.

In the present specification, the source region of the MIS transistor is a “one main electrode region” that can be selected as the emitter region of the insulated gate bipolar transistor (IGBT). Further, in a thyristor such as a MIS controlled electrostatic induction thyristor (SI thyristor), one of the main electrode regions can be selected as a cathode region. The drain region of the MIS transistor is the "other main electrode region" of the semiconductor device, which can be selected as the collector region in the IGBT and the anode region in the thyristor. As used herein, the term "main electrode region" means either one main electrode region or the other main electrode region, which is appropriate from the common general technical knowledge of those skilled in the art. Further, the “control electrode” means an electrode that controls the main current flowing between one main electrode region and the other main electrode region. For example, a gate electrode that controls a main current flowing between a source region and a drain region in a MIS transistor, or between an emitter region and a collector region in an IGBT is applicable.

(Structure of semiconductor device)
As shown in FIG. 1, the semiconductor device according to the representative embodiment includes an insulating circuit board 2, a semiconductor chip 1 mounted on the insulating circuit board 2, and a wiring board 7 arranged above the semiconductor chip 1. The insulating circuit board 2 has an insulating plate 22, a conductive layer 21 which is a wiring layer patterned on the upper surface of the insulating plate 22, and a conductive layer 23 which is a heat radiating layer provided on the lower surface of the insulating plate 22. The wiring board 7 has a resin plate 72, a wiring layer 71 patterned on the upper surface of the resin plate 72, and a wiring layer 73 patterned on the lower surface of the resin plate 72. The lower surface side of the wiring board 7 is provided so as to face parallel to the upper surface side of the conductive layer 21 of the insulating circuit board 2. In the wiring board 7, the first connection pin 5 as a connection pin for a control electrode such as an implant pin and the second connection pin 6 as a connection pin for a main electrode penetrate the first through hole 25 so as to penetrate the wiring board 7. And are press-fitted into the second through hole 26, respectively. The lower surface of the semiconductor chip 1 is electrically connected to the conductive layer 21 of the insulating circuit board 2 via a chip connecting member 3 such as solder. Although not shown, a conductor layer serving as a control electrode (gate electrode) and a semiconductor region serving as a main electrode region (source electrode region) are provided on the upper portion of the semiconductor substrate forming the semiconductor chip 1. As shown in FIG. 2, the upper surface of the semiconductor chip 1 has a first electrode pad (control electrode pad) 15 electrically connected to the control electrode and a second electrode pad electrically connected to the main electrode region. (Main electrode pads) 16 are provided on the protective film 9 made of an insulating film or the like. The first electrode pad 15 is arranged on one end side of the semiconductor chip 1, and the second electrode pad 16 is arranged so as to face the first electrode pad 15 on the other end side of the semiconductor chip 1 as a plane pattern. The first solder material 4a and the second solder material 4b are arranged on the first electrode pad 15 and the second electrode pad 16, respectively. One end of the first connection pin 5 is joined to the first solder material 4a and is electrically connected to the control electrode of the semiconductor chip 1. One end of the second connection pin 6 is joined to the first solder material 4b and is electrically connected to the main electrode region of the semiconductor chip 1. As a semiconductor device according to a typical embodiment, as shown in FIG. 1, a wiring board 7, a first connection pin 5, a second connection pin 6, a semiconductor chip 1, and a part of an insulating circuit board 2 are attached to a sealing resin 8. A sealed structure is exemplified, but is not limited. For example, the conductive layer 23 of the insulating circuit board 2 may be connected to the heat dissipation base via a bonding layer such as solder. Further, the structure may be such that the sealing resin 8 is built in the outer case.

A power semiconductor element such as an insulated gate bipolar transistor (IGBT), a MOS field effect transistor (MOSFET), or a Schottky barrier diode (SBD) using silicon carbide (SiC) is used for the semiconductor chip 1. The semiconductor chip 1 is not limited to SiC. In addition to SiC, hexagonal semiconductor materials such as silicon (Si), gallium nitride (GaN), lonsdaleite (hexagonal diamond), and aluminum nitride (AlN) can be used. Further, as a power semiconductor element, a bipolar transistor (BPT), a static induction transistor (SIT), an electrostatic induction thyristor (SI thyristor), a gate turn-off thyristor (GTO thyristor), or the like can also be used. Further, the above-mentioned semiconductor elements may be used in combination. For example, a hybrid module using a Si-IGBT and a SiC-SBD may be used. Further, as shown in FIGS. 1 and 2, a structure in which one semiconductor chip 1 is mounted has been illustrated, but the structure is not limited. The number of semiconductor chips 1 to be mounted may be plural. Further, the number of the insulating circuit boards 2 and the wiring boards 7 to be mounted may be plural.

As shown in FIG. 2, as the first electrode pad 15 and the second electrode pad 16 provided on the upper surface of the semiconductor chip 1, a rectangular surface pattern has been illustrated, but the present invention is not limited. It is desirable that the second electrode pad 16 on which the main current of the semiconductor chip 1 is energized has a larger area than the first electrode pad 15 electrically connected to the control electrode that controls the energization of the main current. In FIG. 2, one first connection pin 5 is arranged on the first electrode pad 15, and two second connection pins 6 are arranged on the second electrode pad 16, but the present invention is not limited. The first connection pin 5 may be 1 or more, and the second connection pin 6 may be 1 or 3 or more. In addition. The chip size of the semiconductor chip 1 is preferably less than 10 mm square.

As the insulating plate 22 of the insulating circuit board 2, a ceramic substrate having excellent electrical insulation and thermal conductivity is used. For the ceramic substrate, for example, silicon nitride (Si ₃ N ₄ ), aluminum nitride (Al _{N), alumina (Al 2} O ₃ ) and the like can be adopted. Particularly, in the high-voltage applications, the material preferably having both electrical insulation and thermal conductivity, for example, it is possible to use AlN or Si ₃ N _4. As the conductive layers 21 and 23 of the insulating circuit board 2, metal materials such as copper (Cu) and aluminum (Al), which are excellent in workability, are used. Further, the surface of the metal layer such as Cu or Al may be subjected to a treatment such as nickel (Ni) plating for the purpose of rust prevention or the like. The insulating circuit board 2 includes, for example, a direct copper bonded (DCB) substrate in which copper is eutectic bonded to the surface of a ceramic substrate, an AMB substrate in which a metal is arranged on the surface of the ceramic substrate by an active metal brazing (AMB) method, and the like. Can be adopted.

Lead-free solder or the like can be used as the solder material of the chip connecting member 3, the solder material 4a for the control electrode, and the solder material 4b for the main electrode. For example, as a solder material, tin (Sn) -silver (Ag) -copper (Cu) system, Sn-antimon (Sb) system, Sn-Sb-Ag system, Sn-Cu system, Sn-Sb-Ag-Cu system. , Sn-Cu-Ni type, Sn-Ag type and the like can be adopted.

As the wiring board 7, a resin plate 72 such as a polyimide film substrate or an epoxy film substrate, and a printed circuit board (PCB) or the like having wiring layers 71 and 73 in which conductive layers such as Cu and Al are patterned on the resin plate 72 are used. Be done. The surface of the conductive layer such as Cu or Al may be treated with Ni plating or the like for the purpose of preventing rust. Alternatively, a treatment such as tin (Sn) plating may be performed for the purpose of joining. On the surfaces of the first through hole 25 and the second through hole 26 of the wiring board 7, a Sn plating layer is provided on a Ni film as a base layer. When electrical connection with the wiring layers 71 and 73 of the wiring board 7 is required, a Sn plating layer in which the first connection pin 5 and the second connection pin 6 are provided in the first through hole 25 and the second through hole 26 is provided. It is metallically connected to the wiring layer 71 on the upper surface or the wiring layer 73 on the lower surface. If electrical connection to the wiring layers 71 and 73 of the wiring board 7 is not required, the first connection pin 5 is provided without providing a plating layer in the first through hole 25 and the second through hole 26 of the wiring board 7. The structure may be such that the second connection pin 6 is in direct contact with the resin plate 72.

The sealing resin 8 is formed of an epoxy resin composition containing an epoxy resin main agent and a curing agent, to which an inorganic filler and other additives are optionally added. As the epoxy resin main agent, an aliphatic epoxy resin, an alicyclic epoxy resin, or the like can be used. Further, as the main agent, a maleide resin, a cyanate resin or the like may be used instead of the epoxy resin. Alternatively, as the main agent, two or more kinds of resins such as epoxy resin, maleide resin and cyanate resin may be mixed and used.

By pulling out an external terminal pin (not shown) bonded to the conductive layer 21 on the upper surface of the insulating circuit board 2 with a bonding material such as solder to the outside of the sealing resin 8, it can be used as an external connection terminal. As the external connection pin, a metal material such as Cu, which has excellent conductivity, can be adopted.

As shown in FIGS. 1 and 2, the first connection pin 5 and the second connection pin 6 are provided on the upper surface of the semiconductor chip 1 via the first through hole 25 and the second through hole 26 of the wiring board 7, respectively. It is electrically connected to the first electrode pad 15 and the second electrode pad 16 provided. As shown in FIG. 3A, the first connection pin 5 is provided with a columnar pin main portion 10 made of Cu and the surface of the pin main portion 10 by plating treatment, and has good solder wettability, for example, Ag. It has a first plating layer 35 such as. On the other hand, as shown in FIG. 3B, the second connection pin 6 is provided with a columnar pin main portion 10 made of Cu and the surface of the pin main portion 10 by plating treatment, and has first solder wettability. It has a second plating layer 36, such as Ni, which is inferior to the plating layer 35.

Here, the conductive layer 21 of the insulating circuit board 2 and the semiconductor chip 1 are joined, and the first electrode pad 15 and the second electrode pad 16 of the semiconductor chip 1 are joined to the first connection pin 5 and the second connection pin 6. The method will be described. First, a solder paste such as cream solder is selectively applied to the upper surface of the conductive layer 21 of the insulating circuit board 2 by a dispense coating method, a printing method, or the like to a thickness of, for example, about 50 μm or more and 150 μm or less. The semiconductor chip 1 is mounted on the solder paste applied to the upper surface of the conductive layer 21. Next, a solder paste such as cream solder is applied onto each of the first electrode pad 15 and the second electrode pad 16 of the semiconductor chip 1 shown in FIG. 2 by a dispense coating method, a printing method, or the like, for example, about 50 μm or more and 150 μm or less. Selectively apply with the thickness of. Then, the first connection pin 5 and the second connection pin 6 press-fitted into the wiring board 7 are placed in contact with each other on the solder paste applied to each of the first electrode pad 15 and the second electrode pad 16. After that, the solder is melted at a temperature of about 200 ° C. or higher and 300 ° C. or lower by a reflow technique such as vacuum nitrogen reflow or formic acid reduction reflow, and as shown in FIG. 1, the conductive layer 21 and the semiconductor chip 1 are connected by the chip connecting member 3. Be joined. At the same time, the first electrode pad 15, the second electrode pad 16, and the first connection pin 5 and the second connection pin 6 are joined by the control electrode solder material 4a and the main electrode solder material 4b, respectively.

FIG. 4 is an enlarged cross-sectional view of the semiconductor chip 1 of the semiconductor device according to the representative embodiment produced by the above joining method. As shown in FIG. 4, the first connection pin 5 is wetted with the control electrode solder material 4a, and the two second connection pins 6 shown in FIG. 2 are also wetted with the main electrode solder material 4b. Is occurring. Although not explicitly shown in FIG. 4, as shown in FIGS. 3A and 3B, the first plating layer 35 made of Ag or the like of the first connection pin 5 is made of Ni or the like of the second connection pin 6. The wettability of the solder is better than that of the second plating layer 36. Therefore, the wettability of the solder of the first connection pin 5 is larger than that of each of the two second connection pins 6. Further, the chip connecting member 3 for joining the semiconductor chip 1 and the conductive layer 21 of the insulating circuit board 2 has a substantially flat difference of less than 20 μm between the thickness Tg on the control electrode side and the thickness Ts on the main electrode side. .. In the following, as described with reference to FIGS. 5 and 6, in the case of the first connection pin 50 and the second connection pin 60 used in the conventional semiconductor device, the main electrode side is lifted with respect to the control electrode side. There is a problem that the semiconductor chip 1 is tilted. On the other hand, in the semiconductor device according to the representative embodiment, the semiconductor chip 1 can be mounted without being tilted, and cracks due to thermal stress applied to the chip connecting member 3 can be prevented from occurring when a thermal cycle is applied. It is possible to suppress a decrease in reliability.

As shown in FIG. 5A, the first connection pin (connection pin for control electrode) 50 of the semiconductor chip 1 of the conventional semiconductor device is a columnar pin main portion 10 made of Cu and a pin main portion 10. It has a plating layer 35a such as Ag having good solder wettability, which is provided on the surface by a plating treatment. Similarly, as shown in FIG. 5B, the second connection pin (connection pin for main electrode) 60 has a columnar pin main portion 10 made of Cu and a pin main portion, similarly to the first connection pin 50. It has a plating layer 35a such as Ag having good solder wettability, which is provided on the surface of the portion 10 by a plating treatment. As described above, in the conventional semiconductor device, the first connection pin 50 and the second connection pin 60 are both provided with a plating layer 35a having good solder wettability.

Similar to the case of the semiconductor device according to the representative embodiment described above, in the case of the conventional semiconductor device, the solder paste is applied to the upper surface of the conductive layer 21 of the insulating circuit board 2 by a dispense coating method, a printing method, etc. Selectively apply to a thickness of about 150 μm or less. The semiconductor chip 1 is mounted on the solder paste applied to the upper surface of the conductive layer 21. Similar to the semiconductor chip 1 shown in FIG. 2, a solder paste is applied onto each of the first electrode pad 15 and the second electrode pad 16 by a dispense coating method, a printing method, or the like to a thickness of, for example, about 50 μm or more and 150 μm or less. Apply selectively. The first electrode pad 15 corresponds to the “control electrode pad”, and the second electrode pad 16 corresponds to the “main electrode pad”. The first connection pin 50 and the second connection pin 60 press-fitted into the wiring board 7 are placed in contact with each other on the solder paste applied to each of the first electrode pad 15 and the second electrode pad 16. Also in the case of a conventional semiconductor device, the solder is melted at a temperature of about 200 ° C. or higher and 300 ° C. or lower by reflow technology such as vacuum nitrogen reflow or formic acid reduction reflow, and as shown in FIG. 6, the conductive layer 21 and the semiconductor chip 1 are combined. Is joined by the chip connecting member 3a. At the same time, the first electrode pad 15, the second electrode pad 16, and the first connection pin 50 and the second connection pin 60 are joined by the control electrode solder material 40a and the main electrode solder material 40b, respectively.

As shown in FIG. 6, in the first connection pin 50 and the second connection pin 60, the control electrode solder material 40a and the main electrode solder material 40b are wetted with the same magnitude, respectively. Similar to the semiconductor device according to the representative embodiment shown in FIG. 2, two second connection pins 60 are joined to the second electrode pad 16 in the conventional semiconductor device. Therefore, the amount of solder applied to the second electrode pad 16 is larger than that of the first electrode pad 15. Further, as shown in FIGS. 5A and 5B, the first connection pin 50 and the second connection pin 60 both have a plating layer 35a having good solder wettability, which is made of Ag or the like. Therefore, the wetting of the solder during the reflow process is stronger for the two second connection pins 6 than for the one first connection pin 50, and the main electrode side of the semiconductor chip 1 rises with respect to the control electrode side. Power works like this. As a result, as shown in FIG. 6, the semiconductor chip 1 has a problem that the main electrode side is lifted and tilted with respect to the control electrode side. As shown in FIG. 6, in the chip connecting member 3a for joining the semiconductor chip 1 and the conductive layer 21 of the insulating circuit board 2, the difference between the thickness Tg on the control electrode side and the thickness Ts on the main electrode side is 20 μm or more. For example, the inclination is about 50 μm or more and 150 μm or less. As a result, in the conventional semiconductor device, cracks are generated due to the thermal stress applied to the chip connecting member 3a when the thermal cycle is loaded, and the reliability is lowered.

On the other hand, in a typical embodiment, one first connection pin 5 having a first plating layer 35 such as Ag having good solder wettability and a second plating layer 36 such as Ni having inferior solder wettability to Ag have 2 The second connection pin 6 of the book is used to prevent the semiconductor chip 1 from tilting. If the opening area ratio of the first electrode pad 15 and the second electrode pad 16 is reversed and the amount of solder paste applied is also reversed, the solder wettability of the first connection pin 5 and the second connection pin 6 The relationship should be reversed. For example, the second connection pin 6 has a first plating layer 35 such as Ag having good solder wettability, and the first connection pin 5 has a second plating layer 36 such as Ni having inferior solder wettability to Ag. do it. As described above, Ag plating is used as the first plating layer 35, and Ni plating is used as the second plating layer 36, but the description is not limited. For example, Au, Sn, etc., which have better solder wettability than Ni, can be used as the first plating layer 35. Further, as the second plating layer 36, a conductive film such as a metal having a solder wettability inferior to that of Ag, Au, Sn or the like can be used.

The size of the semiconductor chip 1 is preferably less than 10 mm square, more preferably 3 mm square or more and 5 mm square or less. Conventional semiconductor chips using Si have dimensions of 10 mm square or more, for example, 12 mm square or more and 15 mm square or less. As described above, in the conventional Si semiconductor chip having a large area, the solder gets wet during the reflow process, but the fluctuation and inclination of the thickness of the entire solder material under the semiconductor chip do not appear remarkably. In the semiconductor device according to the representative embodiment, the semiconductor chip 1 of a wide bandgap semiconductor such as SiC is used. The SiC semiconductor chip 1 can increase the current density and can be miniaturized as a power semiconductor element. Therefore, even if the size of the semiconductor chip 1 is less than 10 mm square, the characteristics as a power semiconductor element can be sufficiently realized. When the dimensions of the semiconductor chip 1 are reduced to less than 10 mm square, or 3 mm square or more and 5 mm square or less, the semiconductor chip 1 is lifted due to the wetting of the solder during the reflow process. Therefore, it is important to lower the solder wettability of the second connection pin 6 as compared with the first connection pin 5 to prevent the semiconductor chip 1 from being lifted due to the wetting of the solder.

Further, an example of a method of inserting the connection pin of the wiring board 7 of the semiconductor device according to the representative embodiment will be described with reference to FIGS. 7 and 8. The connection pin insertion method described below is an example, and it may be feasible by various other insertion methods including this modification as long as it is within the scope of claims. Of course.

First, as the first connection pin 5, a plurality of first connection pins having a diameter of about 0.45 mm plated with Ag or the like having good solder wettability are prepared. Further, as the second connection pin 6, a plurality of second connection pins having a diameter of about 0.50 mm plated with Ni or the like, which is inferior in solder wettability to Ag, are prepared. Further, a first through hole 25 having a diameter of about 0.46 mm and a second through hole 26 having a diameter of about 0.51 mm are opened at predetermined positions on the wiring board 7. The wiring board 7 is arranged in the pin insertion device, and a plurality of first connection pins are scattered on the wiring board 7 to give vibration to the wiring board 7. As shown in FIG. 7, a plurality of first connection pins are inserted into the first through hole 25 due to the vibration of the wiring board 7, but the second through hole 26 comes off even if it is once inserted. When the first connection pin 5 is inserted into the first through hole 25, a plurality of second connection pins are scattered on the wiring board 7 to give vibration to the wiring board 7. As shown in FIG. 8, a plurality of second connection pins are inserted into the second through hole 26 due to the vibration of the wiring board 7, but are not inserted into the first through hole 25. In this way, the second connection pin 6 is inserted into the second through hole 26. The diameters of the first connection pin and the second connection pin may be reversed, but since the current density of the second connection pin 6 is high, it is desirable to increase the diameter of the second connection pin corresponding to the second connection pin 6. Further, in the above, the thin first connecting pin is inserted first, but the second connecting pin having a large diameter may be inserted first.

As an example, a semiconductor device according to a representative embodiment was prototyped, and the inclination and power cycle of the semiconductor chip 1 were evaluated. Shown in FIG. 1 the insulating circuit board 2, Si ₃ N ₄ ceramic substrate having a thickness of about 0.32mm as the insulating plate 22, and a conductive plate such as Cu having a thickness of 0.3mm as the conductive layers 21 and 23 Using. By soldering using a nitrogen (N ₂ ) atmosphere reflow furnace, the semiconductor chip 1 and the external terminal pin are joined on the insulating circuit board 2, and the connection pin inserted in the wiring board 7 is joined on the semiconductor chip 1. Arranged. The arranged members were installed in the mold. The aliphatic epoxy resin main agent, the curing agent, and the inorganic filler were mixed at a predetermined mass ratio, and vacuum defoaming was performed. Then, the resin was injected into a mold, temporarily cured at 100 ° C. for 1 hour, and then secondarily cured at 150 ° C. for 3 hours to prepare a semiconductor device. In Example 1, the first connection pin 5 was Ag-plated with a diameter of 0.45 μm, and the second connection pin 6 was Ni-plated with a diameter of 0.45 μm. In Example 2, the first connection pin 5 was Ag-plated with a diameter of 0.45 μm, and the second connection pin 6 was Ni-plated with a diameter of 0.50 μm. Further, as Comparative Example 1, the first connection pin 5 was Ag-plated with a diameter of 0.45 μm and the second connection pin 6 was Ag-plated with a diameter of 0.45 μm as in the conventional case.

A thermal cycle test was carried out on the semiconductor devices of Examples 1 and 2 and Comparative Example 1 produced. The thermal cycle test is performed at the maximum joint temperature Tjmax = 175 ° C. and Tjmin = 75 ° C. (temperature difference ΔT = 100 ° C.) to determine the rate of increase in thermal resistance [K / W] between the joint and the case after 200,000 cycles. confirmed. We also confirmed the inclination of the semiconductor chip at the initial stage before the thermal cycle test. FIG. 7 is a table showing the evaluation results by the thermal cycle test. As shown in the table of FIG. 7, the inclination of the semiconductor chip 1 was less than 20 μm in both Example 1 and Example 2, and it was confirmed that the semiconductor chip 1 was substantially flat. It was confirmed that the rate of increase in thermal resistance after 200,000 cycles was about 8% in Example 1 and about 7% in Example 2, and the increase in thermal resistance could be suppressed. On the other hand, in Comparative Example 1, it can be seen that the inclination of the semiconductor chip 1 is as large as about 100 μm or more and 120 μm or less. The rate of increase in thermal resistance after 200,000 cycles is as large as about 20%, and as shown in FIG. 6, the chip connecting member 3a is tilted and partially thinned, so that the chip connecting member 3a is likely to crack. , Invites an increase in thermal resistance.

In a typical embodiment, the first plating layer 35 made of Ag or the like of the first connection pin 5 has better solder wettability than the second plating layer 36 made of Ni or the like of the second connection pin 6. Therefore, the wettability of the solder of the first connection pin 5 is larger than that of each of the two second connection pins 6. Since the wetting of the solder of the second connection pin 6 is reduced, it is possible to prevent the semiconductor chip 1 from being lifted due to the wetting of the solder during reflow. As a result, in the chip connecting member 3 for joining the semiconductor chip 1 and the conductive layer 21 of the insulating circuit board 2, the difference between the thickness Tg on the control electrode side and the thickness Ts on the main electrode side shown in FIG. 4 is 20 μm. If it is less than, it becomes almost flat. Therefore, in the semiconductor device according to the representative embodiment, the semiconductor chip 1 can be mounted without being tilted, and cracks due to thermal stress applied to the chip connecting member 3 are prevented from being generated when a thermal cycle is applied, so that reliability is achieved. It becomes possible to suppress the decrease of.

(Other embodiments)
As mentioned above, the invention has been described in one representative embodiment, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Understanding the gist of disclosure of the above representative embodiments will make it clear to those skilled in the art that various alternative embodiments, examples and operational techniques may be included in the present invention. Further, it goes without saying that the present invention includes various embodiments not described here, such as a configuration in which each configuration described in the above representative embodiment and each modification is arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the claims, which are appropriate from the above exemplary description.

1 ... Semiconductor chip 2 ... Insulated circuit board 3 ... Chip connecting member 4a ... First solder material 4b ... Second solder material 5 ... First connection pin (connection pin for control electrode)
6 ... 2nd connection pin (connection pin for main electrode)
7 ... Wiring board 8 ... Encapsulating resin 9 ... Protective film 10 ... Pin main part 15 ... First electrode pad (control electrode pad)
16 ... Second electrode pad (main electrode pad)
21, 23 ... Conductive layer 22 ... Insulating plate 25 ... First through hole 26 ... Second through hole 35 ... First plating layer 36 ... Second plating layer 71, 73 ... Wiring layer 72 ... Resin plate

Claims (8)

Insulated circuit board and
A chip connecting member arranged on a conductive layer provided on the upper surface of the insulating circuit board, and
A semiconductor chip having a back surface joined by the chip connecting member and having a first electrode pad on one end side and a second electrode pad on the other end side through which a larger current than the first electrode pad flows.
A first connection pin that is press-fitted into a first through hole provided in a wiring board facing the insulating circuit board and one end of which is joined to a first solder material arranged on the first electrode pad.
It is provided with a second connection pin that is press-fitted into a second through hole provided in the wiring board and has one end bonded to a second solder material arranged on the second electrode pad.
A semiconductor device characterized in that the first plating layer provided on the surface of the first connection pin has higher solder wettability than the second plating layer provided on the surface of the second connection pin. The semiconductor device according to claim 1, wherein the difference in film thickness of the chip connecting member between the one end side and the other end side is less than 20 μm. The semiconductor device according to claim 1 or 2, wherein the first plating layer of the first connection pin is made of silver or gold, and the second plating layer of the second connection pin is made of nickel. The semiconductor device according to any one of claims 1 to 3, wherein the number of the second connection pins is at least a plurality and the number is larger than that of the first connection pins. The semiconductor device according to any one of claims 1 to 4, wherein the surface area of the second electrode pad is larger than the surface area of the first electrode pad. The semiconductor device according to any one of claims 1 to 5, wherein the amount of the first solder material is larger than that of the second solder material. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor chip has a size of less than 10 mm × 10 mm. The semiconductor device according to any one of claims 1 to 7, wherein the first connection pin and the second connection pin have different diameters.

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