JP2021044415A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing switching loss.SOLUTION: A semiconductor device 1 includes a cascoded transistor chip 2, a temperature detection element 5 that detects the operating temperature of the transistor chip 2, a heater 6 that heats the transistor chip 2, and a control unit 7 that operates the heater 6 so as to maintain a predetermined temperature on the basis of the temperature detected by the temperature detection element 5.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device including cascode-connected transistors.

The smaller the capacitance component such as the output capacitance Cos in a transistor, the smaller the switching loss of the transistor. Therefore, conventionally, the capacitance component has been reduced by improving the element structure (see, for example, Patent Document 1).

In Patent Document 1, in order to reduce the output capacitance Cass of the GaN transistor, the GaN transistor includes at least one buffer layer and one or more separation regions formed at a part of the interface between the barrier layers. It is described to remove 2DEG.

Special Table 2016-529709

In a conventional transistor made of a Si (silicon) -based material, the capacitance components such as the input capacitance Ciss, the output capacitance Coss, and the feedback capacitance Crss do not depend on the temperature. Therefore, the switching loss does not change even if the temperature is changed.

In recent years, the inventor has confirmed that the capacitance component of a transistor made of a GaN (gallium nitride) -based material, which has been put into practical use, decreases at high temperatures. The result is shown in FIG. The transistor used in the experiment shown in FIG. 1 is a GaN FET (gallium nitride field effect transistor), and two FETs are cascode-connected. In FIG. 1, the vertical axis represents the capacitance (C) and the horizontal axis represents the voltage (Vds) between the drain and the source. The solid line a is the output capacity Coss when the junction temperature is normal temperature (25 ° C.), and the broken line b is the output capacity Coss when the junction temperature is high temperature (175 ° C.). The solid line c is the feedback capacitance Crss when the junction temperature is normal temperature (25 ° C.), and the broken line d is the feedback capacitance Crss when the junction temperature is high temperature (175 ° C.). The alternate long and short dash line e is the input capacitance Ciss at a junction temperature of room temperature (25 ° C.), and the alternate long and short dash line f is an input capacitance Ciss at a high junction temperature (175 ° C.).

From the results shown in FIG. 1, it was clarified that the output capacitance Coss and the feedback capacitance Crss decreased as the junction temperature increased. It is considered that this is due to the temperature characteristics of the cascode connection in the GaN transistor capable of high temperature operation.

As described above, the output capacitance Coss and the feedback capacitance Crss of the cascode-connected transistor decrease at high temperatures. However, these capacities increase relatively at low temperatures, resulting in a large switching loss at low temperatures.

Therefore, in view of the above problems, it is an object of the present invention to provide a semiconductor device capable of reducing switching loss.

The invention made to solve the above problems is that the temperature is based on a cascode-connected transistor, a temperature detection unit that detects the operating temperature of the transistor, and the temperature detected by the temperature detection unit. It is a semiconductor device including a temperature control unit that controls so as to maintain a predetermined temperature higher than room temperature.

As described above, according to the present invention, the temperature control unit maintains a predetermined temperature higher than room temperature based on the temperature detected by the temperature detection unit, so that the output capacity Coss and the feedback capacity Crss decrease. Can be maintained. Therefore, the switching loss can be reduced.

It is a graph which showed the change of the parasitic capacitance of a GaN transistor at normal temperature and high temperature. It is a schematic block diagram of the semiconductor device which concerns on 1st Embodiment of this invention. It is a flowchart of the operation of the control part shown in FIG. It is a schematic block diagram of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a flowchart of the operation of the control part shown in FIG.

(First Embodiment)
Hereinafter, the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a schematic configuration diagram of a semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 2, the semiconductor device 1 includes a transistor chip 2, a substrate 3, a cooling unit 4, a temperature detection element 5, a heater 6, and a control unit 7.

The transistor chip 2 is a semiconductor substrate in which a GaN buffer layer, a GaN electron traveling layer, and an AlGaN electron supply layer are sequentially formed on a substrate made of Si, SiC, or sapphire, and a gate electrode formed on the upper surface of the semiconductor substrate. , A well-known semiconductor device including a source electrode and a drain electrode. That is, the transistor chip 2 is a semiconductor element made of a gallium nitride based material. Further, in the transistor chip 2 shown in the present embodiment, two FETs (one FET may be a MOS FET) are cascode-connected.

With cascode connection, even a transistor such as GaN HEMT (High Electron Mobility Transistor), which has a normally-on switch characteristic by itself, can be used as a normally-off in the circuit.

The substrate 3 is a circuit board on which the transistor chip 2 is mounted. A heater 6 is mounted on the substrate 3 in addition to the transistor chip 2, and a control unit 7 may be mounted on the substrate 3.

The cooling unit 4 is a component for cooling a component such as a transistor chip 2 mounted on the substrate 3. The cooling unit 4 is provided on the surface of the substrate 3 opposite to the mounting surface on which the transistor chip 2 is mounted, and mainly cools the die bond portion that fixes the transistor chip 2 to the substrate 3. The cooling unit 4 may be composed of, for example, a heat sink.

The temperature detecting element 5 detects the operating temperature of the transistor chip 2. This temperature indicates the junction temperature (Tj) of the transistor. That is, the temperature detecting element 5 detects the surface temperature of the transistor chip 2. As the temperature detecting element 5, for example, a well-known temperature sensor such as a thermistor or a thermoelectric pair can be used. Alternatively, it may be estimated based on the ambient temperature, or it may be detected in a non-contact manner using infrared rays or the like.

The heater 6 is arranged at a position on the substrate 3 in contact with the transistor chip 2 or in the vicinity of the transistor chip 2 to heat the transistor chip 2. It is preferable that the heater 6 is arranged so as to raise the junction temperature of the transistor chip 2 and not raise the temperature of the die bond portion.

The control unit 7 controls the operation of the heater 6 based on the temperature detected by the temperature detection element 5. Specifically, the heater 6 is operated so that the temperature detected by the temperature detecting element 5 maintains a predetermined temperature (for example, 175 ° C.). The control unit 7 is composed of a microcomputer provided with a CPU (Central Processing Unit) and the like, and the control is realized by software running on the CPU. Alternatively, the control unit 7 may configure the above operation with hardware such as an FPGA (Field Programmable Gate Array).

Next, the operation of the control unit 7 in the semiconductor device 1 having the above-described configuration will be described with reference to the flowchart of FIG. First, the control unit 7 acquires the temperature detected by the temperature detecting element 5 (step S11). Next, the control unit 7 determines whether or not the acquired temperature is less than the preset lower limit temperature (step S12). This lower limit temperature is a temperature at which the junction temperature of the transistor chip 2 is equal to or lower than a predetermined temperature at which the output capacitance Coss and the feedback capacitance Crss can be maintained at a reduced state such as 175 ° C. shown in FIG.

If it is determined in step S12 that the temperature is equal to or higher than the lower limit temperature (step S12: N), the control unit 7 returns to step S11 without operating the heater 6. On the other hand, when it is determined in step S12 that the temperature is lower than the lower limit temperature (step S12: Y), the control unit 7 operates (ON) the heater 6 to heat the transistor chip 2 (step S13). That is, heating is performed so as to maintain a predetermined temperature at which the output capacitance Coss, the feedback capacitance Crss, and the like as shown in FIG. 1 decrease and the switching loss can be reduced.

Next, the control unit 7 acquires the temperature detected by the temperature detecting element 5 (step S14). Next, the control unit 7 determines whether or not the acquired temperature is equal to or higher than the preset upper limit temperature (step S15). This upper limit temperature is a temperature higher than a predetermined temperature at which the junction temperature of the transistor chip 2 can maintain a state in which the output capacitance Coss and the feedback capacitance Crss, such as 175 ° C. shown in FIG. 1, are lowered.

If it is determined in step S15 that the temperature is lower than the upper limit temperature (step S15: N), the control unit 7 returns to step S14 without stopping the heater 6. On the other hand, if it is determined in step S15 that the temperature is equal to or higher than the upper limit temperature (step S15: Y), the control unit 7 stops (OFF) the heater 6 (step S16).

Here, if the predetermined temperature (the temperature at which the output capacity Coss and the feedback capacity Crss can be maintained in a lowered state, for example, 175 ° C.) is included in a temperature higher than room temperature, above the lower limit temperature, and below the upper limit temperature. Good. Further, it is preferable that both the lower limit temperature and the upper limit temperature are higher than room temperature and the temperature at which the output capacity Coss and the feedback capacity Crss are lowered can be maintained. Further, since the purpose is to maintain the junction temperature at a predetermined temperature, it is preferable to set the temperature difference between the lower limit temperature and the upper limit temperature so as not to be too large, for example, about 10 ° C.

According to the present embodiment, the semiconductor device 1 includes a transistor chip 2 connected by cascode, a temperature detection element 5 for detecting the operating temperature of the transistor chip 2, a heater 6 for heating the transistor chip 2, and temperature detection. A control unit 7 for operating the heater 6 so as to maintain a predetermined temperature based on the temperature detected by the element 5 is provided.

When the semiconductor device 1 is configured as described above, the control unit 7 maintains a predetermined temperature higher than room temperature based on the temperature detected by the temperature detection element 5, so that the output capacity Coss and the feedback capacity Crss Can be maintained in a reduced state. Therefore, the switching loss can be reduced.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. The same parts as those in the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 1, the semiconductor device 1A according to the present embodiment includes a transistor chip 2, a substrate 3, a cooling unit 4, a temperature detecting element 5, a cooling device 8, and a control unit 7A. ing.

The transistor chip 2, the substrate 3, the cooling unit 4, and the temperature detecting element 5 are the same as those in the first embodiment. The cooling device 8 is arranged at a position on the substrate 3 in contact with the transistor chip 2 or in the vicinity of the transistor chip 2 to cool the transistor chip 2. The cooling device 8 can be composed of, for example, a cooling fan, a Peltier element, or the like.

The control unit 7A controls the operation of the cooling device 8 based on the temperature detected by the temperature detecting element 5. Specifically, the cooling device 8 is operated so that the temperature detected by the temperature detecting element 5 maintains a predetermined temperature (for example, 175 ° C.).

Next, the operation of the control unit 7A in the semiconductor device 1A having the above-described configuration will be described with reference to the flowchart of FIG. First, the control unit 7A acquires the temperature detected by the temperature detecting element 5 (step S21). Next, the control unit 7 determines whether or not the acquired temperature is equal to or higher than the preset upper limit temperature (step S12). The upper limit temperature is a temperature equal to or higher than a predetermined temperature at which the junction temperature of the transistor chip 2 can maintain a state in which the output capacitance Coss and the feedback capacitance Crss are lowered, for example, 175 ° C. shown in FIG.

If it is determined in step S22 that the temperature is lower than the upper limit temperature (step S22: N), the control unit 7 returns to step S21 without operating the cooling device 8. On the other hand, when it is determined in step S22 that the temperature is equal to or higher than the upper limit temperature (step S22: Y), the control unit 7 operates (ON) the cooling device 8 to cool the transistor chip 2 (step S23). That is, cooling is performed so as to maintain a temperature at which the output capacitance Coss, the feedback capacitance Crss, and the like as shown in FIG. 1 decrease and the switching loss can be reduced.

Next, the control unit 7 acquires the temperature detected by the temperature detecting element 5 (step S24). Next, the control unit 7 determines whether or not the acquired temperature is less than the preset lower limit temperature (step S25). This lower limit temperature is a temperature lower than a predetermined temperature at which the junction temperature of the transistor chip 2 can maintain a state in which the output capacitance Coss and the feedback capacitance Crss are lowered, for example, 175 ° C. shown in FIG.

If it is determined in step S25 that the temperature is below the lower limit temperature (step S25: N), the control unit 7 returns to step S24 without stopping the cooling device 8. On the other hand, if it is determined in step S25 that the temperature is equal to or higher than the lower limit temperature (step S25: Y), the control unit 7 stops (OFF) the cooling device 8 (step S26).

According to the present embodiment, the semiconductor device 1A includes a transistor chip 2 connected by a cascode, a temperature detecting element 5 for detecting the operating temperature of the transistor chip 2, a cooling device 8 for cooling the transistor chip 2, and a temperature. It includes a control unit 7A that operates the cooling device 8 so as to maintain a predetermined temperature based on the temperature detected by the detection element 5.

When the semiconductor device 1A is configured as described above, the control unit 7A maintains a predetermined temperature higher than room temperature based on the temperature detected by the temperature detecting element 5, so that the output capacitance Coss and the feedback capacitance Crss Can be maintained in a reduced state. Therefore, the switching loss can be reduced. Further, since the cooling device 8 cools the temperature, it is possible to suppress the influence of the temperature rising too much on other than the transistor chip 2 such as the die bond portion.

In the above-described embodiment, the upper limit temperature and the lower limit temperature are set, but the heater 6 and the cooling device 8 may be operated by determining whether or not the temperature is a predetermined temperature.

Further, in the above-described embodiment, the transistor chip 2 which is a GaN transistor is described as the transistor connected by the cascode, but if the transistor is formed by the HEMT structure, it may be a transistor formed of another material. Good. Further, the present invention is not limited to a single transistor component, and may be an integrated circuit composed of a plurality of transistors or the like.

Further, the present invention is not limited to the above embodiment. That is, those skilled in the art can carry out various modifications according to conventionally known knowledge within a range that does not deviate from the gist of the present invention. As long as the semiconductor device of the present invention is still provided by such deformation, it is, of course, included in the category of the present invention.

1 Semiconductor device 2 Transistor chip (transistor)
5 Temperature detection element (temperature detection unit)
6 Heater (temperature control unit, heating unit)
7,7A control unit (temperature control unit)
8 Cooling device (temperature control unit, cooling unit)

Claims (3)

Cascoded transistors and
A temperature detection unit that detects the operating temperature of the transistor, and
A temperature control unit that controls so that the temperature is maintained at a predetermined temperature higher than room temperature based on the temperature detected by the temperature detection unit.
A semiconductor device characterized by comprising. The temperature control unit includes a heating unit that heats the transistor, and operates the heating unit so as to maintain the predetermined temperature based on the temperature detected by the temperature detection unit.
The semiconductor device according to claim 1. The temperature control unit includes a cooling unit that cools the transistor, and operates the cooling unit so as to maintain the predetermined temperature based on the temperature detected by the temperature detection unit.
The semiconductor device according to claim 1.

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