JP2021043315A - Exposure apparatus - Google Patents

Abstract

To provide an exposure apparatus that can perform exposure without a photomask.SOLUTION: An exposure apparatus comprises: a light source panel LP that has a substrate SUB, and a plurality of pixels PX arranged two-dimensionally above the substrate and each including a light emitting device; a driving unit that individually drives the plurality of light emitting devices; a polarizer PO that is opposite to the plurality of light emitting devices; and a fixing member that fixes the relative positions of the polarizer and the light source panel. Each of the light emitting devices emits ultraviolet light and has a length of the longest one side of 500 μm or less in plan view.SELECTED DRAWING: Figure 8

Description

Embodiments of the present invention relate to an exposure apparatus.

A liquid crystal display panel has been developed as a display panel. Generally, a liquid crystal display panel is composed of an array substrate, a facing substrate arranged to face each other with a predetermined gap, a sealing material obtained by joining the array substrate and the facing substrate, and an array substrate, a facing substrate, and a sealing material. It has a liquid crystal layer formed in an enclosed area. The array substrate and the facing substrate each have an alignment film in contact with the liquid crystal layer. The alignment film may be subjected to an alignment treatment.

As an orientation treatment method, a photo-alignment treatment method is known as a rubbingless orientation method. The photo-alignment treatment method can be performed by irradiating the alignment film with linearly polarized light using an exposure apparatus. Thereby, the alignment film subjected to the photo-alignment treatment can control the initial orientation of the liquid crystal molecules.
An exposure device is also used to cure the sealing material. In that case, it can be performed by irradiating the sealing material with light using an exposure device.
As described above, the exposure apparatus is used in various situations such as a manufacturing process of a liquid crystal display panel.

Japanese Unexamined Patent Publication No. 2007-219191 Japanese Unexamined Patent Publication No. 2015-148748

The present embodiment provides an exposure apparatus capable of exposing without a photomask.

The exposure apparatus according to one embodiment is
A light source panel having a substrate, a plurality of pixels two-dimensionally arranged above the substrate and each including a light emitting element, a drive unit for independently driving the plurality of light emitting elements, and the plurality of light emitting elements. Each of the light emitting elements emits ultraviolet light and is the longest in a plan view. The length of the side is configured to be 500 μm or less.

Further, the exposure apparatus according to the embodiment is
Each includes a light source panel having a substrate, a plurality of pixels two-dimensionally arranged above the substrate and each including a light emitting element, and a drive unit for independently driving the plurality of light emitting elements. The light emitting element emits ultraviolet light and has the longest side length of 500 μm or less in a plan view.

FIG. 1 is a perspective view showing a part of a liquid crystal display panel formed by using the first exposure apparatus and the second exposure apparatus according to the first embodiment. FIG. 2 is a cross-sectional view showing a part of the liquid crystal display panel. FIG. 3 is a plan view showing the liquid crystal display panel. FIG. 4 is a plan view showing a part of the array substrate shown in FIGS. 1 to 3. FIG. 5 is an enlarged plan view showing a part of the array substrate, and is a diagram showing a wiring structure of the array substrate. FIG. 6 is an enlarged cross-sectional view showing a part of the liquid crystal display panel, and is a diagram showing the structure of the liquid crystal display panel. FIG. 7 is an enlarged cross-sectional view showing a peripheral edge of the liquid crystal display panel along the line VII-VII of FIG. FIG. 8 is a plan view showing the first exposure apparatus. FIG. 9 is a cross-sectional view showing the first exposure apparatus. FIG. 10 is a perspective view showing a light source panel, a first circuit board, a second circuit board, and a panel driver of the first exposure apparatus. FIG. 11 is a plan view showing the light source panel and the panel driver, and is a diagram showing a circuit configuration of the light source panel. FIG. 12 is a circuit diagram showing an example of the pixels of the light source panel. FIG. 13 is a cross-sectional view showing an example of the structure of the light source panel. FIG. 14 is a plan view showing the second exposure apparatus. FIG. 15 is a diagram illustrating a manufacturing process of a liquid crystal display panel using the first exposure apparatus and the second exposure apparatus, and is a plan view showing a state in which an array pattern is formed on the mother glass. FIG. 16 is a diagram showing a state in which the alignment film on the mother glass is subjected to photoalignment treatment in the manufacturing process of the liquid crystal display panel following FIG. FIG. 17 is a cross-sectional view showing a substrate to be processed including the mother glass, the array pattern, and the alignment film shown in FIG. 16, a stage, and the first exposure apparatus. FIG. 18 is a plan view showing a state in which a facing pattern is formed on the mother glass in the manufacturing process of the liquid crystal display panel. FIG. 19 shows that in the manufacturing process of the liquid crystal display panel following FIGS. 16 and 18, the mother glass on which the six array substrates are formed and the mother glass on which the six opposing substrates are formed are interposed via a sealant. It is a top view which shows the state which is pasted together. FIG. 20 is a diagram showing a state in which the sealant is irradiated with ultraviolet light in the manufacturing process of the liquid crystal display panel following FIG. FIG. 21 is a cross-sectional view showing the stage shown in FIG. 20, the second exposure apparatus, and the substrate to be processed. FIG. 22 is a diagram showing the relationship between the on / off of the plurality of light emitting elements of the first exposure apparatus according to the first embodiment and the irradiation range of light. FIG. 23 is a diagram showing the relationship between the on / off of the plurality of light emitting elements of the first exposure apparatus according to Comparative Example 1 and the irradiation range of light. FIG. 24 is a plan view showing the first exposure apparatus according to the second embodiment. FIG. 25 is a plan view showing the first exposure apparatus according to the third embodiment. FIG. 26 is a plan view showing the first exposure apparatus according to Comparative Example 2. FIG. 27 is a plan view showing the first exposure apparatus according to Comparative Example 3. FIG. 28 is a plan view showing the first exposure apparatus according to Comparative Example 4. FIG. 29 is a diagram showing the relationship between the on / off of a plurality of light emitting elements of the first exposure apparatus and the irradiation range of light when the example of FIG. 26 is used.

Hereinafter, an embodiment, a modification, and a comparative example of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(First Embodiment)
The first embodiment will be described. First, the configuration of the liquid crystal display panel formed by using the exposure apparatus will be described. FIG. 1 is a perspective view showing a part of the liquid crystal display panel DP according to the present embodiment.
As shown in FIG. 1, the liquid crystal display panel DP includes an array substrate 1, an opposed substrate 2 arranged to face the array substrate with a predetermined gap, and a sealing material 51. In the figure, the sealing material 51 is shaded. The liquid crystal display panel DP has a display area DA in which the array substrate 1 and the facing substrate 2 overlap, and a non-display area NDA outside the display area DA. The sealing material 51 is located in the non-display area NDA.

FIG. 2 is a cross-sectional view showing a part of the liquid crystal display panel DP. As shown in FIG. 2, a backlight unit (not shown) is arranged on the outer surface side of the array substrate 1. The liquid crystal display device is formed of a liquid crystal display panel, the backlight unit, and the like.

The array substrate 1 has a glass substrate 11 as a transparent insulating substrate, an array pattern 1p, and an alignment film 28. The array pattern 1p is formed on the glass substrate 11. The alignment film 28 is formed in an array pattern 1p shape. The array pattern 1p and the alignment film 28 are formed not only in the display region DA but also in the non-display region NDA.

The facing substrate 2 includes a glass substrate 41 as a transparent insulating substrate, a facing pattern 2p, a plurality of columnar spacers 8, and an alignment film 43. The facing pattern 2p is formed on the glass substrate 41. The plurality of columnar spacers 8 and the alignment film 43 as the plurality of spacers are formed on the facing pattern 2p. The facing pattern 2p, the plurality of columnar spacers 8, and the alignment film 43 are formed not only in the display region DA but also in the non-display region NDA.

The alignment film 43 faces the alignment film 28. The alignment film 28 and the alignment film 43 are formed by using a photodegradable alignment film material. The alignment film 28 and the alignment film 43 are formed of, for example, a photodegradable polyimide resin. The alignment film 28 and the alignment film 43 are subjected to a photo-alignment treatment.

The columnar spacer 8 holds a gap between the array substrate 1 and the opposing substrate 2. The liquid crystal layer 3 is located between the array substrate 1 and the opposing substrate 2, and is formed in a space surrounded by the array substrate 1, the opposing substrate 2, and the sealing material 51. Optical members including a polarizing plate are arranged on the outer surfaces of the array substrate 1 and the facing substrate 2, respectively.

FIG. 3 is a plan view showing the liquid crystal display panel DP. As shown in FIG. 3, the display area DA has a rectangular shape. The non-display area NDA has a rectangular frame shape. The sealing material 51 is located in the non-display region NDA, is provided between the array substrate 1 (alignment film 28) and the facing substrate 2 (alignment film 43), and is continuously formed in a rectangular frame shape. The sealing material 51 can be formed by using a photocurable resin such as acrylic or epoxy. The liquid crystal display panel DP includes a driver 9. The driver 9 is provided in a region of the array substrate 1 that does not face the opposite substrate 2.

FIG. 4 is a plan view showing a part of the array substrate 1. As shown in FIG. 4, in the display area DA, a plurality of scanning lines 15, a plurality of signal lines 21, and a plurality of auxiliary capacitance lines 17 are arranged on the glass substrate 11. The plurality of scanning lines 15 extend in the first direction d1 and are arranged at intervals in the second direction d2 orthogonal to the first direction d1. The plurality of signal lines 21 intersect with the plurality of scanning lines 15, extend in the second direction d2, and are arranged at intervals in the first direction d1. The plurality of auxiliary capacitance lines 17 intersect with the plurality of signal lines 21, extend in the first direction d1, and are arranged at intervals in the second direction d2.

Here, the array substrate 1 and the opposing substrate 2 have a plurality of pixels 20 arranged in a matrix in the display area DA. Each pixel 20 is provided in an area surrounded by two adjacent signal lines 21 and two adjacent auxiliary capacitance lines 17.

FIG. 5 is an enlarged plan view showing a part of the array substrate 1, and is a diagram showing a wiring structure of the array substrate 1. As shown in FIG. 5, each pixel 20 includes a TFT (thin film transistor) 19, a pixel electrode 26, an auxiliary capacitance electrode 13, and the like as switching elements.
The TFT 19 is provided near the intersection of the scanning line 15 and the signal line 21. The TFT 19 has a semiconductor layer 12 and a gate electrode 16 formed by extending a part of scanning lines 15. The semiconductor layer 12 is formed of a semiconductor such as amorphous silicon or polycrystalline silicon. The gate electrode 16 intersects the semiconductor layer 12.

The signal line 21 is connected to the source region of the semiconductor layer 12. The contact electrode 22 is connected to the drain region of the semiconductor layer 12 and the pixel electrode 26, respectively. The peripheral edge of each pixel electrode 26 overlaps the auxiliary capacitance line 17 and the signal line 21. The auxiliary capacitance electrode 13 overlaps with the auxiliary capacitance line 17, and constitutes the auxiliary capacitance element 24 together with the auxiliary capacitance line 17.

FIG. 6 is an enlarged cross-sectional view showing a part of the liquid crystal display panel DP, and is a diagram showing the structure of the liquid crystal display panel DP. As shown in FIG. 6, in the display region DA, the auxiliary capacitance electrode 13 is formed on the glass substrate 11. The semiconductor layer 12 is also formed on the glass substrate 11.

A gate insulating film 14 is provided on the glass substrate 11 on which the auxiliary capacitance electrode 13 is formed. An auxiliary capacitance line 17 is formed on the gate insulating film 14. A scanning line 15 and a gate electrode 16 are also formed on the gate insulating film 14. The auxiliary capacitance wire 17 and the auxiliary capacitance electrode 13 are arranged so as to face each other with the gate insulating film 14 interposed therebetween. An interlayer insulating film 18 is formed on the gate insulating film 14, the auxiliary capacitance line 17, and the like.
The contact electrode 22 is connected to the auxiliary capacitance electrode 13 through a contact hole formed in the gate insulating film 14 and the interlayer insulating film 18. Here, the auxiliary capacitance line 17 is formed except for the connection portion between the auxiliary capacitance electrode 13 and the contact electrode 22.

A protective insulating film 23 is formed on the interlayer insulating film 18, the signal line 21, and the contact electrode 22. The protective insulating film 23 also serves as a flattening film for flattening irregularities generated by wiring or the like on the substrate. The protective insulating film 23 covers not only the display area DA but also the non-display area NDA.

Pixel electrodes 26 are formed on the protective insulating film 23 with a transparent conductive material such as ITO (indium tin oxide). A contact hole 25 is formed in the protective insulating film 23 that overlaps the contact electrode 22. Each pixel electrode 26 is connected to the contact electrode 22 through the contact hole 25.

In the display region DA, the array pattern 1p is laminated between the glass substrate 11 and the pixel electrode 26. The alignment film 28 covers the protective insulating film 23 and the pixel electrode 26.

On the other hand, in the facing substrate 2, the color filter 4 is provided on the glass substrate 41. The color filter 4 has a light-shielding portion 31, a peripheral light-shielding portion, and a plurality of colored layers. The plurality of colored layers include, for example, a red colored layer 30R, a green colored layer 30G, and a blue colored layer 30B.

The light-shielding portions 31 are formed in a grid pattern. The light-shielding portion 31 is formed so as to face the auxiliary capacitance line 17 and the signal line 21. The peripheral light-shielding portion 32 is formed in a rectangular frame shape, and is formed in the entire non-display region NDA.

The colored layers 30R, 30G, and 30B are formed on the glass substrate 41 and the light-shielding portion 31. The colored layers 30R, 30G, and 30B extend in a band shape along the second direction d2. The colored layers 30R, 30G, and 30B are adjacent to each other in the first direction d1 and are arranged alternately. The peripheral edges of the colored layers 30R, 30G, and 30B overlap the light-shielding portion 31.
An overcoat layer (not shown) may be arranged on the color filter 4. Thereby, the influence of the unevenness on the surface of the light-shielding portion 31 and the color filter 4 can be alleviated. A counter electrode 42 is formed on the color filter 4 (overcoat layer) by a transparent conductive film such as ITO. In the display region DA, the facing pattern 2p is laminated between the glass substrate 41 and the facing electrode 42. The alignment film 43 covers the counter electrode 42.

FIG. 7 is an enlarged cross-sectional view showing a peripheral portion of the liquid crystal display panel DP along the line VII-VII of FIG. As shown in FIG. 7, the sealing material 51 is adhered to the alignment film 28 and the alignment film 43.
The liquid crystal display panel DP is formed as described above.

Next, the first exposure device EX1 and the second exposure device EX2 will be described as exposure devices used when manufacturing the liquid crystal display panel DP.
First, the first exposure apparatus EX1 will be described. FIG. 8 is a plan view showing the first exposure apparatus EX1. The first exposure device EX1 is a polarized light exposure device that emits linearly polarized light.

As shown in FIG. 8, the first exposure apparatus EX1 includes a light source panel LP and a polarizer PO. The light source panel LP has a substrate SUB and a plurality of pixels PX. The plurality of pixels PX are two-dimensionally arranged above the substrate SUB. Each pixel PX includes a light emitting element described later. The polarizer PO faces a plurality of light emitting elements (a plurality of pixels PX).

The light source panel LP includes a plurality of pixel groups PXG. The plurality of pixel groups PXG extend in the row direction X and are arranged in the column direction Y orthogonal to the row direction. Each pixel group PXG is composed of a plurality of pixel PXs arranged in the row direction X among the plurality of pixel PXs. In each pixel group PXG, the plurality of pixel PXs are arranged with a gap g1 in the row direction X. In the present embodiment, the light source panel LP includes four pixel groups PXG, but may include two, three, or five or more pixel groups PXG.

When paying attention to a pair of pixel groups PXG adjacent to each other in the column direction Y, each gap g1 of one pixel group PXG faces the pixel PX of the other pixel group PXG in the column direction Y, and the other pixel group PXG has a gap g1. Each gap g1 faces the pixel PX of one pixel group PXG in the column direction Y. For example, when paying attention to the pixel group PXG1 in the first row and the pixel group PXG2 in the second row, the gap g1 of the pixel group PXG1 faces the pixel PX of the pixel group PXG2 in the column direction Y, and the pixel group PXG2 The gap g1 faces the pixel PX of the pixel group PXG1 in the column direction Y.

In the present embodiment, the pixel PX of the other pixel group PXG is not only the gap g1 of the one pixel group PXG, but also a pair of pixels on both sides of the gap g1 among the plurality of pixel PXs of the one pixel group PXG. Both PX and PX face each other in the row direction Y. Then, the pixel PX of one pixel group PXG is aligned not only with the gap g1 of the other pixel group PXG but also with the pair of pixels PX on both sides of the gap g1 among the plurality of pixel PXs of the other pixel group PXG. It faces the direction Y.
For example, when paying attention to the pixel group PXG1 in the first row and the pixel group PXG2 in the second row, the pixel PX of the pixel group PXG2 is the gap g1 of the pixel group PXG1 and a pair of pixels on both sides of the gap g1. It faces the PX in the row direction Y. The pixel PX of the pixel group PXG1 faces the gap g1 of the pixel group PXG2 and the pair of pixels PX on both sides of the gap g1 in the column direction Y.
As described above, the plurality of pixels PX are aligned in the row direction X, but are not aligned in the column direction Y. The plurality of pixels PX are arranged in a staggered pattern with respect to the column direction Y.

The plurality of pixel PXs of one pixel group PXG and the plurality of pixel PXs of the other pixel group PXG are located with a gap g2 in the column direction Y. For example, when paying attention to the pixel group PXG1 and the pixel group PXG2 adjacent to each other in the column direction Y, the plurality of pixel PXs of the pixel group PXG1 and the plurality of pixel PXs of the pixel group PXG2 have a gap g2 in the column direction Y. It is located.

FIG. 9 is a cross-sectional view showing the first exposure apparatus EX1. As shown in FIG. 9, the first exposure apparatus EX1 further includes a fixing member AL. The fixing member AL is configured to fix the relative positions of the polarizer PO and the light source panel LP. In the present embodiment, the fixing member AL is composed of an adhesive layer, is located between the polarizer PO and the light source panel LP, and adheres the polarizer PO to the light source panel LP.

The polarizer PO faces the light emitting surface of the light emitting element. The polarizer PO is configured to linearly polarize the light emitted from the light source panel LP (light emitting element). The polarizer PO has an absorption axis parallel to the row direction X and an easy transmission axis parallel to the column direction Y. The plane of polarization of linearly polarized light transmitted through the polarizer PO is parallel to the YY plane. Here, the direction Z is orthogonal to each of the row direction X and the column direction Y.

FIG. 10 is a perspective view showing a light source panel LP, a first circuit board 6, a second circuit board 7, and a panel driver 5 of the first exposure apparatus EX1. In addition, in FIG. 10, the illustration of the polarizer PO and the fixing member AL is omitted.
As shown in FIG. 10, the first exposure apparatus EX1 further includes a first circuit board 6, a second circuit board 7, and a panel driver 5 in addition to the light source panel LP. The light source panel LP has a rectangular shape in one example. In the illustrated example, the first side SX of the light source panel LP is parallel to the row direction X, and the second side SY of the light source panel LP is parallel to the column direction Y. The direction Z corresponds to the thickness direction of the light source panel LP. The main surface of the light source panel LP is parallel to the XY plane defined by the row direction X and the column direction Y.

The light source panel LP has a light emitting region LA and a non-light emitting region NLA outside the light emitting region LA. The non-light emitting region NLA has a terminal region MT. In the illustrated example, the non-light emitting region NLA surrounds the light emitting region LA. The light emitting region LA is a region that selectively emits light, and is a region in which a plurality of pixels PX are arranged. The terminal area MT is provided along the first side SX of the light source panel LP, and includes a terminal for electrically connecting the light source panel LP to an external device or the like.

The first circuit board 6 is mounted on the terminal region MT and is connected to the light source panel LP. The first circuit board 6 is, for example, a flexible printed circuit board. The first circuit board 6 includes a panel driver 5 (drive IC chip) for driving the light source panel LP and the like. The second circuit board 7 is, for example, a flexible printed circuit board. The second circuit board 7 is connected to the first circuit board 6 at, for example, below the first circuit board 6. In the illustrated example, the panel driver 5 is arranged on the first circuit board 6, but may be arranged below the first circuit board 6. Further, the panel driver 5 may be mounted on a circuit board other than the first circuit board 6, for example, the panel driver 5 may be mounted on the second circuit board 7.

The panel driver 5 described above is connected to a control board (not shown) via, for example, a second circuit board 7. The panel driver 5 executes control for selectively emitting light to the light source panel LP by driving a plurality of pixels PX based on, for example, a drive signal output from the control board.

FIG. 11 is a plan view showing the light source panel LP and the panel driver 5, and is a diagram showing a circuit configuration of the light source panel LP. As shown in FIG. 11, the light source panel LP has an electrically insulating substrate SUB. A plurality of pixels PX, various wirings, gate drivers GD1 and GD2, and a selection circuit SD are arranged on the substrate SUB.

The various wirings described above extend in the light emitting region LA and are drawn out to the non-light emitting region NLA. In FIG. 11, a plurality of control wiring SSGs and a plurality of signal lines VL are exemplified as a part of various wirings. In the light emitting region LA, the control wiring SSG and the signal line VL are connected to the pixel PX. The control wiring SSG is connected to the gate drivers GD1 and GD2 in the non-emission region NLA. The signal line VL is connected to the selection circuit SD in the non-emission region NLA.

The gate drivers GD1 and GD2 and the selection circuit SD are located in the non-emission region NLA. Various signals and voltages are given to the gate drivers GD1 and GD2 and the selection circuit SD from the panel driver 5. The panel driver 5 constitutes a drive unit DR together with the gate drivers GD1 and GD2 and the selection circuit SD. The drive unit DR is configured to independently drive a plurality of light emitting elements of a plurality of pixels PX.

Next, an example of the circuit configuration (pixel circuit) of the pixel PX in the light source panel LP will be described with reference to FIG. FIG. 12 is a circuit diagram showing an example of the pixel PX of the light source panel LP. In this embodiment, the plurality of pixels PX are similarly configured. Therefore, for the sake of convenience, one pixel PX will be described as a representative of the plurality of pixel PXs.

As shown in FIG. 12, the pixel PX includes a light emitting element LED and a pixel circuit for supplying a driving current to the light emitting element LED to drive the light emitting element. The pixel circuit has a drive transistor DRT, an output transistor BCT, a pixel transistor SST, an initialization transistor IST, a reset transistor RST, a holding capacitance Cs, and an auxiliary capacitance Cad. In the present embodiment, the light emitting element LED and the pixel circuit are arranged for each pixel PX.

Each transistor shown in FIG. 12 is an n-channel transistor. The output transistor BCT, the pixel transistor SST, the initialization transistor IST, and the reset transistor RST do not have to be composed of transistors. The output transistor BCT, the pixel transistor SST, the initialization transistor IST, and the reset transistor RST may function as an output switch, a pixel switch, an initialization switch, and a reset switch, respectively.

In the following description, one of the source electrode and the drain electrode of the transistor is referred to as a first electrode, and the other is referred to as a second electrode. Further, one electrode of the capacitive element is used as a first electrode, and the other electrode is used as a second electrode.

The drive transistor DRT, the pixel electrode described later, and the light emitting element LED are connected in series between the first power supply line PVH and the second power supply line PVL. The first power supply line PVH is held at a constant potential, and the second power supply line PVL is held at a constant potential different from the potential of the first power supply line PVH. In the present embodiment, the potential PVDD of the first power supply line PVH is higher than the potential PVSS of the second power supply line PVL. Specifically, the potential P VDD of the first power supply line PVH is, for example, 9 V, and the potential PVSS of the second power supply line PVL is, for example, 0 V.

The first electrode of the drive transistor DRT is connected to the first electrode (anode) of the light emitting element LED, the first electrode of the holding capacity Cs, and the first electrode of the auxiliary capacity CAD. The second electrode of the drive transistor DRT is connected to the first electrode of the output transistor BCT. The drive transistor DRT can also control the current (current value) supplied to the light emitting element LED.

The second electrode of the output transistor BCT is connected to the first power supply line PVH. Further, the second electrode (cathode) of the light emitting element LED is connected to the second power supply line PVL.
The first electrode of the pixel transistor SST is connected to the gate electrode of the drive transistor DRT, the first electrode of the initialization transistor IST, and the second electrode of the holding capacity Cs. The second electrode of the pixel transistor SST is connected to the signal line VL. The second electrode of the initialization transistor IST is connected to the initialization power line BL.

The holding capacitance Cs is electrically connected between the gate electrode of the drive transistor DRT and the first electrode (source electrode).
The second electrode of the auxiliary capacitance CAD is held at a constant potential. In the present embodiment, the second electrode of the auxiliary capacitance CAD is connected to, for example, the first power supply line PVH and is held at the same constant potential (P VDD) as the potential of the first power supply line PVH. The second electrode of the auxiliary capacitance Cad may be held at the same constant potential (PVSS) as the potential of the second power supply line PVL, or a power source different from the first power supply line PVH and the second power supply line PVL. It may be held at the same constant potential as the line (third power line). As the third power supply line, as the wiring held at a constant potential, the initialization power supply line BL or the reset power supply line RL can be mentioned.

The first electrode of the reset transistor RST is connected to the first electrode of the drive transistor DRT. The second electrode of the reset transistor RST is connected to the reset power line RL.

A drive signal Vsig is supplied to the signal line VL. The drive signal Vsig is a signal written in the pixel PX, the minimum value of the drive signal Vsig is, for example, 0V, and the maximum value of the drive signal Vsig is, for example, 3V.
The initialization potential Vini is supplied to the initialization power line BL. The initialization potential Vini is, for example, 1.2V.

The reset power line RL is set to the reset power potential Vrst. The reset power supply potential Vrst is given a potential having a potential difference with respect to PVSS so that the light emitting element LED does not emit light, and is, for example, -2V.
The gate electrode of the output transistor BCT is connected to the control wiring SBG. An output control signal BG is supplied to this control wiring SBG.
The gate electrode of the pixel transistor SST is connected to the control wiring SSG. A drive control signal SG is supplied to this control wiring SSG.

The gate electrode of the initialization transistor IST is connected to the control wiring SIG. An initialization control signal IG is supplied to this control wiring SIG.
The gate electrode of the reset transistor RST is connected to the control wiring SRG. A reset control signal RG is supplied to this control wiring SRG.
The element capacitance Cled shown in FIG. 12 is the capacitance between the first electrode (anode) and the second electrode (cathode) of the light emitting element LED.

In FIG. 12, it has been described that all the above transistors are Nch TFTs, but for example, all the transistors other than the drive transistor DRT may be Pch TFTs, or Nch TFTs and Pch TFTs may be mixed.

Further, the drive transistor DRT may be a Pch TFT. In that case, it is sufficient that the light emitting element LED is configured so that a current flows in the opposite direction to the present embodiment. In any case, the auxiliary capacitance CAD may be coupled to the electrode on the drive transistor DRT side of the electrodes of the light emitting element LED.

Further, as described with reference to FIG. 11, since the light source panel LP includes two gate drivers GD1 and GD2, it is possible to supply power to one pixel PX from the gate drivers GD1 and GD2 on both sides. Here, it is assumed that the two-sided power supply method is adopted for the above-mentioned control wiring SSG, and the one-sided power supply method is adopted for the other control wiring. However, the light source panel LP does not have to include two gate drivers GD1 and GD2, and may include at least one gate driver.

The circuit configuration described in FIG. 12 is an example, and the circuit configuration of the light source panel LP may be another configuration as long as it includes the drive transistor DRT, the holding capacitance Cs, and the auxiliary capacitance CAD described above. Absent. For example, a part of the circuit configurations described with reference to FIG. 12 may be omitted, or other configurations may be added.

Next, the cross-sectional structure of the light source panel LP will be described with reference to FIG. FIG. 13 is a cross-sectional view showing an example of the structure of the light source panel LP. In FIG. 13, the cross-sectional structure of the three pixels PX of the light source panel LP and the non-light emitting region NLA will be mainly described.
As shown in FIG. 13, the array substrate AR of the light source panel LP includes a substrate SUB. As the substrate SUB, a glass substrate such as quartz or non-alkali glass, or a resin substrate such as polyimide can be mainly used. The resin substrate is not limited to polyimide, and other resin materials may be used. As a result, the substrate SUB may be referred to as an organic insulating layer, a resin layer, or the like.

An undercoat layer 62 having a three-layer laminated structure is provided on the substrate SUB. The undercoat layer 62 is first formed in silicon oxide second layer 62b is formed in the first layer 62a formed of (SiO _2), silicon nitride (SiN), and silicon oxide (SiO ₂₎ It has three layers 62c. The first layer 62a of the lowermost layer is provided as a blocking film of moisture and impurities from the outside in order to improve the adhesion to the substrate SUB which is the base material. Further, the third layer 62c of the uppermost layer is provided as a block film for preventing hydrogen atoms contained in the second layer 62b from diffusing toward the semiconductor layer SC side described later.

The undercoat layer 62 is not limited to this structure. The undercoat layer 62 may be further laminated, or may have a single-layer structure or a two-layer structure. For example, when the substrate SUB is glass, the silicon nitride film has relatively good adhesion, so that the silicon nitride film may be formed directly on the substrate SUB.

The light-shielding layer 63 is arranged on the substrate SUB. The position of the light-shielding layer 63 is adjusted to the position where the TFT is formed later. In the present embodiment, the light-shielding layer 63 is made of, for example, metal, but may be made of a material having a light-shielding property such as a black layer.
Further, in the present embodiment, the light-shielding layer 63 is provided on the first layer 62a and is covered with the second layer 62b. The light-shielding layer 63 may be provided on the substrate SUB and covered with the first layer 62a.

According to such a light-shielding layer 63, it is possible to suppress the intrusion of light into the back surface of the TFT channel, so that it is possible to suppress the change in TFT characteristics due to the light that can be incident from the substrate SUB side. Further, when the light-shielding layer 63 is formed of a conductive layer, it is possible to impart a back gate effect to the TFT by applying a predetermined potential to the light-shielding layer 63.

A TFT such as a drive transistor DRT is formed on the undercoat layer 62 described above. As an example of the TFT, a polysilicon TFT that uses polysilicon for the semiconductor layer SC is taken as an example. In this embodiment, the semiconductor layer SC is formed using low-temperature polysilicon. Here, the drive transistor DRT is an N-channel type TFT (Nch TFT).

The semiconductor layer SC of the Nch TFT has a channel region between a first region, a second region, a first region and a second region, a channel region and a first region, and a channel region and a second region, respectively. It has a low-concentration impurity region provided. One of the first and second regions functions as a source region, and the other of the first and second regions functions as a drain region.

A silicon oxide film is used as the gate insulating film GI. The gate electrode GE is made of MoW (molybdenum / tungsten). The wiring and electrodes formed on the gate insulating film GI such as the gate electrode GE are referred to as 1st wiring or 1st metal. The gate electrode GE has a function as a holding capacitance electrode, which will be described later, in addition to a function as a gate electrode of the TFT. Although the top gate type TFT is described here as an example, the TFT may be a bottom gate type TFT.

An interlayer insulating film 64 is provided on the gate insulating film GI and the gate electrode GE. The interlayer insulating film 64 is formed by laminating, for example, a silicon nitride film and a silicon oxide film in this order on the gate insulating film GI and the gate electrode GE.

A first electrode E1, a second electrode E2, and a routing wiring LL are provided on the interlayer insulating film 64. A three-layer laminated structure (Ti system / Al system / Ti system) is adopted for each of the first electrode E1, the second electrode E2, and the routing wiring LL. In this three-layer laminated structure, the lower layer is made of a metal material containing Ti as a main component, such as Ti (titanium) and an alloy containing Ti. The intermediate layer is made of a metal material containing Al as a main component, such as Al (aluminum) and an alloy containing Al. The upper layer is made of a metal material containing Ti as a main component, such as Ti and an alloy containing Ti. The wiring and electrodes formed on the interlayer insulating film 64 such as the first electrode E1 are referred to as 2nd wiring or 2nd metal.

The first electrode E1 is connected to the first region of the semiconductor layer SC. The second electrode E2 is connected to the second region of the semiconductor layer SC. For example, when the first region of the semiconductor layer SC functions as a source region, the first electrode E1 is a source electrode and the second electrode E2 is a drain electrode. In this case, the first electrode E1 forms a holding capacitance Cs together with the interlayer insulating film 64 and the gate electrode (holding capacitance electrode) GE of the TFT.

The routing wiring LL extends to the end of the peripheral edge of the substrate SUB and forms a terminal for connecting the first circuit board 6 and the panel driver 5.
The flattening film 65 is formed on the interlayer insulating film 64, the first electrode E1, the second electrode E2, and the routing wiring LL so as to cover the TFT and the routing wiring LL. As the flattening film 65, an organic insulating material such as photosensitive acrylic is often used. Compared to the inorganic insulating material formed by CVD or the like, it is excellent in coverage of wiring steps and flatness of the surface. The flattening film 65 is removed at the pixel contact portion and the peripheral region.

A conductive layer including the conductive layers 66a and 66b is provided on the flattening film 65. This conductive layer is formed of, for example, ITO (indium tin oxide) as the oxide conductive layer.
The conductive layer 66a covers the portion where the first electrode E1 is exposed due to, for example, the removal of the flattening film 65. One of the purposes of the conductive layer 66a is to serve as a barrier film for preventing damage to the first electrode E1 and the exposed portion of the routing wiring LL in the manufacturing process.
The wiring and electrodes formed on the flattening film 65 such as the conductive layer 66b are referred to as 3rd wiring or 3rd metal. Further, the conductive layer 66c shown in FIG. 4 may be formed as the conductive layer forming the surface of the terminal portion.

The flattening film 65 and the conductive layers (conductive layers 66a and 66b) are covered with an insulating layer 67. The insulating layer 67 is formed of, for example, a silicon nitride film. A pixel electrode 68 is formed on the insulating layer 67. The pixel electrode 68 contacts the conductive layer 66a through the opening of the insulating layer 67 and is electrically connected to the first electrode E1. Here, the pixel electrode 68 serves as a connection terminal for mounting the light emitting element LED. The pixel electrode 68 is formed of a laminated body including a single conductive layer and two or more conductive layers. In the pixel electrode 68, for example, a two-layer laminated structure (Al system / Mo system) is adopted. In this two-layer laminated structure, the lower layer is made of Mo, a metal material containing Mo as a main component, such as an alloy containing Mo. The upper layer is made of a metal material containing Al as a main component, such as Al and an alloy containing Al.
The conductive layer 66b, the insulating layer 67, and the pixel electrode 68 form the auxiliary capacitance CAD described above.

An insulating layer 69 is provided on the insulating layer 67 and the pixel electrode 68. The insulating layer 69 is made of, for example, silicon nitride. The insulating layer 69 insulates the end portion of the pixel electrode 68 and the like, and has an opening for mounting the light emitting element LED on a part of the surface of the pixel electrode 68. The size of the opening of the insulating layer 69 is set to be one size larger than that of the light emitting element LED in consideration of the amount of mounting deviation in the mounting process of the light emitting element LED.

In the light emitting region LA, the light emitting element LED is mounted on the array substrate AR (pixel electrode 68). The light emitting element LED has an anode AN, a cathode CA, and a light emitting layer LI that emits light. The anode AN and the cathode CA are arranged at positions facing each other via the light emitting layer LI.

In the light emitting element LED, the anode side terminal is in contact with and fixed to the corresponding pixel electrode 68. The bonding between the anode AN of the light emitting element LED and the pixel electrode 68 is not particularly limited as long as good conduction can be ensured between them and the formation of the array substrate AR is not damaged. For example, a reflow process using a low-temperature molten solder material, a method such as placing a light emitting element LED on an array substrate AR via a conductive paste and then bonding by firing, or a method of bonding the light emitting element LED to the surface of the pixel electrode 68 and the anode of the light emitting element LED. A material similar to AN can be used, and a solid-layer bonding method such as ultrasonic bonding can be adopted.

Each light emitting element LED is configured to emit ultraviolet light. In the present embodiment, the first exposure apparatus EX1 is a polarization exposure apparatus for performing a photo-alignment treatment on an alignment film. Therefore, it is desirable that the ultraviolet light emitted by the light emitting element LED has a main peak within the wavelength range of 280 nm or less (200-280 nm). The ultraviolet light may have a main peak in a wavelength range other than the above.

Each light emitting element LED is composed of a light emitting diode (LED). Each light emitting element LED has a longest side length of 500 μm or less in a plan view. The light emitting element LED of the present embodiment has a square shape having a side length of 500 μm in a plan view.

However, the size of the light emitting element LED is not limited to this embodiment and can be variously modified. The light emitting element LED may be a mini LED having the longest side length of more than 100 μm and less than 300 μm in a plan view. Alternatively, the light emitting element LED may be a micro LED having the longest side length of 100 μm or less in a plan view. Alternatively, the light emitting element LED may be an LED having the longest side length of 300 μm or more and 500 μm or less in a plan view.

An element insulating layer 70 is provided on the array substrate AR on which the light emitting element LED is mounted. The element insulating layer 70 is formed of a resin material filled in the gaps between the light emitting element LEDs on the array substrate AR. The element insulating layer 70 exposes the surface of the cathode CA of the light emitting element LEDs.

The counter electrode 71 is arranged at a position facing the pixel electrode 68 via the light emitting element LED. The counter electrode 71 is formed on the surface of the cathode CA of the counter electrode 71 and on the element insulating layer 70, and is electrically connected to the cathode CA by coming into contact with the cathode CA. The counter electrode 71 needs to be formed as a transparent electrode in order to take out the emitted light from the light emitting element LED. The counter electrode 71 is formed by using, for example, ITO as the transparent conductive material. The counter electrode 71 commonly connects the cathode CAs of the plurality of light emitting element LEDs mounted in the light emitting region LA. Although not shown, the counter electrode 71 is connected to, for example, a wiring provided on the AR side of the array substrate by a cathode contact portion provided outside the light emitting region LA.

The counter electrode 71 is formed so as to cover the light emitting region LA in a plan view, extends to the non-light emitting region NLA, and is electrically connected to the conductive layer 66d. The conductive layer 66d is connected to the second power supply line PVL.

On the other hand, when the side wall portion of the light emitting element LED is insulated by a protective film or the like, it is not always necessary to fill the gap with a resin material or the like, and the resin material is the anode AN and the pixel electrode 68 exposed from the anode AN. It suffices if it can at least insulate the surface. In this case, it is sufficient that the counter electrode 71 can continuously cover the plurality of light emitting element LEDs without breaking the step.

As described above, the array substrate AR has a structure from the substrate SUB to the counter electrode 71. The polarizer PO faces the plurality of light emitting element LEDs and is located above the counter electrode 71.

Next, the second exposure apparatus EX2 will be described. FIG. 14 is a plan view showing the second exposure apparatus. The second exposure device EX2 is an exposure device that emits unpolarized light, unlike the first exposure device EX1.
As shown in FIG. 14, the second exposure device EX2 is different from the first exposure device EX1 in that it is configured without the polarizer PO and the fixing member AL.

The light source panel LP of the second exposure device EX2 of the present embodiment is configured in the same manner as the light source panel LP of the first exposure device EX1 except for the light emitting element LED. The light source panel LP has a substrate SUB and a plurality of pixels PX two-dimensionally arranged above the substrate SUB and each including a light emitting element. The drive unit DR is configured to independently drive a plurality of light emitting element LEDs (FIGS. 11 to 13). Each light emitting element LED emits ultraviolet light, and the length of one side, which is the longest in a plan view, is 500 μm or less.

In the present embodiment, the second exposure apparatus EX2 is an exposure apparatus for exposing the sealing material 51 without polarization. The sealing material 51 is cured by non-polarization in the ultraviolet region. Therefore, it is desirable that the ultraviolet light emitted by the light emitting element LED has a main peak in the wavelength range of 315 nm or more (315-400 nm). The ultraviolet light may have a main peak in a wavelength range other than the above.

Next, a method of manufacturing the liquid crystal display panel DP using the first exposure apparatus EX1 and the second exposure apparatus EX2 will be described. FIG. 15 is a diagram illustrating a manufacturing process of the liquid crystal display panel DP, and is a plan view showing a state in which an array pattern is formed on the mother glass 101.

As shown in FIGS. 1 to 7 and 15, first, a mother glass 101 as a first mother substrate having a size larger than that of the array substrate 1 is prepared as a transparent insulating substrate. According to this embodiment, the mother glass 101 has six rectangular array substrate forming regions R6 for forming the array substrate 1 and an ineffective region R7 deviating from the array substrate forming region R6. The mother glass 101 has a first planned division line e1 that overlaps the peripheral edge of the array substrate forming region R6.

An array pattern 1p including a TFT 19, an auxiliary capacitance element 24, a pixel electrode 26, and the like is formed on the prepared mother glass 101 by a normal manufacturing process such as repeating film formation and patterning.

Next, a photodegradable alignment film material is applied onto the alignment film material coating region of the mother glass 101 to form an alignment film 28 made of the alignment film material on the mother glass 101. For example, the alignment film material can be applied to the mother glass 101 on which the array pattern 1p is formed by using the spin coating method to form the alignment film 28. When the spin coating method is used, the alignment film material coating area is the entire area on the mother glass 101.
It is also possible to apply the alignment film material by using an inkjet method instead of the spin coating method. When the inkjet method is used, the alignment film material coating region may be limited to the array substrate forming region R6.

FIG. 16 is a diagram showing a state in which the alignment film 28 on the mother glass 101 is photoaligned in the manufacturing process of the liquid crystal display panel DP following FIG. FIG. 17 is a cross-sectional view showing a substrate 110 to be processed including the mother glass 101 shown in FIG. 16, an array pattern 1p, and an alignment film 28, a stage ST, and a first exposure apparatus EX1.
As shown in FIGS. 16 and 17, the substrate 110 to be processed is then placed on the stage ST so that the alignment film 28 faces the first exposure apparatus EX1 side. At that time, the first direction d1 of the substrate 110 to be processed and the row direction X of the first exposure device EX1 are made parallel to each other, and the second direction d2 of the substrate 110 to be processed and the column direction Y of the first exposure device EX1 are aligned. It is parallel. The polarizer PO of the first exposure apparatus EX1 faces the alignment film 28.

Here, in the direction Z, the distance from the surface of the polarizer PO facing the light source panel LP to the surface of the substrate 110 to be processed facing the polarizer PO is defined as DI1. Let T be the thickness of the polarizer PO. DI2 is the distance from the surface of the polarizing element PO facing the substrate 110 to be processed to the surface of the substrate 110 to be processed facing the polarizer PO. The distance DI1 is set to 2 mm or less. The thickness T is 0.5 mm or less. The distance DI2 is set to 1.0 mm or less. As a result, it is possible to suppress the diffusion of light emitted from the first exposure apparatus EX1 to the substrate 110 to be processed.
In this embodiment, the thickness T is 0.5 mm and the distance DI2 is 1.0 mm. Therefore, the distance DI1 is set to 1.5 mm.

Subsequently, the alignment film 28 of the substrate 110 to be processed is irradiated with linearly polarized light in the row direction Y and exposed while scanning in a direction parallel to the row direction Y. At that time, the drive unit DR switches the light emitting element LED on / off while moving the stage ST in a direction parallel to the column direction Y at a constant speed. As described above, the alignment film 28 can be subjected to photoalignment treatment (irradiation with polarized UV) without a photomask.

The target of the photo-alignment treatment is at least the entire display region DA of the alignment film 28. The region of the alignment film 28 in contact with the sealing material 51 is excluded from the photo-alignment treatment. As a result, it is possible to suppress a decrease in the adhesive strength between the array substrate 1 and the opposing substrate 2 that are bonded via the sealing material 51.
The plurality of pixels PX are arranged in a staggered pattern with respect to the column direction Y. Therefore, unevenness in the amount of light irradiation can be suppressed.
As a result, six array substrates 1 are completed with one mother glass 101.

FIG. 18 is a plan view showing a state in which the facing pattern 2p is formed on the mother glass 102 in the manufacturing process of the liquid crystal display panel DP.
As shown in FIGS. 1, 2, 3, 6, 7, and 18, on the other hand, in the method for manufacturing the opposed substrate 2, first, as a transparent insulating substrate, the size is larger than that of the opposed substrate 2. 2 A mother glass 102 as a mother substrate is prepared. According to this embodiment, the mother glass 102 has six rectangular facing substrate forming regions R8 and an ineffective region R9 deviating from the facing substrate forming region R8 in order to form the facing substrate 2. The mother glass 102 has a second scheduled division line e2 that overlaps the peripheral edge of the facing substrate forming region R8.

An opposed pattern 2p is formed on the prepared mother glass 102 by a normal manufacturing process. Next, using a spinner, for example, a photosensitive acrylic transparent resin is applied to the entire surface of the mother glass 102. Subsequently, the transparent resin is dried. Then, the patterning is exposed on the transparent resin using a predetermined photomask. Next, the exposed transparent resin is developed and then fired and cured. As a result, the columnar spacer 8 is formed.

After that, the alignment film 43 is formed on the mother glass 102 on which the facing pattern 2p is formed, and the alignment film 43 is subjected to photoalignment treatment. At that time, using the first exposure apparatus EX1 or the like, the alignment film 43 was subjected to the same photo-alignment treatment as the photo-alignment treatment applied to the alignment film 28. The target of the photo-alignment treatment is at least the entire display region DA of the alignment film 43. Also in the alignment film 43, the region in contact with the sealing material 51 is excluded from the photo-alignment treatment. As a result, it is possible to suppress a decrease in the adhesive strength between the array substrate 1 and the opposing substrate 2 that are bonded via the sealing material 51.
As a result, six opposed substrates 2 are completed with one mother glass 102.

In FIG. 19, in the manufacturing process of the liquid crystal display panel DP, the mother glass 101 on which the six array substrates 1 are formed and the mother glass 102 on which the six opposing substrates 2 are formed are laminated with each other via a sealant. It is a top view which shows the state.
Next, as shown in FIGS. 7 and 19, the sealant 51a is provided on the non-display region NDA of the alignment film (28, 43) of either the mother glass 101 or the mother glass 102. Here, the sealant 51a is applied over the entire circumference on the non-display region NDA of the alignment film 28 of the array substrate 1 by a printing method. An ultraviolet curable sealant is used as the sealant 51a. As a result, the sealing agent 51a is formed in a frame shape.

Then, the liquid crystal material is dropped into the region surrounded by the sealant 51a. Subsequently, the mother glass 101 and the mother glass 102 are arranged to face each other so that the alignment film 28 and the alignment film 43 face each other, and the array substrate 1 and the facing substrate 2 are arranged to face each other while holding a predetermined gap by a plurality of columnar spacers 8. Then, the peripheral edges of the array substrate 1 and the facing substrate 2 are bonded to each other with the sealing agent 51a.

FIG. 20 is a diagram showing a state in which the sealant 51a is irradiated with ultraviolet light in the manufacturing process of the liquid crystal display panel DP following FIG. FIG. 21 is a cross-sectional view showing the stage ST shown in FIG. 20, the second exposure apparatus EX2, and the substrate to be processed 120. The substrate 120 to be processed includes mother glass 101, 102, an array pattern 1p, an opposing pattern 2p, an alignment film 28, 43, a sealing agent 51a, and a liquid crystal layer 3.

As shown in FIGS. 20 and 21, the substrate 120 to be processed is then placed on the stage ST. The second exposure apparatus EX2 is arranged so that unpolarized light can be irradiated toward the substrate 120 to be processed.

Here, in the direction Z, the distance from the surface of the light source panel LP facing the light source panel 120 to the surface of the light source panel 120 facing the light source panel LP is defined as DI3. The distance DI3 is set to 1.0 mm or less. As a result, it is possible to suppress the diffusion of light emitted from the second exposure apparatus EX2 to the substrate 120 to be processed.
In this embodiment, the distance DI3 is 1.0 mm.

Subsequently, the sealant 51a of the substrate 120 to be processed is irradiated with unpolarized light and exposed while scanning in a direction parallel to the column direction Y. At that time, the drive unit DR switches the light emitting element LED on / off while moving the stage ST in a direction parallel to the column direction Y at a constant speed. As described above, the patterning can be exposed to the sealant 51a without a photomask. The object of exposure is at least the entire area of the sealant 51a. Liquid crystal materials are not subject to exposure. As a result, deterioration of the quality of the liquid crystal layer 3 can be suppressed.
As described above, the sealant 51a can be cured by irradiating the sealant 51a with ultraviolet light from the outside. If necessary, the sealant 51a may be further subjected to a thermosetting treatment to further cure it. By forming the sealing material 51 formed by curing the sealing agent 51a, the mother glass 101 and the mother glass 102 are joined via the sealing material 51.

Further, by laminating the mother glass 101 and the mother glass 102, the liquid crystal layer 3 can be formed in the space surrounded by the mother glass 101, the mother glass 102 and the sealing material 51.

Subsequently, the mother glass 101 is divided along the first planned division line e1, and the mother glass 102 is divided along the second planned division line e2. At the time of division, for example, a scribe line is drawn along the first scheduled division line e1 and the second scheduled division line e2 to divide. As a result, the array substrate 1 is cut out from the mother glass 101, and the facing substrate 2 is cut out from the mother glass 102.
As a result, as shown in FIG. 3, six liquid crystal display panel DPs are taken out from the divided mother glass 101 and mother glass 102. Then, each of the six liquid crystal display panel DPs is completed.

According to the first exposure apparatus EX1 and the second exposure apparatus EX2 according to the embodiment configured as described above, the first exposure apparatus EX1 performs photoalignment treatment on the alignment films 28 and 43 without a photomask. Can be done. The second exposure apparatus EX2 can expose the sealant 51a without a photomask. Therefore, it is possible to obtain the first exposure device EX1 and the second exposure device EX2 that can be exposed without a photomask.

Next, in the first embodiment, the detailed size will be examined. FIG. 22 is a diagram showing the relationship between the on / off of the plurality of light emitting element LEDs of the first exposure apparatus EX1 according to the present embodiment and the light irradiation range IA.

As shown in FIG. 22, in the first exposure apparatus EX1, 100 of the plurality of pixels PX of the light source panel LP are arranged in the row direction X and 100 in the column direction Y. In the figure, a plurality of pixel PXs are extracted from the pixel PXs having 100 rows and 100 columns. In FIG. 22, the plurality of pixels PX are arranged in a matrix in the row direction X and the column direction Y, but in reality, as shown in FIG. 8, they are arranged so as to be offset by half a pitch in the column direction. There is. Each pixel PX has a square shape and has a length of 500 μm in the row direction X and the column direction Y. In the light emitting region LA, the lengths of the row direction X and the column direction Y are 50 mm, respectively.

The ultraviolet light emitted by the light emitting element LED of the first exposure apparatus EX1 has a main peak at 365 nm. The polarizer PO is formed of a quartz plate, and the thickness T of the polarizer PO is 0.2 mm. The distance DI2 between the substrate 110 to be processed and the polarizer PO is 0.5 mm. When forming the alignment film 28 and the alignment film 43, a polyimide that photodecomposes with ultraviolet light having a main peak at 365 nm was applied.

The illuminance when all the lights were turned on (the light emitting element LEDs of all the pixels PX were made to emit light) was ^{0.5 mW / cm 2.} The stage ST (substrate 110) was moved below the first exposure apparatus EX1 as described above at a constant speed of 0.5 mm / s. This scanning was performed 30 times in total (30 times one way), and the irradiation dose was 1.5 J / cm ² .

In the above-mentioned first exposure apparatus EX1, in order to obtain the irradiation range IA as shown in the figure, a plurality of light emitting element LEDs were switched on / off as shown in the figure during a certain period, and a pattern was given to the alignment film. The plurality of light emitting element LEDs were turned on / off according to the relative positions of the substrate 110 to be transported and the first exposure device EX1. The irradiation range IA on the alignment film was expanded by 1 pixel PX from the desired range, but was not expanded by 2 pixels PX or more from the desired range. Then, it was confirmed that the photo-alignment treatment was not applied to the region of the alignment film other than the irradiation range IA. In other words, it was possible to avoid a decrease in the adhesive strength between the array substrate 1 and the opposing substrate 2 which are adhered via the sealing material 51.

In this embodiment, the plurality of light emitting element LEDs are independently driven, and the distance DI2 is 0.5 mm. Therefore, the alignment film can be irradiated with linearly polarized light without a photomask, and the diffusion of light emitted from the first exposure apparatus EX1 to the substrate 110 to be processed can be suppressed.

(Comparative Example 1)
Next, Comparative Example 1 will be described. FIG. 23 is a diagram showing the relationship between the on / off of the plurality of light emitting element LEDs of the first exposure device EX1 according to the first comparative example 1 and the light irradiation range IA.
In the first exposure apparatus EX1 of Comparative Example 1, the configuration of the light source panel LP is the same as that of the first embodiment.
Further, the ultraviolet light emitted by the light emitting element LED of the first exposure apparatus EX1 and the polarizer PO are also the same as those in the first embodiment. The difference from the first embodiment is that the distance DI2 between the substrate 110 to be processed and the polarizer PO is set to 1.5 mm.

The irradiation of the substrate 110 to be processed with linearly polarized light from the first exposure apparatus EX1 was performed under the same conditions as in the first embodiment.
In the above-mentioned first exposure apparatus EX1, in order to obtain the irradiation range IA as shown in the figure, a plurality of light emitting element LEDs were switched on / off as shown in the figure during a certain period to give a pattern to the alignment film. The irradiation range IA on the alignment film was expanded by 3 pixels PX from the desired range.

As a result, image burn-in occurs at the periphery of the display area DA due to insufficient orientation.
In addition, the region of the alignment film in contact with the sealing material 51 was also irradiated with light. When the tensile strength test was performed on the liquid crystal display panel DP, it was confirmed that the array substrate 1 and the opposing substrate 2 were easily peeled off. Further, even if the above test was not performed, when the liquid crystal display panel DP was washed with acetone after the completion of the liquid crystal display panel DP, it was confirmed that the alignment film irradiated with light was dissolved and the sealing material 51 was peeled off.
In the first embodiment and Comparative Example 1 described above, examples of successful and unsuccessful photo-alignment due to the setting of the distance DI2 between the substrate 110 to be processed and the polarizer PO are shown. As a result of further examination, it was found that when the thickness T of the polarizer PO is 0.5 mm or less, it is desirable that the distance DI2 is set to 1.0 mm or less.

(Second embodiment)
Next, the second embodiment will be described. When exposing a large-sized mother glass, the first exposure device EX1 and the second exposure device EX2 may be configured by arranging a plurality of light source panel LPs side by side. Here, the first exposure apparatus EX1 will be described on behalf of the first exposure apparatus EX1 and the second exposure apparatus EX2. FIG. 22 is a plan view showing the first exposure apparatus EX1 according to the present embodiment.

As shown in FIG. 22, the first exposure apparatus EX1 further includes a first exposure unit EU1 and a second exposure unit EU2. The first exposure unit EU1 and the second exposure unit EU2 are each composed of a light source panel LP, a polarizer PO, and an aggregate of the fixing member (AL). In the case of the second exposure device EX2, the first exposure unit EU1 and the second exposure unit EU2 may each be composed of the light source panel LP.
The drive unit (DR) is configured to independently drive a plurality of light emitting elements (LEDs) of the first exposure unit EU1 and a plurality of light emitting elements (LEDs) of the second exposure unit EU2. ..

In the example of the present embodiment, the first exposure unit EU1 and the second exposure unit EU2 are arranged so as to be offset in the column direction Y, and in the row direction X, the right end portion of the light source panel LP of the first exposure unit EU1 and the right end portion of the light source panel LP of the first exposure unit EU1. The second exposure unit EU2 is arranged so as to overlap with the left end of the light source panel LP.

In such an arrangement, the gap g1 between the pixels PX in the first exposure unit EU1, the gap g1 between the pixels PX in the second exposure unit EU2, and the rightmost pixel PX of the first exposure unit EU1 in the row direction X. The gap g3 with the leftmost pixel PX of the second exposure unit EU2 is arranged so as to have the same spacing.

For example, pay attention to the pixel group PXG1 in the first row of the first exposure unit EU1 and the pixel group PXG1 in the first row of the second exposure unit EU2. The gap g1 in the first exposure unit EU1, the gap g1 in the second exposure unit EU2, the rightmost pixel PX of the pixel group PXG1 of the first exposure unit EU1, and the leftmost pixel PX of the pixel group PXG1 of the second exposure unit EU2. Is the same as the gap g3 of.

By adjusting to such a gap, the integrated irradiation amount of the substrate 110 to be processed does not change even at the connecting portion of the exposure unit EU in the scanning process, and uniform irradiation is possible. Further, even if there is a polarization axis difference between different exposure units, the integrated irradiation amount at the time of scanning is the integrated irradiation amount derived from the terminal pixel PX of each different exposure unit, so that the liquid crystal display panel is intermediate. It is possible to suppress uneven brightness due to the deviation of the polarization axis angle of the connecting portion when the display is adjusted.

As described above, a plurality of exposure units EU may be arranged in the row direction X to form the first exposure apparatus EX1 according to the length of the first direction d1 of the substrate 110 to be processed. The first exposure apparatus EX1 may be configured by arranging three or more exposure units EU in the row direction X. As a result, the irradiation period by the first exposure apparatus EX1 can be shortened.
Alternatively, the first exposure apparatus EX1 may be configured by arranging three or more exposure units EU in the column direction Y. In that case as well, the irradiation period by the first exposure apparatus EX1 can be shortened.
The same effect as that of the above-described embodiment can be obtained in the exposure apparatus EX according to the second embodiment configured as described above.

(Third Embodiment)
Next, a third embodiment will be described. FIG. 25 is a plan view showing the first exposure apparatus EX1 according to the present embodiment.

As shown in FIG. 25, in the first exposure apparatus EX1, the polarizing element PO is composed of a plurality of polarizing plate PPs. The plurality of polarizing plates PP are physically independent of each other and are arranged in the row direction X without overlapping each other in the row direction X and the column direction Y. In the present embodiment, the polarizing element PO includes two polarizing plate PPs, but the present invention is not limited to this, and three or more polarizing plate PPs may be arranged side by side in the row direction X.

The plurality of polarizing plates PP face each other of a plurality of pixel PXs that are different from each other. Therefore, the pixel PX that overlaps the one polarizing plate PP does not overlap the other polarizing plate PP.

Here, attention is paid to the boundary portion B of the pair of polarizing plates PP adjacent to each other in the row direction X among the plurality of polarizing plates PP. The pixel groups PXG1 to PXG4 are arranged in the column direction Y so as to be offset in the row direction X by half a pitch of one pixel PX. The end portion of the polarizing plate PP of the present modification 2 in the row direction X is formed in a stepped shape according to the deviation of the pixel groups PXG1 to PXG4. Therefore, the boundary portion B overlaps the gap g1 in the row direction X and the gap g2 in the column direction Y, and does not overlap the pixel PX. Therefore, even if the first exposure apparatus EX1 is brought close to the substrate 110 to be processed and the distance DI2 is set to 1.0 mm or less, unevenness in the amount of light irradiation and unevenness in the polarization axis can be suppressed.
The exposure apparatus EX according to the third embodiment configured as described above can also obtain the same effects as those of the first and second embodiments.

(Comparative Example 2, Comparative Example 3, and Comparative Example 4)
Next, a comparative example of the second and third embodiments will be described. FIG. 26 is a plan view showing the first exposure apparatus EX1 according to Comparative Example 2. FIG. 27 is a plan view showing the first exposure apparatus EX1 according to Comparative Example 3. FIG. 28 is a plan view showing the first exposure apparatus EX1 according to Comparative Example 4.

In Comparative Example 2 of FIG. 26, the end portion of the polarizing plate PP in the row direction X is formed linearly in the column direction Y regardless of the displaced arrangement of the pixel groups PXG1 to 4. Therefore, a part of the boundary portion B of the polarizing plate PP intersects with the pixel PX. Therefore, when the first exposure device EX1 of Comparative Example 2 is used, the polarization axis becomes uneven at the boundary portion B.

Here, FIG. 29 shows the relationship between the on / off of the plurality of light emitting element LEDs of the first exposure apparatus EX1 and the light irradiation range IA when the example of FIG. 26 is used.
In the first exposure apparatus EX1 of FIG. 29, a plurality of polarizer PPs are used in the light source panel LP as shown in FIG. 26, and the boundary of the polarizer shown in B of FIG. 26 is x in FIG. 29. Corresponds to the location of coordinates 51.

However, since the position of the x-coordinate 51 in FIG. 29 corresponds to pixels having different orientation axes on the left and right of the boundary B of the polarizer in FIG. 24, when the liquid crystal display panel DP is displayed in halftone, the boundary portion at the time of manufacturing At the position facing B, linear display unevenness in the second direction d2 (row direction Y) was generated.

In Comparative Example 3 of FIG. 27, a gap is formed between the polarizing plates PP. The boundary portion B has a width. Also in Comparative Example 3, a part of the boundary portion B intersects with the pixel PX. Therefore, when the first exposure device EX1 of Comparative Example 3 is used, unevenness in the amount of light irradiation occurs at the boundary portion B.

In Comparative Example 4 of FIG. 28, among the gaps g1 between the plurality of pixels PX, the gap g1 sandwiching the boundary portion B is larger than the other gaps g1. Unlike the above-described embodiment and Comparative Examples 2 and 3, in Comparative Example 4, although there is no overlapping pixel PX at the end of the polarizing plate PP, the gap g1 between the pixels PX is not constant. Therefore, when the first exposure device EX1 of Comparative Example 4 is used, unevenness in the amount of light irradiation occurs in the vicinity of the boundary portion B.

Although the embodiments and modifications of the present invention have been described, these embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. The above-mentioned novel embodiments and modifications can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. The above-described embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

EX, EX1, EX2 ... exposure device, EU ... exposure unit, EU1 ... first exposure unit,
EU2 ... 2nd exposure unit, LP ... Light source panel, PX ... Pixel, PXG ... Pixel group,
LED ... light emitting element, PO ... polarizer, PP ... polarizing plate, AL ... fixing member, DR ... drive unit,
LA ... light emitting region, NLA ... non-light emitting region, B ... boundary portion, g1, g2, g3 ... gap,
X ... row direction, Y ... column direction, ST ... stage, DP ... liquid crystal display panel,
28, 43 ... Alignment film, 51 ... Sealing material, 51a ... Sealing agent, DA ... Display area,
NDA ... non-display area, d1 ... first direction, d2 ... second direction,
DI1, DI2, DI3 ... Distance.

Claims (13)

A light source panel having a substrate and a plurality of pixels two-dimensionally arranged above the substrate, each including a light emitting element.
A drive unit that independently drives the plurality of light emitting elements,
With the polarizer facing the plurality of light emitting elements,
A fixing member for fixing the relative positions of the polarizer and the light source panel is provided.
Each of the light emitting elements emits ultraviolet light and has the longest side length of 500 μm or less in a plan view.
Exposure device. The ultraviolet light has a main peak in the wavelength range of 280 nm or less.
The exposure apparatus according to claim 1. Further, a plurality of pixel groups extending in the row direction and arranged in the column direction orthogonal to the row direction are further provided.
Each of the pixel groups is composed of a plurality of pixels arranged in the row direction among the plurality of pixels.
The exposure apparatus according to claim 1. The plurality of pixels of each of the pixel groups are arranged with a gap in the row direction.
When focusing on the pair of pixels adjacent to each other in the column direction,
Each of the gaps in one of the pixel groups faces the pixel in the other pixel group in the column direction.
Each of the gaps in the other pixel group faces the pixel in the one pixel group in the column direction.
The exposure apparatus according to claim 3. The pixels of the other pixel group are not only in the gap of the one pixel group, but also in the row of a pair of pixels on both sides of the gap among the plurality of pixels of the one pixel group. Facing the direction,
The pixel of the one pixel group is not only with the gap of the other pixel group, but also with a pair of pixels on both sides of the gap among the plurality of pixels of the other pixel group. Opposing in the direction,
The exposure apparatus according to claim 4. Further equipped with a first exposure unit and a second exposure unit,
The first exposure unit and the second exposure unit are each composed of an assembly of the light source panel, the polarizer, and the fixing member.
The driving unit independently drives the plurality of light emitting elements of the first exposure unit and the plurality of light emitting elements of the second exposure unit.
When the row direction is parallel to the left-right direction, the right end of the light source panel of the first exposure unit and the left end of the light source panel of the second exposure unit face each other in the column direction. And
When paying attention to the nth row pixel group among the plurality of pixel groups of the first exposure unit and the nth row pixel group among the plurality of pixel groups of the second exposure unit,
With the gap in the first exposure unit,
With the gap in the second exposure unit,
The gap between the rightmost pixel of the first exposure unit and the leftmost pixel of the second exposure unit in the row direction is the same.
The exposure apparatus according to claim 4 or 5. The polarizers are composed of a plurality of polarizing plates that are physically independent of each other and are arranged in the row direction without overlapping each other.
The plurality of polarizing plates face each other of the plurality of pixels, which are different from each other.
When focusing on the pair of pixels adjacent to each other in the column direction,
The plurality of pixels of the one pixel group and the plurality of pixels of the other pixel group are located with a gap in the column direction.
When paying attention to the boundary portion of a pair of polarizing plates adjacent to each other in the row direction among the plurality of polarizing plates,
The boundary portion overlaps the gap in the row direction and the gap in the column direction, and does not overlap the pixel.
The exposure apparatus according to claim 4 or 5. A light source panel having a substrate and a plurality of pixels two-dimensionally arranged above the substrate, each including a light emitting element.
A drive unit that independently drives the plurality of light emitting elements is provided.
Each of the light emitting elements emits ultraviolet light and has the longest side length of 500 μm or less in a plan view.
Exposure device. The ultraviolet light has a main peak in the wavelength range of 315 nm or more.
The exposure apparatus according to claim 8. Further, a plurality of pixel groups extending in the row direction and arranged in the column direction orthogonal to the row direction are further provided.
Each of the pixel groups is composed of a plurality of pixels arranged in the row direction among the plurality of pixels.
The exposure apparatus according to claim 8. The plurality of pixels of each of the pixel groups are arranged with a gap in the row direction.
When focusing on the pair of pixels adjacent to each other in the column direction,
Each of the gaps in one of the pixel groups faces the pixel in the other pixel group in the column direction.
Each of the gaps in the other pixel group faces the pixel in the one pixel group in the column direction.
The exposure apparatus according to claim 10. The pixel of the other pixel group is not only the gap of the one pixel group, but also a pair of light emitting elements on both sides of the gap among the plurality of pixels of the one pixel group. Facing in the row direction,
The pixel of the one pixel group is not only with the gap of the other pixel group, but also with a pair of pixels on both sides of the gap among the plurality of pixels of the other pixel group. Opposing in the direction,
The exposure apparatus according to claim 11. Further equipped with a first exposure unit and a second exposure unit,
The first exposure unit and the second exposure unit are each composed of the light source panel.
The driving unit independently drives the plurality of light emitting elements of the first exposure unit and the plurality of light emitting elements of the second exposure unit.
When the row direction is parallel to the left-right direction, the right end of the light source panel of the first exposure unit and the left end of the light source panel of the second exposure unit face each other in the column direction. And
When paying attention to the nth row pixel group among the plurality of pixel groups of the first exposure unit and the nth row pixel group among the plurality of pixel groups of the second exposure unit,
With the gap in the first exposure unit,
With the gap in the second exposure unit,
The gap between the rightmost pixel of the first exposure unit and the leftmost pixel of the second exposure unit in the row direction is the same.
The exposure apparatus according to claim 11 or 12.

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