JP2021022598A - Board processing method, board processing device, and wiring pattern formation system - Google Patents
Board processing method, board processing device, and wiring pattern formation system Download PDFInfo
- Publication number
- JP2021022598A JP2021022598A JP2019136393A JP2019136393A JP2021022598A JP 2021022598 A JP2021022598 A JP 2021022598A JP 2019136393 A JP2019136393 A JP 2019136393A JP 2019136393 A JP2019136393 A JP 2019136393A JP 2021022598 A JP2021022598 A JP 2021022598A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- substrate
- film
- laser
- processing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
Abstract
Description
本開示は、基板処理方法、基板処理装置及び配線パターン形成システムに関する。 The present disclosure relates to a substrate processing method, a substrate processing apparatus, and a wiring pattern forming system.
例えば、複数の凸部を有するパターンが表面に形成された基板において、変形したパターン凸部を復元する基板処理方法が知られている。 For example, in a substrate in which a pattern having a plurality of convex portions is formed on the surface, a substrate processing method for restoring the deformed pattern convex portions is known.
特許文献１には、倒壊したパターンを復元する基板処理方法が開示されている。 Patent Document 1 discloses a substrate processing method for restoring a collapsed pattern.
一の側面では、本開示は、膜に形成されたパターンの変形を改善する基板処理方法、基板処理装置及び配線パターン形成システムを提供する。 In one aspect, the present disclosure provides a substrate processing method, a substrate processing apparatus and a wiring pattern forming system that improve the deformation of a pattern formed on a film.
上記課題を解決するために、一の態様によれば、表面の膜にパターンが形成された基板を準備する工程と、前記基板の表面にレーザを照射して、前記パターンを改質する工程と、を有する、基板処理方法が提供される。 In order to solve the above problems, according to one embodiment, a step of preparing a substrate having a pattern formed on a surface film and a step of irradiating the surface of the substrate with a laser to modify the pattern. , A substrate processing method is provided.
一の側面によれば、膜に形成されたパターンの変形を改善する基板処理方法、基板処理装置及び配線パターン形成システムを提供することができる。 According to one aspect, it is possible to provide a substrate processing method, a substrate processing apparatus, and a wiring pattern forming system that improve the deformation of the pattern formed on the film.
以下、図面を参照して本開示を実施するための形態について説明する。各図面において、同一構成部分には同一符号を付し、重複した説明を省略する場合がある。 Hereinafter, embodiments for carrying out the present disclosure will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.
＜配線パターン形成システム＞
本実施形態に係る配線パターン形成システム１００について、図１を用いて説明する。図１は、本実施形態に係る配線パターン形成システム１００の構成の一例を示す模式図である。
<Wiring pattern formation system>
The wiring pattern forming system 100 according to this embodiment will be described with reference to FIG. FIG. 1 is a schematic view showing an example of the configuration of the wiring pattern forming system 100 according to the present embodiment.
配線パターン形成システム１００は、パターン形成装置１０１と、改質装置（基板処理装置）１０２と、成膜装置１０３と、搬送装置１０４，１０５と、制御装置１０６と、を備えている。 The wiring pattern forming system 100 includes a pattern forming device 101, a reforming device (board processing device) 102, a film forming device 103, transfer devices 104 and 105, and a control device 106.
パターン形成装置１０１は、基板Ｗの膜に所望のパターンを形成する装置である。例えば、後述する図４（ａ）に示すように、パターン形成装置１０１に提供される基板Ｗには、Ｓｉ基板２０の上に絶縁膜であるＳｉＮ膜２１が成膜され、その上に所望のパターンを有するアモルファスシリコン膜（以下「ａ−Ｓｉ膜」と称する。）２２が形成されている。パターン形成装置１０１は、ａ−Ｓｉ膜２２をマスクとして、ＳｉＮ膜２１をエッチングすることにより、後述する図４（ｂ）に示すように、所望のパターンを有する膜（ＳｉＮ膜２１、ａ−Ｓｉ膜２２）を形成する。以下の説明では、所望のパターンは、トレンチ２３（ラインアンドスペース）を形成するものして説明する。なお、パターン形成装置１０１によるエッチングは、ウェットプロセスで行われてもよく、ドライプロセスで行われてもよい。 The pattern forming apparatus 101 is an apparatus for forming a desired pattern on the film of the substrate W. For example, as shown in FIG. 4A described later, a SiN film 21 which is an insulating film is formed on the Si substrate 20 on the substrate W provided in the pattern forming apparatus 101, and a desired film is formed on the SiN film 21. An amorphous silicon film (hereinafter referred to as “a—Si film”) 22 having a pattern is formed. The pattern forming apparatus 101 etches the SiN film 21 using the a-Si film 22 as a mask, and as shown in FIG. 4B described later, the pattern forming apparatus 101 has a film having a desired pattern (SiN film 21, a-Si). A film 22) is formed. In the following description, the desired pattern will be described as forming a trench 23 (line and space). The etching by the pattern forming apparatus 101 may be performed by a wet process or a dry process.
改質装置１０２は、基板Ｗの表面にレーザを照射して、表面を改質する装置である。これにより、膜（ＳｉＮ膜２１、ａ−Ｓｉ膜２２）に形成されたパターンの変形（例えば、撚れ、曲り、倒れ）を改善する。なお、改質装置１０２については、図２を用いて後述する。 The reforming device 102 is a device that irradiates the surface of the substrate W with a laser to reform the surface. This improves the deformation (for example, twisting, bending, and tilting) of the pattern formed on the film (SiN film 21, a-Si film 22). The reformer 102 will be described later with reference to FIG.
成膜装置１０３は、基板Ｗのトレンチ２３に金属を成膜して配線パターン（例えば、ビットライン）を形成する装置である。配線パターンに用いられる金属としては、タングステン（Ｗ）、ルテニウム（Ｒｕ）、コバルト（Ｃｏ）等を用いることができる。なお、成膜装置１０３は、例えば、ＡＬＤ（Atomic Layer Deposition）装置、ＣＶＤ（Chemical Vapor Deposition）装置により実現される。 The film forming apparatus 103 is an apparatus for forming a wiring pattern (for example, a bit line) by forming a metal film in the trench 23 of the substrate W. As the metal used for the wiring pattern, tungsten (W), ruthenium (Ru), cobalt (Co) and the like can be used. The film forming apparatus 103 is realized by, for example, an ALD (Atomic Layer Deposition) apparatus and a CVD (Chemical Vapor Deposition) apparatus.
搬送装置１０４は、パターン形成装置１０１と改質装置１０２との間で基板Ｗまたは基板Ｗを収容したキャリアを搬送する。搬送装置１０５は、改質装置１０２と成膜装置１０３との間で基板Ｗまたは基板Ｗを収容したキャリアを搬送する。 The transport device 104 transports the substrate W or the carrier accommodating the substrate W between the pattern forming device 101 and the reformer 102. The transport device 105 transports the substrate W or the carrier containing the substrate W between the reformer 102 and the film forming apparatus 103.
制御装置１０６は、これら各構成装置を制御することにより、配線パターン形成システム１００による処理全体を制御する。制御装置１０６は、ＣＰＵ（Central Processing Unit）、ＲＯＭ（Read Only Memory）及びＲＡＭ（Random Access Memory）を有している。ＣＰＵは、ＲＡＭ等の記憶領域に格納されたレシピに従って、所望の処理を実行する。レシピにはプロセス条件に対する装置の制御情報であるプロセス時間、各種ガス流量、圧力（ガスの排気）などが設定されている。 The control device 106 controls the entire processing by the wiring pattern forming system 100 by controlling each of these constituent devices. The control device 106 has a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The CPU executes a desired process according to a recipe stored in a storage area such as RAM. In the recipe, process time, various gas flow rates, pressure (gas exhaust), etc., which are control information of the device for process conditions, are set.
＜改質装置１０２＞
次に、改質装置１０２について、図２を用いて更に説明する。図２は、改質装置１０２の構成図である。基板Ｗを載置するステージ１１と、レーザ照射装置１２と、走査機構１３と、を備える。
<Reformer 102>
Next, the reformer 102 will be further described with reference to FIG. FIG. 2 is a block diagram of the reformer 102. A stage 11 on which the substrate W is placed, a laser irradiation device 12, and a scanning mechanism 13 are provided.
改質装置１０２は、基板Ｗを載置するステージ１１を備える。 The reformer 102 includes a stage 11 on which the substrate W is placed.
改質装置１０２は、ステージ１１に載置された基板Ｗにレーザを照射するレーザ照射装置１２を備える。ここで、照射するレーザは、ＫｒＦエキシマレーザ（波長：２４８ｎｍ）を用いることができる。レーザ装置の各パラメータは、以下の通りである。
エキシマレーザ（ＫｒＦ）２４８ｎｍ，光学パルスストレッチャ（ＯＰＳ；Optical Pulse Stretcher）７ｍ，照射フルエンス２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎ
The reformer 102 includes a laser irradiation device 12 that irradiates the substrate W mounted on the stage 11 with a laser. Here, as the laser to irradiate, a KrF excimer laser (wavelength: 248 nm) can be used. Each parameter of the laser device is as follows.
Excimer laser (KrF) 248 nm, optical pulse stretcher (OPS; Optical Pulse Stretcher) 7 m, irradiation fluence 200 m J / cm 2 , 20 shot / location
改質装置１０２は、レーザを基板Ｗ上で走査させるための走査機構１３を備える。例えば、走査機構１３は、ステージ１１に載置された基板Ｗを水平方向に移動可能なＸＹテーブルとして構成されていてもよい。この構成では、レーザ照射装置１２を固定し、ＸＹテーブルで基板Ｗを移動させることにより、レーザを基板Ｗ上で走査させる。また、走査機構１３は、レーザ照射装置１２を水平方向に移動可能な移動機構として構成されていてもよい。この構成では、ステージ１１を固定し、移動機構でレーザ照射装置１２を移動させることにより、レーザを基板Ｗ上で走査させる。また、走査機構１３は、角度制御可能なミラーとして構成されていてもよい。この構成では、レーザ照射装置１２から照射されたレーザはミラーで反射されステージ１１に載置された基板Ｗに照射される。この際、ミラーの角度を制御することにより、レーザを基板Ｗ上で走査させる。 The reformer 102 includes a scanning mechanism 13 for scanning the laser on the substrate W. For example, the scanning mechanism 13 may be configured as an XY table in which the substrate W mounted on the stage 11 can be moved in the horizontal direction. In this configuration, the laser irradiation device 12 is fixed and the substrate W is moved on the XY table to scan the laser on the substrate W. Further, the scanning mechanism 13 may be configured as a moving mechanism capable of moving the laser irradiation device 12 in the horizontal direction. In this configuration, the stage 11 is fixed and the laser irradiation device 12 is moved by the moving mechanism to scan the laser on the substrate W. Further, the scanning mechanism 13 may be configured as a mirror whose angle can be controlled. In this configuration, the laser irradiated from the laser irradiation device 12 is reflected by the mirror and irradiated to the substrate W mounted on the stage 11. At this time, the laser is scanned on the substrate W by controlling the angle of the mirror.
このような構成により、改質装置１０２は、基板Ｗ上の所望の位置にレーザを照射することができる。 With such a configuration, the reformer 102 can irradiate the laser at a desired position on the substrate W.
なお、改質装置１０２は、大気雰囲気で基板Ｗにレーザを照射してもよい。また、ステージ１１を収容するチャンバを備えていてもよい。また、改質装置１０２は、チャンバ内からガスを排気する排気装置を備えていてもよい。これにより、基板Ｗの照射雰囲気を真空雰囲気としてもよい。また、改質装置１０２は、チャンバ内にガスを供給するガス供給装置を備えていてもよい。これにより、基板Ｗの照射雰囲気を所望のガス雰囲気としてもよい。なお、レーザ照射装置１２は、チャンバ内に配置されていてもよい。また、レーザ照射装置１２は、チャンバ外に配置され、チャンバに設けられた窓を介してチャンバ内の基板Ｗにレーザを照射してもよい。 The reformer 102 may irradiate the substrate W with a laser in an atmospheric atmosphere. Further, a chamber for accommodating the stage 11 may be provided. Further, the reformer 102 may include an exhaust device for exhausting gas from the chamber. As a result, the irradiation atmosphere of the substrate W may be a vacuum atmosphere. Further, the reformer 102 may include a gas supply device for supplying gas into the chamber. As a result, the irradiation atmosphere of the substrate W may be a desired gas atmosphere. The laser irradiation device 12 may be arranged in the chamber. Further, the laser irradiation device 12 may be arranged outside the chamber and may irradiate the substrate W in the chamber with a laser through a window provided in the chamber.
＜配線パターン形成システム１００の動作＞
次に、配線パターン形成システム１００の動作について図３及び図４を用いて説明する。図３は、配線パターン形成システム１００の処理を説明するフローチャートである。図４は、各工程における基板Ｗの断面模式図である。
<Operation of wiring pattern forming system 100>
Next, the operation of the wiring pattern forming system 100 will be described with reference to FIGS. 3 and 4. FIG. 3 is a flowchart illustrating the processing of the wiring pattern forming system 100. FIG. 4 is a schematic cross-sectional view of the substrate W in each step.
図４（ａ）に示すように、基板Ｗは、例えばＳｉ基板２０の上に絶縁膜であるＳｉＮ膜２１が成膜され更に所望のパターンを有するａ−Ｓｉ膜２２が形成されている。基板Ｗは、パターン形成装置１０１にセットされる。 As shown in FIG. 4A, in the substrate W, for example, a SiN film 21 as an insulating film is formed on the Si substrate 20, and an a-Si film 22 having a desired pattern is further formed. The substrate W is set in the pattern forming apparatus 101.
ステップＳ１において、制御装置１０６は、パターン形成装置１０１を制御して、基板Ｗのａ−Ｓｉ膜２２をマスクとして、ＳｉＮ膜２１をエッチングすることにより、図４（ｂ）に示すように、ＳｉＮ膜２１に所望のパターン（トレンチ２３）を形成する。ここで、基板Ｗの表面の膜に形成されたパターンには、膜の応力による変形（図４（ｂ）の例では、倒れ）が生じている。 In step S1, the control device 106 controls the pattern forming device 101 to etch the SiN film 21 using the a-Si film 22 of the substrate W as a mask, thereby performing SiN as shown in FIG. 4 (b). A desired pattern (trench 23) is formed on the film 21. Here, the pattern formed on the film on the surface of the substrate W is deformed by the stress of the film (in the example of FIG. 4B, it collapses).
パターン形成装置１０１による処理が完了すると、制御装置１０６は、搬送装置１０４を制御して、基板Ｗをパターン形成装置１０１から改質装置１０２へと搬送し、ステージ１１に載置させる。即ち、改質装置１０２で処理する基板Ｗを準備する（ステップＳ２）。 When the processing by the pattern forming device 101 is completed, the control device 106 controls the transport device 104 to transport the substrate W from the pattern forming device 101 to the reforming device 102 and place it on the stage 11. That is, the substrate W to be processed by the reformer 102 is prepared (step S2).
次に、ステップＳ３において、制御装置１０６は、改質装置１０２を制御して、基板Ｗの表面にレーザを照射する。これにより、パターンを改質する。具体的には、表面の膜の応力による変形を改善する。なお、図４（ｃ）の断面模式図では、基板Ｗの表面の膜に形成されたパターンの倒れを改善する場合を示す。 Next, in step S3, the control device 106 controls the reforming device 102 to irradiate the surface of the substrate W with a laser. This modifies the pattern. Specifically, it improves the deformation of the surface film due to stress. The schematic cross-sectional view of FIG. 4C shows a case of improving the collapse of the pattern formed on the film on the surface of the substrate W.
図５は、基板Ｗ上のラインパターンを上から見たＳＥＭ（Scanning Electron Microscope）画像の一例を示す。（ａ）はレーザ未照射のＳＥＭ画像の一例を示し、（ｂ）はレーザ照射後のＳＥＭ画像の一例を示す。なお、図５の例において、基板Ｗは、ＳｉＮ膜の膜厚を１２０ｎｍとし、パターンのピッチを５２ｎｍとした。また、図５（ｂ）において、基板Ｗの表面にＫｒＦエキシマレーザを２４８ｎｍ，２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎで照射した。 FIG. 5 shows an example of an SEM (Scanning Electron Microscope) image of a line pattern on the substrate W viewed from above. (A) shows an example of an SEM image without laser irradiation, and (b) shows an example of an SEM image after laser irradiation. In the example of FIG. 5, the substrate W has a SiN film thickness of 120 nm and a pattern pitch of 52 nm. Further, in FIG. 5B, the surface of the substrate W was irradiated with a KrF excimer laser at 248 nm, 200 mJ / cm 2 , and 20 shots / location.
図５（ａ）に示すように、レーザを照射していない場合、膜（ＳｉＮ膜２１、ａ−Ｓｉ膜２２）に形成されるパターンには、膜の応力による変形（例えば、撚れ、曲り、倒れ）が生じている。図５（ａ）の例では、ＬＥＲ（Line Edge Roughness）、つまり、パターンのラインエッジの撚れは、ラインの左側（ＬＥＲ−Ｌ）が６．７０ｎｍ、ラインの右側（ＬＥＲ−Ｒ）が１０．９０ｎｍであった。また、ＬＷＲ（Line Width Roughness）、つまり、ラインエッジの撚れにより生じるライン幅の揺らぎは、６．２４ｎｍであった。 As shown in FIG. 5A, when the laser is not irradiated, the pattern formed on the film (SiN film 21, a-Si film 22) is deformed (for example, twisted or bent) due to the stress of the film. , Collapse) has occurred. In the example of FIG. 5A, the LER (Line Edge Roughness), that is, the twist of the line edge of the pattern is 6.70 nm on the left side (LER-L) of the line and 10 on the right side (LER-R) of the line. It was .90 nm. Further, the LWR (Line Width Roughness), that is, the fluctuation of the line width caused by the twisting of the line edge was 6.24 nm.
これに対し、図５（ｂ）の例では、ＬＥＲは、ラインの左側（ＬＥＲ−Ｌ）が６．０２ｎｍ、ラインの右側（ＬＥＲ−Ｒ）が４．３０ｎｍであった。また、ＬＷＲは、４．２１ｎｍであった。 On the other hand, in the example of FIG. 5B, the LER was 6.02 nm on the left side (LER-L) of the line and 4.30 nm on the right side (LER-R) of the line. The LWR was 4.21 nm.
上記結果から、基板Ｗの表面にレーザを照射した場合、レーザを照射しなかった場合と比べて、ＬＥＲ及びＬＷＲのいずれの値も小さくなった。また、レーザを照射した場合とレーザを照射しなかった場合で、ＬＷＲ比で、約４８％の改善がみられた。以上から、レーザを照射して膜を加熱し膜の応力を緩和することにより、膜の応力による変形を改善する（変形を小さくする）ことができた。 From the above results, when the surface of the substrate W was irradiated with the laser, both the values of LER and LWR were smaller than those when the surface of the substrate W was not irradiated with the laser. In addition, an improvement of about 48% was observed in the LWR ratio between the case where the laser was irradiated and the case where the laser was not irradiated. From the above, it was possible to improve (reduce the deformation) the deformation due to the stress of the film by irradiating the laser to heat the film and relaxing the stress of the film.
改質装置１０２による処理が完了すると、制御装置１０６は、搬送装置１０５を制御して、基板Ｗを改質装置１０２から成膜装置１０３へと搬送する。 When the processing by the reformer 102 is completed, the control device 106 controls the transfer device 105 to transfer the substrate W from the reformer 102 to the film forming apparatus 103.
次に、ステップＳ４において、制御装置１０６は、成膜装置１０３を制御して、トレンチ２３に金属を成膜して配線パターンを形成する。 Next, in step S4, the control device 106 controls the film forming apparatus 103 to form a metal film in the trench 23 to form a wiring pattern.
成膜装置１０３による処理が完了すると、制御装置１０６は、搬送装置１０５を制御して、基板Ｗを成膜装置１０３から搬出する。 When the processing by the film forming apparatus 103 is completed, the control device 106 controls the transport device 105 to carry out the substrate W from the film forming apparatus 103.
以上、本実施形態に係る配線パターン形成システム１００によれば、基板Ｗの表面の膜に形成されたパターンの撚れ（Wiggling）、曲り（Bending）、倒れを改善することができる。 As described above, according to the wiring pattern forming system 100 according to the present embodiment, it is possible to improve the twisting (Wiggling), bending (Bending), and tilting of the pattern formed on the film on the surface of the substrate W.
ここで、半導体の高集積化に伴う微細化や細線化により、配線プロセスでは低抵抗な膜が求められている。本実施形態に係る配線パターン形成システム１００によれば、パターンの撚れ、曲り、倒れを改善できるので、トレンチ２３に金属を埋め込んで配線パターンを形成する際、配線パターンのシーム、ボイド、カバレッジを向上させることができる。これにより、低抵抗の配線パターンとすることができる。 Here, a film having low resistance is required in the wiring process due to miniaturization and thinning of semiconductors due to high integration of semiconductors. According to the wiring pattern forming system 100 according to the present embodiment, twisting, bending, and tilting of the pattern can be improved. Therefore, when a metal is embedded in the trench 23 to form a wiring pattern, seams, voids, and coverage of the wiring pattern can be obtained. Can be improved. As a result, a wiring pattern with low resistance can be obtained.
また、基板Ｗに高温でのアニール処理を施して膜の応力を緩和させることにより、ビットラインの撚れ、曲り、倒れを改善する手法が考えられる。しかしながら、この手法では、膜の材質や電気特性の観点より高温での熱処理を施せない場合がある。これに対し、本実施形態では、レーザにより基板表面の所望の位置に選択的に照射することができる。これにより、表面の膜を加熱して膜の応力を緩和するとともに、下層の構造に与える熱の影響を抑制することができる。 Further, a method of improving twisting, bending, and tilting of the bit line by subjecting the substrate W to an annealing treatment at a high temperature to relieve the stress of the film can be considered. However, in this method, heat treatment at a high temperature may not be possible from the viewpoint of the material of the film and the electrical characteristics. On the other hand, in the present embodiment, the laser can selectively irradiate a desired position on the surface of the substrate. As a result, the surface film can be heated to relieve the stress of the film, and the influence of heat on the structure of the lower layer can be suppressed.
また、本実施形態係る配線パターン形成システム１００によれば、レーザの照射位置を自在に制御することができる。これにより、基板Ｗ全体にレーザを照射するだけでなく、基板Ｗの所定の位置を局所的にレーザを照射することができる。これにより、局所的にレーザを照射して膜質を改善することができる。 Further, according to the wiring pattern forming system 100 according to the present embodiment, the laser irradiation position can be freely controlled. As a result, not only the entire substrate W can be irradiated with the laser, but also the laser can be locally irradiated at a predetermined position on the substrate W. As a result, the film quality can be improved by locally irradiating the laser.
なお、レーザを照射する絶縁膜は、ＳｉＮ膜である場合を例に説明したが、これに限られるものではなく、ＳｉＯ２膜であってもよい。 The case where the insulating film that irradiates the laser is a SiN film has been described as an example, but the present invention is not limited to this, and a SiO 2 film may be used.
なお、レーザを照射する膜がＳｉＮ膜の場合、基板Ｗを窒素含有ガス雰囲気としてもよい。例えば、ガス供給装置からチャンバ内にＮ２ガス、ＮＨ３ガスを供給してもよい。これにより、高温での熱処理を行うことなく、低温での窒化処理を実現することが可能となる。 When the film to be irradiated with the laser is a SiN film, the substrate W may have a nitrogen-containing gas atmosphere. For example, N 2 gas and NH 3 gas may be supplied into the chamber from the gas supply device. This makes it possible to realize nitriding treatment at low temperature without performing heat treatment at high temperature.
また、レーザを照射する膜が、ＳｉＯ２膜の場合、基板Ｗを酸素含有ガス雰囲気としてもよい。例えば、ガス供給装置からチャンバ内にＯ２ガスを供給してもよい。これにより、高温での熱処理を行うことなく、低温での酸化処理を実現することが可能となる。 Further, when the film to be irradiated with the laser is a SiO 2 film, the substrate W may be an oxygen-containing gas atmosphere. For example, O 2 gas may be supplied into the chamber from the gas supply device. This makes it possible to realize an oxidation treatment at a low temperature without performing a heat treatment at a high temperature.
以上、配線パターン形成システム１００の実施形態等について説明したが、本開示は上記実施形態等に限定されるものではなく、特許請求の範囲に記載された本開示の要旨の範囲内において、種々の変形、改良が可能である。 Although the embodiment of the wiring pattern forming system 100 has been described above, the present disclosure is not limited to the above-described embodiment and the like, and various types are within the scope of the gist of the present disclosure described in the claims. It can be transformed and improved.
パターン形成装置１０１と改質装置１０２とは、別個に設ける場合を例に説明したが、パターン形成装置１０１に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、1つの装置内でパターン形成（ステップＳ１）及び表面改質（ステップＳ３）を同一チャンバプロセスで行ってもよい。また、成膜装置１０３に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、1つの装置内で表面改質（ステップＳ３）と配線パターン形成（ステップＳ４）を同一チャンバプロセスで行ってもよい。 Although the case where the pattern forming device 101 and the reforming device 102 are provided separately has been described as an example, the pattern forming device 101 is equipped with the laser irradiation device 12 and the scanning mechanism 13 of the reforming device 102, and is contained in one device. Pattern formation (step S1) and surface modification (step S3) may be performed in the same chamber process. Further, the film forming apparatus 103 is equipped with the laser irradiation apparatus 12 and the scanning mechanism 13 of the reforming apparatus 102, and the surface modification (step S3) and the wiring pattern formation (step S4) are performed in the same chamber process in one apparatus. You may go.
また、配線パターン形成システム１００は、真空搬送室を介して基板Ｗを搬送し、真空を破らずにパターン形成（ステップＳ１）、表面改質（ステップＳ３）、配線パターン形成（ステップＳ４）を行うInsituシステムとしてもよい。また、大気搬送室を介して基板Ｗを搬送するExsituシステムとしてもよい。 Further, the wiring pattern forming system 100 conveys the substrate W through the vacuum transfer chamber, and performs pattern formation (step S1), surface modification (step S3), and wiring pattern formation (step S4) without breaking the vacuum. It may be an Insitu system. Further, it may be an Exsitu system in which the substrate W is transported via the atmospheric transport chamber.
１１ ステージ
１２ レーザ照射装置
１３ 走査機構
２０ Ｓｉ基板
２１ ＳｉＮ膜（表面の膜）
２２ ａ−Ｓｉ膜（表面の膜）
２３ トレンチ
１００ 配線パターン形成システム
１０１ パターン形成装置
１０２ 改質装置（基板処理装置）
１０３ 成膜装置（金属成膜装置）
１０４，１０５ 搬送装置
１０６ 制御装置
Ｗ 基板
11 Stage 12 Laser irradiation device 13 Scanning mechanism 20 Si substrate 21 SiN film (surface film)
22 a-Si film (surface film)
23 Trench 100 Wiring pattern forming system 101 Pattern forming device 102 Reformer (board processing device)
103 Film deposition equipment (metal film deposition equipment)
104, 105 Transport device 106 Control device W board
Claims (15)
前記基板の表面にレーザを照射して、前記パターンを改質する工程と、を有する、
基板処理方法。 The process of preparing a substrate with a pattern formed on the surface film and
It comprises a step of irradiating the surface of the substrate with a laser to modify the pattern.
Substrate processing method.
前記表面の膜の応力による変形を改善する、
請求項１に記載の基板処理方法。 The step of modifying the pattern is
To improve the deformation of the surface film due to stress,
The substrate processing method according to claim 1.
エキシマレーザ（ＫｒＦ）２４８ｎｍ，光学パルスストレッチャ（ＯＰＳ）７ｍ，照射フルエンス２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎである、
請求項１または請求項２に記載の基板処理方法。 The laser
Excimer laser (KrF) 248 nm, optical pulse stretcher (OPS) 7 m, irradiation fluence 200 mJ / cm 2 , 20 shot / location,
The substrate processing method according to claim 1 or 2.
エッチングプロセスにより、前記基板の前記表面の膜に前記パターンを形成する工程を更に有する、
請求項１乃至請求項３のいずれか１項に記載の基板処理方法。 Before the process of preparing the substrate,
It further comprises a step of forming the pattern on the surface film of the substrate by an etching process.
The substrate processing method according to any one of claims 1 to 3.
請求項４に記載の基板処理方法。 The step of forming the pattern and the step of modifying the pattern are performed in the same apparatus.
The substrate processing method according to claim 4.
該パターン内に金属を成膜して配線パターンを形成する工程を更に有する、
請求項１乃至請求項５のいずれか１項に記載の基板処理方法。 After the step of modifying the pattern,
Further comprising a step of forming a metal film in the pattern to form a wiring pattern.
The substrate processing method according to any one of claims 1 to 5.
該パターン内に金属を成膜して配線パターンを形成する工程を更に有し、
前記パターンを形成する工程、前記パターンを改質する工程、及び、前記配線パターンを形成する工程は、真空を破らずに行う、
請求項４または請求項５に記載の基板処理方法。 After the step of modifying the pattern,
Further, it has a step of forming a metal film in the pattern to form a wiring pattern.
The step of forming the pattern, the step of modifying the pattern, and the step of forming the wiring pattern are performed without breaking the vacuum.
The substrate processing method according to claim 4 or 5.
請求項６または請求項７に記載の基板処理方法。 The wiring pattern is one of tungsten, ruthenium, and cobalt.
The substrate processing method according to claim 6 or 7.
請求項１乃至請求項８のいずれか１項に記載の基板処理方法。 The surface film on which the pattern is formed is an insulating film.
The substrate processing method according to any one of claims 1 to 8.
請求項９に記載の基板処理方法。 The insulating film is a SiN film or a SiO 2 film.
The substrate processing method according to claim 9.
前記載置台に載置された前記基板にレーザを照射するレーザ照射装置と、
制御装置と、を備え、
前記制御装置は、
表面の膜にパターンが形成された前記基板を準備する工程と、
前記基板の表面にレーザを照射して、前記パターンを改質する工程と、を行う、
基板処理装置。 A mounting table on which the board is mounted and
A laser irradiation device that irradiates the substrate mounted on the above-mentioned stand with a laser,
Equipped with a control device,
The control device is
The process of preparing the substrate having a pattern formed on the surface film and
A step of irradiating the surface of the substrate with a laser to modify the pattern is performed.
Board processing equipment.
前記表面の膜の応力による変形を改善する、
請求項１１に記載の基板処理装置。 The step of modifying the pattern is
To improve the deformation of the surface film due to stress,
The substrate processing apparatus according to claim 11.
エキシマレーザ（ＫｒＦ）２４８ｎｍ，光学パルスストレッチャ（ＯＰＳ）７ｍ，照射フルエンス２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎである、
請求項１１または請求項１２に記載の基板処理装置。 The laser irradiation device is
Excimer laser (KrF) 248 nm, optical pulse stretcher (OPS) 7 m, irradiation fluence 200 mJ / cm 2 , 20 shot / location,
The substrate processing apparatus according to claim 11 or 12.
前記パターンが形成された前記基板にレーザを照射し前記表面の膜を改質する改質装置と、
改質された前記基板に金属を成膜し配線パターンを形成する金属成膜装置と、を備える、配線パターン形成システム。 A pattern forming device that forms a pattern on the film on the surface of the substrate,
A reformer that irradiates the substrate on which the pattern is formed with a laser to modify the film on the surface.
A wiring pattern forming system comprising a metal film forming apparatus for forming a metal film on the modified substrate to form a wiring pattern.
ＫｒＦエキシマレーザを有する、
請求項１４に記載の配線パターン形成システム。 The reformer
Has a KrF excimer laser,
The wiring pattern forming system according to claim 14.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019136393A JP2021022598A (en) | 2019-07-24 | 2019-07-24 | Board processing method, board processing device, and wiring pattern formation system |
| PCT/JP2020/027944 WO2021015142A1 (en) | 2019-07-24 | 2020-07-17 | Substrate processing method, substrate processing device, and wiring pattern forming system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019136393A JP2021022598A (en) | 2019-07-24 | 2019-07-24 | Board processing method, board processing device, and wiring pattern formation system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2021022598A true JP2021022598A (en) | 2021-02-18 |
Family
ID=74193679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019136393A Pending JP2021022598A (en) | 2019-07-24 | 2019-07-24 | Board processing method, board processing device, and wiring pattern formation system |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2021022598A (en) |
| WO (1) | WO2021015142A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208775A (en) * | 1999-01-18 | 2000-07-28 | Furontekku:Kk | Semiconductor device and its manufacture |
| JP5629098B2 (en) * | 2010-01-20 | 2014-11-19 | 東京エレクトロン株式会社 | Pattern repair method on silicon substrate |
| JP2014060184A (en) * | 2012-09-14 | 2014-04-03 | V Technology Co Ltd | Method of forming low temperature polysilicon film and method of manufacturing thin film transistor |
| JP6466315B2 (en) * | 2015-12-25 | 2019-02-06 | 東京エレクトロン株式会社 | Substrate processing method and substrate processing system |
| JP6875811B2 (en) * | 2016-09-16 | 2021-05-26 | 株式会社Ｓｃｒｅｅｎホールディングス | Pattern collapse recovery method, board processing method and board processing equipment |
| CN111279454A (en) * | 2017-10-23 | 2020-06-12 | 朗姆研究公司 | System and method for preventing stiction of high aspect ratio structures and/or repairing high aspect ratio structures |
-
2019
- 2019-07-24 JP JP2019136393A patent/JP2021022598A/en active Pending
-
2020
- 2020-07-17 WO PCT/JP2020/027944 patent/WO2021015142A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021015142A1 (en) | 2021-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8202805B2 (en) | Substrate processing method | |
| KR100382725B1 (en) | Method of manufacturing semiconductor device in the clustered plasma apparatus | |
| US6960515B2 (en) | Method of forming a metal gate | |
| US20050136610A1 (en) | Process for forming oxide film, apparatus for forming oxide film and material for electronic device | |
| JP2014165494A (en) | Oxygen monolayer on semiconductor | |
| JP2015515641A (en) | Atomic layer deposition lithography | |
| JP4624207B2 (en) | Film forming method and film forming apparatus | |
| TW202040799A (en) | Memory cell fabrication for 3d nand applications | |
| JP6601257B2 (en) | Substrate processing method | |
| JP2008135632A (en) | Method and system for manufacturing capacitor electrode, and recording medium | |
| JP2007503009A (en) | Method for processing thin layers with high resolution using electron beams | |
| US7556970B2 (en) | Method of repairing damaged film having low dielectric constant, semiconductor device fabricating system and storage medium | |
| US11658043B2 (en) | Selective anisotropic metal etch | |
| WO2021015142A1 (en) | Substrate processing method, substrate processing device, and wiring pattern forming system | |
| US10818512B2 (en) | Photo-assisted chemical vapor etch for selective removal of ruthenium | |
| JP2020047617A (en) | Substrate processing device, method of manufacturing semiconductor device, and processed substrate | |
| KR20220150965A (en) | Substrate processing method and substrate processing apparatus | |
| TWI750364B (en) | Method for forming titanium silicide region | |
| WO2021015019A1 (en) | Capacitor-forming system and capacitor-forming method | |
| JP2005330546A (en) | Treatment method for metal film and treatment device for metal film | |
| US11139205B2 (en) | Self-aligned subtractive interconnect patterning | |
| KR102490920B1 (en) | Silicon film forming method and substrate processing apparatus | |
| JP4540368B2 (en) | Manufacturing method of semiconductor device | |
| WO2022209982A1 (en) | Method for forming ruthenium film and processing apparatus | |
| JP7368545B2 (en) | Substrate processing apparatus and method |