JP2021018740A - Control system and inter-cpu mutual monitoring method - Google Patents

Abstract

To provide a control system and an inter-CPU mutual monitoring method capable of improving user convenience.SOLUTION: In an inter-CPU mutual monitoring method in a control system 100 including: CPUs including a main CPU 110, a first sub-CPU 120, and a second sub-CPU 130; and a GPIO 140 which has a plurality of terminals operations of which are controlled by the respective CPUs, upon the occurrence of abnormality in the operation of any of the CPUs, the normal CPU other than the abnormal CPU detects the abnormal CPU, and based on resetting terminal information as information related to the terminal operation upon the occurrence of abnormality in the operation of the CPU, which is previously stored in the control system 100, and terminal information stored by the abnormal CPU, the normal CPU controls the terminal information for controlling the terminal operation related to the abnormal CPU in a terminal device.SELECTED DRAWING: Figure 1

Description

The present invention relates to a control system having a plurality of CPUs and a method for monitoring between CPUs in this control system.

Conventionally, in a control system equipped with a plurality of CPUs, when a problem such as a failure in executing a task of any CPU occurs, the remaining CPUs supplement the CPU in which the failure occurs. ing. For example, in a control system having a main CPU and a spare CPU, the spare CPU monitors the processing status of tasks of the main CPU and stores the processing status. Then, when a failure occurs in the main CPU and the operation of the main CPU becomes impossible and a failure occurs in the execution of the task, the spare CPU performs this task from the beginning based on the stored processing status. It was supposed to be done.

However, in such a control system, execution can be performed only for each task. Therefore, if a failure occurs in the execution of a task composed of a series of processes, even if a failure occurs in the middle of the task, the beginning of the task There was a problem that it was inefficient because it was executed from the process of.

As a method for solving this problem, for example, in Patent Document 1, if each process is not completed within the time required for each process of a series of tasks stored in advance in the control system, after this process. A mutual monitoring method between CPUs, in which a spare CPU performs processing, is disclosed.

Japanese Unexamined Patent Publication No. 7-64930

Here, in a task executed by a control system having a plurality of CPUs, a plurality of tasks are often complicatedly associated with each other. Therefore, if only one task is restarted, a waiting time will be generated for the other task, which causes a problem that the other task will be affected. It is difficult to solve such a problem by the mutual monitoring method between CPUs described in Patent Document 1.

For example, when a compound machine having functions such as a copier, a facsimile machine, and a printer is controlled by a control system equipped with a plurality of CPUs, there are tasks such as fixing temperature control, motor control, and paper transport control. Fixing temperature control, motor control, paper transport control, etc. are related to each other, and if one of the controls fails, simply re-executing only the task that caused the failure is enough to re-execute the entire multifunction machine. There is a problem that the operating condition of the machine is not improved.

In particular, if the cause of the task delay is a CPU malfunction, there is a possibility that other tasks that are not surfaced are also malfunctioning, and while the delayed task is being executed again, other tasks may be malfunctioning. There is also a problem that the malfunctioning state of the task will continue and the control of the entire control system may become unstable.

As described above, in a control system provided with a plurality of CPUs, when a problem occurs in any of the CPUs, various methods have been proposed in which the operation of the CPU in which the problem occurs is complemented by the other CPU. The above-mentioned problems have not been improved, and a more convenient control system and a mutual monitoring method between CPUs are desired.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a control system and a mutual monitoring method between CPUs that can improve the convenience of the user.

The inter-CPU mutual monitoring method according to one aspect of the present invention is a terminal having a plurality of terminals that input and output signals between a plurality of CPUs and the outside and whose operation is controlled by each of the plurality of CPUs. A mutual monitoring method between CPUs in a control system including a device, and when the operation of any of the CPUs becomes abnormal, a normal CPU other than the abnormal CPU detects the abnormal CPU. Then, the normal CPU is stored in advance in the control system, and the reset terminal information which is information on the operation of the terminal when an abnormal CPU occurs and the terminal stored by the abnormal CPU It is characterized in that the operation of the terminal with respect to the abnormal CPU in the terminal device is controlled based on the information.

As a result, when a CPU with abnormal operation occurs, a normal CPU other than this CPU controls the terminal controlled by the abnormal CPU instead. As a result, the load that was controlled before the abnormal operation of the CPU becomes abnormal will be continuously controlled by the normal CPU instead, so that the control of the entire control system can be suppressed from being delayed. it can. Further, by controlling the terminals instead, the load controlled by the abnormal CPU is switched to the control of the normal CPU, so that the switching can be easily performed. In addition, the time for switching the CPU can be shortened. Therefore, even if a problem such as an abnormality occurs in any of the CPUs, the control problem in the control system can be quickly resolved, so that the convenience of the user can be improved.

Further, in the above-mentioned mutual monitoring method between CPUs, each of the plurality of CPUs can request the other CPUs to restart, and the normal CPU operates the terminals related to the abnormal CPU. When the control is started, the normal CPU may request the abnormal CPU to restart.

As a result, the load that was controlled when the abnormal CPU is normal is restarted after the normal CPU starts to control, so that the control system can be used while the abnormal CPU is restarting. Since the control is not delayed and the control system can continue the control, the convenience of the user can be improved.

Further, in the above-mentioned mutual monitoring method between CPUs, after the restart request, the normal CPU may continue to control the operation of the terminal related to the abnormal CPU until the abnormal CPU is restarted. ..

As a result, the normal CPU can control the load that should be controlled by the abnormal CPU until it becomes normal by restarting the abnormal CPU, so that the control of the control system is not delayed and the abnormal CPU Can be returned to the normal state. Therefore, even if a problem such as an abnormality occurs in any of the CPUs, the control problem in the control system can be quickly resolved, so that the convenience of the user can be improved.

Further, in the above-mentioned mutual monitoring method between CPUs, the terminal device may store the terminals controlled for each CPU when all the CPUs are operating normally.

As a result, the terminals can be easily switched from the abnormal CPU to the normal CPU, and the time required for switching these CPUs can be shortened. Therefore, even if a problem such as an abnormality occurs in any of the CPUs, the control problem in the control system can be quickly resolved, so that the convenience of the user can be improved.

Further, the control system according to one aspect of the present invention is a control system including a plurality of CPUs, which inputs and outputs signals to and from the outside, and the operation is controlled by each of the plurality of CPUs. A terminal device having a plurality of terminals, and a reset terminal information storage unit that stores in advance reset terminal information that is information on the operation of each of the terminals when any of the plurality of CPUs becomes abnormal. Each of the CPUs has a terminal information control unit that controls the operation of each terminal, a CPU abnormality monitoring unit that monitors the life / death information of the other CPUs, and all of the plurality of CPUs operate normally. It has a terminal information storage unit that stores terminal information that is information about the terminal to be controlled in the case of the above, and a terminal information comparison unit that compares the terminal information with the reset terminal information. When the CPU abnormality monitoring unit in the CPU detects the CPU whose operation is abnormal based on the life / death information of the other CPU, the CPU that has detected the abnormal CPU is the terminal information comparison unit. Based on the comparison result, the terminal information control unit controls the operation of the terminal with respect to the abnormal CPU in the terminal device.

As a result, in a control system including a plurality of CPUs, even if a CPU having an abnormal operation occurs, the normal CPU will instead control the terminals controlled by the abnormal CPU. As a result, the load that was controlled before the abnormal operation of the CPU becomes abnormal will be continuously controlled by the normal CPU instead, so that the control of the entire control system will not be delayed. Further, by controlling the terminals instead, the load controlled by the abnormal CPU is switched so that the normal CPU controls the load, so that the configuration is not complicated and the switching can be performed with a simple configuration. In addition, the time for switching the CPU can be shortened. Therefore, even if a problem such as an abnormality occurs in any of the CPUs, the control problem in the control system can be quickly resolved, so that the convenience of the user can be improved.

According to the present invention, it is possible to provide a control system and a mutual monitoring method between CPUs that can improve the convenience of the user.

It is a block diagram which shows schematic structure of the control system which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the terminal state in GPIO provided in the control system which concerns on 1st Embodiment of this invention. It is a block diagram which shows schematic the functional configuration of the CPU provided in the control system which concerns on 1st Embodiment of this invention. It is a flowchart which shows an example of the control operation of the control system which concerns on 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the control system which concerns on 2nd Embodiment of this invention. It is a block diagram which shows schematic the functional configuration of the CPU provided in the control system which concerns on 2nd Embodiment of this invention. It is a flowchart which shows an example of the control operation of the control system which concerns on 2nd Embodiment of this invention.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

(First Embodiment)
FIG. 1 is a block diagram schematically showing the configuration of the control system 100 according to the first embodiment of the present invention. Further, FIG. 2 is a diagram showing an example of a terminal state in GPIO 140, which is a terminal device included in the control system 100 according to the first embodiment of the present invention. Further, FIG. 3 is a block diagram schematically showing a functional configuration of a main CPU 110 (first sub CPU 120, second sub CPU 130) included in the control system 100 according to the first embodiment of the present invention.

As shown in FIG. 1, the control system 100 includes a main CPU 110, a first sub CPU 120, a second sub CPU 130, a GPIO (General-purpose input / output) 140, and a reset terminal information storage unit 150, which are a plurality of CPUs. A user operation detection unit 160 and a data transmission / reception unit 170 are provided. The control system 100 is, for example, an SOC (System on a Chip).

The control system 100 controls the operation of the device. The control system 100 controls a controlled device 201 such as a multifunction device (MFP (Multi-function Peripherals)) having functions such as a copier, a facsimile machine, and a printer. The device controlled by the control system 100 may be a device other than the MFP, and is not particularly limited. Further, in FIG. 1, the control system 100 is shown to be provided outside the controlled device 201, but the control system 100 may be mounted inside the controlled device 201.

The main CPU 110, the first sub CPU 120, and the second sub CPU 130 are all CPUs (Central Processing Units). The main CPU 110, the first sub CPU 120, and the second sub CPU 130 realize a plurality of functions as described later by executing a predetermined program (see FIG. 3), and load in each operation of the controlled device 201. To control.

The main CPU 110, the first sub CPU 120, and the second sub CPU 130 control different loads, but if any of the CPUs becomes abnormal and becomes inoperable, the remaining CPUs do not operate. It controls the load that was controlled by the enabled CPU. That is, the main CPU 110, the first sub CPU 120, and the second sub CPU 130 usually control the load determined independently of each other, but if a problem occurs in any of the CPUs, the CPU of that CPU You will be able to do it instead. As a result, even if a problem occurs in one CPU, the operation of the control system 100 does not stop for a long time, and the CPUs efficiently complement each other. Therefore, it is possible to prevent a malfunction from occurring in the operation of the controlled device 201 controlled by the control system 100.

The GPIO140 has a plurality of terminals, and the operation of these terminals is not fixed and can be controlled. Specifically, each terminal in the GPIO 140 can be used as both an input and an output, and the functions of these terminals can be changed. Therefore, the terminal can be changed to either an input or an output, and the operation of the terminal can also be changed. Further, the terminals in the GPIO 140 are controlled by the main CPU 110, the first sub CPU 120, and the second sub CPU 130. Specifically, the terminals used by each of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 to control the load of the controlled device 201 are the terminals of the main CPU 110, the first sub CPU 120, and the second sub CPU 130. Each is in control.

The GPIO 140 has a first block 142, a second block 143, and a third block 144 having a plurality of terminals, respectively. When the main CPU 110, the first sub CPU 120, and the second sub CPU 130 are operating normally, the first block 142 is provided with a terminal for inputting / outputting the signal of the main CPU 110, and the second block 143 is provided with a terminal. A terminal for inputting / outputting a signal of the first sub CPU 120 is provided, and a terminal for inputting / outputting a signal of the second sub CPU 130 is provided in the third block 144. Further, the main CPU 110 controls the terminals of the first block 142, the first sub CPU 120 controls the terminals of the second block 143, and the second sub CPU 130 controls the terminals of the third block 144.

Further, the GPIO 140 is connected to the controlled device 201 via the terminals of the first block 142, the second block 143, and the third block 144. As a result, the main CPU 110, the first sub CPU 120, and the second sub CPU 130 control each load of the controlled device 201 via the GPIO 140.

The GPIO register 141 is a storage circuit, and in order to control each load of the controlled device 201 by the main CPU 110, the first sub CPU 120, and the second sub CPU 130, the first block 142, the second block 143, and the third block 144 The input / output signals from the terminals at each are stored. For example, it is used for calculation and holding the execution state of the main CPU 110, the first sub CPU 120, and the second sub CPU 130.

The reset terminal information storage unit 150 is, for example, a storage device such as a ROM (Read Only Memory). The reset terminal information storage unit 150 is a terminal of each terminal of the first block 142, the second block 143, and the third block 144 when the operations of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 become abnormal. The reset terminal information, which is information, is stored in advance.

Here, the reset terminal information will be described. First, the terminal information is terminal setting information for controlling each load in the controlled device 201. Although details will be described later, each of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 stores terminal information when all of these CPUs are operating normally. Specifically, it stores the function of each terminal, that is, the type of signal input / output to each terminal.

Then, when the operations of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 become abnormal, the remaining normal CPU applies the load of the controlled device 201 controlled by the abnormal CPU. It will be controlled. That is, the normal CPU executes the control of the load controlled by the abnormal CPU in addition to the load controlled up to now.

Therefore, for example, when the main CPU 110 becomes abnormal and operation becomes impossible, the terminals of the first block 142 are controlled by the first sub CPU 120 and the second sub CPU 130, so that the first sub CPU 120 and the second sub The CPU 130 inputs / outputs a load and a signal controlled by the main CPU 110 at the normal time via the terminal of the first block 142, and the first sub CPU 120 and the second sub CPU 130 control this load. Similarly, when the first sub CPU 120 becomes abnormal and operation becomes impossible, the terminals of the second block 143 are controlled by the second sub CPU 130 and the main CPU 110, so that the first sub CPU 120 in the normal state is controlled. The load that has been applied is controlled by the second sub CPU 130 and the main CPU 110. Similarly, when the second sub CPU 130 becomes abnormal and operation becomes impossible, the terminals of the third block 144 are controlled by the main CPU 110 and the first sub CPU 120, so that the second sub CPU 130 in the normal state is used. The load controlled by the main CPU 110 and the first sub CPU 120 control the load. When one CPU becomes abnormal, it is complemented by the remaining two CPUs, but it may be complemented by any one of the remaining two CPUs. Further, when two CPUs become abnormal, the two CPUs may be complemented by the remaining one CPU.

As described above, when any of the CPUs becomes abnormal, each terminal of the GPIO 140 is controlled so as to be different from the case where all the CPUs are normal. The terminal information when any of the CPUs becomes abnormal in this way is the reset terminal information.

The terminals in the GPIO 140 will be described with reference to FIG. Note that FIG. 2 shows an example of the state of the terminal when the control system 100 is reset and the state of the terminal while the controlled device 201 is being controlled.

As shown in FIG. 2, the first sub CPU 120 is assigned 10 terminals from pins 1 to 10 in the second block 143. Further, the main CPU 110 is assigned 10 terminals from pins 11 to 20 in the first block 142. Further, the second sub CPU 130 is assigned 10 terminals from pins 21 to 30 in the third block 144. Then, signals are transmitted and received between the main CPU 110, the first sub CPU 120, the second sub CPU 130, and the controlled device 201 via each pin (terminal).

For example, the first pin is controlled by the first sub CPU 120 so as to function as a terminal for outputting the on / off of the drive signal of the motor in the printing process of the controlled device 201 from the control system 100. Further, the fifth pin is controlled by the first sub CPU 120 so as to function as a terminal for outputting the on / off of the drive signal of the heater of the controlled device 201 from the control system 100. Further, the ninth pin is controlled by the first sub CPU 120 so as to function as a terminal for inputting a signal from a sensor for detecting the presence or absence of paper in the paper feed cassette of the controlled device 201 to the control system 100.

Further, the 15th pin functions as a terminal for inputting a signal from the operation panel of the controlled device 201 to the control system 100, and the 16th pin outputs a signal from the control system 100 to the operation panel of the controlled device 201. It is controlled by the main CPU 110 so as to function as a terminal of.

Further, the 28th pin is controlled by the second sub CPU 130 so as to function as a terminal for outputting the on / off of the drive signal of the motor in the scanner processing of the controlled device 201 from the control system 100.

In FIG. 2, “H” indicates that the function is ON, and “L” indicates that the function is OFF. Further, "H / L" indicates that the function is turned on or the function is turned off.

The user operation detection unit 160 detects that the control system 100 has been operated by a user (user) from the outside. The control system 100 is configured by, for example, a touch panel type monitor, and is connected to a user I / F 202 capable of receiving input from the user and displaying information to the user. When the user operates the user I / F 202, the user operation detection unit 160 detects that the operation has been performed from the outside.

The data transmission / reception unit 170 communicates with the outside. The control system 100 is connected to a LAN via, for example, a network I / F 203, and communicates with an external communication device by a packet conforming to TCP / IP (Transmission Control Protocol / Internet Protocol). The data transmission / reception unit 170 can detect that the control system 100 has communicated with an external communication device.

Next, the configurations of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 will be described with reference to FIG. Since the main CPU 110, the first sub CPU 120, and the second sub CPU 130 have the same configuration, the configuration of the main CPU 110 will be mainly described with reference to FIG. 3, and the first sub CPU 120 and the second sub CPU 130 will be described. A detailed description of the configuration will be omitted.

The main CPU 110, the first sub CPU 120, and the second sub CPU 130 execute each function as shown below by executing a control program for each of them.

As shown in FIG. 3, the main CPU 110 (first sub CPU 120, second sub CPU 130) includes a terminal information storage unit 111 (121, 131), a terminal information control unit 112 (122, 132), and a CPU abnormality monitoring unit 113 ( It includes 123), a terminal information comparison unit 114 (124, 134), a restart transmission unit 115 (125, 135), and a restart reception unit 116 (126, 136).

Similarly, the first sub CPU 120 includes a terminal information storage unit 121, a terminal information control unit 122, a CPU abnormality monitoring unit 123, a terminal information comparison unit 124, a restart transmission unit 125, and a restart reception unit 126.

Similarly, the second sub CPU 130 includes a terminal information storage unit 131, a terminal information control unit 132, a CPU abnormality monitoring unit 133, a terminal information comparison unit 134, a restart transmission unit 135, and a restart reception unit 136. ..

The terminal information storage unit 111 stores terminal information regarding the main CPU 110 when all of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 in the control system 100 are operating normally. Specifically, the terminal information of the terminal of the first block 142 controlled by the main CPU 110 is stored.

The terminal information control unit 112 controls the terminals of the first block 142 based on the terminal information stored in the terminal information storage unit 111.

The CPU abnormality monitoring unit 113 detects life / death information from the first sub CPU 120 and the second sub CPU 130, which are CPUs other than the main CPU 110, and monitors whether or not the operation of these CPUs is abnormal. Here, the life / death information is information indicating whether or not the operation of each CPU is abnormal. Life-and-death information, which is information for determining whether or not the first sub-CPU 120 and the second sub-CPU 130 are abnormal, is emitted, and based on this life-and-death information, the first sub-CPU 120 and the second sub-CPU 130 are abnormal. Determine if it exists. For example, the main CPU 110, the first sub CPU 120, and the second sub CPU 130 may each generate a signal periodically, and the other CPU may read the signal. If this signal cannot be read, the CPU abnormality monitoring unit 113 determines that the operation of the CPU that should emit the signal that could not be read is abnormal. Further, the main CPU 110, the first sub CPU 120, and the second sub CPU 130 each have an abnormality detection register, and the abnormality detection register value may be updated. The main CPU 110, the first sub CPU 120, and the second sub CPU 130 each periodically read the abnormality detection register values of the other CPUs, and the CPU in which the abnormality detection register values are not updated continues. , It may be determined that the operation is abnormal.

When the CPU abnormality monitoring unit 113 identifies an abnormal CPU, the terminal information comparison unit 114 sets the reset terminal information stored in the reset terminal information storage unit 150 and the terminal information storage unit 111 of the abnormal CPU. The terminal information in the normal state stored in 121 and 131 is compared, and these differences are detected.

Then, the terminal information control unit 112 changes the control of the terminal based on the detected difference. As a result, each load of the controlled device 201 that was controlled by the abnormal CPU at the time of normal control is controlled by the normal CPU instead of the abnormal CPU. In addition, the abnormal CPU does not control any load of the controlled device 201. As a result, the control of the control system 100 is prevented from becoming unstable, and malfunctions in operation are suppressed. In addition, it is possible to prevent problems such as delay in the operation of the controlled device 201.

In the restart transmission unit 115, when the operation of the first sub CPU 120 or the second sub CPU 130, which is a CPU other than the main CPU 110, becomes abnormal, the terminal information control unit 112 sets the terminal information control unit 112 based on the comparison result of the terminal information comparison unit 114. After changing the control of the terminal, an instruction is sent to the abnormal CPU at a predetermined timing to execute a restart. For example, when the user operates the control system 100 or when the control system 100 communicates with the outside, an instruction is sent to the abnormal CPU to execute a restart. And it is sufficient.

The restart receiving unit 116 receives an instruction to execute a restart from the first sub CPU 120 or the second sub CPU 130 in a state where the operation of the main CPU 110 is abnormal. When the restart receiving unit 116 receives an instruction to execute the restart, the main CPU 110 executes the restart. As a result, the main CPU 110 returns and performs normal operation.

Next, the operation of the control system 100 will be described with reference to the drawings. FIG. 4 is a flowchart showing an example of the control operation of the control system 100 according to the first embodiment of the present invention.

The main CPU 110, the first sub CPU 120, and the second sub CPU 130 read each other's abnormality detection register values from other CPUs (step S11). It is determined whether or not the read abnormality detection register value has been updated (changed) from the previously read value (step S12). If the read abnormality detection register value is updated (step S12: Yes), step S11 is performed again. As a result, it is possible to periodically check whether or not the abnormality detection register value has been updated.

Further, when the read abnormality detection register value is not updated (step S12: No), it can be detected that the operation of the CPU whose read abnormality detection register value is not updated is abnormal. This abnormal CPU is stored and reads the currently set normal terminal information (step S13). For example, if the CPU abnormality monitoring unit 113 (133) of the main CPU 110 or the second sub CPU 130 detects that the operation of the first sub CPU 120 has become abnormal, it is stored in the terminal information storage unit 121 of the first sub CPU 120. The terminal information comparison unit 114 (134) of the main CPU 110 or the second sub CPU 130 reads the terminal information.

Further, the terminal information comparison unit 114 (134) reads the reset terminal information stored in the reset terminal information storage unit 150 (step S14).

The terminal information comparison unit 114 (134) compares the normal terminal information stored in the terminal information storage unit 121 of the first sub CPU 120 with the reset terminal information, and determines whether or not there is a difference between them. (Step S15). If it is determined that there is a difference (step S15: Yes), the terminal information control unit 112 of the main CPU 110 and the terminal information control unit 132 of the second sub CPU 130 set the reset terminal information (step S16). Specifically, the terminals that were normally controlled by the first sub CPU 120 are set to be controlled by the main CPU 110 and the second sub CPU 130. Then, each load of the controlled device 201 that was normally controlled by the first sub CPU 120 is controlled by the main CPU 110 and the second sub CPU 130.

Further, when it is not determined that the terminal information of the first sub CPU 120 and the reset terminal information are different from each other (step S15: No), and after step S16, from the detection result of the user operation detection unit 160. , It is determined whether or not the control system 100 has been operated by the user from the outside (step S17). If there is no operation (user operation) by the user (step S17: No), the data transmission / reception unit 170 determines whether or not the control system 100 communicates with the outside and receives the data (step S18). .. If the data is not received (step S18: No), the process returns to step S17 again.

When there is an operation by the user (step S17: Yes) and when data reception is performed (step S18: Yes), the restart transmission unit 115 (135) of the main CPU 110 or the second sub CPU 130 to the first sub A signal instructing the restart is transmitted to the CPU 120 (step S19).

Then, when the restart receiving unit 126 of the first sub CPU 120 receives a signal instructing the restart, the first sub CPU 120 restarts.

In this way, when the user operates the control system 100 and when the control system 100 communicates with the outside, the first sub CPU 120 immediately restarts. By recovering by restarting, the abnormality in the operation of the first sub CPU 120 is resolved. By returning the first sub CPU 120, it is possible to reduce the burden on the main CPU 110 and the second sub CPU 130, which have increased the burden by substituting for the first sub CPU 120.

In particular, when the load on the main CPU 110 and the second sub CPU 130 becomes large, such as when the user operates the control system 100 or when the control system 100 communicates with the outside, the first sub CPU 120 is used. By returning, it is possible to prevent the load on the main CPU 110 and the second sub CPU 130 from further increasing.

When the first sub CPU 120 is restarted and restored, the terminals are controlled by the original terminal information instead of the reset terminal information. That is, the main CPU 110 and the second sub CPU 130 may perform control based on the reset terminal information until the first sub CPU 120 restarts and returns.

The mutual monitoring method between CPUs in the control system 100 and the control system 100 according to the first embodiment of the present invention has been described above. As described above, according to the control system 100 according to the first embodiment, even if a CPU whose operation is abnormal occurs, the normal CPU instead controls the terminals controlled by the abnormal CPU. .. As a result, the load that was controlled before the abnormal operation of the CPU becomes abnormal will be continuously controlled by the normal CPU instead, so that the control of the entire control system will not be delayed. Further, by controlling the terminals instead, the load controlled by the abnormal CPU is switched so that the normal CPU controls the load, so that the configuration is not complicated and the switching can be performed with a simple configuration. In addition, the time for switching the CPU can be shortened. Therefore, even if a problem such as an abnormality of any CPU occurs, a control problem in the entire control system 100 is unlikely to occur, efficient control can be performed, and user convenience can be improved.

For example, when the controlled device 201 is an MFP, as described above, the first sub CPU 120 controls loads such as motor drive, heater drive, and paper detection in the paper feed cassette in the printing process, and the main CPU 110 Controls the load such as input / output of signals from the operation panel, the second sub CPU 130 controls the load such as driving the motor in the scanner processing, and a plurality of mutually related loads are controlled by different CPUs. .. In such a state, even if any CPU becomes abnormal, the control of the entire controlled device 201 is executed without delay. Therefore, the convenience of the user can be improved.

The control system 100 according to the first embodiment of the present invention is not limited to the above configuration. For example, the terminal information storage units 111, 121, and 131 each store the terminal information of the main CPU 110, the first sub CPU 120, and the second sub CPU 130 at normal times, and the reset terminal information storage unit 150 stores the terminal information. It may be assumed that the GPIO register 141 stores the reset terminal information. As a result, it is possible to more easily switch the terminals from the abnormal CPU to the normal CPU, and it is possible to shorten the time required for switching these CPUs.

(Second Embodiment)
The control system according to the second embodiment of the present invention has a timer in each CPU that measures a predetermined time after the reset terminal information is set after any CPU becomes abnormal. According to the control system according to the second embodiment of the present invention, this point is different from the control system 100 according to the first embodiment of the present invention, and other than that, it is the same as the control system 100 according to the first embodiment. .. Therefore, in the following description, the same members as those in the first embodiment are designated by the same reference numerals in the drawings, and the same contents as those in the first embodiment will be omitted.

FIG. 5 is a block diagram schematically showing the configuration of the control system 100a according to the second embodiment of the present invention. FIG. 6 is a block diagram schematically showing a functional configuration of a main CPU 110a (first sub CPU 120a, second sub CPU 130a) included in the control system 100a according to the second embodiment of the present invention.

As shown in FIG. 5, the control system 100a according to the second embodiment has the main CPU 110a and the first sub instead of the main CPU 110, the first sub CPU 120 and the second sub CPU 130 in the control system 100 according to the first embodiment. It includes a CPU 120a and a second sub CPU 130a. Note that these control the terminals of the first block 142, the second block 143, and the third block 144, similarly to the main CPU 110, the first sub CPU 120, and the second sub CPU 130.

As shown in FIG. 6, the main CPU 110a, the first sub CPU 120a, and the second sub CPU 130a include timers 117, 127, and 137, respectively, in addition to the configurations of the main CPU 110, the first sub CPU 120, and the second sub CPU 130. ..

The timers 117, 127, and 137 start timing when the CPU abnormality monitoring units 113, 123, and 133 detect that the operation of another CPU is abnormal. Then, if the abnormal CPU has not restarted after the lapse of a predetermined time, the restart transmission units 115, 125, 135 of the normal CPU transmit a signal instructing the abnormal CPU to restart. ..

According to such a control system 100a, for example, when the operation of the first sub CPU 120a becomes abnormal, the CPU abnormality monitoring unit 113 (133) of the main CPU 110a or the second sub CPU 130a causes an abnormality from the first sub CPU 120a. Based on the detection register value, it is detected that the first sub CPU 120a is abnormal, and the reset terminal information stored in the reset terminal information storage unit 150 and the terminal of the first sub CPU 120a which is an abnormal CPU. The difference is detected by comparing with the terminal information in the normal state stored in the information storage unit 121. Then, the terminal information control units 112 and 132 change the control of the terminals based on this difference.

As a result, instead of the abnormal first sub CPU 120a, the main CPU 110a and the second sub CPU 130a control each load of the controlled device 201 controlled by the first sub CPU 120a when it is normal. Further, when the main CPU 110a and the second sub CPU 130a control instead of the first sub CPU 120a, the timer 117 (137) starts timing. Then, when the user does not operate the control system 100a and the control system 100a does not communicate with the outside, and the timer 117 (137) clocks a predetermined time, the restart transmitter 115 (135) ) Instructs the first sub CPU 120a to execute the restart. When the restart receiving unit 126 of the first sub CPU 120a receives the signal instructing the restart, the first sub CPU 120a executes the restart.

As described above, in the control system 100a according to the second embodiment, when any CPU is abnormal, the user does not operate the control system 100a and the control system 100a does not communicate with the outside. However, since the abnormal CPU restarts after the lapse of a predetermined time, the state in which the abnormal CPU does not recover does not continue. As a result, even in a state where a normal CPU is not heavily burdened, the abnormal CPU is restarted and restored, so that stable control can be performed.

Next, the operation of the control system 100a will be described with reference to the drawings. FIG. 7 is a flowchart showing an example of the control operation of the control system 100a according to the second embodiment of the present invention.

Note that FIG. 7 is a flowchart in which step S20 is added to a flowchart showing an example of the control operation of the control system 100 according to the first embodiment shown in FIG. 4, and is the same as in FIG. 4 except for the added portion. Is omitted, and only the added part is explained.

As shown in FIG. 7, in step S18, when the data transmission / reception unit 170 determines whether or not the control system 100a communicates with the outside and receives the data, and the data is not received (step S18: No), it is determined whether the timer 117 (137), which has started timing from the time when the main CPU 110a and the second sub CPU 130a start controlling instead of the first sub CPU 120a, is timing a predetermined time (step S20). If the timer 117 has not timed the predetermined time (step S20: No), the process returns to step S17 again. Then, when the timer 117 (137) is timing the predetermined time (step S20: Yes), the restart transmission unit 115 of the main CPU 110a transmits a signal instructing the restart to the first sub CPU 120a (step). S19).

(Other embodiments)
As the timing for restarting the abnormal CPU, in addition to those shown in the first embodiment and the second embodiment, for example, the operating status of a normal CPU that controls the load instead of the abnormal CPU is measured. However, a restart instruction may be transmitted according to the load on the normal CPU.

The present invention is not limited to the embodiments described above, and can be implemented in various other forms. Therefore, such embodiments are merely exemplary in all respects and should not be construed in a limited way. The scope of the present invention is shown by the claims and is not bound by the text of the specification. Furthermore, all modifications and modifications that fall within the equivalent scope of the claims are within the scope of the present invention.

100, 100a Control system 110, 110a Main CPU
111, 121, 131 Terminal information storage units 112, 122, 132 Terminal information control units 113, 123, 133 CPU error monitoring units 114, 124, 134 Terminal information comparison units 115, 125, 135 Reboot transmission units 116, 126, 136 Reboot receiver 117, 127, 137 Timer 120, 120a 1st sub CPU
130, 130a 2nd sub CPU
140 GPIO
141 GPIO register 142 1st block 143 2nd block 144 3rd block 150 Reset terminal Information storage unit 160 User operation detection unit 170 Data transmission / reception unit 201 Controlled device 202 User I / F
203 Network I / F

Claims (5)

A mutual monitoring method between CPUs in a control system including a plurality of CPUs and a terminal device having a plurality of terminals whose operations are controlled by each of the plurality of CPUs by inputting / outputting signals to / from the outside. And
When the operation of any of the CPUs becomes abnormal, a normal CPU other than the abnormal CPU detects the abnormal CPU, and the abnormal CPU is detected.
The normal CPU is stored in the control system in advance in the reset terminal information which is information about the operation of the terminal when an abnormal CPU occurs and the terminal information stored in the abnormal CPU. Based on this, a method for mutual monitoring between CPUs, which controls the operation of the terminal with respect to the abnormal CPU in the terminal device. The method for mutual monitoring between CPUs according to claim 1.
Each of the plurality of CPUs can request the other CPUs to restart.
A method for mutual monitoring between CPUs, characterized in that when the normal CPU starts to control the operation of the terminal with respect to the abnormal CPU, the normal CPU requests the abnormal CPU to restart. The method for mutual monitoring between CPUs according to claim 2.
A method for mutual monitoring between CPUs, characterized in that, after the restart request, the normal CPU continues to control the operation of the terminal with respect to the abnormal CPU until the abnormal CPU is restarted. The method for mutual monitoring between CPUs according to any one of claims 1 to 3.
A method for mutual monitoring between CPUs, wherein the terminal device stores the terminals controlled for each CPU when all the CPUs are operating normally. A control system with multiple CPUs
A terminal device having a plurality of terminals that input and output signals to and from the outside and whose operations are controlled by each of the plurality of CPUs.
It is provided with a reset terminal information storage unit that stores in advance reset terminal information that is information on the operation of each of the terminals when any of the plurality of CPUs becomes abnormal.
Each CPU is
A terminal information control unit that controls the operation of each terminal,
Another CPU abnormality monitoring unit that monitors the life and death information of the CPU,
A terminal information storage unit that stores terminal information that is information about the terminal to be controlled when all of the plurality of CPUs are operating normally.
It has a terminal information comparison unit that compares the terminal information with the reset terminal information.
When the CPU abnormality monitoring unit in any of the CPUs detects the CPU whose operation is abnormal based on the life / death information of the other CPU, the CPU that has detected the abnormal CPU compares the terminal information. A control system characterized in that the terminal information control unit controls the operation of the terminal with respect to the abnormal CPU in the terminal device based on the comparison result of the units.

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