JP2021007176A - Solid-state image pickup device and electronic apparatus - Google Patents

Abstract

To easily provide a high-quality laminated image sensor.SOLUTION: A solid-state image pickup device is laminated with: a first semiconductor substrate including a first wiring layer, a photodiode, and at least a transfer transistor, a reset transistor, and an amplifier transistor; a second semiconductor substrate including a second wiring layer and a plurality of transistors; and a third semiconductor substrate including a third wiring layer. The first semiconductor substrate includes a first connection part connected to the first wiring layer. The second semiconductor substrate includes a second connection part extending in a lateral direction on the other side of a surface facing the second semiconductor substrate. The second connection part is connected to the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate. The plurality of transistors are arranged in a longitudinal direction between opposed surfaces of the second semiconductor substrate.SELECTED DRAWING: Figure 6

Description

The present technology relates to solid-state image sensors and electronic devices, and more particularly to solid-state image sensors and electronic devices that make it possible to easily provide high-quality stacked image sensors.

As a solid-state image sensor, an amplified solid-state image sensor represented by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state image sensor represented by a CCD (Charge Coupled Device) image sensor is known.

These solid-state image sensors are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state image sensors mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) because of their low power supply voltage and power consumption.

The MOS type solid-state image sensor is formed of a photodiode whose unit pixel is a photoelectric conversion unit and a plurality of pixel transistors, and a pixel array (pixel area) in which the plurality of unit pixels are arranged in a two-dimensional array and a periphery. It is configured to have a circuit area. The plurality of pixel transistors are formed of MOS transistors, and are composed of a transfer transistor, a reset transistor, three transistors of amplification and a transistor, or four transistors including a selection transistor.

Further, in the solid-state image sensor as described above, a laminated structure in which a plurality of semiconductor chips having different functions are stacked and electrically connected is also proposed.

In the laminated structure, each circuit can be optimally formed so as to correspond to the function of each semiconductor chip, so that it is possible to easily realize high functionality of the device.

For example, high functionality is achieved by optimally forming the sensor circuit and logic circuit so as to correspond to each function of the semiconductor chip including the sensor circuit and the semiconductor chip including the logic circuit provided with the circuit for processing the signal. A solid-state image sensor can be manufactured. At this time, by providing a through electrode on the substrate of the semiconductor chip, these plurality of semiconductor chips are electrically connected.

However, when a semiconductor device is configured by connecting different types of chips with a connecting conductor that penetrates the substrate, it is necessary to make a connection hole while ensuring insulation in a deep substrate, which is necessary for processing the connection hole and embedding the connection conductor. It was considered difficult to put it into practical use due to the cost economy of the manufacturing process.

On the other hand, in order to form a small contact hole of, for example, about 1 μm, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning the film and an increase in cost are caused. Moreover, in order to fill the connection holes with a high aspect ratio with the connection conductor, it is inevitably required to use a CVD film having good coating properties such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

Therefore, a method for manufacturing a semiconductor device such as a solid-state image sensor has been proposed in which the respective performances are fully exhibited to improve the performance, and the mass productivity and cost are reduced (see, for example, Patent Document 1). ..

Patent Document 1 proposes that a support substrate of a back surface type image sensor is laminated as a logic circuit, and a large number of connection contacts are provided from above by utilizing the thinning process of the image sensor to form a laminated structure.

However, in recent years, a three-layer laminated solid-state image sensor has also been proposed. When a laminated image sensor is configured as a three-layer laminated structure, the sensor having a light receiving portion needs to take in light, so it is arranged at the top, and two chips are laminated on the lower layer. Become. In this case, the lower two chips can be, for example, a logic or a memory chip.

Normally, when stacking circuits, it is desirable not to use a support substrate in order to thin the silicon substrate. In that case, in the generation of the circuit, first, the circuit surfaces of the two lower layers are faced to each other and bonded to each other, and the chip to be the second layer is thinned. After that, the uppermost sensor is laminated as a back surface type to further reduce the thickness.

JP-A-2010-245506

However, in this way, the following problems occur in the three-layer laminated structure.

That is, the pad opening to the pad metal becomes too deep than necessary. That is, in order to open to the AL layer of the second layer chip, the opening penetrates the sensor of the uppermost layer chip and further penetrates the silicon substrate of the second layer chip to reach the AL located at the bottom layer of the wiring layer. There must be.

In order to open a deep pad, in addition to thickening the resist film, curing the resist after dry etching becomes a problem.

For example, since an organic lens is already formed on the chip at the time of opening, the resist must be removed with a chemical solution, but the cured resist tends to remain as a residue, which hinders light incident on the lens.

In addition, depots generated by dry etching also become a problem. In particular, the depot that cannot be removed by adhering to the metal surface of the pad or the side wall of the pad opening absorbs humidity after the chip is completed to generate fluorine ions, which causes a defect of melting the metal of the pad (corrosion).

In this way, the increased pad depth makes the process difficult.

Further, if the hot carrier light emission generated from the second layer chip cannot be shielded by the wiring layout of the second layer chip, and the unnecessary wiring layer is reduced even in the sensor chip, a sufficient shading layout is provided. Cannot be configured.

The present technology is disclosed in view of such a situation, and makes it possible to easily provide a high-quality laminated image sensor.

A solid-state imaging device, which is one aspect of the present technology, includes a plurality of photodiodes, at least one of a transfer transistor, a reset transistor, and an amplifier transistor, and a first wiring layer including a first electrode. A second semiconductor substrate including a second semiconductor substrate, a second wiring layer including a second electrode, and a third wiring layer including a third electrode, and a fourth wiring layer including a fourth electrode. A third semiconductor substrate including the second semiconductor substrate is provided, and the second wiring layer and the third wiring layer are formed on opposite surface sides of the second semiconductor substrate, respectively, and the first wiring layer and the first wiring layer are formed. The first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are laminated so that the second wiring layer, the third wiring layer, and the fourth wiring layer face each other. The first semiconductor substrate and the second semiconductor substrate are electrically connected by directly joining the first electrode and the second electrode, and the second semiconductor substrate and the third semiconductor are connected to each other. The substrate is a solid-state imaging device that is electrically connected by directly joining the third electrode and the fourth electrode.

An electronic device, which is one aspect of the present technology, includes an optical unit including at least one lens that receives incident light, and a solid-state imaging device that receives the incident light. The solid-state imaging device includes a plurality of photodiodes. , A first semiconductor substrate including at least one of a transfer transistor, a reset transistor, and an amplifier transistor, a first wiring layer including a first electrode, and a second wiring layer including a second electrode. A second semiconductor substrate including a third wiring layer including a third electrode, a third semiconductor substrate including a fourth wiring layer including a fourth electrode, and the second wiring layer. The third wiring layer is formed on the opposite surface side of the second semiconductor substrate, respectively, and the first wiring layer and the second wiring layer, the third wiring layer and the fourth wiring are formed. The first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are laminated so that the layers face each other, and the first semiconductor substrate and the second semiconductor substrate are the first. The second electrode and the second electrode are directly bonded to each other to be electrically connected, and the second semiconductor substrate and the third semiconductor substrate are directly bonded to the third electrode and the fourth electrode. It is an electronic device that is electrically connected by being connected.

In a solid-state imaging device and an electronic device, which is one aspect of the present technology, a first wiring layer including a plurality of photodiodes, at least one of a transfer transistor, a reset transistor, and an amplifier transistor, and a first electrode. A first semiconductor substrate including the above, a second semiconductor substrate including a second wiring layer including a second electrode, and a third wiring layer including a third electrode, and a second semiconductor substrate including a fourth electrode. A third semiconductor substrate including the wiring layer 4 is provided. The second wiring layer and the third wiring layer are formed on the opposite surface sides of the second semiconductor substrate, respectively, and the first wiring layer and the second wiring layer, the third wiring layer and the fourth wiring are formed. The first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are laminated so that the layers face each other, and the first semiconductor substrate and the second semiconductor substrate are the first electrode and the second semiconductor substrate. The electrodes are directly bonded to each other to be electrically connected, and the second semiconductor substrate and the third semiconductor substrate are electrically connected to each other by directly bonding the third electrode to the fourth electrode. ..

According to this technique, it is possible to easily provide a high-quality laminated image sensor.

It is sectional drawing explaining the structure of the pixel part of the conventional laminated solid-state image sensor. It is sectional drawing explaining another structure of the pixel part of the conventional laminated solid-state image sensor. It is a figure explaining the manufacturing method of the three-layer laminated type solid-state image sensor. It is a figure explaining the manufacturing method of the three-layer laminated type solid-state image sensor. It is sectional drawing explaining the structure of the pixel part of the solid-state image sensor of the three-layer laminated structure manufactured by the prior art. It is sectional drawing explaining the structure which concerns on one Embodiment of the pixel part of the solid-state image pickup apparatus to which this technique is applied. It is a figure explaining the structure of the pad hole and the aluminum pad of FIG. It is sectional drawing explaining the structure which concerns on another Embodiment of the pixel part of the solid-state image pickup apparatus to which this technique is applied. It is sectional drawing explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image pickup apparatus to which this technique is applied. It is a figure which shows the schematic structure of the solid-state image sensor to which this technique is applied. FIG. 6 is a schematic cross-sectional view relating to the configuration of the pixel portion of the solid-state image sensor shown in FIG. It is a diagram which simplifies the cross-sectional view explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image sensor to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a diagram which simplifies the sectional view explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image sensor to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a diagram which simplifies the cross-sectional view explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image sensor to which this technique is applied. It is a diagram which simplifies the cross-sectional view explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image sensor to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. It is a diagram which simplifies the cross-sectional view explaining the structure which concerns on still another Embodiment of the pixel part of the solid-state image sensor to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. 35. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. 35. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. 35. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. 35. It is a figure explaining the manufacturing process of the solid-state image sensor shown in FIG. 35. It is a figure explaining the combination of configurations which can be adopted as the embodiment of the solid-state image pickup apparatus to which this technique is applied. It is a diagram which simplifies the cross-sectional view explaining the structure of the pixel part of the solid-state image sensor which applied this technique in the case of adopting a four-layer structure. It is a block diagram which shows the structural example of the electronic device to which this technology is applied.

Hereinafter, embodiments of the techniques disclosed herein will be described with reference to the drawings.

First, the problems of the prior art will be described.

As a solid-state image sensor, an amplified solid-state image sensor represented by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state image sensor represented by a CCD (Charge Coupled Device) image sensor is known.

These solid-state image sensors are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state image sensors mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) because of their low power supply voltage and power consumption.

The MOS type solid-state image sensor is formed of a photodiode whose unit pixel is a photoelectric conversion unit and a plurality of pixel transistors, and a pixel array (pixel area) in which the plurality of unit pixels are arranged in a two-dimensional array and a periphery. It is configured to have a circuit area. The plurality of pixel transistors are formed of MOS transistors, and are composed of a transfer transistor, a reset transistor, three transistors of amplification and a transistor, or four transistors including a selection transistor.

Further, in the solid-state image sensor as described above, a laminated structure in which a plurality of semiconductor chips having different functions are stacked and electrically connected is also proposed.

In the laminated structure, each circuit can be optimally formed so as to correspond to the function of each semiconductor chip, so that it is possible to easily realize high functionality of the device.

For example, high functionality is achieved by optimally forming the sensor circuit and logic circuit so as to correspond to each function of the semiconductor chip including the sensor circuit and the semiconductor chip including the logic circuit provided with the circuit for processing the signal. A solid-state image sensor can be manufactured. At this time, by providing a through electrode on the substrate of the semiconductor chip (semiconductor substrate), these plurality of semiconductor substrates are electrically connected.

FIG. 1 is a cross-sectional view illustrating the configuration of a pixel portion of a conventional laminated solid-state image sensor.

The solid-state image sensor according to the pixel portion is configured as a back-illuminated CMOS image sensor configured by laminating a first semiconductor substrate and a second semiconductor substrate. That is, the solid-state image sensor shown in FIG. 1 has a two-layer laminated structure.

As shown in FIG. 1, an image sensor, that is, a pixel array (hereinafter referred to as a pixel region) and a control region are formed in each region of the first semiconductor substrate 31.

That is, a photodiode (PD) 34 serving as a photoelectric conversion unit of each pixel is formed in each region of a semiconductor substrate (for example, a silicon substrate) 31, and a source / drain region of each pixel transistor is formed in the semiconductor well region.

A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and a pixel transistor Tr1 and a pixel transistor Tr2 are formed by a source / drain region paired with the gate electrode.

The pixel transistor Tr1 adjacent to the photodiode (PD) 34 corresponds to a transfer transistor, and its source / drain region corresponds to floating diffusion (FD).

Next, the first layer of the interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, and then a connection hole is formed in the interlayer insulating film 39 to form a connecting conductor to be connected to a required transistor.

Next, a plurality of layers (two layers in this example) of metal wiring are formed via the interlayer insulating film 39 so as to be connected to each connecting conductor to form the multilayer wiring layer 41. The metal wiring is formed of copper (Cu) wiring. Normally, each copper wiring (metal wiring) is covered with a barrier metal film that prevents Cu diffusion. Therefore, a protective film, which is a cap film for copper wiring, is formed on the multilayer wiring layer 41.

By the steps up to this point, the first semiconductor substrate 31 having the pixel region and the control region is formed.

On the other hand, in each region of the second semiconductor substrate 45, for example, a logic circuit including a signal processing circuit related to signal processing for controlling a pixel region and controlling communication with the outside is formed. That is, in the p-type semiconductor well region on the surface side of the semiconductor substrate (for example, a silicon substrate) 45, a plurality of MOS transistors Tr6, MOS transistors Tr7, and MOS transistors Tr8 that form a logic circuit so as to be separated by an element separation region are provided. Form.

Next, a first layer interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, and then a connection hole is formed in the interlayer insulating film 49 to form a connecting conductor 54 to be connected to a required transistor. ..

Next, a plurality of layers, in this example, four layers of metal wiring are formed via the interlayer insulating film 49 so as to be connected to each connecting conductor 54 to form a multilayer wiring layer 55.

The metal wiring is formed of copper (Cu) wiring. A protective film, which is a cap film for copper wiring (metal wiring), is formed on the multilayer wiring layer 55. However, the uppermost layer of the multilayer wiring layer 55 is formed of an aluminum pad serving as an electrode.

By the steps up to this point, a second semiconductor substrate 45 having a logic circuit is formed.

Then, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other on the joint surface 99 so that the multilayer wiring layer 41 and the multilayer wiring layer 55 face each other. The bonding includes, for example, plasma bonding and bonding with an adhesive.

Then, when the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31b side of the first semiconductor substrate 31, and the back surface of the first semiconductor substrate 31 is configured as a back-illuminated solid-state image sensor. , The light incident surface.

Penetration through the first semiconductor substrate 31 from the back surface side to reach the uppermost aluminum pad of the multilayer wiring layer 55 of the second semiconductor substrate 45 at a required position with respect to the thinned first semiconductor substrate 31. Form a connection hole. At the same time, a connection hole is formed in the first semiconductor substrate 31 in the vicinity of the through connection hole to reach the wiring of the first layer from the back surface side to the first semiconductor substrate 31 side.

Next, the through connection conductor 64 and the connection conductor 65 are embedded in the through connection hole. As the through-connecting conductor 64 and the connecting conductor 65, for example, a metal such as copper (Cu) or tungsten (W) can be used.

As described above, since a logic circuit for executing signal processing and the like is formed on the second semiconductor substrate 45, the electrodes of each transistor and the signal line are connected so that signals can be input and output. There is a need. That is, the logic circuit is adapted to operate with the input and output of signals from the outside. Therefore, the aluminum pad 53 of the second semiconductor substrate 45 serves as an electrode for external connection.

Therefore, a pad hole 81 penetrating the first semiconductor substrate 31 is formed so that the aluminum pad 53 of the second semiconductor substrate can be wire-bonded, and the aluminum pad 53 is exposed.

After that, an insulating protective film is formed on the entire back surface of the first semiconductor substrate 31, and a light-shielding film 67 is formed on the region to be light-shielded. As the light-shielding film 67, a metal film such as tungsten can be used.

After that, a flattening film is formed on the light-shielding film 67, and for example, red (R), green (G), and blue (B) on-chip color filters 74 are formed on the flattening film corresponding to each pixel. An on-chip microlens 75 is formed on the on-chip microlens 75.

Further, the aluminum pad 53, which is an electrode used for transmitting and receiving signals to and from an external device, circuit, etc., reaches the first semiconductor substrate 31 from the back surface side (light receiving surface side) of the first semiconductor substrate 31. The pad hole 81 is formed as described above.

This completes the process of the laminated semiconductor structure. That is, in the first semiconductor substrate 31, a pixel region and a control region are formed, and in the second semiconductor substrate 45, a logic circuit is formed.

Then, each chip is divided into chips for a back-illuminated solid-state image sensor.

Further, in a solid-state image sensor having a laminated structure, the influence of noise due to hot carriers must be taken into consideration. Hot carriers are high-speed electrons with high kinetic energy emitted from transistors, and light is generated when hot carriers collide with silicon atoms.

In the solid-state image sensor having a laminated structure, a transistor is also provided on a second semiconductor substrate other than the first semiconductor substrate on which the PD is formed. Therefore, the light generated by the hot carriers emitted from the transistors of the second semiconductor substrate may enter from the back side (opposite side of the light receiving surface) of the PD of the first semiconductor substrate and become noise.

For this reason, in the solid-state image sensor having a laminated structure, measures such as providing a light-shielding body have been taken in order to block light caused by hot carriers.

FIG. 2 is a cross-sectional view illustrating another configuration of a pixel portion of a conventional stacked solid-state image sensor.

In the example of FIG. 2, the light-shielding body 90 is formed under the PD 34 in the first semiconductor substrate 31. As a result, the light generated by the hot carriers emitted from the MOS transistor Tr6, MOS transistor Tr7, and MOS transistor Tr8 of the second semiconductor substrate 45 is blocked.

Alternatively, it is also possible to change the shape of the copper wiring in the multilayer wiring layer 55 so that the light caused by the hot carriers emitted from the MOS transistor Tr6, the MOS transistor Tr7, and the MOS transistor Tr8 is blocked. ..

As described above with reference to FIGS. 1 and 2, in the solid-state imaging device having a two-layer laminated structure, the pad holes 81 can be provided to enable electrical connection with the outside, and the light-shielding body 90 and the multilayer wiring layer can be provided. The shape of the copper wiring in 55 shielded the light caused by the hot carrier.

On the other hand, in recent years, a three-layer laminated solid-state image sensor has also been developed. The three-layer laminated solid-state imaging device includes, for example, a first semiconductor substrate in which a pixel region and a control region (hereinafter, also referred to as a sensor circuit) are formed, and a second semiconductor substrate in which a logic circuit is formed. It consists of a third semiconductor substrate on which a memory circuit is formed.

The three-layer laminated solid-state image sensor is manufactured, for example, as shown in FIGS. 3 and 4.

First, as shown in FIG. 3, the second semiconductor substrate 112 and the third semiconductor substrate 113 are bonded to each other with their circuit surfaces facing each other. In reality, the interlayer films of the two semiconductor substrates are bonded to each other. Then, the second semiconductor substrate 112 is thinned.

After that, as shown in FIG. 4, the first semiconductor substrate 111 is attached onto the thinned second semiconductor substrate 112 with the back surface facing up. In reality, the interlayer films of the two semiconductor substrates are bonded to each other. Then, the first semiconductor substrate 111 is thinned.

In this way, when the laminated image sensor is configured as a three-layer laminated structure, the sensor circuit having the light receiving portion needs to take in light, so it is arranged at the uppermost part, and two logic circuits are arranged in the lower layer. And memory circuits will be stacked.

Further, when laminating circuits, it is desired to avoid using a support substrate for thinning the silicon substrate. Therefore, in the generation of the circuit, the circuit surfaces of the two lower semiconductor substrates are first faced to each other and bonded to each other, and the semiconductor substrate (second semiconductor substrate 112) to be the second layer is thinned. After that, the uppermost semiconductor substrate (first semiconductor substrate 111) is bonded and laminated as a back surface type to further reduce the thickness.

However, in this way, the following problems occur in the three-layer laminated structure.

FIG. 5 is a cross-sectional view illustrating the configuration of the pixel portion of the solid-state image sensor having a three-layer laminated structure manufactured by the prior art.

The first problem in the conventional three-layer laminated structure is that the pad holes become too deep. In FIG. 5, a pad hole 121 deeper than the pad hole 81 of FIG. 1 is formed.

That is, in the case of a three-layer laminated structure, as described above with reference to FIGS. 3 and 4, the circuit surface of the second semiconductor substrate 112 is attached so as to face the circuit surface of the third semiconductor substrate. .. Therefore, the aluminum pad on the uppermost layer of the multilayer wiring layer of the second semiconductor substrate is far from the light receiving surface of the first semiconductor substrate 111, penetrates the first semiconductor substrate, and further substantially passes through the second semiconductor substrate. The aluminum pad 133 (electrode for external connection) of the second semiconductor substrate is not exposed unless it is opened until it penetrates.

In order to open the deep pad hole 121, it is necessary to thicken the resist. If the resist is thickened to open the deep pad holes 121, curing of the resist after dry etching becomes a problem.

For example, since an on-chip microlens using an organic material is already formed on the first semiconductor substrate at the time of opening, the resist must be removed with a chemical solution, but the cured resist tends to remain as a residue. Therefore, it hinders the light incident on the lens.

Further, when the deep pad hole 121 is opened, the depot generated by dry etching also becomes a problem.

In particular, the depot that cannot be removed by adhering to the surface of the aluminum pad 133 or the side wall of the pad hole 121 absorbs humidity after the three-layer laminated structure is completed to generate fluorine ions and melts the metal of the aluminum pad ( Corrosion) Causes defects.

As described above, in the conventional technique, the deep pad holes make the manufacturing process of the solid-state image sensor difficult.

The second problem in the three-layer laminated structure of the prior art is that it becomes difficult to block light due to hot carriers.

That is, in the case of a three-layer laminated structure, as described above with reference to FIGS. 3 and 4, the circuit surface of the second semiconductor substrate 112 is attached so as to face the circuit surface of the third semiconductor substrate. .. Therefore, the transistor of the second semiconductor substrate faces the first semiconductor substrate without going through the multilayer wiring layer. Therefore, as in the case of a two-layer laminated structure, for example, the copper wiring of the multilayer wiring layer of the second semiconductor substrate cannot block the light caused by hot carriers.

Therefore, in the present technology, it is not necessary to provide a deep pad hole, and light caused by hot carriers can be easily blocked.

FIG. 6 is a cross-sectional view illustrating a configuration according to an embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied. The solid-state imaging device related to the pixel portion is configured as a back-illuminated CMOS image sensor formed by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. That is, the solid-state image sensor according to the pixel portion shown in FIG. 6 has a three-layer laminated structure.

Further, this solid-state image sensor is composed of, for example, a first semiconductor substrate on which a sensor circuit is formed, a second semiconductor substrate on which a logic circuit is formed, and a third semiconductor substrate on which a memory circuit is formed. ing. The logic circuit and the memory circuit are designed to operate with input / output of signals to and from the outside.

As shown in FIG. 6, a photodiode (PD) 234 serving as a photoelectric conversion part of a pixel is formed on a semiconductor substrate (for example, a silicon substrate) 211, and a source / drain region of each pixel transistor is formed in the semiconductor well region. It is formed.

A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and a pixel transistor Tr1 and a pixel transistor Tr2 are formed by a source / drain region paired with the gate electrode.

The pixel transistor Tr1 adjacent to the photodiode (PD) 234 corresponds to the transfer transistor, and its source / drain region corresponds to floating diffusion (FD).

Further, an interlayer insulating film is formed on the first semiconductor substrate 211, a connection hole is formed in the interlayer insulating film, and a connection conductor 244 connected to the pixel transistor Tr1 and the pixel transistor Tr2 is formed.

Further, a plurality of layers of metal wiring 240 are formed so as to be connected to each connecting conductor 244, and a multilayer wiring layer 245 is formed. The copper wiring 240 (metal wiring) is formed of copper (Cu) wiring. Normally, each copper wiring is covered with a barrier metal film that prevents Cu diffusion. Therefore, a protective film, which is a cap film for copper wiring, is formed on the multilayer wiring layer 245.

Further, an aluminum pad 280 serving as an electrode for external connection is formed on the lowermost layer of the multilayer wiring layer 245 of the first semiconductor substrate 211. That is, the aluminum pad 280 is formed at a position closer to the adhesive surface 291 with the second semiconductor substrate 212 than the copper wiring 240. The electrode for external connection is used as one end of wiring related to input / output of a signal to the outside. Although the electrode is described here as being made of aluminum, the electrode may be made of another metal.

Further, the first semiconductor substrate 211 is formed with a contact 265 used for electrical connection with the second semiconductor substrate 212. The contact 265 is connected to the contact 311 of the second semiconductor substrate 212, which will be described later, and is also connected to the aluminum pad 280a of the first semiconductor substrate 211.

The pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

FIG. 7 is a diagram illustrating the configuration of the pad hole 351 and the aluminum pad 280a. FIG. 7A is an enlarged view of the vicinity of the pad hole 351 and FIG. 7B is a view of the aluminum pad 280a viewed from above the pad hole 351.

As shown in FIG. 7B, a large number of contacts 265 are connected side by side to the end of the aluminum pad 280a, so that the connection resistance can be reduced.

Returning to FIG. 6, as in the case described above with reference to FIG. 1, an insulating protective film is formed on the entire back surface of the first semiconductor substrate 211, and a light-shielding film is formed on the region to be shielded from light. .. Further, an on-chip color filter 274 is formed on the flattening film corresponding to each pixel, and an on-chip microlens 275 is formed on the on-chip color filter 274.

On the other hand, a logic circuit is formed on the second semiconductor substrate 212. That is, MOS transistors Tr6, MOS transistors Tr7, and MOS transistors Tr8, which are a plurality of transistors constituting a logic circuit, are formed in a p-type semiconductor well region of a semiconductor substrate (for example, a silicon substrate) 212.

Further, in the second semiconductor substrate 212, a MOS transistor Tr6, a MOS transistor Tr7, and a connection conductor 254 connected to the MOS transistor Tr8 are formed.

Further, a plurality of layers of metal wiring 250 are formed so as to be connected to each connection conductor 254 to form a multilayer wiring layer 255.

The metal wiring is formed of copper (Cu) wiring. A protective film, which is a cap film of copper wiring (metal wiring) 250, is formed on the multilayer wiring layer 255.

Further, an aluminum pad 320 serving as an electrode is formed on the lowermost layer of the multilayer wiring layer 255 of the second semiconductor substrate 212.

Further, the second semiconductor substrate 212 is formed with contacts 311 used for electrical connection with the first semiconductor substrate 211 and the third semiconductor substrate 213. The contact 311 is connected to the contact 265 of the first semiconductor substrate 211 and also to the aluminum pad 330a of the third semiconductor substrate 213.

In addition, a memory circuit is formed on the third semiconductor substrate 213. That is, MOS transistors Tr11, MOS transistors Tr12, and MOS transistors Tr13, which are a plurality of transistors constituting the memory circuit, are formed in the p-type semiconductor well region of the semiconductor substrate (for example, a silicon substrate) 213.

Further, in the third semiconductor substrate 213, a MOS transistor Tr11, a MOS transistor Tr12, and a connection conductor 344 connected to the MOS transistor Tr13 are formed.

Further, a plurality of layers of metal wiring 340 are formed so as to be connected to each connecting conductor 344, and a multilayer wiring layer 345 is formed.

The metal wiring is formed of copper (Cu) wiring. A protective film, which is a cap film of copper wiring (metal wiring) 340, is formed on the multilayer wiring layer 345.

Further, an aluminum pad 330 serving as an electrode is formed on the uppermost layer of the multilayer wiring layer 345.

In the solid-state image sensor shown in FIG. 6, since the contact 265 and the contact 311 are provided, input / output of signals to and from each of the first semiconductor substrate 211 to the third semiconductor substrate 213 via the aluminum pad 280a Is possible.

In the solid-state image sensor shown in FIG. 6, as described above with reference to FIGS. 3 and 4, the interlayer films of the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded to each other on the adhesive surface 292. to paste together. The second semiconductor substrate 212 and the first semiconductor substrate 211 are formed by bonding interlayer films on the adhesive surface 291.

That is, as described above with reference to FIGS. 3 and 4, the circuit surfaces of the two lower semiconductor substrates are first faced to each other and bonded to each other, and the semiconductor substrate as the second layer (second semiconductor substrate 212). To be thinned. After that, the uppermost semiconductor substrate (first semiconductor substrate 211) is laminated as a back surface type and further thinned. At this time, after the upper layer of the contact 311 is flattened, the first semiconductor substrate 211 is attached to the second semiconductor substrate 212 as a back surface type.

By doing so, it is not necessary to use a support substrate for thinning the silicon substrate when laminating the circuits.

In the present technology, the aluminum pad 280 is also provided on the first semiconductor substrate 211. The second semiconductor substrate 212 having a logic circuit that requires input / output of signals from the outside or the third semiconductor substrate 213 having a memory circuit is not provided with electrodes for external connection. An electrode (aluminum pad 280a) for external connection is provided on the first semiconductor substrate 211 having a sensor circuit.

By doing so, the electrode for external connection can be exposed without deepening the pad hole 351.

Further, in the present technology, since the aluminum pad 280 is also provided on the first semiconductor substrate 211, the aluminum pad 280 shields the light caused by the hot carriers emitted from each transistor of the second semiconductor substrate 212. You can also do it.

As described above, in the present technology, it is not necessary to provide deep pad holes, and light caused by hot carriers can be easily blocked.

In FIG. 6, the aluminum pad 320 is provided on the second semiconductor substrate, and the aluminum pad 330 is provided on the third semiconductor substrate 213, but the aluminum pad 320 and the aluminum pad 330 are not provided. It may be. For example, if the contact 311 is directly connected to the copper wiring 340 of the third semiconductor substrate 213, it is not necessary to provide the aluminum pad 320 and the aluminum pad 330.

Further, the shapes of the contacts that electrically connect the semiconductor substrates to each other are not limited to those shown as the contact 265 and the contact 311. Further, the hole for forming the contact can be opened before the on-chip microlens is formed, so that the hole may be a deep hole. For example, a contact may be provided that penetrates the second semiconductor substrate and connects the copper wiring of the first semiconductor substrate and the copper wiring of the third semiconductor substrate.

Alternatively, a light-shielding body for blocking light caused by hot carriers may be formed.

FIG. 8 is a cross-sectional view illustrating a configuration according to another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied. Similar to FIG. 6, the solid-state imaging device related to the pixel portion serves as a back-illuminated CMOS image sensor formed by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. It is composed. That is, the solid-state image sensor according to the pixel portion shown in FIG. 8 also has a three-layer laminated structure.

In the example of the figure, the light-shielding body 360 is arranged in the interlayer film which is the uppermost layer in the figure of the second semiconductor substrate 212. This makes it possible to more reliably block the light caused by the hot carriers emitted from each transistor of the second semiconductor substrate 212.

Since the aluminum pad 280 is formed on the first semiconductor substrate 211, the light-shielding body 360 is not arranged on the first semiconductor substrate 211, and the light-shielding body 360 is formed in the interlayer film of the second semiconductor substrate 212. Is placed.

Since the other configurations in FIG. 8 are the same as those described above with reference to FIG. 6, detailed description thereof will be omitted.

Alternatively, copper wiring is formed in the interlayer film which is the uppermost layer in the figure of the second semiconductor substrate 212, and the combination of the aluminum pad and the copper wiring shields the light caused by the hot carrier. It is also good.

FIG. 9 is a cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied. Similar to FIG. 6, the solid-state imaging device related to the pixel portion serves as a back-illuminated CMOS image sensor formed by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. It is composed. That is, the solid-state image sensor according to the pixel portion shown in FIG. 9 also has a three-layer laminated structure.

In the example of the figure, the copper wiring 370 is arranged in the interlayer film which is the uppermost layer in the figure of the second semiconductor substrate 212.

A part of the contact 311 is formed in the interlayer film which is the uppermost layer in the drawing of the second semiconductor substrate 212. For example, if the copper wiring 370 is further formed in the interlayer film when the contact 311 is formed, the solid-state image sensor having the configuration shown in FIG. 9 can be obtained.

If the light is blocked by the combination of the copper wiring 370 and the aluminum pad 280, the light caused by the hot carriers emitted from each transistor of the second semiconductor substrate 212 can be blocked more reliably. Further, in the case of the configuration shown in FIG. 9, for example, as shown in FIG. 6, the degree of freedom in designing the wiring related to the aluminum pad 280 is improved as compared with the case where the light is shielded only by the aluminum pad 280.

Since the other configurations in FIG. 9 are the same as those described above with reference to FIG. 6, detailed description thereof will be omitted.

FIG. 10 is a diagram showing a schematic configuration of a solid-state image sensor to which the present technology is applied. The solid-state image sensor 401 is configured as, for example, a CMOS image sensor.

The solid-state image sensor 401 of FIG. 10 has a pixel region (so-called pixel array) 403 in which pixels 402 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate 411, and a peripheral circuit unit. It is composed of.

The pixel 402 includes, for example, a photodiode that serves as a photoelectric conversion unit, and a plurality of pixel transistors (so-called MOS transistors).

Further, the pixel 402 may have a shared pixel structure. This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one share of another pixel transistor.

The peripheral circuit unit includes a vertical drive circuit 404, a column signal processing circuit 405, a horizontal drive circuit 406, an output circuit 407, a control circuit 408, and the like.

The control circuit 408 receives an input clock and data for instructing an operation mode and the like, and outputs data such as internal information of the solid-state image sensor. That is, the control circuit 408 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 404, the column signal processing circuit 405, the horizontal drive circuit 406, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. Then, these signals are input to the vertical drive circuit 404, the column signal processing circuit 405, the horizontal drive circuit 406, and the like.

The vertical drive circuit 404 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving a pixel to the selected pixel drive wiring, and drives the pixels row by row. That is, the vertical drive circuit 404 selectively scans each pixel 402 in the pixel region 403 in a row-by-row manner in the vertical direction, and passes through the vertical signal line 409 to be a photoelectric conversion unit of each pixel 402, for example, in a photodiode according to the amount of light received. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 405.

The column signal processing circuit 405 is arranged for each column of the pixel 402, for example, and performs signal processing such as noise removal for each pixel string of signals output from the pixel 402 for one row. That is, the column signal processing circuit 405 performs signal processing such as CDS for removing fixed pattern noise peculiar to the pixel 402, signal amplification, and AD conversion. A horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 405 by being connected to the horizontal signal line 410.

The horizontal drive circuit 406 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 405 is sequentially selected, and a pixel signal is output from each of the column signal processing circuits 405 as a horizontal signal line. Output to 410.

The output circuit 407 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 405 through the horizontal signal line 410 and outputs the signals. For example, there are cases where only buffering is performed, black level adjustment, column variation correction, and various digital signal processing are performed. The input / output terminal 412 exchanges signals with the outside.

The solid-state image sensor 401 shown in FIG. 10 is configured as a back-illuminated CMOS image sensor having a three-layer laminated structure. For example, the pixel 402 shown in FIG. 10 is a sensor circuit formed on the first semiconductor substrate, and a logic circuit whose peripheral circuits are formed on the second semiconductor substrate or a memory formed on the third semiconductor substrate. It is a circuit.

By the way, in the above-described embodiment, it has been described that the aluminum pad 280 is formed on the lowermost layer of the multilayer wiring layer 245 of the first semiconductor substrate 211. However, for example, when the aluminum pad 280 is arranged in the first semiconductor substrate 211, an ESD (Electro-Static Discharge) circuit which is a circuit for protecting the circuit in the first semiconductor substrate 211 from overcurrent is provided. It is necessary to increase the number of processes.

Further, in the above-described example with reference to FIG. 6, the aluminum pad 280 arranged in the first semiconductor substrate 211 has an effect of blocking light caused by the hot carrier. However, since the multilayer wiring layer 245 of the first semiconductor substrate 211 is composed of three wiring layers, it is possible to block light caused by hot carriers without restricting the shape of the copper wiring 240. It is difficult to arrange the aluminum pad 280 as described above.

For example, since the multilayer wiring layer 255 of the second semiconductor substrate 212 is composed of six wiring layers, if the aluminum pad 280 is arranged in the second semiconductor substrate 212, the shape of the metal wiring 250 is restricted. It becomes easy to arrange the aluminum pad 280 so as to block the light caused by the hot carrier without giving it.

Further, in the above-described embodiment, the contact 265 used for the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 has two through holes that vertically penetrate the first semiconductor substrate 211. The conductor embedded in the semiconductor substrate 211 is connected on the light receiving surface (the uppermost surface in the drawing) of the first semiconductor substrate 211. Such contacts are also referred to as twin contacts. The contact 311 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is also configured as a twin contact.

However, since the twin contact needs to be provided with two through holes, the manufacturing process is increased and the area on the substrate is increased.

For example, the first semiconductor substrate 211 penetrates the first semiconductor substrate 211 from the uppermost side in the drawing to reach the wiring in the multilayer wiring layer 255 of the second semiconductor substrate, and a part of the first semiconductor substrate 211 By forming a contact that reaches the wiring of the multilayer wiring layer 245, the first semiconductor substrate 211 and the second semiconductor substrate 212 can be electrically connected by providing only one through hole. Such contacts are also referred to as shared contacts.

If shared contacts are used for electrical connection between semiconductor substrates, the manufacturing process can be simplified and the area on the substrates can be reduced as compared with the case of using twin contacts. ..

Further, a method of directly joining copper wirings in a multilayer wiring layer when laminating semiconductor substrates has also been put into practical use. If the copper wirings in the multilayer wiring layer are directly bonded to each other, it is not necessary to provide contacts for electrical connection between the semiconductor substrates, so that the manufacturing process can be further simplified and the area on the substrates can be reduced. can do. The method of directly joining copper wirings is also referred to as direct joining.

FIG. 11 is a schematic cross-sectional view relating to the configuration of the pixel portion of the solid-state image sensor shown in FIG. As shown in the figure, the first semiconductor substrate 211 is formed with pad holes 351 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

Further, in the configuration of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the third semiconductor substrate 213 side (lower side in the figure), and the first semiconductor substrate 211 and the second semiconductor substrate 212 are arranged. It is pasted together.

Further, in the configuration of FIG. 11, the contact 265 used for the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, and the electricity between the second semiconductor substrate 212 and the third semiconductor substrate 213. A contact 311 used for a target connection is provided. The contacts 265 and 311 are configured as twin contacts.

FIG. 12 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the configuration of FIG. 12, unlike the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the first semiconductor substrate 211 side (upper side in the drawing), and the first semiconductor substrate 211 and the second The semiconductor substrate 212 of the above is bonded.

Further, in the configuration of FIG. 12, unlike the case of FIG. 11, the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212. A pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

As shown in FIG. 12, by directing the multilayer wiring layer 255 of the second semiconductor substrate 212 toward the first semiconductor substrate side, the multilayer wiring layer 255 can block light caused by hot carriers. Furthermore, by arranging the aluminum pad 280 in the multi-layer wiring layer 255 composed of 6 wiring layers, aluminum can be shielded from light caused by hot carriers without restricting the shape of the metal wiring 250. It becomes easy to arrange the pad 280.

Further, since the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (in the second semiconductor substrate). It can be manufactured at low cost (because it is sufficient to form an ESD circuit).

Further, in the configuration of FIG. 12, the contact 266 used for the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, and the electricity between the second semiconductor substrate 212 and the third semiconductor substrate 213. A contact 312 used for a target connection is provided. The contacts 266 and 312 are configured as twin contacts.

In the case of the configuration of FIG. 12, unlike the case of FIG. 11, the contact 312 penetrates the first semiconductor substrate 211 and the second semiconductor substrate 212 and reaches the multilayer wiring layer 345 of the third semiconductor substrate 213. ..

Next, the manufacturing process of the solid-state image sensor shown in FIG. 12 will be described.

First, as shown in FIG. 13, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 on which a multilayer wiring layer is formed are prepared. As shown in the figure, the first semiconductor substrate 211 is formed with the multilayer wiring layer 245, the second semiconductor substrate 212 is formed with the multilayer wiring layer 255, and the third semiconductor substrate 213 is formed. A multilayer wiring layer 345 is formed on the vehicle.

Further, as shown in FIG. 13, an aluminum pad 280 is formed on the multilayer wiring layer 255 of the second semiconductor substrate 212.

Next, as shown in FIG. 14, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded so that the multilayer wiring layer 245 and the multilayer wiring layer 255 face each other.

Then, as shown in FIG. 15, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the figure is thin.

Next, as shown in FIG. 16, the third semiconductor substrate 213 and the second semiconductor substrate 212 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 345 of the third semiconductor substrate faces upward in the drawing.

Then, as shown in FIG. 17, the first semiconductor substrate 211 is thinned. In the figure, the width of the first semiconductor substrate 211 in the vertical direction is reduced in the drawing.

Next, contacts 312 and 266 are formed, as shown in FIG. At this time, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the aluminum pad 280 of the multilayer wiring layer 255 from the light receiving surface are provided to form the contact 266. Further, a hole reaching the aluminum pad 280 of the multilayer wiring layer 255 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the multilayer wiring layer 345 from the light receiving surface are provided to form the contact 312.

Then, as shown in FIG. 19, the pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

In this way, the solid-state image sensor described above with reference to FIG. 12 is manufactured. By doing so, the multi-layer wiring layer 255 can block light caused by hot carriers. Furthermore, by arranging the aluminum pad 280 in the multi-layer wiring layer 255 composed of 6 wiring layers, aluminum can be shielded from light caused by hot carriers without restricting the shape of the metal wiring 250. It becomes easy to arrange the pad 280. Further, since the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (in the second semiconductor substrate). It can be manufactured at low cost (because it is sufficient to form an ESD circuit).

FIG. 20 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the configuration of FIG. 20, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the third semiconductor substrate 213 side (lower side in the figure), and the first semiconductor substrate 211 and the first semiconductor substrate 211 are directed. The semiconductor substrate 212 of 2 is bonded.

Further, in the configuration of FIG. 20, as in the case of FIG. 11, the contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, and the second semiconductor substrate 212 and the second semiconductor substrate 212. A contact 311 used for electrical connection with the semiconductor substrate 213 of No. 3 is provided. The contacts 265 and 311 are configured as twin contacts.

Further, in the configuration of FIG. 20, unlike the case of FIG. 11, the insulating film layer 230 is formed between the first semiconductor substrate 211 and the second semiconductor substrate 212. Then, the aluminum pad 280a is arranged in the insulating film layer 230, and the aluminum pad 280a is connected to the contact 313 connected to the multilayer wiring layer 255 of the second semiconductor substrate 212.

Then, in the configuration of FIG. 20, the first semiconductor substrate 211 has pad holes 351 so as to reach the aluminum pad 280a in the insulating film layer 230 from the back surface side (light receiving surface side) of the first semiconductor substrate 211. It is formed.

In the case of the configuration of FIG. 20, since the aluminum pad 280 is provided in the insulating film layer 230, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (ESD circuit in the second semiconductor substrate). It is possible to manufacture at low cost (because it is sufficient to form).

Next, the manufacturing process of the solid-state image sensor shown in FIG. 20 will be described.

First, as shown in FIG. 21, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 on which a multilayer wiring layer is formed are prepared. As shown in the figure, the first semiconductor substrate 211 is formed with the multilayer wiring layer 245, the second semiconductor substrate 212 is formed with the multilayer wiring layer 255, and the third semiconductor substrate 213 is formed. A multilayer wiring layer 345 is formed on the vehicle.

As shown in FIG. 21, the aluminum pad 280 is not formed on the multilayer wiring layer 255 of the second semiconductor substrate 212.

Next, as shown in FIG. 22, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other.

Then, as shown in FIG. 23, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the figure is thin.

Next, contacts 311 and contacts 313 are formed, as shown in FIG. At this time, a hole reaching the multilayer wiring layer 345 from the upper surface in the drawing of the second semiconductor substrate 212 and a hole reaching the multilayer wiring layer 255 from the upper surface in the drawing of the second semiconductor substrate 212 are provided. Contact 311 is formed. Further, a hole reaching the multilayer wiring layer 255 is provided from the upper surface of the second semiconductor substrate 212 in the drawing, and the contact 313 is formed.

Then, as shown in FIG. 25, the aluminum pad 280a is formed and the insulating film layer 230 is formed. As shown in the figure, the aluminum pad 280a is formed by connecting to the upper end of the contact 313 in the drawing. Further, an insulating film layer 230 is formed around the aluminum pad 280a on the upper surface of the second semiconductor substrate 212 in the drawing.

Next, as shown in FIG. 26, the first semiconductor substrate 211 and the second semiconductor substrate 212 (more accurately, the insulating film layer 230) are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded so that the multilayer wiring layer 245 is in contact with the insulating film layer 230.

Further, the first semiconductor substrate 211 is thinned. In FIG. 26, the width of the first semiconductor substrate 211 in the vertical direction in the drawing is thin.

Then, as shown in FIG. 27, the pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. After that, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the contact 311 from the light receiving surface are provided to form the contact 265.

In this way, the solid-state image sensor described above with reference to FIG. 20 is manufactured. Since the aluminum pad 280 is provided in the insulating film layer 230, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (since the ESD circuit may be formed in the second semiconductor substrate). It can be manufactured at low cost.

FIG. 28 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the configuration of FIG. 28, as in the case of FIG. 11, pad holes 351 are formed in the first semiconductor substrate 211 so as to reach the aluminum pads 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Has been done. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

Further, in the configuration of FIG. 28, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the third semiconductor substrate 213 side (lower side in the figure), and the first semiconductor substrate 211 is directed. And the second semiconductor substrate 212 are bonded together.

Further, in the configuration of FIG. 28, as in the case of FIG. 11, a contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is provided. The contact 265 is configured as a twin contact.

In the configuration of FIG. 28, unlike the case of FIG. 11, the contact 311 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is not provided. On the other hand, contacts 314 and 315 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 are provided.

Each of the contact 314 and the contact 315 is formed by embedding a conductor by providing a through hole that penetrates the second semiconductor substrate 212 and reaches the multilayer wiring layer 345 of the third semiconductor substrate 213. That is, each of the contact 314 and the contact 315 is configured to connect the multilayer wiring layer 255 of the second semiconductor substrate 212 and the multilayer wiring layer 345 of the third semiconductor substrate 213 by providing only one through hole. There is.

That is, each of the contact 314 and the contact 315 is configured as a shared contact.

In the configuration shown in FIG. 28, by using the shared contact, the manufacturing process can be simplified and the area on the substrate can be reduced.

Here, it has been described that the shared contact is used for the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213, but the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 has been described. It is also possible to allow shared contacts to be used for the connection.

Further, also in the solid-state imaging device having the above-described configuration with reference to FIGS. 11, 12, or 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second A shared contact may be used for the electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213.

That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), the shared contact may be used for the electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), a shared contact may be used for the electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), a shared contact may be used for the electrical connection between the semiconductor substrates.

FIG. 29 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the configuration of FIG. 29, as in the case of FIG. 11, pad holes 351 are formed in the first semiconductor substrate 211 so as to reach the aluminum pads 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Has been done. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

Further, in the configuration of FIG. 29, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the third semiconductor substrate 213 side (lower side in the figure) and the first semiconductor substrate 211. And the second semiconductor substrate 212 are bonded together.

Further, in the configuration of FIG. 29, a contact 267 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is provided. The contact 267 is configured as a twin contact.

Further, in the configuration of FIG. 29, the metal wiring 250a in the multilayer wiring layer 255 of the second semiconductor substrate 212 and the metal wiring 340a in the multilayer wiring layer 345 of the third semiconductor substrate 213 are directly joined. Further, the metal wiring 250b in the multilayer wiring layer 255 and the metal wiring 340b in the multilayer wiring layer 345 are directly joined. As a result, the second semiconductor substrate 212 and the third semiconductor substrate 213 are electrically connected.

That is, in the case of the configuration of FIG. 29, direct bonding is used without using contacts for the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213. Therefore, the manufacturing process can be simplified and the area on the substrate can be reduced.

The direct bonding is disclosed in detail in, for example, Japanese Patent Application Laid-Open No. 2013-033900.

Next, the manufacturing process of the solid-state image sensor shown in FIG. 29 will be described.

First, as shown in FIG. 30, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 on which a multilayer wiring layer is formed are prepared. As shown in the figure, the first semiconductor substrate 211 is formed with the multilayer wiring layer 245, the second semiconductor substrate 212 is formed with the multilayer wiring layer 255, and the third semiconductor substrate 213 is formed. A multilayer wiring layer 345 is formed on the vehicle.

As shown in FIG. 30, an aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211. Further, a metal wiring 250a and a metal wiring 250b are formed on the multilayer wiring layer 255 of the second semiconductor substrate, and a metal wiring 340a and a metal wiring 340b are formed on the multilayer wiring layer 345 of the third semiconductor substrate. There is.

Next, as shown in FIG. 31, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other. Then, the metal wiring 250a and the metal wiring 340a are directly joined, and the metal wiring 250b and the metal wiring 340b are directly joined.

Further, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the figure is thin.

Then, as shown in FIG. 32, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the multilayer wiring layer 255 of the second semiconductor substrate is directed toward the third semiconductor substrate 213 side (lower side in the drawing), and the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together.

Further, the first semiconductor substrate 211 is thinned. In the figure, the width of the first semiconductor substrate 211 in the vertical direction is reduced in the drawing.

Next, a contact 267 is formed, as shown in FIG. At this time, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the multilayer wiring layer 255 from the light receiving surface are provided to form the contact 267.

Then, as shown in FIG. 34, the pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

In this way, the solid-state image sensor described above with reference to FIG. 29 is manufactured. Since direct bonding was used for the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 without using contacts, the manufacturing process could be simplified and the area on the substrate could be reduced. It can be made smaller.

Here, it has been described that direct bonding is used for the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213, but the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 has been described. It is also possible to allow direct bonding to be used for the connection.

Further, also in the solid-state image sensor having the above-described configuration with reference to FIGS. 11, 12, or 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second Direct bonding may be used for the electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213.

That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), direct bonding may be used for the electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), direct bonding may be used for the electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), direct bonding may be used for electrical connection between the semiconductor substrates.

FIG. 35 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the configuration of FIG. 35, unlike the case of FIG. 29, contacts 268 and contacts 316 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 are provided. That is, in the case of the configuration of FIG. 35, the lower end of the contact 268 in the drawing is connected to the upper end of the contact 316 in the drawing, so that the first semiconductor substrate 211 and the second semiconductor substrate 212 are connected. It is electrically connected. The contact 268 is configured as a twin contact.

In the configuration of FIG. 35, it is not necessary to provide a hole reaching the multilayer wiring layer 255 from the light receiving surface as in the formation of the contact 267 of FIG. 29, for example. Therefore, the formation of the contact can be performed more simply.

Since the configuration of other parts in FIG. 35 is the same as that in FIG. 29, detailed description thereof will be omitted.

Next, the manufacturing process of the solid-state image sensor shown in FIG. 35 will be described.

First, as shown in FIG. 36, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 on which a multilayer wiring layer is formed are prepared. As shown in the figure, the first semiconductor substrate 211 is formed with the multilayer wiring layer 245, the second semiconductor substrate 212 is formed with the multilayer wiring layer 255, and the third semiconductor substrate 213 is formed. A multilayer wiring layer 345 is formed on the vehicle.

As shown in FIG. 36, an aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211. Further, a metal wiring 250a and a metal wiring 250b are formed on the multilayer wiring layer 255 of the second semiconductor substrate, and a metal wiring 340a and a metal wiring 340b are formed on the multilayer wiring layer 345 of the third semiconductor substrate. There is.

Next, as shown in FIG. 37, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other. Then, the metal wiring 250a and the metal wiring 340a are directly joined, and the metal wiring 250b and the metal wiring 340b are directly joined.

Further, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the figure is thin.

Then, as shown in FIG. 38, the contact 316 is formed. At this time, a hole reaching the multilayer wiring layer 255 is provided from the upper surface of the second semiconductor substrate 212 in the drawing, and the contact 316 is formed.

Next, as shown in FIG. 39, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together so that the back surface of the first semiconductor substrate 211 serves as the light receiving surface.

Further, the first semiconductor substrate 211 is thinned. In FIG. 39, the width of the first semiconductor substrate 211 in the vertical direction is reduced in the drawing.

Further, a hole from the light receiving surface of the first semiconductor substrate 211 to the upper surface in the drawing of the second semiconductor substrate and a hole from the light receiving surface to the aluminum pad 280 of the multilayer wiring layer 245 are provided, and the contact 268 is provided. Is formed.

Then, as shown in FIG. 40, the pad hole 351 is formed so as to reach the aluminum pad 280a from the light receiving surface of the first semiconductor substrate 211.

In this way, the solid-state image sensor described above with reference to FIG. 35 is manufactured. In the configuration of FIG. 35, as described above, the contacts 268 and 316 are used to electrically connect the first semiconductor substrate 211 and the second semiconductor substrate 212. That is, on the bonding surface between the first semiconductor substrate 211 and the second semiconductor substrate 212, the conductor forming the contact 268 and the conductor forming the contact 316 are bonded. As described above, in the case of the configuration of FIG. 35, a part of the twin contacts for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is divided into two stages.

By doing so, it is not necessary to provide a deep hole reaching the multilayer wiring layer 255 from the light receiving surface as in the formation of the contact 267 in FIG. 29, for example. Therefore, the formation of the contact can be performed more simply.

Here, a part of the twin contacts used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 has been described as being configured in two stages, but the second semiconductor substrate 212 has been described. It is also possible that a part of the twin contacts used for the electrical connection between the and the third semiconductor substrate 213 is configured in two stages.

Further, also in the solid-state imaging device having the above-described configuration with reference to FIGS. 11, 12, or 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second A part of the twin contacts used for electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213 may be configured in two stages.

That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), a part of the twin contacts used for electrical connection between the semiconductor substrates is divided into two stages. May be configured. Further, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), a part of the twin contacts used for electrical connection between the semiconductor substrates is divided into two stages. May be configured. Further, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), a part of the twin contacts used for electrical connection between the semiconductor substrates is configured in two stages. May be good.

As described above with reference to FIGS. 11 to 40, in the solid-state imaging device to which the present technology is applied, the aluminum pad 280 may be provided in the multilayer wiring layer 245 of the first semiconductor substrate 211. The aluminum pad 280 may be provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, or the aluminum pad 280 may be provided in the insulating film layer 230. Further, as the form of electrical connection between the semiconductor substrates, twin contact, shared contact, direct bonding, and a configuration in which a part of the twin contact is divided into two stages can be adopted.

That is, as an embodiment of the solid-state image sensor to which the present technology is applied, a combination as shown in FIG. 41 can be adopted.

In the above-described embodiment, the embodiment of the solid-state image sensor to which the present technology is applied has been described on the premise of a three-layer structure. However, the solid-state image sensor to which this technology is applied can also adopt, for example, a four-layer structure in which a first semiconductor substrate, a second semiconductor substrate, a third semiconductor substrate, and a fourth semiconductor substrate are laminated. Is.

FIG. 42 shows an example in which a four-layer structure is adopted in a solid-state image sensor to which the present technology is applied. FIG. 42 is a schematic cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state image sensor to which the present technology is applied.

In the example of FIG. 42, a four-layer structure in which a first semiconductor substrate 211, a second semiconductor substrate 212, a third semiconductor substrate 213, and a fourth semiconductor substrate 214 are laminated is adopted.

Similarly, it is possible to adopt a structure of five or more layers in a solid-state image sensor to which the present technology is applied.

FIG. 43 is a block diagram showing a configuration example of a camera device as an electronic device to which the present technology is applied.

The camera device 600 of FIG. 43 includes an optical unit 601 including a lens group and the like, a solid-state image pickup device (imaging device) 602 in which each configuration of the pixels 402 described above is adopted, and a DSP circuit 603 which is a camera signal processing circuit. The camera device 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via the bus line 609.

The optical unit 601 captures incident light (image light) from the subject and forms an image on the image pickup surface of the solid-state image pickup device 602. The solid-state image sensor 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electric signal in pixel units and outputs it as a pixel signal. As the solid-state image sensor 602, the solid-state image sensor according to the above-described embodiment can be used.

The display unit 605 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 602. The recording unit 606 records a moving image or a still image captured by the solid-state image sensor 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

The operation unit 607 issues operation commands for various functions of the camera device 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources serving as operating power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.

In addition, this technology is not limited to application to a solid-state image sensor that detects the distribution of the incident light amount of visible light and captures it as an image, but is also a solid that captures the distribution of the incident amount of infrared rays, X-rays, particles, etc. as an image. It can be applied to image sensors and, in a broad sense, solid-state image sensors (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images as images. is there.

Further, the embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present technology.

211 1st semiconductor substrate, 212 2nd semiconductor substrate, 213 3rd semiconductor substrate, 230 insulating film layer, 234 photodiode, 245 multi-layer wiring layer, 240 copper wiring, 255 multi-layer wiring layer, 250 copper wiring, 265 contacts , 266 contacts, 267 contacts, 280 aluminum pads, 311 contacts, 312 contacts, 313 contacts, 320 aluminum pads, 330 aluminum pads, 340 copper wiring, 345 multi-layer wiring layers, 351 pad holes, 360 shading bodies, 370 copper wiring, 401 Solid imager, 402 pixels, 600 camera device, 602 Solid imager

Claims (7)

A first semiconductor substrate that includes a plurality of photodiodes, at least one of a transfer transistor, a reset transistor, and an amplifier transistor, and a first wiring layer that includes a first electrode.
A second semiconductor substrate including a second wiring layer including a second electrode and a third wiring layer including a third electrode,
A third semiconductor substrate including a fourth wiring layer including a fourth electrode is provided.
The second wiring layer and the third wiring layer are formed on opposite surface sides of the second semiconductor substrate, respectively.
The first semiconductor substrate, the second semiconductor substrate, and the first wiring layer so that the first wiring layer and the second wiring layer, and the third wiring layer and the fourth wiring layer face each other. 3 semiconductor substrates are laminated,
The first semiconductor substrate and the second semiconductor substrate are electrically connected by directly joining the first electrode and the second electrode.
A solid-state image sensor in which the second semiconductor substrate and the third semiconductor substrate are electrically connected by directly joining the third electrode and the fourth electrode. The solid-state image sensor according to claim 1, wherein the second semiconductor substrate includes a plurality of transistors. The solid-state image sensor according to claim 1 or 2, wherein the third semiconductor substrate includes a plurality of transistors. The solid-state image sensor according to any one of claims 1 to 3, wherein the second semiconductor substrate includes a logic circuit. The solid-state imaging device according to any one of claims 1 to 4, wherein the third semiconductor substrate includes a memory circuit. The second semiconductor substrate includes a logic circuit.
The third semiconductor substrate includes a memory circuit.
The solid-state image sensor according to any one of claims 1 to 3, wherein the logic circuit and the memory circuit operate in association with input / output of a signal to and from the outside. An optical unit containing at least one lens that receives incident light,
A solid-state image sensor that receives the incident light is provided.
The solid-state image sensor
A first semiconductor substrate that includes a plurality of photodiodes, at least one of a transfer transistor, a reset transistor, and an amplifier transistor, and a first wiring layer that includes a first electrode.
A second semiconductor substrate including a second wiring layer including a second electrode and a third wiring layer including a third electrode,
A third semiconductor substrate including a fourth wiring layer including a fourth electrode is provided.
The second wiring layer and the third wiring layer are formed on opposite surface sides of the second semiconductor substrate, respectively.
The first semiconductor substrate, the second semiconductor substrate, and the first wiring layer so that the first wiring layer and the second wiring layer, and the third wiring layer and the fourth wiring layer face each other. 3 semiconductor substrates are laminated,
The first semiconductor substrate and the second semiconductor substrate are electrically connected by directly joining the first electrode and the second electrode.
An electronic device in which the second semiconductor substrate and the third semiconductor substrate are electrically connected by directly joining the third electrode and the fourth electrode.

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