JP2017139497A - Solid-state image pickup device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily provide a high-quality laminated image sensor.SOLUTION: A solid-state image pickup device is laminated with: a first semiconductor substrate including a first wiring layer, a photodiode, and at least a transfer transistor, a reset transistor, and an amplifier transistor; a second semiconductor substrate including a second wiring layer and a plurality of transistors; and a third semiconductor substrate including a third wiring layer. The first semiconductor substrate includes a first connection part connected to the first wiring layer. The second semiconductor substrate includes a second connection part extending in a lateral direction on the other side of a surface facing the second semiconductor substrate. The second connection part is connected to the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate. The plurality of transistors are arranged in a longitudinal direction between opposed surfaces of the second semiconductor substrate.SELECTED DRAWING: Figure 6

Description

  The present technology relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that can easily provide a high-quality stacked image sensor.

  As a solid-state imaging device, an amplification-type solid-state imaging device represented by a MOS type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is known. There is also known a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor.

  These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) from the viewpoint of low power supply voltage and power consumption.

  The MOS type solid-state imaging device includes a pixel array (pixel region) in which unit pixels are formed by a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors, and the unit pixels are arranged in a two-dimensional array, and a peripheral area. It has a circuit area. The plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.

  In the solid-state imaging device as described above, a stacked structure in which a plurality of semiconductor chips having different functions are stacked and electrically connected has been proposed.

  In the stacked structure, since each circuit can be optimally formed so as to correspond to the function of each semiconductor chip, it is possible to easily realize high functionality of the device.

  For example, by forming the sensor circuit and the logic circuit optimally so as to correspond to the functions of the semiconductor chip including the sensor circuit and the semiconductor chip including the logic circuit provided with a circuit for processing a signal, high functionality A solid-state imaging device can be manufactured. At this time, by providing a through electrode on the substrate of the semiconductor chip, these semiconductor chips are electrically connected.

  However, when a semiconductor device is configured by connecting different types of chips with connection conductors that penetrate the substrate, the connection holes must be opened while ensuring insulation on the deep substrate, which is necessary for processing the connection holes and embedding the connection conductors. It has been considered difficult to put it into practical use because of the cost-effectiveness of a simple manufacturing process.

  On the other hand, in order to form a small contact hole of about 1 μm, for example, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning the film and cost increase are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is inevitably required to use a CVD film having a good coverage such as tungsten (W) as the connection conductor, which restricts the connection conductor material.

  In view of this, a method for manufacturing a semiconductor device such as a solid-state imaging device has been proposed in which each performance is fully exhibited to achieve high performance, and mass production and cost reduction are attempted (see, for example, Patent Document 1). .

  Patent Document 1 proposes that a support substrate of a back surface type image sensor is stacked as a logic circuit, and a large number of connection contacts are provided from the top using a thinning process of the image sensor to form a stacked structure.

  However, in recent years, a three-layer stacked solid-state imaging device has also been proposed. When a stacked image sensor is configured as a three-layer stacked structure, a sensor having a light receiving unit needs to take in light, so it is arranged at the top, and two chips are stacked below it. Become. In this case, the lower two chips can be, for example, logic or memory chips.

  In general, when stacking circuits, it is desirable not to use a support substrate for thinning a silicon substrate. In that case, in the generation of the circuit, first, the circuit surfaces of the lower two chips are faced and bonded together, and the chip of the second layer is thinned. After that, the uppermost sensor is bonded and laminated as a back surface type, and further thinned.

JP 2010-245506 A

  However, in this case, the following problem occurs in the three-layer structure.

  That is, the pad opening to the pad metal becomes deeper than necessary. In other words, since it opens to the AL layer of the second layer chip, it penetrates the sensor of the uppermost layer chip, and further penetrates the silicon substrate of the second layer chip to reach the AL located at the lowermost layer of the wiring layer. There must be.

  In order to open a deep pad, in addition to increasing the thickness of the resist, curing of the resist after dry etching becomes a problem.

  For example, since an organic lens is already formed on the chip at the time of opening, the resist must be removed with a chemical solution. However, the hardened resist tends to remain in the form of a residue, which impedes light incidence on the lens.

  In addition, deposits generated by dry etching also become a problem. In particular, deposits that cannot be removed by adhering to the metal surface of the pad or the side wall of the pad opening cause moisture to be absorbed after the completion of the chip to generate fluorine ions, resulting in a defect that melts the metal of the pad (corrosion).

  Thus, the process becomes difficult due to the increased depth of the pad.

  Furthermore, the hot carrier emission generated from the second layer chip cannot be shielded by the wiring layout of the second layer chip, and if the unnecessary wiring layer is reduced even in the sensor chip, sufficient light shielding layout is provided. Cannot be configured.

  The present technology is disclosed in view of such a situation, and makes it possible to easily provide a high-quality stacked image sensor.

  A solid-state imaging device according to one aspect of the present technology includes a first wiring layer on one side of an opposing surface, and includes a photodiode, and at least a transfer transistor, a reset transistor, and an amplifier transistor on the other side of the opposing surface. A first semiconductor substrate including the second semiconductor substrate including a second wiring layer and a plurality of transistors on one side of the opposing surface, and one of the opposing surfaces connected to the first semiconductor substrate; A third semiconductor substrate including a third wiring layer on the side and connected to the second semiconductor substrate, the first semiconductor substrate, the second semiconductor substrate, and the first semiconductor The substrates are stacked, the first semiconductor substrate has a first connection portion connected to the first wiring layer, and the second semiconductor substrate is opposed to the second semiconductor substrate. On the other side of the surface A second connecting portion extending in a direction, wherein the second connecting portion includes the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate. The plurality of transistors are arranged in a vertical direction between opposing surfaces of the second semiconductor substrate.

  An electronic apparatus according to an aspect of the present technology is an electronic apparatus including an optical unit including at least one lens that receives incident light, and a solid-state imaging device that receives the incident light. The solid-state imaging device faces each other. A first wiring layer on one side of the surface, a photodiode on the other side of the opposing surface, and a first semiconductor substrate including at least a transfer transistor, a reset transistor, and an amplifier transistor, and one side of the opposing surface Including a second wiring layer and a plurality of transistors, a second semiconductor substrate connected to the first semiconductor substrate, a third wiring layer on one side of the opposing surface, and the second semiconductor substrate. A semiconductor substrate and a third semiconductor substrate connected to each other, wherein the first semiconductor substrate, the second semiconductor substrate, and the first semiconductor substrate are stacked, The first semiconductor substrate has a first connection portion connected to the first wiring layer, and the second semiconductor substrate is disposed on the other side of the opposing surface of the second semiconductor substrate. A second connecting portion extending in a direction, wherein the second connecting portion includes the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate. The plurality of transistors are arranged in a vertical direction between corresponding surfaces of the second semiconductor substrate.

  According to the present technology, a high-quality stacked image sensor can be easily provided.

It is sectional drawing explaining the structure of the pixel part of the conventional lamination type solid-state imaging device. It is sectional drawing explaining another structure of the pixel part of the conventional lamination type solid-state imaging device. It is a figure explaining the manufacturing system of a 3 layer lamination type solid-state imaging device. It is a figure explaining the manufacturing system of a 3 layer lamination type solid-state imaging device. It is sectional drawing explaining the structure of the pixel part of the solid-state imaging device of the 3 layer laminated structure manufactured by the prior art. It is sectional drawing explaining the structure which concerns on one Embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is a figure explaining the structure of the pad hole of FIG. 6, and an aluminum pad. It is sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is a figure which shows schematic structure of the solid-state imaging device to which this technique is applied. FIG. 7 is a diagram schematically illustrating a cross-sectional view relating to a configuration of a pixel portion of the solid-state imaging device illustrated in FIG. 6. It is the figure which schematized sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is the figure which schematized sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is the figure which schematized sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is the figure which schematized sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is a figure explaining the manufacturing process of the solid-state imaging device shown by FIG. It is the figure which schematized sectional drawing explaining the structure which concerns on another embodiment of the pixel part of the solid-state imaging device to which this technique is applied. FIG. 36 is a diagram illustrating a manufacturing process of the solid-state imaging device shown in FIG. FIG. 36 is a diagram illustrating a manufacturing process of the solid-state imaging device shown in FIG. FIG. 36 is a diagram illustrating a manufacturing process of the solid-state imaging device shown in FIG. FIG. 36 is a diagram illustrating a manufacturing process of the solid-state imaging device shown in FIG. FIG. 36 is a diagram illustrating a manufacturing process of the solid-state imaging device shown in FIG. It is a figure explaining the combination of the structure which can be employ | adopted as embodiment of the solid-state imaging device to which this technique is applied. It is the figure which schematized sectional drawing explaining the structure of the pixel part of the solid-state imaging device to which this technique in the case of employ | adopting 4 layer structure is applied. It is a block diagram which shows the structural example of the electronic device to which this technique is applied.

  Hereinafter, embodiments of the technology disclosed herein will be described with reference to the drawings.

  First, problems of the prior art will be described.

  As a solid-state imaging device, an amplification-type solid-state imaging device represented by a MOS type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is known. There is also known a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor.

  These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) from the viewpoint of low power supply voltage and power consumption.

  The MOS type solid-state imaging device includes a pixel array (pixel region) in which unit pixels are formed by a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors, and the unit pixels are arranged in a two-dimensional array, and a peripheral area. It has a circuit area. The plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.

  In the solid-state imaging device as described above, a stacked structure in which a plurality of semiconductor chips having different functions are stacked and electrically connected has been proposed.

  In the stacked structure, since it is possible to optimally form each circuit so as to correspond to the function of each semiconductor chip, it is possible to easily realize high performance of the device.

  For example, by forming the sensor circuit and the logic circuit optimally so as to correspond to the functions of the semiconductor chip including the sensor circuit and the semiconductor chip including the logic circuit provided with a circuit for processing a signal, high functionality A solid-state imaging device can be manufactured. At this time, by providing a through electrode on the substrate of the semiconductor chip (semiconductor substrate), the plurality of semiconductor substrates are electrically connected.

  FIG. 1 is a cross-sectional view illustrating a configuration of a pixel portion of a conventional stacked solid-state imaging device.

  The solid-state imaging device according to the pixel unit is configured as a backside illumination type CMOS image sensor configured by stacking a first semiconductor substrate and a second semiconductor substrate. That is, the solid-state imaging device shown in FIG. 1 has a two-layer structure.

  As shown in FIG. 1, an image sensor, that is, a pixel array (hereinafter referred to as a pixel region) and a control region are formed in each region of the first semiconductor substrate 31.

  That is, a photodiode (PD) 34 that becomes a photoelectric conversion portion of each pixel is formed in each region of a semiconductor substrate (for example, a silicon substrate) 31, and a source / drain region of each pixel transistor is formed in the semiconductor well region.

  A gate electrode is formed on a substrate surface constituting a pixel through a gate insulating film, and a pixel transistor Tr1 and a pixel transistor Tr2 are formed by a source / drain region paired with the gate electrode.

  A pixel transistor Tr1 adjacent to the photodiode (PD) 34 corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD).

  Next, a first interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, and then a connection hole is formed in the interlayer insulating film 39 to form a connection conductor connected to a required transistor.

  Next, a multilayer wiring layer 41 is formed by forming a plurality of layers (two layers in this example) of metal wiring via the interlayer insulating film 39 so as to be connected to each connection conductor. The metal wiring is formed of copper (Cu) wiring. Usually, each copper wiring (metal wiring) is covered with a barrier metal film that prevents Cu diffusion. Therefore, a protective film that is a cap film for copper wiring is formed on the multilayer wiring layer 41.

  Through the steps so far, the first semiconductor substrate 31 having the pixel region and the control region is formed.

  On the other hand, in each region of the second semiconductor substrate 45, for example, a logic circuit including a signal processing circuit related to signal processing for controlling a pixel region or controlling communication with the outside is formed. That is, a plurality of MOS transistors Tr 6, MOS transistors Tr 7, and MOS transistors Tr 8 that constitute a logic circuit are separated in a p-type semiconductor well region on the surface side of a semiconductor substrate (for example, a silicon substrate) 45 by an element isolation region. Form.

  Next, a first interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, and then a connection hole is formed in the interlayer insulating film 49, and a connection conductor 54 connected to a required transistor is formed. .

  Next, a multilayer wiring layer 55 is formed by forming a plurality of layers, that is, four layers of metal wirings in this example via the interlayer insulating film 49 so as to be connected to each connection conductor 54.

  The metal wiring is formed of copper (Cu) wiring. A protective film that is a cap film for copper wiring (metal wiring) is formed on the multilayer wiring layer 55. However, the uppermost layer of the multilayer wiring layer 55 is formed of an aluminum pad serving as an electrode.

  Through the steps up to here, the second semiconductor substrate 45 having the logic circuit is formed.

  Then, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded together at the bonding surface 99 so that the multilayer wiring layer 41 and the multilayer wiring layer 55 face each other. The bonding includes, for example, plasma bonding and bonding with an adhesive.

  Then, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31b side of the first semiconductor substrate 31, and the back surface of the first semiconductor substrate 31 is configured as a back-illuminated solid-state imaging device. The light incident surface.

  The first semiconductor substrate 31 having a reduced thickness penetrates the first semiconductor substrate 31 from the rear surface side to the uppermost aluminum pad of the multilayer wiring layer 55 of the second semiconductor substrate 45 at a required position. A connection hole is formed. At the same time, a connection hole reaching the first layer wiring on the first semiconductor substrate 31 side from the back surface side is formed in the first semiconductor substrate 31 in the vicinity of the through-connection hole.

  Next, the through connection conductor 64 and the connection conductor 65 are embedded in the through connection hole. For example, a metal such as copper (Cu) or tungsten (W) can be used for the through connection conductor 64 and the connection conductor 65.

  As described above, since the logic circuit for performing signal processing and the like is formed on the second semiconductor substrate 45, the electrode of each transistor and the signal line are connected so that signal input / output is performed. There is a need. That is, the logic circuit is operated with input / output of signals from / to the outside. Therefore, the aluminum pad 53 of the second semiconductor substrate 45 becomes an electrode for external connection.

Therefore, in order to be able to wire bond to the aluminum pad 53 of the second semiconductor substrate,
A pad hole 81 penetrating the first semiconductor substrate 31 is formed, and the aluminum pad 53 is exposed.

  Thereafter, an insulating protective film is formed on the entire back surface of the first semiconductor substrate 31, and a light shielding film 67 is formed on a region to be shielded from light. As the light shielding film 67, for example, a metal film such as tungsten can be used.

  Thereafter, a planarizing film is formed on the light shielding film 67, and on-chip color filters 74 of, for example, red (R), green (G), and blue (B) are formed on the planarizing film corresponding to each pixel, On-chip microlens 75 is formed thereon.

  In addition, the aluminum pad 53 serving as an electrode used for transmission / reception of signals to / from the external device, circuit, or the like reaches the first semiconductor substrate 31 from the back surface side (light receiving surface side) of the first semiconductor substrate 31. Thus, the pad hole 81 is formed.

  This completes the process of the stacked semiconductor structure. That is, the pixel region and the control region are formed in the first semiconductor substrate 31, and the logic circuit is formed in the second semiconductor substrate 45.

  Next, the chip is divided into each chip to obtain a chip of a backside illumination type solid-state imaging device.

  In addition, in a solid-state imaging device having a stacked structure, the influence of noise and the like due to hot carriers must be taken into consideration. A hot carrier is a high-speed electron having high kinetic energy emitted from a transistor, and light is generated when the hot carrier collides with a silicon atom.

  In a solid-state imaging device having a stacked structure, a transistor is also provided on a second semiconductor substrate different from the first semiconductor substrate on which the PD is formed. For this reason, the light generated by the hot carriers emitted from the transistor of the second semiconductor substrate may enter from the back side of the PD of the first semiconductor substrate (opposite the light receiving surface) and become noise.

  For this reason, in a solid-state imaging device having a laminated structure, for example, a measure such as providing a light-shielding body has been taken to shield light caused by hot carriers.

  FIG. 2 is a cross-sectional view illustrating another configuration of a pixel portion of a conventional stacked solid-state imaging device.

  In the example of FIG. 2, a light shield 90 is formed under the PD 34 in the first semiconductor substrate 31. Thereby, light caused by hot carriers emitted from the MOS transistor Tr6, the MOS transistor Tr7, and the MOS transistor Tr8 of the second semiconductor substrate 45 is shielded.

  Alternatively, the light caused by hot carriers emitted from the MOS transistor Tr6, the MOS transistor Tr7, and the MOS transistor Tr8 can be blocked by changing the shape of the copper wiring in the multilayer wiring layer 55. .

  As described above with reference to FIGS. 1 and 2, in the solid-state imaging device having a two-layer structure, by providing the pad hole 81, electrical connection with the outside is possible, and the light shielding body 90 and the multilayer wiring layer are provided. The shape of the copper wiring at 55 shields light caused by hot carriers.

  On the other hand, in recent years, a three-layer stacked solid-state imaging device has also been developed. In addition to a first semiconductor substrate in which a pixel region and a control region (hereinafter also referred to as a sensor circuit) are formed, and a second semiconductor substrate in which a logic circuit is formed, for example, It consists of a third semiconductor substrate on which a memory circuit is formed.

  The three-layer stacked solid-state imaging device is manufactured as shown in FIGS. 3 and 4, for example.

  First, as shown in FIG. 3, the second semiconductor substrate 112 and the third semiconductor substrate 113 are bonded to each other with their circuit surfaces facing each other. In practice, the interlayer films of the two semiconductor substrates are bonded together. Then, the second semiconductor substrate 112 is thinned.

  Thereafter, as shown in FIG. 4, the first semiconductor substrate 111 is bonded onto the thinned second semiconductor substrate 112 with the back surface facing up. In practice, the interlayer films of the two semiconductor substrates are bonded together. Then, the first semiconductor substrate 111 is thinned.

  As described above, when a stacked image sensor is configured as a three-layer stacked structure, a sensor circuit having a light receiving unit needs to take in light, so it is disposed at the top, and two logic circuits are provided below that. And the memory circuit are stacked.

  In addition, it is desirable to eliminate the use of a support substrate for thinning a silicon substrate when stacking circuits. For this reason, in the generation of the circuit, first, the circuit surfaces of the two lower semiconductor substrates are faced and bonded to each other, and the semiconductor substrate (second semiconductor substrate 112) as the second layer is thinned. After that, the uppermost semiconductor substrate (first semiconductor substrate 111) is bonded and laminated as a back surface type, and further thinned.

  However, in this case, the following problem occurs in the three-layer structure.

  FIG. 5 is a cross-sectional view illustrating a configuration of a pixel portion of a solid-state imaging device having a three-layer structure manufactured by a conventional technique.

  The first problem in the three-layer structure of the prior art is that the pad hole is too deep. In FIG. 5, a pad hole 121 deeper than the pad hole 81 of FIG. 1 is formed.

  That is, in the case of a three-layer stacked structure, as described above with reference to FIGS. 3 and 4, the circuit surface of the second semiconductor substrate 112 is attached so as to face the circuit surface of the third semiconductor substrate. . For this reason, the uppermost aluminum pad of the multilayer wiring layer of the second semiconductor substrate is far from the light-receiving surface of the first semiconductor substrate 111, penetrates the first semiconductor substrate, and further passes through the second semiconductor substrate. If the opening is not made until it penetrates, the aluminum pad 133 (external connection electrode) of the second semiconductor substrate is not exposed.

  In order to open the deep pad hole 121, it is necessary to increase the thickness of the resist. When the resist is thickened to open the deep pad hole 121, resist hardening after dry etching becomes a problem.

  For example, since an on-chip microlens using an organic material has already been formed on the first semiconductor substrate at the time of opening, the resist must be removed with a chemical solution, but the cured resist tends to remain in a residue state This impedes the incidence of light on the lens.

  Further, when the deep pad hole 121 is opened, deposits generated by dry etching also become a problem.

  In particular, the deposit deposited on the surface of the aluminum pad 133 and the side wall of the pad hole 121, for example, absorbs humidity after the three-layer laminated structure is completed to generate fluorine ions, thereby melting the metal of the aluminum pad ( Corrosion) causes a defect.

  Thus, in the conventional technique, the manufacturing process of the solid-state imaging device becomes difficult due to the deep pad hole.

  The second problem in the conventional three-layer structure is that it is difficult to block light caused by hot carriers.

  That is, in the case of a three-layer stacked structure, as described above with reference to FIGS. 3 and 4, the circuit surface of the second semiconductor substrate 112 is attached so as to face the circuit surface of the third semiconductor substrate. . For this reason, the transistor of the second semiconductor substrate faces the first semiconductor substrate without going through the multilayer wiring layer. For this reason, for example, as in the case of the two-layer stacked structure, light caused by hot carriers cannot be shielded by the copper wiring of the multilayer wiring layer of the second semiconductor substrate.

  Therefore, in the present technology, it is not necessary to provide a deep pad hole, and light caused by hot carriers can be easily blocked.

  FIG. 6 is a cross-sectional view illustrating a configuration according to an embodiment of a pixel unit of a solid-state imaging device to which the present technology is applied. The solid-state imaging device according to the pixel unit is configured as a backside illumination type CMOS image sensor configured by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. That is, the solid-state imaging device according to the pixel portion shown in FIG. 6 has a three-layer stacked structure.

  The solid-state imaging device includes, for example, a first semiconductor substrate on which a sensor circuit is formed, a second semiconductor substrate on which a logic circuit is formed, and a third semiconductor substrate on which a memory circuit is formed. ing. Each of the logic circuit and the memory circuit operates with input / output of signals from / to the outside.

  As shown in FIG. 6, a photodiode (PD) 234 serving as a photoelectric conversion unit of a pixel is formed on a semiconductor substrate (for example, a silicon substrate) 211, and the source / drain regions of each pixel transistor are formed in the semiconductor well region. It is formed.

  A gate electrode is formed on a substrate surface constituting a pixel through a gate insulating film, and a pixel transistor Tr1 and a pixel transistor Tr2 are formed by a source / drain region paired with the gate electrode.

  A pixel transistor Tr1 adjacent to the photodiode (PD) 234 corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD).

  Further, an interlayer insulating film is formed on the first semiconductor substrate 211, a connection hole is formed in the interlayer insulating film, and a connection conductor 244 connected to the pixel transistor Tr1 and the pixel transistor Tr2 is formed.

  Further, a multilayer wiring layer 245 is formed by forming a plurality of layers of metal wiring 240 so as to be connected to each connection conductor 244. The copper wiring 240 (metal wiring) is formed of a copper (Cu) wiring. Usually, each copper wiring is covered with a barrier metal film that prevents Cu diffusion. Therefore, a protective film that is a cap film for copper wiring is formed on the multilayer wiring layer 245.

  In addition, an aluminum pad 280 serving as an electrode for external connection is formed in the lowermost layer of the multilayer wiring layer 245 of the first semiconductor substrate 211. That is, the aluminum pad 280 is formed at a position closer to the bonding surface 291 with the second semiconductor substrate 212 than to the copper wiring 240. This external connection electrode is used as one end of a wiring related to signal input / output with the outside. In addition, although demonstrated here as an electrode being formed with aluminum, you may make it form an electrode with another metal.

  Further, a contact 265 used for electrical connection with the second semiconductor substrate 212 is formed on the first semiconductor substrate 211. The contact 265 is connected to a contact 311 of a second semiconductor substrate 212, which will be described later, and is also connected to an aluminum pad 280a of the first semiconductor substrate 211.

  A pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

  FIG. 7 is a diagram illustrating the configuration of the pad hole 351 and the aluminum pad 280a. FIG. 7A is an enlarged view of the vicinity of the pad hole 351, and FIG. 7B is a view of the aluminum pad 280 a as viewed from above the pad hole 351.

  As shown in FIG. 7B, the connection resistance can be reduced by connecting a large number of contacts 265 side by side to the end of the aluminum pad 280a.

  Returning to FIG. 6, similarly to the case described above with reference to FIG. 1, the first semiconductor substrate 211 has an insulating protective film formed on the entire back surface, and a light shielding film is formed on the region to be shielded from light. . An on-chip color filter 274 is formed on the planarizing film corresponding to each pixel, and an on-chip microlens 275 is formed thereon.

  On the other hand, a logic circuit is formed on the second semiconductor substrate 212. That is, in the p-type semiconductor well region of the semiconductor substrate (for example, silicon substrate) 212, a plurality of transistors constituting the logic circuit, the MOS transistor Tr6, the MOS transistor Tr7, and the MOS transistor Tr8 are formed.

  In the second semiconductor substrate 212, a connection conductor 254 connected to the MOS transistor Tr6, the MOS transistor Tr7, and the MOS transistor Tr8 is formed.

  Further, a multilayer wiring layer 255 is formed by forming a plurality of layers of metal wirings 250 so as to be connected to the connection conductors 254.

  The metal wiring is formed of copper (Cu) wiring. A protective film, which is a cap film for the copper wiring (metal wiring) 250, is formed on the multilayer wiring layer 255.

  In addition, an aluminum pad 320 serving as an electrode is formed in the lowermost layer of the multilayer wiring layer 255 of the second semiconductor substrate 212.

  Further, a contact 311 used for electrical connection with the first semiconductor substrate 211 and the third semiconductor substrate 213 is formed on the second semiconductor substrate 212. The contact 311 is connected to the contact 265 of the first semiconductor substrate 211 and is also connected to the aluminum pad 330 a of the third semiconductor substrate 213.

  In addition, a memory circuit is formed on the third semiconductor substrate 213. That is, in the p-type semiconductor well region of the semiconductor substrate (for example, a silicon substrate) 213, a plurality of transistors constituting the memory circuit, the MOS transistor Tr11, the MOS transistor Tr12, and the MOS transistor Tr13 are formed.

  Further, on the third semiconductor substrate 213, a MOS transistor Tr11, a MOS transistor Tr12, and a connection conductor 344 connected to the MOS transistor Tr13 are formed.

  Further, a multilayer wiring layer 345 is formed by forming a plurality of layers of metal wiring 340 so as to be connected to each connection conductor 344.

  The metal wiring is formed of copper (Cu) wiring. A protective film, which is a cap film for copper wiring (metal wiring) 340, is formed on the multilayer wiring layer 345.

  Further, an aluminum pad 330 serving as an electrode is formed on the uppermost layer of the multilayer wiring layer 345.

  In the solid-state imaging device shown in FIG. 6, since the contact 265 and the contact 311 are provided, signal input / output with each of the first semiconductor substrate 211 to the third semiconductor substrate 213 via the aluminum pad 280a. Is possible.

  Note that the solid-state imaging device shown in FIG. 6 also has the second semiconductor substrate 212 and the third semiconductor substrate 213 formed between the interlayer films on the bonding surface 292 as described above with reference to FIGS. to paste together. The second semiconductor substrate 212 and the first semiconductor substrate 211 are configured by bonding interlayer films to each other on the bonding surface 291.

  That is, as described above with reference to FIGS. 3 and 4, first, the circuit surfaces of the two lower semiconductor substrates face each other and are bonded together to form the second semiconductor substrate (second semiconductor substrate 212). Is thinned. Thereafter, the uppermost semiconductor substrate (first semiconductor substrate 211) is bonded and laminated as a back surface type, and further thinned. At this time, after planarizing the upper layer of the contact 311, the first semiconductor substrate 211 is bonded to the second semiconductor substrate 212 as a back surface type.

  By doing so, it is not necessary to use a support substrate for thinning the silicon substrate when stacking circuits.

  In the present technology, an aluminum pad 280 is also provided on the first semiconductor substrate 211. The second semiconductor substrate 212 having a logic circuit that requires input / output of a signal from the outside or the third semiconductor substrate 213 having a memory circuit is not provided with an electrode for external connection, An electrode (aluminum pad 280a) for external connection is provided on the first semiconductor substrate 211 having a sensor circuit.

  By doing in this way, the electrode for external connection can be exposed, without the pad hole 351 becoming deep.

  In the present technology, since the aluminum pad 280 is also provided on the first semiconductor substrate 211, the aluminum pad 280 blocks light caused by hot carriers emitted from each transistor of the second semiconductor substrate 212. You can also

  Thus, in the present technology, it is not necessary to provide a deep pad hole, and light caused by hot carriers can be easily blocked.

  In FIG. 6, the aluminum pad 320 is provided on the second semiconductor substrate and the aluminum pad 330 is provided on the third semiconductor substrate 213, but the aluminum pad 320 and the aluminum pad 330 are not provided. It may be. For example, if the contact 311 is directly connected to the copper wiring 340 of the third semiconductor substrate 213, the aluminum pad 320 and the aluminum pad 330 need not be provided.

  Further, the shape of the contact for electrically connecting the semiconductor substrates is not limited to that shown as the contact 265 and the contact 311. Further, the hole for forming the contact can be opened before the on-chip microlens is formed, so that it may be a deep hole. For example, a contact that penetrates the second semiconductor substrate and connects the copper wiring of the first semiconductor substrate and the copper wiring of the third semiconductor substrate may be provided.

  Or you may make it form the light-shielding body for light-shielding the light resulting from a hot carrier.

  FIG. 8 is a cross-sectional view illustrating a configuration according to another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied. As in FIG. 6, the solid-state imaging device according to this pixel unit is a back-illuminated CMOS image sensor configured by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. Composed. That is, the solid-state imaging device according to the pixel portion shown in FIG.

  In the example shown in the figure, a light shield 360 is disposed in an interlayer film that is the uppermost layer in the drawing of the second semiconductor substrate 212. Thus, light caused by hot carriers emitted from each transistor of the second semiconductor substrate 212 can be more reliably shielded.

  Note that since the aluminum pad 280 is formed on the first semiconductor substrate 211, the light shielding body 360 is not disposed on the first semiconductor substrate 211, and the light shielding body 360 is included in the interlayer film of the second semiconductor substrate 212. Is arranged.

  Since the other configuration in FIG. 8 is the same as that described above with reference to FIG. 6, detailed description thereof is omitted.

  Alternatively, a copper wiring is formed in the interlayer film which is the uppermost layer in the drawing of the second semiconductor substrate 212, and light caused by hot carriers is shielded by a combination of the aluminum pad and the copper wiring. Also good.

  FIG. 9 is a cross-sectional view illustrating a configuration according to still another embodiment of a pixel portion of a solid-state imaging device to which the present technology is applied. As in FIG. 6, the solid-state imaging device according to this pixel unit is a back-illuminated CMOS image sensor configured by stacking a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate. Composed. That is, the solid-state imaging device according to the pixel portion shown in FIG. 9 has a three-layer stacked structure.

  In the example of the figure, a copper wiring 370 is arranged in an interlayer film which is the uppermost layer in the drawing of the second semiconductor substrate 212.

  A part of the contact 311 is formed in the interlayer film which is the uppermost layer in the drawing of the second semiconductor substrate 212. For example, when the contact 311 is formed, if the copper wiring 370 is further formed in the interlayer film, a solid-state imaging device having the configuration shown in FIG. 9 can be obtained.

  If the light is blocked by the combination of the copper wiring 370 and the aluminum pad 280, the light caused by the hot carriers emitted from each transistor of the second semiconductor substrate 212 can be more reliably blocked. In the case of the configuration shown in FIG. 9, for example, as shown in FIG. 6, the degree of freedom in designing the wiring related to the aluminum pad 280 is improved as compared with a case where light shielding is performed only by the aluminum pad 280.

  The other configurations in FIG. 9 are the same as those described above with reference to FIG.

FIG. 10 is a diagram illustrating a schematic configuration of a solid-state imaging device to which the present technology is applied. The solid-state imaging device 401 is configured as a CMOS image sensor, for example.

  A solid-state imaging device 401 in FIG. 10 includes a pixel region (so-called pixel array) 403 in which pixels 402 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate 411, and a peripheral circuit unit. Configured.

  The pixel 402 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors).

  In addition, the pixel 402 can have a shared pixel structure. This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other shared pixel transistor.

  The peripheral circuit portion includes a vertical drive circuit 404, a column signal processing circuit 405, a horizontal drive circuit 406, an output circuit 407, a control circuit 408, and the like.

  The control circuit 408 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device. In other words, the control circuit 408 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 404, the column signal processing circuit 405, the horizontal drive circuit 406, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 404, the column signal processing circuit 405, the horizontal drive circuit 406, and the like.

  The vertical drive circuit 404 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 404 sequentially selects and scans each pixel 402 in the pixel area 403 in the vertical direction in units of rows, and according to the amount of light received in, for example, a photodiode serving as a photoelectric conversion unit of each pixel 402 through the vertical signal line 409. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 405.

  The column signal processing circuit 405 is disposed, for example, for each column of the pixels 402, and performs signal processing such as noise removal on the signal output from the pixels 402 for one row for each pixel column. That is, the column signal processing circuit 405 performs signal processing such as CDS for removing fixed pattern noise unique to the pixel 402, signal amplification, and AD conversion. A horizontal selection switch (not shown) is connected to the horizontal signal line 410 at the output stage of the column signal processing circuit 405.

  The horizontal drive circuit 406 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 405 in order, and outputs a pixel signal from each of the column signal processing circuits 405 to the horizontal signal line. 410 is output.

  The output circuit 407 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 405 through the horizontal signal line 410. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 412 exchanges signals with the outside.

  The solid-state imaging device 401 shown in FIG. 10 is configured as a backside illumination type CMOS image sensor having a three-layer structure. For example, the pixel 402 shown in FIG. 10 is a sensor circuit formed on a first semiconductor substrate, and a peripheral circuit is a logic circuit formed on a second semiconductor substrate or a memory formed on a third semiconductor substrate. A circuit.

  In the above-described embodiment, the aluminum pad 280 is described as being formed on the lowermost layer of the multilayer wiring layer 245 of the first semiconductor substrate 211. However, for example, when the aluminum pad 280 is disposed in the first semiconductor substrate 211, an ESD (Electro-Static Discharge) circuit which is a circuit for protecting the circuit in the first semiconductor substrate 211 from overcurrent is provided. It is necessary and the process is increased.

  In the example described above with reference to FIG. 6, the aluminum pad 280 disposed in the first semiconductor substrate 211 can obtain an effect of shielding light caused by hot carriers. However, since the multilayer wiring layer 245 of the first semiconductor substrate 211 is constituted by three wiring layers, light caused by hot carriers can be shielded without restricting the shape of the copper wiring 240. Thus, it is difficult to arrange the aluminum pad 280.

  For example, the multilayer wiring layer 255 of the second semiconductor substrate 212 is composed of six wiring layers. Therefore, if the aluminum pad 280 is arranged in the second semiconductor substrate 212, the shape of the metal wiring 250 is restricted. It is easy to dispose the aluminum pad 280 so that light caused by hot carriers can be shielded without giving.

  Furthermore, in the above-described embodiment, the contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 has two through-holes that penetrate the first semiconductor substrate 211 in the vertical direction. The conductor embedded in is connected on the light receiving surface (the uppermost surface in the drawing) of the first semiconductor substrate 211. Such a contact is also referred to as a twin contact. The contact 311 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is also configured as a twin contact.

  However, since the twin contact needs to be provided with two through holes, the manufacturing process increases and the area on the substrate increases.

  For example, the first semiconductor substrate 211 penetrates the first semiconductor substrate 211 from the uppermost side in the drawing and reaches the wiring in the multilayer wiring layer 255 of the second semiconductor substrate, and a part thereof is the first semiconductor substrate 211. If the contact reaching the wiring of the multilayer wiring layer 245 is formed, the first semiconductor substrate 211 and the second semiconductor substrate 212 can be electrically connected by providing only one through hole. Such a contact is also referred to as a shared contact.

  If a shared contact is used for electrical connection between semiconductor substrates, the manufacturing process can be simplified and the area on the substrate can be reduced as compared with the case of using a twin contact. .

  Also, a method of directly bonding copper wirings in a multilayer wiring layer when a semiconductor substrate is bonded has been put into practical use. If the copper wirings in the multilayer wiring layer are directly joined to each other, it is not necessary to provide a contact for electrical connection between the semiconductor substrates, which can further simplify the manufacturing process and reduce the area on the substrate. can do. The method of directly bonding copper wirings is also referred to as direct bonding.

  FIG. 11 is a schematic view of a cross-sectional view relating to the configuration of the pixel portion of the solid-state imaging device shown in FIG. As shown in the figure, a pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

  In the configuration of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the third semiconductor substrate 213 side (lower side in the figure), and the first semiconductor substrate 211 and the second semiconductor substrate 212 are It is pasted.

  Further, in the configuration of FIG. 11, the contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, and the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 are used. A contact 311 that is used for general connection is provided. The contacts 265 and 311 are configured as twin contacts.

  FIG. 12 is a diagram schematically illustrating a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  In the configuration of FIG. 12, unlike the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the first semiconductor substrate 211 side (upper side in the drawing) and the first semiconductor substrate 211 and the second semiconductor substrate 211 The semiconductor substrate 212 is bonded.

  12, the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, unlike the case of FIG. A pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

  As illustrated in FIG. 12, the multilayer wiring layer 255 of the second semiconductor substrate 212 is directed to the first semiconductor substrate side, whereby the multilayer wiring layer 255 can block light caused by hot carriers. Further, the aluminum pad 280 is arranged in the multilayer wiring layer 255 composed of six wiring layers, so that the light caused by hot carriers can be blocked without restricting the shape of the metal wiring 250. It becomes easy to arrange the pad 280.

  In addition, since the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (in the second semiconductor substrate). Since it is sufficient to form an ESD circuit, it can be manufactured at low cost.

  Further, in the configuration of FIG. 12, the contact 266 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 and the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 are used. A contact 312 is provided that is used for general connection. The contact 266 and the contact 312 are configured as twin contacts.

  In the configuration of FIG. 12, unlike the case of FIG. 11, the contact 312 passes through the first semiconductor substrate 211 and the second semiconductor substrate 212 and reaches the multilayer wiring layer 345 of the third semiconductor substrate 213. .

  Next, a manufacturing process of the solid-state imaging device shown in FIG. 12 will be described.

  First, as shown in FIG. 13, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 each having a multilayer wiring layer are prepared. As shown in the figure, a multilayer wiring layer 245 is formed on the first semiconductor substrate 211, a multilayer wiring layer 255 is formed on the second semiconductor substrate 212, and a third semiconductor substrate 213 is formed. Is formed with a multilayer wiring layer 345.

  As shown in FIG. 13, an aluminum pad 280 is formed on the multilayer wiring layer 255 of the second semiconductor substrate 212.

  Next, as shown in FIG. 14, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded so that the multilayer wiring layer 245 and the multilayer wiring layer 255 face each other.

  Then, as shown in FIG. 15, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the drawing is thin.

  Next, as illustrated in FIG. 16, the third semiconductor substrate 213 and the second semiconductor substrate 212 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 345 of the third semiconductor substrate faces upward in the drawing.

  Then, as shown in FIG. 17, the first semiconductor substrate 211 is thinned. In the drawing, the width of the first semiconductor substrate 211 in the vertical direction in the drawing is thin.

  Next, as shown in FIG. 18, a contact 312 and a contact 266 are formed. At this time, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the aluminum pad 280 of the multilayer wiring layer 255 from the light receiving surface are provided, and a contact 266 is formed. In addition, a hole reaching the aluminum pad 280 of the multilayer wiring layer 255 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the multilayer wiring layer 345 from the light receiving surface are provided, and a contact 312 is formed.

  Then, as shown in FIG. 19, a pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

  In this way, the solid-state imaging device described above with reference to FIG. 12 is manufactured. In this way, the multilayer wiring layer 255 can block light caused by hot carriers. Further, the aluminum pad 280 is arranged in the multilayer wiring layer 255 composed of six wiring layers, so that the light caused by hot carriers can be blocked without restricting the shape of the metal wiring 250. It becomes easy to arrange the pad 280. In addition, since the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (in the second semiconductor substrate). Since it is sufficient to form an ESD circuit, it can be manufactured at low cost.

  FIG. 20 is a diagram schematically illustrating a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  In the configuration of FIG. 20, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the third semiconductor substrate 213 side (lower side in the drawing) and the first semiconductor substrate 211 and the first semiconductor substrate 211. Two semiconductor substrates 212 are bonded together.

  In the configuration of FIG. 20, as in FIG. 11, the contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, and the second semiconductor substrate 212 and the second semiconductor substrate 212 A contact 311 used for electrical connection with the third semiconductor substrate 213 is provided. The contacts 265 and 311 are configured as twin contacts.

  Further, in the configuration of FIG. 20, unlike the case of FIG. 11, an insulating film layer 230 is formed between the first semiconductor substrate 211 and the second semiconductor substrate 212. An aluminum pad 280 a is disposed in the insulating film layer 230, and the aluminum pad 280 a is connected to the contact 313 connected to the multilayer wiring layer 255 of the second semiconductor substrate 212.

  In the configuration of FIG. 20, the first semiconductor substrate 211 has a pad hole 351 so as to reach the aluminum pad 280a in the insulating film layer 230 from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Is formed.

  In the case of the configuration of FIG. 20, since the aluminum pad 280 is provided in the insulating film layer 230, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (the ESD circuit in the second semiconductor substrate). Can be manufactured at low cost.

  Next, a manufacturing process of the solid-state imaging device shown in FIG. 20 will be described.

  First, as shown in FIG. 21, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 each having a multilayer wiring layer are prepared. As shown in the figure, a multilayer wiring layer 245 is formed on the first semiconductor substrate 211, a multilayer wiring layer 255 is formed on the second semiconductor substrate 212, and a third semiconductor substrate 213 is formed. Is formed with a multilayer wiring layer 345.

  As shown in FIG. 21, the aluminum pad 280 is not formed on the multilayer wiring layer 255 of the second semiconductor substrate 212.

  Next, as shown in FIG. 22, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other.

  Then, as shown in FIG. 23, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the drawing is thin.

  Next, as shown in FIG. 24, a contact 311 and a contact 313 are formed. At this time, a hole reaching the multilayer wiring layer 345 from the upper surface in the drawing of the second semiconductor substrate 212 and a hole reaching the multilayer wiring layer 255 from the upper surface in the drawing of the second semiconductor substrate 212 are provided, A contact 311 is formed. Further, a hole reaching the multilayer wiring layer 255 from the upper surface in the drawing of the second semiconductor substrate 212 is provided, and a contact 313 is formed.

  Then, as shown in FIG. 25, an aluminum pad 280a is formed, and an insulating film layer 230 is formed. As shown in the figure, an aluminum pad 280a is formed so as to be connected to the upper end of the contact 313 in the figure. In addition, an insulating film layer 230 is formed around the aluminum pad 280a on the upper surface of the second semiconductor substrate 212 in the drawing.

  Next, as shown in FIG. 26, the first semiconductor substrate 211 and the second semiconductor substrate 212 (more precisely, the insulating film layer 230) are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded so that the multilayer wiring layer 245 is in contact with the insulating film layer 230.

  Further, the first semiconductor substrate 211 is thinned. In FIG. 26, the width of the first semiconductor substrate 211 in the vertical direction in the drawing is thin.

  27, a pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Thereafter, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the contact 311 from the light receiving surface are provided, and a contact 265 is formed.

  In this way, the solid-state imaging device described above with reference to FIG. 20 is manufactured. Since the aluminum pad 280 is provided in the insulating film layer 230, it is not necessary to form an ESD circuit in the first semiconductor substrate 211 (since the ESD circuit may be formed in the second semiconductor substrate). It becomes possible to manufacture at low cost.

  FIG. 28 is a diagram schematically illustrating a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  In the configuration of FIG. 28, as in the case of FIG. 11, a pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280 a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Has been. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

  In the configuration of FIG. 28, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the third semiconductor substrate 213 side (the lower side in the figure) and the first semiconductor substrate 211 is placed. And the second semiconductor substrate 212 are bonded to each other.

  Further, in the configuration of FIG. 28, as in the case of FIG. 11, a contact 265 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is provided. The contact 265 is configured as a twin contact.

  In the configuration of FIG. 28, unlike the case of FIG. 11, the contact 311 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is not provided. On the other hand, a contact 314 and a contact 315 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 are provided.

  Each of the contact 314 and the contact 315 is formed by burying a conductor by providing a through hole that penetrates the second semiconductor substrate 212 and reaches the multilayer wiring layer 345 of the third semiconductor substrate 213. That is, each of the contact 314 and the contact 315 is configured to connect the multilayer wiring layer 255 of the second semiconductor substrate 212 and the multilayer wiring layer 345 of the third semiconductor substrate 213 by providing only one through hole. Yes.

  That is, each of the contact 314 and the contact 315 is configured as a shared contact.

  In the configuration shown in FIG. 28, by using the shared contact, the manufacturing process can be simplified and the area on the substrate can be reduced.

  Here, although it has been described that a shared contact is used for the electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is described. It is also possible to use a shared contact for connection.

  Also in the solid-state imaging device having the configuration described above with reference to FIG. 11, FIG. 12, or FIG. 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second A shared contact may be used for electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213.

  That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), a shared contact may be used for electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), a shared contact may be used for electrical connection between the semiconductor substrates. Furthermore, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), a shared contact may be used for electrical connection between the semiconductor substrates.

  FIG. 29 is a diagram schematically illustrating a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  In the configuration of FIG. 29, as in the case of FIG. 11, a pad hole 351 is formed in the first semiconductor substrate 211 so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211. Has been. An aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211.

  In the configuration of FIG. 29, as in the case of FIG. 11, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the third semiconductor substrate 213 side (lower side in the figure) and the first semiconductor substrate 211 is arranged. And the second semiconductor substrate 212 are bonded to each other.

  Further, in the configuration of FIG. 29, a contact 267 used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 is provided. The contact 267 is configured as a twin contact.

  29, the metal wiring 250a in the multilayer wiring layer 255 of the second semiconductor substrate 212 and the metal wiring 340a in the multilayer wiring layer 345 of the third semiconductor substrate 213 are directly joined. Furthermore, the metal wiring 250b in the multilayer wiring layer 255 and the metal wiring 340b in the multilayer wiring layer 345 are directly joined. As a result, the second semiconductor substrate 212 and the third semiconductor substrate 213 are electrically connected.

  That is, in the case of the configuration in FIG. 29, direct bonding is used without electrical contact for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213. Therefore, the manufacturing process can be simplified and the area on the substrate can be reduced.

  The direct bonding is disclosed in detail in, for example, JP2013-033900A.

  Next, a manufacturing process of the solid-state imaging device shown in FIG. 29 will be described.

  First, as shown in FIG. 30, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 each having a multilayer wiring layer are prepared. As shown in the figure, a multilayer wiring layer 245 is formed on the first semiconductor substrate 211, a multilayer wiring layer 255 is formed on the second semiconductor substrate 212, and a third semiconductor substrate 213 is formed. Is formed with a multilayer wiring layer 345.

  As shown in FIG. 30, an aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211. Also, metal wiring 250a and metal wiring 250b are formed in the multilayer wiring layer 255 of the second semiconductor substrate, and metal wiring 340a and metal wiring 340b are formed in the multilayer wiring layer 345 of the third semiconductor substrate. Yes.

  Next, as shown in FIG. 31, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other. Then, the metal wiring 250a and the metal wiring 340a are directly bonded, and the metal wiring 250b and the metal wiring 340b are directly bonded.

  Further, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the drawing is thin.

  Then, as shown in FIG. 32, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the multilayer wiring layer 255 of the second semiconductor substrate is directed to the third semiconductor substrate 213 side (lower side in the drawing), and the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together.

  Further, the first semiconductor substrate 211 is thinned. In the drawing, the width of the first semiconductor substrate 211 in the vertical direction in the drawing is thin.

  Next, as shown in FIG. 33, a contact 267 is formed. At this time, a hole reaching the multilayer wiring layer 245 from the light receiving surface of the first semiconductor substrate 211 and a hole reaching the multilayer wiring layer 255 from the light receiving surface are provided, and a contact 267 is formed.

  Then, as shown in FIG. 34, a pad hole 351 is formed so as to reach the aluminum pad 280a from the back surface side (light receiving surface side) of the first semiconductor substrate 211.

  In this way, the solid-state imaging device described above with reference to FIG. 29 is manufactured. Since direct bonding is used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213 without using a contact, the manufacturing process can be simplified, and the area on the substrate can be reduced. Can be small.

  Here, description has been made assuming that direct bonding is used for electrical connection between the second semiconductor substrate 212 and the third semiconductor substrate 213, but electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is used. It is also possible to use a direct bond for connection.

  Also in the solid-state imaging device having the configuration described above with reference to FIG. 11, FIG. 12, or FIG. 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second Direct bonding may be used for electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213.

  That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), direct bonding may be used for electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), direct bonding may be used for electrical connection between the semiconductor substrates. Further, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), direct bonding may be used for electrical connection between the semiconductor substrates.

  FIG. 35 is a diagram schematically illustrating a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  35, unlike the case of FIG. 29, a contact 268 and a contact 316 used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 are provided. That is, in the configuration of FIG. 35, the lower end portion on the left side of the contact 268 in the drawing is connected to the upper end portion of the contact 316 in the drawing, whereby the first semiconductor substrate 211 and the second semiconductor substrate 212 are connected. Electrically connected. The contact 268 is configured as a twin contact.

  In the configuration of FIG. 35, for example, it is not necessary to provide a hole reaching the multilayer wiring layer 255 from the light receiving surface as in the formation of the contact 267 of FIG. For this reason, it becomes possible to form a contact more simply.

  The configuration of other parts in FIG. 35 is the same as that in FIG. 29, and thus detailed description thereof is omitted.

  Next, a manufacturing process of the solid-state imaging device shown in FIG. 35 will be described.

  First, as shown in FIG. 36, a first semiconductor substrate 211, a second semiconductor substrate 212, and a third semiconductor substrate 213 each having a multilayer wiring layer are prepared. As shown in the figure, a multilayer wiring layer 245 is formed on the first semiconductor substrate 211, a multilayer wiring layer 255 is formed on the second semiconductor substrate 212, and a third semiconductor substrate 213 is formed. Is formed with a multilayer wiring layer 345.

  36, an aluminum pad 280 is formed on the multilayer wiring layer 245 of the first semiconductor substrate 211. As shown in FIG. Also, metal wiring 250a and metal wiring 250b are formed in the multilayer wiring layer 255 of the second semiconductor substrate, and metal wiring 340a and metal wiring 340b are formed in the multilayer wiring layer 345 of the third semiconductor substrate. Yes.

  Next, as shown in FIG. 37, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded together. At this time, the second semiconductor substrate 212 and the third semiconductor substrate 213 are bonded so that the multilayer wiring layer 255 and the multilayer wiring layer 345 face each other. Then, the metal wiring 250a and the metal wiring 340a are directly bonded, and the metal wiring 250b and the metal wiring 340b are directly bonded.

  Further, the second semiconductor substrate 212 is thinned. In the figure, the width of the second semiconductor substrate 212 in the vertical direction in the drawing is thin.

  Then, as shown in FIG. 38, a contact 316 is formed. At this time, a hole reaching the multilayer wiring layer 255 from the upper surface of the second semiconductor substrate 212 in the drawing is provided, and a contact 316 is formed.

  Next, as shown in FIG. 39, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded together. At this time, the first semiconductor substrate 211 and the second semiconductor substrate 212 are bonded so that the back surface of the first semiconductor substrate 211 becomes a light receiving surface.

  Further, the first semiconductor substrate 211 is thinned. In FIG. 39, the width of the first semiconductor substrate 211 in the vertical direction in the drawing is thin.

  Further, a hole reaching from the light receiving surface of the first semiconductor substrate 211 to the upper surface in the drawing of the second semiconductor substrate and a hole reaching from the light receiving surface to the aluminum pad 280 of the multilayer wiring layer 245 are provided. Is formed.

  Then, as shown in FIG. 40, a pad hole 351 is formed so as to reach the aluminum pad 280a from the light receiving surface of the first semiconductor substrate 211.

  In this way, the solid-state imaging device described above with reference to FIG. 35 is manufactured. In the configuration of FIG. 35, as described above, the contact 268 and the contact 316 are used to electrically connect the first semiconductor substrate 211 and the second semiconductor substrate 212. That is, the conductor forming the contact 268 and the conductor forming the contact 316 are bonded to each other at the bonding surface between the first semiconductor substrate 211 and the second semiconductor substrate 212. As described above, in the configuration of FIG. 35, a part of the twin contact for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is divided into two stages.

  By doing so, there is no need to provide a deep hole reaching the multilayer wiring layer 255 from the light receiving surface, for example, as in the formation of the contact 267 in FIG. For this reason, it becomes possible to form a contact more simply.

  Here, a part of a twin contact used for electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212 is described as being divided into two stages, but the second semiconductor substrate 212 is described. A part of the twin contact used for electrical connection between the semiconductor substrate 213 and the third semiconductor substrate 213 may be divided into two stages.

  Also in the solid-state imaging device having the configuration described above with reference to FIG. 11, FIG. 12, or FIG. 20, the electrical connection between the first semiconductor substrate 211 and the second semiconductor substrate 212, or the second A part of a twin contact used for electrical connection between the semiconductor substrate 212 and the third semiconductor substrate 213 may be divided into two stages.

  That is, in the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 245 of the first semiconductor substrate 211 (FIG. 11), a part of the twin contact used for electrical connection between the semiconductor substrates is divided into two stages. You may make it comprise. In the configuration in which the aluminum pad 280 is provided in the multilayer wiring layer 255 of the second semiconductor substrate 212 (FIG. 12), a part of the twin contact used for electrical connection between the semiconductor substrates is divided into two stages. You may make it comprise. Further, in the configuration in which the aluminum pad 280 is provided in the insulating film layer 230 (FIG. 20), a part of the twin contact used for electrical connection between the semiconductor substrates is divided into two stages. Also good.

  As described above with reference to FIGS. 11 to 40, in the solid-state imaging device to which the present technology is applied, the aluminum pad 280 may be provided in the multilayer wiring layer 245 of the first semiconductor substrate 211. The aluminum pad 280 may be provided in the multilayer wiring layer 255 of the second semiconductor substrate 212, or the aluminum pad 280 may be provided in the insulating film layer 230. In addition, as a form of electrical connection between the semiconductor substrates, a configuration in which a twin contact, a shared contact, a direct junction, and a part of the twin contact are divided into two stages can be adopted.

  That is, a combination as shown in FIG. 41 can be adopted as an embodiment of a solid-state imaging device to which the present technology is applied.

  In the above-described embodiment, the embodiment of the solid-state imaging device to which the present technology is applied has been described on the assumption of a three-layer structure. However, a solid-state imaging device to which the present technology is applied can adopt, for example, a four-layer structure in which a first semiconductor substrate, a second semiconductor substrate, a third semiconductor substrate, and a fourth semiconductor substrate are stacked. It is.

FIG. 42 shows an example where a four-layer structure is adopted in a solid-state imaging device to which the present technology is applied.
FIG. 42 is a schematic view of a cross-sectional view illustrating a configuration according to still another embodiment of the pixel portion of the solid-state imaging device to which the present technology is applied.

  In the example of FIG. 42, a four-layer structure in which a first semiconductor substrate 211, a second semiconductor substrate 212, a third semiconductor substrate 213, and a fourth semiconductor substrate 214 are stacked is employed.

  Similarly, it is possible to adopt a structure of five layers or more in the solid-state imaging device to which the present technology is applied.

  FIG. 43 is a block diagram illustrating a configuration example of a camera device as an electronic apparatus to which the present technology is applied.

  A camera apparatus 600 in FIG. 43 includes an optical unit 601 including a lens group, a solid-state imaging apparatus (imaging device) 602 that employs the above-described configuration of the pixel 402, and a DSP circuit 603 that is a camera signal processing circuit. The camera device 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608. The DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus line 609.

  The optical unit 601 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 602. The solid-state imaging device 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electrical signal for each pixel and outputs it as a pixel signal. As the solid-state imaging device 602, the solid-state imaging device according to the above-described embodiment can be used.

  The display unit 605 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 602. The recording unit 606 records a moving image or a still image captured by the solid-state imaging device 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation unit 607 issues operation commands for various functions of the camera device 600 under the operation of the user. The power supply unit 608 appropriately supplies various power sources serving as operation power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.

  In addition, the present technology is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image. Applicable to imaging devices and, in a broad sense, solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images as images. is there.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  211 First semiconductor substrate, 212 Second semiconductor substrate, 213 Third semiconductor substrate, 230 Insulating film layer, 234 Photodiode, 245 Multi-layer wiring layer, 240 Copper wiring, 255 Multi-layer wiring layer, 250 Copper wiring, 265 Contacts , 266 contact, 267 contact, 280 aluminum pad, 311 contact, 312 contact, 313 contact, 320 aluminum pad, 330 aluminum pad, 340 copper wiring, 345 multilayer wiring layer, 351 pad hole, 360 light-shielding body, 370 copper wiring, 401 Solid-state imaging device, 402 pixels, 600 camera device, 602 solid-state imaging device

Claims (26)

A first semiconductor substrate including a first wiring layer on one side of the opposing surface, a photodiode on the other side of the opposing surface, and at least a transfer transistor, a reset transistor, and an amplifier transistor;
A second semiconductor substrate including a second wiring layer and a plurality of transistors on one side of the opposing surface, and connected to the first semiconductor substrate;
A third semiconductor substrate including a third wiring layer on one side of the opposing surface and connected to the second semiconductor substrate;
The first semiconductor substrate, the second semiconductor substrate, and the first semiconductor substrate are stacked,
The first semiconductor substrate has a first connection portion connected to the first wiring layer,
The second semiconductor substrate has a second connection portion extending in the lateral direction on the other side of the opposing surface of the second semiconductor substrate,
The second connection portion is connected to the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate,
The plurality of transistors are arranged in a vertical direction between opposing surfaces of the second semiconductor substrate. The solid-state imaging device according to claim 1, wherein the first connection portion is formed by embedding a conductive material in two through holes opened in the first semiconductor substrate. The solid-state imaging device according to claim 2, wherein the conductive material embedded in the two through holes is connected on a light receiving surface side of the first semiconductor substrate. At least one of the two through holes opened in the first semiconductor substrate passes through the first semiconductor substrate and a connection layer between the first semiconductor substrate and the second semiconductor substrate. The solid-state imaging device according to claim 3. The solid-state imaging device according to claim 4, wherein a pad hole that is opened from the light receiving surface side to the pad is formed in the first semiconductor substrate. The solid-state imaging device according to claim 5, wherein the pad is formed in the first wiring layer of the first semiconductor substrate. The solid-state imaging device according to claim 4, further comprising an insulating film layer between the first semiconductor substrate and the second semiconductor substrate. The solid-state imaging device according to claim 7, wherein a pad is formed on the insulating film layer. The solid-state imaging device according to claim 4, wherein the second wiring layer and the third wiring layer are connected to face each other. The second connection portion is formed by embedding a conductive material in two through holes opened in the second semiconductor substrate,
The solid-state imaging device according to claim 9, wherein the conductive material embedded in the two through holes is connected in an interlayer film of the second semiconductor substrate. The solid-state imaging device according to claim 10, wherein the interlayer film is formed on an uppermost layer of the second semiconductor substrate. The solid-state imaging according to claim 11, wherein one of the two through-holes opened in the second semiconductor substrate reaches the third wiring layer of the third semiconductor substrate from the surface of the second semiconductor substrate. apparatus. The solid-state imaging device according to claim 12, wherein the one of the two through holes opened in the second semiconductor substrate penetrates the second semiconductor substrate and the second wiring layer. The solid-state imaging device according to claim 1, further comprising a light shielding film formed on a surface of the first semiconductor substrate. The solid-state imaging device according to claim 1, further comprising an on-chip color filter that covers the photodiode. The solid-state imaging device according to claim 15, further comprising an on-chip microlens formed above the on-chip color filter. The second connection portion is formed by embedding a conductive material in two through holes opened in the second semiconductor substrate,
The solid-state imaging device according to claim 1, wherein the conductive material embedded in the two through holes is connected in an interlayer film of the second semiconductor substrate. The solid-state imaging device according to claim 17, wherein the interlayer film is formed on an uppermost layer of the second semiconductor substrate. 18. The solid-state imaging according to claim 17, wherein one of the two through holes opened in the second semiconductor substrate reaches the third wiring layer of the third semiconductor substrate from the surface of the second semiconductor substrate. apparatus. The solid-state imaging device according to claim 19, wherein the one of the two through holes opened in the second semiconductor substrate penetrates the second semiconductor substrate and the second wiring layer. The solid-state imaging device according to claim 1, wherein the third wiring layer and the second wiring layer are connected to face each other. The solid-state imaging device according to claim 1, further comprising a pad electrode for external connection. The solid-state imaging device according to claim 22, wherein the pad electrode is arranged to shield light generated from one or a plurality of the transistors of the second semiconductor substrate. The first semiconductor substrate includes a sensor circuit;
At least one of the second semiconductor substrate or the third semiconductor substrate includes a logic circuit,
The solid-state imaging device according to claim 1, wherein at least one of the second semiconductor substrate and the third semiconductor substrate includes a memory circuit. The solid-state imaging device according to claim 1, wherein the third semiconductor substrate includes a plurality of transistors. An optical unit including at least one lens for receiving incident light;
In an electronic apparatus having a solid-state imaging device that receives the incident light,
The solid-state imaging device
A first semiconductor substrate including a first wiring layer on one side of the opposing surface, a photodiode on the other side of the opposing surface, and at least a transfer transistor, a reset transistor, and an amplifier transistor;
A second semiconductor substrate including a second wiring layer and a plurality of transistors on one side of the opposing surface, and connected to the first semiconductor substrate;
A third semiconductor substrate including a third wiring layer on one side of the opposing surface and connected to the second semiconductor substrate;
The first semiconductor substrate, the second semiconductor substrate, and the first semiconductor substrate are stacked,
The first semiconductor substrate has a first connection portion connected to the first wiring layer,
The second semiconductor substrate has a second connection portion extending in the lateral direction on the other side of the opposing surface of the second semiconductor substrate,
The second connection portion is connected to the second wiring layer of the second semiconductor substrate and the third wiring layer of the third semiconductor substrate,
The plurality of transistors are arranged in a vertical direction between corresponding surfaces of the second semiconductor substrate.

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