JP2020532118A - Systems and methods that allow repair of the first interconnect of power module dies - Google Patents

Systems and methods that allow repair of the first interconnect of power module dies Download PDF

Info

Publication number
JP2020532118A
JP2020532118A JP2020509524A JP2020509524A JP2020532118A JP 2020532118 A JP2020532118 A JP 2020532118A JP 2020509524 A JP2020509524 A JP 2020509524A JP 2020509524 A JP2020509524 A JP 2020509524A JP 2020532118 A JP2020532118 A JP 2020532118A
Authority
JP
Japan
Prior art keywords
interconnect
power module
interconnects
periodic current
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020509524A
Other languages
Japanese (ja)
Other versions
JP6968264B2 (en
Inventor
エヴァンチュク、ジェフリー
ブランデレロ、ジュリオ
モロヴ、ステファン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric R&D Centre Europe BV Netherlands
Original Assignee
Mitsubishi Electric R&D Centre Europe BV Netherlands
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric R&D Centre Europe BV Netherlands filed Critical Mitsubishi Electric R&D Centre Europe BV Netherlands
Publication of JP2020532118A publication Critical patent/JP2020532118A/en
Application granted granted Critical
Publication of JP6968264B2 publication Critical patent/JP6968264B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)
  • Inverter Devices (AREA)

Abstract

本発明は、ダイを電気回路に接続する、パワーモジュールのダイの第１の相互接続体の修復を可能にするシステムに関する。システムは、パワーモジュールの少なくとも１つの他の相互接続体と、所定の持続時間の間に第１の相互接続体の少なくとも一部において所定の温度に達するために少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、少なくとも１つの他の相互接続体に接続される周期電流源とを備える。本発明はまた、関連する方法に関する。The present invention relates to a system that allows repair of a first interconnect of die of a power module that connects the die to an electrical circuit. The system has at least one other interconnect of the power module and at least one other interconnect to reach a predetermined temperature in at least a portion of the first interconnect over a predetermined duration. It comprises a periodic current source connected to at least one other interconnect so as to generate a periodic current flow through. The present invention also relates to related methods.

Description

本発明は、包括的には、パワーモジュールのダイの相互接続体の修復を可能にするデバイス及び方法及びシステムに関する。 Comprehensively, the present invention relates to devices, methods and systems that allow repair of die interconnects of power modules.

アプリケーションに組み込まれたパワーモジュールには、各々が異なる特性を有する種々の層状材料から構成されているという事実があるため、劣化が発生する。 Deterioration occurs due to the fact that the power modules incorporated in the application are each composed of various layered materials with different properties.

パワーモジュールは、動作中、大きな温度の逸脱をサポートしなければならない。動作に固有する劣化は、はんだ層又はボンディングワイヤ等の様々な界面層におけるクラックの増大として現れる。 The power module must support large temperature deviations during operation. The degradation inherent in operation manifests itself as an increase in cracks in various interfacial layers such as solder layers or bonding wires.

劣化を抑制するために、パワーモジュールは、より整合するような材料を用いて設計されるが、この解決法では、多くの場合、電気的性能が不十分になるとともに製造コストが高くなる。さらに、これらの追加の製造コストが必要となることに起因して、最も過酷な使用条件に適応するようにパワーモジュールを設計することは現実的ではなく、パワーモジュールの寿命が短くなるため、ストレスが多いアプリケーションとなる。 To control degradation, power modules are designed with more consistent materials, but this solution often results in poor electrical performance and high manufacturing costs. In addition, due to these additional manufacturing costs, it is impractical to design the power module to adapt to the harshest operating conditions, which shortens the life of the power module and is stressful. It becomes an application with many.

通常、劣化によって故障が起こると、パワーモジュールは交換され、ミッションの停止時間と、パワーモジュールの交換が必要となるための追加コストとが必要になる。多くのアプリケーションにおいて、パワーモジュールの故障による停止時間、介入及び予測不可能性によるコスト増大は甚だしく、パワーエレクトロニクスを用いる全体の金銭的利益をなくしてしまう可能性がある。 Usually, when a failure occurs due to deterioration, the power module is replaced, which requires a mission downtime and an additional cost for the power module to need to be replaced. In many applications, downtime due to power module failure, interventions and unpredictable cost increases can be significant and can eliminate the overall financial benefit of using power electronics.

パワーモジュールの弱点は上面における相互接続体にある。この相互接続体では、アルミニウムボンディングワイヤ及び／又は銅の相互接続体における微細構造のクラックが生じやすい。 The weakness of power modules lies in the interconnects on the top surface. In this interconnect, microstructure cracks in the aluminum bonding wire and / or copper interconnect are prone to occur.

本発明は、パワーモジュールのダイの少なくとも１つの相互接続体の修復を可能にすることを目的とする。 It is an object of the present invention to allow repair of at least one interconnect of power module dies.

このために、本発明は、ダイを電気回路に接続する、パワーモジュールのダイの第１の相互接続体の修復を可能にするシステムに関し、本システムは、
パワーモジュールの少なくとも１つの他の相互接続体と、
第１の相互接続体の少なくとも一部が所定の持続時間内に所定の温度に達するために、少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、少なくとも１つの他の相互接続体に接続される周期電流源と、
を備えることを特徴とする。 To this end, the present invention relates to a system that connects a die to an electrical circuit, allowing repair of the first interconnect of the die of the power module.
With at least one other interconnect of power modules,
At least one other interconnect so that at least a portion of the first interconnect produces a periodic current flow through at least one other interconnect in order to reach a predetermined temperature within a predetermined duration. The periodic current source connected to the connector and
It is characterized by having.

本発明はまた、ダイを電気回路に接続する、パワーモジュールのダイの第１の相互接続体の修復を可能にする方法に関し、本方法は、
第１の相互接続体の少なくとも一部が所定の温度に達するために、少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、周期電流源をパワーモジュールの少なくとも１つの他の相互接続体に接続するステップと、
所定の持続時間内に所定の温度において周期電流源を制御するステップと、
を含むことを特徴とする。 The present invention also relates to a method that allows repair of a first interconnect of dies of a power module that connects the dies to an electrical circuit.
The periodic current source is at least one other of the power module so that at least a portion of the first interconnect produces a periodic current flow through at least one other interconnect in order to reach a predetermined temperature. Steps to connect to the interconnect,
A step of controlling a periodic current source at a given temperature within a given duration, and
It is characterized by including.

このようにすることによって、パワーモジュールの健全性（health）は、単純な介入によって修復することができる。 By doing so, the health of the power module can be repaired with a simple intervention.

特に、相互接続体における微細構造のクラックは、相互接続体の温度を上昇させるだけでなく、これらのクラックに沿う応力を上昇させ、それによってこの範囲における拡散速度を上昇させるため、高周波電流を注入する標的となる。この拡散によってクラックは修復し、その結果、パワーモジュールの寿命が延びる。 In particular, microstructured cracks in the interconnect not only raise the temperature of the interconnect, but also increase the stress along these cracks, thereby increasing the diffusion rate in this range, thus injecting high frequency currents. Become a target. This diffusion repairs the cracks, thus extending the life of the power module.

特定の特徴によれば、第１の相互接続体の第１の端子はダイに接続され、少なくとも１つの第２の相互接続体の第１の端子は、第１の相互接続体の第１の端子に接続され、周期電流源は、相互接続体を通る周期電流フローを生成するように両方の相互接続体の第２の端子に接続される。 According to certain features, the first terminal of the first interconnect is connected to the die and the first terminal of at least one second interconnect is the first terminal of the first interconnect. Connected to the terminals, the periodic current source is connected to the second terminal of both interconnects to generate a periodic current flow through the interconnect.

したがって、パワーモジュールの単純かつ低コストである変更によって修復プロセスが可能になる。 Therefore, simple and low-cost changes to the power module enable the repair process.

周期電流を注入しても半導体コンポーネントには無害である。なぜなら、この電流は、ダイの上面メタライゼーション部および相互接続体を通して短絡されているため、温度は、通常は１７５℃である臨界シリコン温度未満に維持されるからである。 Injecting periodic current is harmless to semiconductor components. This is because this current is shorted through the die's top metallization section and interconnect so that the temperature is maintained below the critical silicon temperature, which is typically 175 ° C.

特定の特徴によれば、相互接続体はボンディングワイヤである。 According to certain features, the interconnect is a bonding wire.

したがって、修復プロセスを、融通性及び低コストでの製造することが求められるパッケージに適用することができる。 Therefore, the repair process can be applied to packages that are required to be manufactured flexibly and at low cost.

特定の特徴によれば、ボンディングワイヤはアルミニウム合金ボンディングワイヤである。 According to certain features, the bonding wire is an aluminum alloy bonding wire.

したがって、修復プロセスは、現行技術水準のパワーモジュールパッケージで見られる標準的な合金に対して適用可能である。 Therefore, the repair process is applicable to the standard alloys found in current state-of-the-art power module packages.

特定の特徴によれば、周期電流源が発生する電流は、１００ｋＨｚを超える周波数及び８２アンペア〜１０８アンペアのＲＭＳ値の矩形波信号又は正弦波信号である。 According to certain features, the current generated by the periodic current source is a square or sinusoidal signal with a frequency above 100 kHz and an RMS value of 82 amps to 108 amps.

したがって、電流源は、標準的なパワーエレクトロニクスコンバータ技術によって開発することができる。 Therefore, the current source can be developed by standard power electronics converter technology.

特定の特徴によれば、所定の温度は１５０℃〜２００℃の間であり、所定の持続時間は５０時間〜１００時間の間である。 According to certain characteristics, the predetermined temperature is between 150 ° C. and 200 ° C. and the predetermined duration is between 50 and 100 hours.

したがって、修復プロセスは、保守のためにコンバーターが停止している短い期間中に行うことができる。 Therefore, the repair process can be performed during a short period of time when the converter is stopped for maintenance.

特定の特徴によれば、相互接続体は銅ビアであり、周期電流源は他の２つの相互接続体に接続され、パワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの誘導コイルを更に備える。 According to certain features, the interconnect is a copper via, the periodic current source is connected to the other two interconnects, and the power module is at least one of the first interconnects within a predetermined duration. It further comprises one induction coil connected to the two interconnects in order for the portions to reach a predetermined temperature.

したがって、修復プロセスは、銅ビアに対する直接の接触を伴わず、局所的な熱を印加することによって、組込みパッケージにおいて開始することができる。 Therefore, the repair process can be initiated in the built-in package by applying local heat without direct contact with the copper vias.

特定の特徴によれば、相互接続体は銅ビアであり、周期電流源は他の２つの相互接続体に接続され、パワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの磁気構造体を更に備える。 According to certain features, the interconnect is a copper via, the periodic current source is connected to the other two interconnects, and the power module is at least one of the first interconnects within a predetermined duration. It further comprises one magnetic structure connected to the two interconnects in order for the portions to reach a predetermined temperature.

したがって、修復プロセスは、銅ビアに対する直接の接触を伴わず、局所的な熱及び誘導された電流フローを印加することによって、組込みパッケージにおいて開始することができる。 Therefore, the repair process can be initiated in the built-in package by applying local heat and induced current flow without direct contact with the copper vias.

本発明の特徴は、例示の実施形態の以下の説明を読むことによってより明らかになる。この説明は、添付図面に関して作成されたものである。 The features of the present invention will become more apparent by reading the following description of the exemplary embodiments. This description was made with respect to the accompanying drawings.

パワーモジュールのアルミニウムボンディングワイヤの上面相互接続体の一例を表す図である。It is a figure which shows an example of the upper surface interconnect of the aluminum bonding wire of a power module. 本発明を実施することを可能にする少なくとも１つの追加接続体を備えるパワーモジュールの側面図である。It is a side view of the power module including at least one additional connection which makes it possible to carry out this invention. ボンディングワイヤにおけるクラックと、ボンディングワイヤにおけるパルス電流フローとを表す拡大図である。It is an enlarged view which shows the crack in a bonding wire, and the pulse current flow in a bonding wire. ボンディングワイヤにおけるクラックと、ボンディングワイヤにおけるパルス電流フローと、本発明によるクラックの回復プロセス（healing process）とを表す拡大図である。It is an enlarged view which shows the crack in a bonding wire, the pulse current flow in a bonding wire, and the crack healing process according to the present invention. 少なくとも１つの追加接続体と、本発明を実施することを可能にする少なくとも１つの組込み誘導コイルとを備えるパワーモジュールの側面図である。FIG. 5 is a side view of a power module comprising at least one additional connector and at least one built-in induction coil that makes it possible to carry out the present invention. 少なくとも１つの追加接続体と、本発明を実施することを可能にする少なくとも１つの組込み磁気構造体とを備えるパワーモジュールの側面図である。FIG. 5 is a side view of a power module comprising at least one additional connector and at least one embedded magnetic structure that makes it possible to carry out the present invention. 本発明によるコントローラーのアーキテクチャの一例を表す図である。It is a figure which shows an example of the architecture of the controller by this invention. パワーダイの少なくとも１つの上部接続体の回復プロセスを制御するアルゴリズムを表す図である。FIG. 5 represents an algorithm that controls the recovery process of at least one top connector on a power die.

図１は、パワーモジュールのアルミニウムボンディングワイヤの上面相互接続体の一例を表している。 FIG. 1 shows an example of an upper surface interconnect of aluminum bonding wires of a power module.

ボンディングワイヤＢｄは、メタライゼーション層Ｍｅを介してダイＤｉ上に固定されている。 The bonding wire Bd is fixed on the die Di via the metallization layer Me.

ボンディングワイヤＢｄには、微細構造のクラックＣｒが生じている。図２は、本発明を実施することを可能にする少なくとも１つの追加接続体を備えるパワーモジュールの側面図を表している。 Crack Cr having a fine structure is generated in the bonding wire Bd. FIG. 2 represents a side view of a power module with at least one additional connector that makes it possible to carry out the present invention.

従来のパワーモジュールは、上部相互接続体Ｃｎ２０及びＣｎ２１を備える。相互接続体Ｃｎ２０及びＣｎ２１は、ベースプレートＢＰ及びヒートシンクＨＳに固定されるダイレクト銅ボンディングＤＣＢの銅層２０及び２１上にそれぞれ固定されている。 Conventional power modules include upper interconnects Cn20 and Cn21. The interconnects Cn20 and Cn21 are fixed on the copper layers 20 and 21 of the direct copper bonding DCB fixed to the base plate BP and the heat sink HS, respectively.

相互接続体Ｃｎ２１及び銅層２１は、微細構造のクラックが生じている可能性があるボンディングワイヤＢｄ２１によってダイＤｉに接続されている。 The interconnect Cn21 and the copper layer 21 are connected to the die Di by a bonding wire Bd21 that may have cracks in the microstructure.

本発明によれば、パワーモジュールは、ダイレクト銅ボンディングＤＣＢの銅層２２上に固定される追加相互接続体Ｃｎ２２を更に備える。相互接続体Ｃｎ２２、銅層２２は、追加ボンディングワイヤＢｄ２２によってダイＤｉに接続されている。 According to the present invention, the power module further comprises an additional interconnect Cn22 fixed on the copper layer 22 of the direct copper bonding DCB. The interconnect Cn22 and the copper layer 22 are connected to the die Di by the additional bonding wire Bd22.

相互接続体Ｃｎ２１、Ｃｎ２２、銅層２１及び２２、ボンディングワイヤＢｄ２１及びＢｄ２２が電路を形成する。 The interconnects Cn21 and Cn22, the copper layers 21 and 22, and the bonding wires Bd21 and Bd22 form an electric circuit.

相互接続体Ｃｎ２１及びＣｎ２２が、例えば高周波電流源のような電源に接続されると、電流は、相互接続体Ｃｎ２１及びＣｎ２２、銅層２１及び２２、ボンディングワイヤＢｄ２１及びＢｄ２２を通過する。 When the interconnects Cn21 and Cn22 are connected to a power source such as a high frequency current source, the current passes through the interconnects Cn21 and Cn22, the copper layers 21 and 22, and the bonding wires Bd21 and Bd22.

本発明によれば、高周波電流は、高い構造統合性状態を保持するために定期的な間隔をおいて、相互接続体Ｃｎ２１及びＣｎ２２、銅層２１及び２２、ボンディングワイヤＢｄ２１及びＢｄ２２を通過する。特に、アルミニウムボンディングワイヤにおける微細構造のクラックは、ボンディングワイヤ温度を上昇させるだけでなく、これらのクラックに沿う応力を上昇させ、それによってこの範囲における拡散速度を上昇させるため、高周波電流を注入する標的となる。この拡散によってクラックは修復し、その結果、パワーモジュールの寿命が延びる。 According to the present invention, high frequency currents pass through interconnects Cn21 and Cn22, copper layers 21 and 22, bonding wires Bd21 and Bd22 at regular intervals to maintain a high structural integrity state. In particular, microstructured cracks in aluminum bonding wires not only increase the temperature of the bonding wire, but also increase the stress along these cracks, thereby increasing the diffusion rate in this range, so targets that inject high frequency currents. It becomes. This diffusion repairs the cracks, thus extending the life of the power module.

高周波電流を注入しても半導体コンポーネントに無害である。なぜなら、高周波電流は、上面メタライゼーション部Ｍｅ、ボンディングワイヤＢｄ２１及びＢｄ２２、並びに相互接続点Ｃｎ２１及びＣｎ２２を通して短絡されており、温度は、通常は１７５℃である臨界Ｓｉ温度未満に維持されるからである。 It is harmless to semiconductor components even if high frequency current is injected. This is because the high frequency current is shorted through the top metallization section Me, the bonding wires Bd21 and Bd22, and the interconnection points Cn21 and Cn22, and the temperature is maintained below the critical Si temperature, which is usually 175 ° C. is there.

追加のボンディングワイヤの数は、従来のパワーモジュールに既に存在するボンディングワイヤの数に少なくとも等しくあるべきであることに留意されたい。 Note that the number of additional bonding wires should be at least equal to the number of bonding wires already present in the conventional power module.

実装の一例として、ダイは６本のボンディングワイヤを備える。各ボンディングワイヤにおける電流密度を９５Ａ／ｍｍ２〜１４３Ａ／ｍｍ２の間で維持するように、注入される高周波電流が８２Ａ〜１０８ＡのＲＭＳ値を有していれば、１４ｍｍのボンディングワイヤ接続体にわたって（周辺温度が３５℃であると仮定して）ボンディングワイヤのピーク温度は１５０℃〜２００℃になる。 As an example of mounting, the die comprises 6 bonding wires. If the injected high frequency current has an RMS value of 82A-108A so that the current density in each bonding wire is maintained between 95A / mm 2 and 143A / mm 2 , then over the 14mm bonding wire connector. The peak temperature of the bonding wire is 150 ° C. to 200 ° C. (assuming the ambient temperature is 35 ° C.).

これほどの高温であれば、５０時間〜１００時間の期間、すなわち介入時間にわたって自己回復特質がボンディングワイヤの微細構造に大きく影響を及ぼすために必要な高拡散速度を誘導するためには十分である。自己回復効果の重要な要素は、物質の高拡散速度を生み出すための、クラックにおける熱応力の持続時間および温度である。 Such a high temperature is sufficient to induce the high diffusion rate required for the self-healing properties to significantly affect the microstructure of the bonding wire over a period of 50 to 100 hours, i.e. the intervention time. .. An important factor in the self-healing effect is the duration and temperature of the thermal stress in the cracks to produce a high diffusion rate of the material.

ここで、自己回復特性を向上するのに、又はより高速の自己拡散速度をもたらすためには、他のアルミニウム合金、すなわちＡｌ−Ｃｕの使用を検討できることに留意しなければならない。 It should be noted here that the use of other aluminum alloys, namely Al—Cu, can be considered to improve the self-healing properties or to provide faster self-diffusion rates.

高周波電流注入は、表皮効果に起因する、クラックの縁に沿うボンディングワイヤの抵抗を更に高めるために必要である。一例として、４００ｕｍのアルミニウムボンディングワイヤに対して５００ｋＨｚの電流を注入することができ、これは、同じ電流の大きさに対するボンディングワイヤにおいて１１５ｕｍの表皮深さ及び４倍の損失に相当する。この電流は、５００ｋＨｚの矩形波信号又は正弦波信号によって構成することができる。 High frequency current injection is necessary to further increase the resistance of the bonding wire along the edge of the crack due to the skin effect. As an example, a current of 500 kHz can be injected into a 400 um aluminum bonding wire, which corresponds to a skin depth of 115 um and a four-fold loss in a bonding wire for the same magnitude of current. This current can be configured with a 500 kHz square or sinusoidal signal.

図３ａは、ボンディングワイヤにおけるクラックと、ボンディングワイヤにおけるパルス電流フローとの拡大図を表している。 FIG. 3a shows an enlarged view of a crack in the bonding wire and a pulse current flow in the bonding wire.

図３ａで、矢印はボンディングワイヤＢｄを流れる高周波電流を表している。 In FIG. 3a, the arrow represents the high frequency current flowing through the bonding wire Bd.

パワーモジュールパッケージにおいて、アルミニウム（９９％Ａｌ合金）ボンディングワイヤは、通常、一番もろいコンポーネントであり、これらのワイヤのリフトオフが最もありふれた故障モードである。ボンディングワイヤが通常稼働中に熱疲労を受けるにつれて、クラックは、ボンディングワイヤとチップメタライゼーション表面の境界内で、外縁から中心に向かって形成される。高周波注入電流を印加するのは、ボンディングワイヤ界面におけるクラックがボンディングワイヤＢｄにおいて微視的レベル、すなわち１ｕｍ〜１０ｕｍである時点が好ましい。パワーモジュールが２０年の稼働寿命に設計されている場合、すなわち、熱サイクルに起因する熱機械摩耗を想定することによって２０年の稼働寿命に設計されている場合、保守間隔は、例えば、約５年とすることができる。 In power module packages, aluminum (99% Al alloy) bonding wires are usually the most fragile component, and lift-off of these wires is the most common failure mode. As the bonding wire undergoes thermal fatigue during normal operation, cracks form from the outer edge to the center within the boundary between the bonding wire and the chip metallization surface. The high frequency injection current is preferably applied when the cracks at the bonding wire interface are at a microscopic level in the bonding wire Bd, that is, 1 um to 10 um. If the power module is designed for a 20 year operating life, i.e., if it is designed for a 20 year operating life by assuming thermomechanical wear due to the thermal cycle, then the maintenance interval is, for example, about 5 Can be a year.

高周波注入電流は、矢印によって示されるようにアルミニウムボンディングワイヤを通過する。クラックは高抵抗の局所点であるので、残りの注入回路部分と比較して、大量の熱がボンディングワイヤ内のクラックゾーンＺｎａに発生する。この局所的な熱が外方向の熱膨張を引き起こし、クラックの両側が高応力及び高温を受けて接着するようになり、それにより、クラック内で物質の拡散が起こるようになる。このような状況下でしばらく経つと、図３ｂに示すようにクラックが修復され、図３ａにおけるクラックゾーンＺｎａは、図３ｂにおけるクラックゾーンＺｎｂに変化する。 The high frequency injection current passes through the aluminum bonding wire as indicated by the arrows. Since the crack is a high resistance local point, a large amount of heat is generated in the crack zone Zna in the bonding wire as compared to the rest of the injection circuit portion. This local heat causes an outward thermal expansion, causing both sides of the crack to adhere under high stress and high temperature, which causes material diffusion within the crack. After a while under such a situation, the crack is repaired as shown in FIG. 3b, and the crack zone Zna in FIG. 3a changes to the crack zone Znb in FIG. 3b.

図４は、少なくとも１つの追加接続体と、本発明を実施することができる少なくとも１つの組込み誘導コイルとを備えるパワーモジュールの側面図を表している。 FIG. 4 represents a side view of a power module comprising at least one additional connector and at least one built-in induction coil capable of carrying out the present invention.

パワーモジュールは、ダイＤｉを外部のコンポーネントと接続する、例えば銅層のような、Ｖｉ１、Ｖｉ２及びＶｉ３と表記されるビアの形態で相互接続体を備える。 The power module comprises an interconnect in the form of vias labeled Vi1, Vi2 and Vi3 that connect the die Di to external components, such as a copper layer.

ダイＤｉは、ソルダー１３０を用いてダイレクト銅ボンディング（ＤＣＢ）基板のうちの銅層１４０上に固定され、セラミック１５０は、コールドプレート上に固定された銅ベースプレート１６０上に固定されている。 The die Di is fixed on the copper layer 140 of the direct copper bonding (DCB) substrate using the solder 130, and the ceramic 150 is fixed on the copper base plate 160 fixed on the cold plate.

本発明によれば、パワーモジュールは、少なくとも１つの相互接続体に対して、組込み誘導コイルＩｎ１及びＩｎ２並びに追加相互接続体Ｅｘｔｐ４１及びＥｘｔｐ４２を更に備える。 According to the present invention, the power module further comprises built-in induction coils In1 and In2 and additional interconnects Extp41 and Extp42 for at least one interconnect.

このように、組込み誘導コイル層Ｉｎ１及びＩｎ２が、各Ｖｉ１、Ｖｉ２及びＶｉ３に沿って加熱コイルを複製するように設置されているので、電流は、各銅ビア内で加熱を誘導するために相互接続体Ｅｘｔｐ４１及びＥｘｔｐ４２を通して注入される。通常、ビア長がビア幅より大きいので、これらの組込みコイルの設置が可能だが、当然ながら、ビアごとのターン数と積層の複雑度との間のトレードオフが存在する。 In this way, the built-in induction coil layers In1 and In2 are installed so as to replicate the heating coil along each Vi1, Vi2 and Vi3, so that the currents are mutually to induce heating in each copper via. It is injected through the connectors Extp41 and Extp42. These built-in coils can usually be installed because the via length is larger than the via width, but of course there is a trade-off between the number of turns per via and the complexity of stacking.

図５は、少なくとも１つの追加接続体と、本発明を実施することができる少なくとも１つの組込み磁気構造体とを備えるパワーモジュールの側面図を表している。 FIG. 5 represents a side view of a power module comprising at least one additional connector and at least one embedded magnetic structure capable of carrying out the present invention.

パワーモジュールは、ダイＤｉを外部のコンポーネントと接続する、例えば銅層のような、Ｖｉ５１、Ｖｉ５２及びＶｉ５３と表記されるビアの形態で相互接続体を備える。 The power module comprises an interconnect in the form of vias labeled Vi51, Vi52 and Vi53 that connect the die Di to external components, such as a copper layer.

ダイＤｉは、ソルダー１３０を用いてダイレクト銅ボンディング（ＤＣＢ）基板のうちの銅層１４０上に固定され、セラミック１５０は、コールドプレート上に固定された銅ベースプレート１６０上に固定されている。 The die Di is fixed on the copper layer 140 of the direct copper bonding (DCB) substrate using the solder 130, and the ceramic 150 is fixed on the copper base plate 160 fixed on the cold plate.

本発明によれば、パワーモジュールは、少なくとも１つの相互接続体に対して、組込み磁気構造体Ｍｍ１、Ｍｍ２、Ｍｍ３及びＭｍ４を更に備える。ニッケル鉄フレーク等の物質を、ＰＣＢ構造内に組み込むことができる。この構造は、変圧器と同じように銅ビアから相互接続表面及びメタライゼーション表面を流れるように電流を誘導するように、配置される。磁気構造体Ｍｍ１及びＭｍ２は第１の変圧器を形成し、磁気構造体Ｍｍ３及びＭｍ４は第２の変圧器を形成する。 According to the present invention, the power module further comprises built-in magnetic structures Mm1, Mm2, Mm3 and Mm4 for at least one interconnect. Substances such as nickel-iron flakes can be incorporated into the PCB structure. This structure is arranged to direct current from the copper vias to the interconnect surface and the metallization surface, similar to a transformer. The magnetic structures Mm1 and Mm2 form a first transformer, and the magnetic structures Mm3 and Mm4 form a second transformer.

図６は、本発明によるコントローラのアーキテクチャの一例を表している。 FIG. 6 shows an example of the controller architecture according to the present invention.

コントローラ１０は、例えば、バス６０１によって合わせて接続されたコンポーネントに基づくアーキテクチャと、図７に開示するようなプログラムによって制御されるプロセッサ６００とを有する。 The controller 10 has, for example, an architecture based on components connected together by bus 601 and a processor 600 controlled by a program as disclosed in FIG.

バス６０１は、プロセッサ６００を、リードオンリーメモリＲＯＭ６０２、ランダムアクセスメモリＲＡＭ６０３及び入出力インターフェースＩ／Ｏ ＩＦ６０５に連結する。 The bus 601 connects the processor 600 to the read-only memory ROM 602, the random access memory RAM 603, and the input / output interface I / O IF 605.

メモリ６０３は、変数と、図７に開示するようなアルゴリズムに関するプログラムの命令とを受け取るように意図されたレジスタを含む。 Memory 603 includes variables and registers intended to receive program instructions for the algorithm as disclosed in FIG.

プロセッサ６００は、入出力インターフェースＩ／Ｏ ＩＦ６０５を通じて、コレクタ電流Ｉｃ、温度センサによって感知された温度、又は熱感受性パラメータフィードバックを受信し、回復状態を誘導する特定のレベルにまでパワーモジュール内の電力散逸を制御するように追加相互接続体を通過する電流を制御する。パワーモジュールにおける修復材料の特性に応じて、温度は一定に保持される必要となる可能性がある。その場合、調整の目的で、パワーモジュール上に組み込まれる熱電対を採用することができ、又は、熱感受性電気パラメータ（例えば、或る特定の電流Ｉｃに対するＶｇ）を採用することができる。 Through the input / output interface I / O IF605, the processor 600 receives the collector current Ic, the temperature sensed by the temperature sensor, or the heat-sensitive parameter feedback, and dissipates power in the power module to a specific level that induces a recovery state. Control the current passing through the additional interconnect to control. Depending on the properties of the repair material in the power module, the temperature may need to be kept constant. In that case, thermocouples built onto the power module can be employed for tuning purposes, or thermosensitive electrical parameters (eg, Vg for a particular current Ic) can be employed.

リードオンリーメモリ又は場合によりフラッシュメモリ６０２は、図７に開示するようなアルゴリズムに関するプログラムの命令を収容し、その命令は、コントローラ１０に電源が投入されると、ランダムアクセスメモリ６０３に転送される。 The read-only memory or, optionally, the flash memory 602 accommodates program instructions relating to the algorithm as disclosed in FIG. 7, which are transferred to the random access memory 603 when the controller 10 is powered on.

コントローラ１０は、ＰＣ（パーソナルコンピュータ）、ＤＳＰ（デジタル信号プロセッサ）若しくはマイクロコントローラ等のプログラマブルコンピューティングマシンによって、命令若しくはプログラムのセットの実行により、ソフトウェアで実装するか、又は、ＦＰＧＡ（フィールドプログラマブルゲートアレイ）若しくはＡＳＩＣ（特定用途向け集積回路）等、マシン若しくは専用コンポーネントにより、ハードウェアで実装することができる。 The controller 10 is implemented in software by a programmable computing machine such as a PC (personal computer), DSP (digital signal processor) or microcontroller by executing a set of instructions or programs, or is an FPGA (field programmable gate array). ) Or ASIC (application specific integrated circuit), etc., can be implemented in hardware by a machine or a dedicated component.

言い換えれば、コントローラ１０は、コントローラ１０が図７に開示するようなアルゴリズムに関するプログラムを実行することができるようにする、回路、又は回路を備える装置を備える。 In other words, the controller 10 comprises a circuit or a device comprising the circuit that allows the controller 10 to execute a program relating to the algorithm as disclosed in FIG.

図７は、本発明による回復プロセスを実現するためにはんだ層の加熱状態を制御するアルゴリズムを表している。 FIG. 7 represents an algorithm for controlling the heating state of the solder layer in order to realize the recovery process according to the present invention.

本アルゴリズムは、コントローラ１０のプロセッサ６００によって実行される一例によって開示する。 The algorithm is disclosed by an example executed by processor 600 of controller 10.

ステップＳ７００において、修復プロセスが無効にされる。 In step S700, the repair process is disabled.

次のステップＳ７０１では、プロセッサ６００は、高周波電流が接続体Ｃｎ２１及びＣｎ２２、又はＥｘｔｐ４１及びＥｘｔｐ４２、又はＥｘｔｐ５１及びＥｘｔｐ５２を通過することを可能にするとともに、加熱状態制御ループを制御する。 In the next step S701, the processor 600 allows the high frequency currents to pass through the connectors Cn21 and Cn22, or Extp41 and Extp42, or Extp51 and Extp52, and controls the heating state control loop.

温度は、所与の時間、アルミニウム合金ボンディングワイヤに対して、例えば３０分間１５０℃に調整される。 The temperature is adjusted to 150 ° C. for the aluminum alloy bonding wire for a given time, eg, 30 minutes.

ステップＳ７０２において、プロセッサ６００は、所与の時間が完了したか否か判断する。所与の時間が完了した場合、プロセッサ６００はステップＳ７０３に進む。完了していない場合、プロセッサ６００はステップＳ７０１に戻る。 In step S702, processor 600 determines if a given time has been completed. When the given time is complete, processor 600 proceeds to step S703. If not completed, processor 600 returns to step S701.

ステップＳ７０３では、プロセッサ６００は、修復プロセスを無効にする。 In step S703, processor 600 disables the repair process.

当然のことながら、本発明の範囲から逸脱することなく、上記で説明した本発明の実施形態に対して多くの変更を行うことができる。 Of course, many modifications can be made to the embodiments of the invention described above without departing from the scope of the invention.

このために、本発明は、ダイを電気回路に接続する、パワーモジュールのダイの第１の相互接続体の修復を可能にするシステムに関し、本システムは、
パワーモジュールの少なくとも１つの他の相互接続体と、
第１の相互接続体の温度を上昇させることによって、及び、第１の相互接続体におけるクラックに沿って応力を上昇させ、それによってクラックにおける拡散速度を上昇させてクラックの回復を引き起こすことによって第１の相互接続体の修復を可能にするために、第１の相互接続体の少なくとも一部が所定の持続時間内に所定の温度に達するために、少なくとも１つの他の相互接続体を通る高周波周期電流フローを生成するように、少なくとも１つの他の相互接続体に接続される周期電流源と、
を備え、
相互接続体はボンディングワイヤであるか、又は相互接続体は銅ビアであり、周期電流源は他の２つの相互接続体に接続され、パワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの誘導コイルを更に備えるか、又はパワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの磁気構造体を更に備えることを特徴とする。 To this end, the present invention relates to a system that connects a die to an electrical circuit, allowing repair of the first interconnect of the die of the power module.
With at least one other interconnect of power modules,
First by increasing the temperature of the first interconnect and by increasing the stress along the cracks in the first interconnect, thereby increasing the diffusion rate in the cracks and causing crack recovery. To allow repair of one interconnect, a high frequency through at least one other interconnect so that at least a portion of the first interconnect reaches a predetermined temperature within a predetermined duration. With a periodic current source connected to at least one other interconnect to generate a periodic current flow,
Equipped with a,
The interconnect is a bonding wire or the interconnect is a copper via, the periodic current source is connected to the other two interconnects, and the power module is the first interconnect within a predetermined duration. In order for at least a part of the body to reach a predetermined temperature, it further comprises one induction coil connected to the two interconnects, or the power module of the first interconnect within a predetermined duration. to at least partially reaches a predetermined temperature, further comprising characterized Rukoto one magnetic structure that is connected to the two interconnects.

本発明はまた、ダイを電気回路に接続する、パワーモジュールのダイの第１の相互接続体の修復を可能にする方法に関し、本方法は、
第１の相互接続体の少なくとも一部が所定の温度に達するために、少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、高周波周期電流源をパワーモジュールの少なくとも１つの他の相互接続体に接続するステップと、
第１の相互接続体の温度を上昇させることによって、及び、第１の相互接続体におけるクラックに沿って応力を上昇させ、それによってクラック内の拡散速度を上昇させてクラックの回復を引き起こすことによって第１の相互接続体の修復を可能にするために、所定の持続時間内に所定の温度において周期電流源を制御するステップと、
を含み、
相互接続体はボンディングワイヤであるか、又は相互接続体は銅ビアであり、高周波周期電流源は他の２つの相互接続体に接続され、パワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの誘導コイルを更に備えるか、又はパワーモジュールは、所定の持続時間内に第１の相互接続体の少なくとも一部が所定の温度に達するために、２つの相互接続体に接続される１つの磁気構造体を更に備えることを特徴とする。 The present invention also relates to a method that allows repair of a first interconnect of dies of a power module that connects the dies to an electrical circuit.
A high frequency periodic current source at least one other of the power module so that at least a portion of the first interconnect produces a periodic current flow through at least one other interconnect in order to reach a predetermined temperature. Steps to connect to the interconnect and
By increasing the temperature of the first interconnect and by increasing the stress along the cracks in the first interconnect, thereby increasing the diffusion rate within the cracks and causing crack recovery. A step of controlling a periodic current source at a given temperature within a given duration to allow repair of the first interconnect , and
Only including,
The interconnect is a bonding wire, or the interconnect is a copper via, a high frequency periodic current source is connected to the other two interconnects, and the power module is a first interconnect within a predetermined duration. An induction coil connected to the two interconnects is further provided so that at least a portion of the interconnect reaches a predetermined temperature, or the power module is a first interconnect within a predetermined duration. It is characterized by further comprising one magnetic structure connected to two interconnects so that at least a portion of the above reaches a predetermined temperature .

Claims (9)

ダイを電気回路に接続する、パワーモジュールの前記ダイの第１の相互接続体の修復を可能にするシステムであって、前記システムは、
前記パワーモジュールの少なくとも１つの他の相互接続体と、
前記第１の相互接続体の少なくとも一部が所定の持続時間内に所定の温度に達するために、前記少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、前記少なくとも１つの他の相互接続体に接続される周期電流源と、
を備えることを特徴とする、システム。 A system that allows repair of the first interconnect of said die of a power module that connects the die to an electrical circuit.
With at least one other interconnect of the power module,
The at least one such that at least a portion of the first interconnect produces a periodic current flow through the at least one other interconnect in order to reach a predetermined temperature within a predetermined duration. With periodic current sources connected to other interconnects,
A system characterized by being equipped with. 前記第１の相互接続体の第１の端子は前記ダイに接続され、前記少なくとも１つの他の相互接続体である第２の相互接続体の第１の端子は、前記第１の相互接続体の第１の端子に接続され、前記周期電流源は、前記第１および前記第２の相互接続体を通る周期電流フローを生成するように前記第１および前記第２の相互接続体の第２の端子に接続されることを特徴とする、請求項１に記載のシステム。 The first terminal of the first interconnect is connected to the die, and the first terminal of the second interconnect, which is at least one other interconnect, is the first interconnect. Connected to the first terminal of the first and second interconnects so that the periodic current source produces a periodic current flow through the first and second interconnects. The system according to claim 1, wherein the system is connected to the terminal of. 前記相互接続体はボンディングワイヤであることを特徴とする、請求項２に記載のシステム。 The system according to claim 2, wherein the interconnect is a bonding wire. 前記ボンディングワイヤはアルミニウム合金ボンディングワイヤであることを特徴とする、請求項３に記載のシステム。 The system according to claim 3, wherein the bonding wire is an aluminum alloy bonding wire. 前記周期電流源が発生する電流は、１００ｋＨｚを超える周波数及び８２アンペア〜１０８アンペアのＲＭＳ値の矩形波信号又は正弦波信号であることを特徴とする、請求項２〜４のいずれか１項に記載のシステム。 The present according to any one of claims 2 to 4, wherein the current generated by the periodic current source is a square wave signal or a sinusoidal signal having a frequency exceeding 100 kHz and an RMS value of 82 amperes to 108 amperes. Described system. 前記所定の温度は１５０℃〜２００℃の間であり、前記所定の持続時間は５０時間〜１００時間の間であることを特徴とする、請求項２〜５のいずれか１項に記載のシステム。 The system according to any one of claims 2 to 5, wherein the predetermined temperature is between 150 ° C. and 200 ° C., and the predetermined duration is between 50 hours and 100 hours. .. 前記相互接続体は銅ビアであり、前記周期電流源は他の２つの相互接続体に接続され、前記パワーモジュールは、前記所定の持続時間内に前記第１の相互接続体の少なくとも一部が前記所定の温度に達するために、前記２つの相互接続体に接続される１つの誘導コイルを更に備える、請求項１に記載のシステム。 The interconnect is a copper via, the periodic current source is connected to two other interconnects, and the power module is such that at least a portion of the first interconnect is within the predetermined duration. The system of claim 1, further comprising one induction coil connected to the two interconnects to reach the predetermined temperature. 前記相互接続体は銅ビアであり、前記周期電流源は他の２つの相互接続体に接続され、前記パワーモジュールは、前記所定の持続時間内に前記第１の相互接続体の少なくとも一部が前記所定の温度に達するために、前記２つの相互接続体に接続される１つの磁気構造体を更に備える、請求項１に記載のシステム。 The interconnect is a copper via, the periodic current source is connected to two other interconnects, and the power module is such that at least a portion of the first interconnect is within the predetermined duration. The system of claim 1, further comprising one magnetic structure connected to the two interconnects to reach the predetermined temperature. ダイを電気回路に接続する、パワーモジュールの前記ダイの第１の相互接続体の修復を可能にする方法であって、前記方法は、
前記第１の相互接続体の少なくとも一部が所定の温度に達するために、少なくとも１つの他の相互接続体を通る周期電流フローを生成するように、周期電流源を前記パワーモジュールの前記少なくとも１つの他の相互接続体に接続するステップと、
所定の持続時間内に前記所定の温度において前記周期電流源を制御するステップと、
を含むことを特徴とする、方法。 A method that allows repair of a first interconnect of said die of a power module that connects the die to an electrical circuit.
The periodic current source is at least one of the power modules so that at least a portion of the first interconnect produces a periodic current flow through at least one other interconnect in order to reach a predetermined temperature. With the steps to connect to two other interconnects,
A step of controlling the periodic current source at the predetermined temperature within a predetermined duration, and
A method characterized by including.
JP2020509524A 2017-11-28 2018-10-31 Systems and methods that allow repair of the first interconnect of power module dies Active JP6968264B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP17204198.0 2017-11-28
EP17204198.0A EP3489997B1 (en) 2017-11-28 2017-11-28 System for allowing the restoration of an interconnection of a die of a power module
PCT/JP2018/041258 WO2019107095A1 (en) 2017-11-28 2018-10-31 System for allowing the restoration of an interconnection of a die of a power module

Publications (2)

Publication Number Publication Date
JP2020532118A true JP2020532118A (en) 2020-11-05
JP6968264B2 JP6968264B2 (en) 2021-11-17

Family

ID=60543369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020509524A Active JP6968264B2 (en) 2017-11-28 2018-10-31 Systems and methods that allow repair of the first interconnect of power module dies

Country Status (5)

Country Link
US (1) US11114349B2 (en)
EP (1) EP3489997B1 (en)
JP (1) JP6968264B2 (en)
CN (1) CN111373529B (en)
WO (1) WO2019107095A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023508605A (en) * 2020-04-02 2023-03-02 ミツビシ・エレクトリック・アールアンドディー・センター・ヨーロッパ・ビーヴィ APPARATUS AND METHOD FOR IMPROVING RELIABILITY OF POWER MODULE

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102022208367A1 (en) * 2022-08-11 2024-02-22 Zf Friedrichshafen Ag Power module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311213A (en) * 2004-04-26 2005-11-04 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
WO2015083250A1 (en) * 2013-12-04 2015-06-11 三菱電機株式会社 Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148523A (en) * 1995-11-21 1997-06-06 Toshiba Corp Semiconductor device
JP2006073810A (en) * 2004-09-02 2006-03-16 Toyota Motor Corp Power semiconductor module and manufacturing method thereof
US7234218B2 (en) * 2005-03-08 2007-06-26 International Business Machines Corporation Method for separating electronic component from organic board
JP2008270455A (en) * 2007-04-19 2008-11-06 Hitachi Ltd Power semiconductor module
DE102009015757A1 (en) * 2009-04-01 2010-10-14 Siemens Aktiengesellschaft Pressure support for an electronic circuit
JP2014160804A (en) * 2013-01-23 2014-09-04 Toyota Motor Corp Semiconductor device and controller of the same
CN107024786B (en) * 2017-05-02 2021-03-23 京东方科技集团股份有限公司 Metal wire crack repairing method of display substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005311213A (en) * 2004-04-26 2005-11-04 Mitsubishi Electric Corp Semiconductor device and manufacturing method therefor
WO2015083250A1 (en) * 2013-12-04 2015-06-11 三菱電機株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023508605A (en) * 2020-04-02 2023-03-02 ミツビシ・エレクトリック・アールアンドディー・センター・ヨーロッパ・ビーヴィ APPARATUS AND METHOD FOR IMPROVING RELIABILITY OF POWER MODULE
JP7395017B2 (en) 2020-04-02 2023-12-08 ミツビシ・エレクトリック・アールアンドディー・センター・ヨーロッパ・ビーヴィ Apparatus and method for improving reliability of power module

Also Published As

Publication number Publication date
EP3489997B1 (en) 2022-06-15
US11114349B2 (en) 2021-09-07
CN111373529B (en) 2023-12-05
CN111373529A (en) 2020-07-03
US20200286797A1 (en) 2020-09-10
JP6968264B2 (en) 2021-11-17
WO2019107095A1 (en) 2019-06-06
EP3489997A1 (en) 2019-05-29

Similar Documents

Publication Publication Date Title
US10168381B2 (en) Method for determining a deterioration of power semiconductor modules as well as a device and circuit arrangement
JP6968264B2 (en) Systems and methods that allow repair of the first interconnect of power module dies
Loh et al. Wire bond reliability for power electronic modules-effect of bonding temperature
JP3988735B2 (en) Semiconductor device and manufacturing method thereof
US9978664B2 (en) Semiconductor module
DE102018217231B4 (en) Semiconductor device and method for manufacturing the same
Dudek et al. Electro-thermo-mechanical analyses on silver sintered IGBT-module reliability in power cycling
Sato et al. Forced-air-cooled 10 kW three-phase SiC inverter with output power density of more than 20 kW/L
Pawlak et al. Durability and reliability enhancement of selected electronic components achieved by laser technologies
JP5245306B2 (en) Degradation protection method for semiconductor device
WO2011152151A1 (en) Method for predicting lifetime of element, and circuit board provided with function of predicting lifetime of element
Kim et al. Thermo-mechanical fatigue induced unexpected strain hardening of Cu clip wiring on transfer-mold type EV power modules
Choi Studies on IGBT module to improve the reliability of power electronic systems
Sanfins et al. Preliminary failure-mode characterization of emerging direct-lead-bonding power module. Comparison with standard wire-bonding interconnection
Savu et al. Preheating and heat addition by LASER beam in hybrid LASER-ultrasonic welding
US10861816B2 (en) Electronic assemblies having a mesh bond material and methods of forming thereof
Dudek et al. FE analyses and power cycling tests on the thermo-mechanical performance of silver sintered power semiconductors with different interconnection technologies
JP6890712B2 (en) Systems and methods that allow repair of power module die interconnects
JP2006049567A (en) Semiconductor apparatus and using method of the same
JP5975007B2 (en) Semiconductor device and manufacturing method thereof
US11929346B2 (en) Device and method for increasing the reliability of a power module
Nagl et al. Transient thermomechanical study of a thick-wire bond with particular attention to the interfacial shearing stress
Gao et al. Research on Fast Design Method for Power Module Terminal RMS Current Capacity via Thermal Equivalent Model
Ring et al. Fast Power-Temperature Cycling of BEOL test structures for Power Devices
CN117083708A (en) Semiconductor device and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200218

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210324

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210406

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210609

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210928

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211026

R150 Certificate of patent or registration of utility model

Ref document number: 6968264

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150