JP2020198558A - Image processing apparatus, image processing method, and program - Google Patents

Abstract

To provide an image processing apparatus, an image processing method, and a program that can appropriately detect an abnormal image included in a read image transferred to the next stage due to an abnormality in a transfer clock.SOLUTION: An image processing circuit comprises: a phase synchronization circuit that generates a reference clock; and an abnormality detection unit that detects a LSYNC signal indicating line synchronization that is generated based on the reference clock and is a control signal for transferring read image data to the next stage, a lock signal that indicates the lock state of the phase synchronization circuit, a register that counts and holds the number of transferred lines, and the presence or absence of the occurrence of an abnormal image, and the image processing circuit specifies and detects a line on which the abnormal image occurs.SELECTED DRAWING: Figure 3

Description

The present application relates to an image processing apparatus, an image processing method, and a program.

Conventionally, in an image processing device that transfers an image such as a scanned original image between a plurality of units, label data is added to at least one of the front end or the rear end of each line of the image to be transferred by the transmitting side unit, and the receiving side unit. There is known a technique for detecting an abnormality during transfer and correcting an abnormal image based on the label data.

Further, a technique for detecting and correcting an abnormal image included in a received image based on candidate pixel information of an abnormality such as a streak extracted in each line of the received image is disclosed (see, for example, Patent Document 1).

However, with the technique of Patent Document 1, there are cases where an abnormal image included in a received image cannot be detected appropriately.

An object of the disclosed technique is to appropriately detect an abnormal image included in a received image.

The image processing apparatus according to one aspect of the disclosed technique includes an abnormality detection unit that detects an abnormality line image in a received image based on a locked state of a phase-locked loop.

According to the disclosed technique, an abnormal image included in the received image can be appropriately detected.

It is a block diagram which shows the whole structure example of the image processing apparatus which concerns on embodiment. It is a block diagram which shows the structural example of the scanner and the image processing ASIC which concerns on embodiment. It is a block diagram which shows the functional structure example of the image processing circuit which concerns on 1st Embodiment. It is a figure which shows the signal example at the time of image transfer from a scanner to an image processing ASIC, (a) is a figure which shows the case where an abnormal image has occurred, and (b) is a figure which shows the case where an abnormal image has occurred. .. It is a figure which shows the abnormality detection processing example which concerns on 1st Embodiment. It is a flowchart which shows the abnormality detection processing example which concerns on 1st Embodiment. It is a figure which shows the correction processing example which concerns on 1st Embodiment, (a) is a figure which shows the received image stored in the local memory, (b) is the figure which shows the abnormal line image and the vicinity line image. It is a block diagram which shows the functional structure example of the image processing circuit which concerns on 2nd Embodiment.

Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.

[First Embodiment]
<Structure of image processing device 1 according to the first embodiment>
(Overall configuration of image processing device 1)
FIG. 1 is a block diagram illustrating an example of the overall configuration of the image processing device 1 according to the embodiment. As shown in FIG. 1, the image processing device 1 includes a scanner 2, an image processing ASIC (Application Specific Integrated Circuit) 3, a local memory 4 as a storage unit, a controller ASIC 5, a chipset 6, and a CPU (Central). It includes a Processing Unit) 7 and a main memory 8 which is a storage unit. Here, the local memory 4 is an example of an image storage unit.

Of these, the scanner 2 reads the original image and transfers the read image data to the image processing ASIC3.

The image processing ASIC 3 executes various image processing on the image read by the scanner 2 and received from the scanner 2 (hereinafter referred to as a received image), and outputs the processed received image to the controller ASIC 5. Further, the image processing ASIC 3 expands and stores the received images on the front surface and the back surface of the document simultaneously read by the scanner 2 in the local memory 4 used as the copy image buffer and the code buffer. Then, the received images on the front surface and the back surface of the accumulated document are read out in order and transferred to the controller ASIC5.

The controller ASIC 5 expands the received image to the main memory 8 via the chipset 6. The chipset 6 is used together with the CPU 7 to control access to the main memory 8 by the controllers ASIC 5 and the CPU 7.

(Configuration of Scanner 2 and Image Processing ASIC3)
Next, FIG. 2 is a block diagram illustrating details of an example of the configuration of the scanner 2 and the image processing ASIC3. As shown in FIG. 2, the scanner 2 includes a CCD (Charge Coupled Device) 21, an A / D (Analog / Digital) conversion circuit 22, and an LVDS (Low Voltage Differential Signaling) transmitter 23.

Of these, the CCD 21 is configured by arranging light-receiving elements that output voltage signals in response to the amount of light received in one-dimensional or two-dimensional arrangement, and A / D analog voltage signals corresponding to the original in each light-receiving element. Output to the conversion circuit 22.

The A / D conversion circuit 22 is an electric circuit that converts an analog voltage signal input from the CCD 21 into a digital voltage signal and outputs it to the LVDS transmitter 23.

The LVDS transmitter 23 is an electronic circuit that outputs an LVDS signal obtained by serializing and encoding a digital voltage signal input from the A / D conversion circuit 22 to an image processing ASIC3.

As shown in FIG. 2, the image processing ASIC 3 includes an LVDS receiver 31, an image processing circuit 32, and an image transfer I / F (Interface) unit 33.

Of these, the LVDS receiver 31 is an electronic circuit that outputs a received image obtained by decoding an LVDS signal input from the LVDS transmitter 23 of the scanner 2 to the image processing circuit 32. Further, the LVDS receiver 31 includes a PLL (Phase Locked Loop; phase-locked loop) that synchronizes reception processing with a reference clock when receiving an LVDS signal from the LVDS transmitter 23, and images a lock signal indicating a locked state of the PLL. Output to the processing circuit 32.

Here, the lock of the PLL means that the output signal of the PLL is synchronized with the reference clock to be referred to. In the following, the state in which the PLL is not locked (the state in which the synchronization is not achieved) may be referred to as the “state in which the PLL lock is released”.

The image processing circuit 32 inputs image data, a lock signal, and the like of the received image from the LVDS receiver 31, and performs various processes described later on the received image. Then, it is an electronic circuit that outputs the received image after processing to the controller ASIC5 via the image transfer I / F33. Further, the image processing circuit 32 includes a FIFO (First In First Out) circuit for speed conversion, and uses the FIFO circuit to synchronize the received image input from the LVDS receiver 31 with the internal clock used in the image processing circuit 32. It is configured so that it can be done.

<Functional configuration of image processing circuit 32>
Next, FIG. 3 is a block diagram illustrating an example of the functional configuration of the image processing circuit 32 in the image processing device 1. As shown in FIG. 3, the image processing circuit 32 includes an abnormality detection unit 321, a FIFO processing unit 322, an image processing unit 323, a local memory access control unit 324, and an image correction unit 325.

In the image processing device 1, the abnormality detection unit 321 detects an abnormality line image in the received image based on the lock signal input from the LVDS receiver 31. Here, the abnormal line image refers to a line image including an abnormal image among the line images included in the received image. Further, the abnormal image refers to a portion of the received image in which image data is missing due to a transfer error from the scanner 2 to the image processing ASIC3 or a portion in which noise is increased.

The received image is stored in the local memory 4 via the abnormality detection unit 321, the FIFO processing unit 322, the image processing unit 323, and the local memory access control unit 324. The image correction unit 325 corrects the abnormal image in the received image stored in the local memory 4 based on the detection result of the abnormal line image by the abnormality detecting unit 321 and outputs the corrected received image to the controller ASIC5. The details of each part will be described below.

The abnormality detection unit 321 includes an internal LSYNC generation unit 3211, an internal FGATE generation unit 3212, a line count unit 3213, an abnormality line position detection unit 3214, an abnormality line position resist unit 3215, an abnormality line number detection unit 3216, and the like. An abnormal number of lines The resist unit 3217 and the register switching unit 3218 are provided.

Of these, the internal LSYNC generation unit 3211 generates an internal LSYNC signal that asserts at intervals of a predetermined internal LSYNC interval set value based on the assertion of the input FGATE signal input to the image processing circuit 32. To do.

The internal FGATE generation unit 3212 generates an internal FGATE signal in which the input FGATE signal is delayed so as to synchronize with the assert timing of the internal LSYNC signal generated by the internal LSYNC generation unit 3211.

The line counting unit 3213 counts the number of lines of the line image input to the image processing circuit 32 among the line images included in the received image for one page.

The abnormal line position detection unit 3214 detects the line position of the abnormal line image based on the falling timing of the lock signal. More specifically, the abnormal line position detection unit 3214 acquires the line count value at the falling timing of the lock signal from the line count unit 3213, and uses this line count value as the line position information of the abnormal line image as the abnormal line position resist unit. Output to 3215 and hold.

The abnormal line position resist unit 3215 is configured to include a plurality of registers, and holds the line position information detected by the abnormal line position detection unit 3214.

The abnormal line number detection unit 3216 detects the number of lines in the abnormal line image starting from the line position detected by the abnormal line position detection unit 3214 based on the rising timing of the lock signal. More specifically, the abnormal line number detection unit 3216 acquires the line count value at the rising timing of the lock signal from the line count unit 3213. Further, the abnormal line number detection unit 3216 acquires the line position information held in the abnormal line position resist unit 3215. Then, the line position information is subtracted from the line count value at the time of rising, and this subtracted value is output to the abnormal line number resist unit 3217 as the line number information of the abnormal line image and held.

The abnormal line number resist unit 3217 is configured to include a plurality of registers, and holds the line number information detected by the abnormal line number detection unit 3216.

The register switching unit 3218 is a received image for one page, and when the PLL lock is released a plurality of times, among the plurality of registers included in the abnormal line position resist unit 3215, the register in which the line position information is already held is the register. Switch to another register to hold the next line position information. Similarly, the register switching unit 3218 is a register in which line number information is already held among a plurality of registers included in the abnormal line number resist unit 3217 when the PLL lock is released multiple times in the received image for one page. Switch to a different register to hold the next line number information. Abnormal line position If the number of registers included in each of the resist unit 3215 and the number of abnormal lines resist unit 3217 is increased, the number of abnormal line images that can be detected can be increased accordingly, which is preferable.

The FIFO processing unit 322 synchronizes the received image with the operation clock of the processing by the image processing unit 323 by converting the transfer speed of the received image to the image processing unit 323.

The image processing unit 323 executes various image processing for correcting image quality deterioration due to A / D conversion by the scanning optical system of the scanner 2 and the A / D conversion circuit 22.

The local memory access control unit 324 controls to store the image data of the received image in the local memory 4.

The image correction unit 325 includes an abnormality neighborhood pixel extraction unit 3251, an image interpolation unit 3252, and a correction image output unit 3253.

Of these, the abnormal neighborhood pixel extraction unit 3251 refers to the abnormal line position resist unit 3215 to acquire line position information of the abnormal line image, and refers to the abnormal line number resist unit 3217 to obtain line number information of the abnormal line image. To get. Further, the abnormal neighborhood pixel extraction unit 3251 reads out the received image stored in the local memory 4.

When reading the received image, the abnormal neighborhood pixel extraction unit 3251 extracts pixel data in the vicinity of the abnormal line image based on the line position information and the number of lines information of the abnormal line image, and image interpolation together with the pixel data of the abnormal line image. Output to unit 3252.

The image interpolation unit 3252 corrects the abnormal image included in the abnormal line image by interpolation processing using pixel data in the vicinity of the abnormal line image. Then, the corrected image (corrected image) is output to the corrected image output unit 3253.

The corrected image output unit 3253 outputs the corrected image input from the image interpolation unit 3252 to the controller ASIC5 via the image transfer I / F33 (see FIG. 2).

<Processing by the image processing device 1 according to the first embodiment>
Next, the processing by the image processing apparatus 1 will be described with reference to FIGS. 4 to 7.

4A and 4B are diagrams for explaining an example of a signal at the time of image transfer from the scanner 2 to the image processing ASIC3, FIG. 4A is a diagram for explaining a case where an abnormal image is not generated, and FIG. 4B is a diagram for explaining an abnormal image. It is a figure explaining the case which occurred.

In FIG. 4, the CLOCK signal is a pixel clock signal of an image decoded by the LVDS receiver 31 and input to the image processing circuit 32, and the lock signal is a signal indicating the PLL lock state of the LVDS receiver 31 as described above. Is. Further, the input LSYNC signal is a signal representing the beginning of each line image included in the received image, the WE (Write Enable) signal is the FIFA write enable signal of the received image, and the DATA signal is the pixel data of the received image. It is a signal indicating.

In FIG. 4A, during image transfer from the scanner 2 to the image processing ASIC3, if the transfer is normally performed without releasing the PLL lock, the abnormality detection unit 321 performs image processing based on the assertion of the input LSYNC signal. Turn the counter in the circuit 32. Then, when the pixel data of the received image corresponds to the pixel of the effective image area, the abnormality detection unit 321 asserts the WE signal and writes the pixel data of the effective image area to the FIFO processing unit 322.

As shown in FIG. 4A, the DATA signal during the period in which the WE signal is asserted is written to the FIFO processing unit 322 as a valid image, and the blank transfer DATA signal shown by the lattice hatching is the FIFO processing unit 322. Not lighted up. In this way, the image processing circuit 32 can output an image that does not include an abnormal image such as an empty transfer DATA signal to the image transfer I / F 33 as an output image.

On the other hand, as shown in FIG. 4B, when the PLL lock is released during the image transfer from the scanner 2 to the image processing ASIC3, the lock signal is negated and the CLOCK signal is stopped during the period when the PLL lock is released. To do. Along with this, the abnormality detection unit 321 stops the counter in the image processing circuit 32. After that, when the PLL is locked again and the oscillation of the CLOCK signal is restarted, the abnormality detection unit 321 starts turning the counter in the image processing circuit 32 again at the timing of this restart. As a result, the pixel data of the invalid image region during the empty transfer period indicated by the lattice hatching is written to the FIFA processing unit 322, and the pixel data of the invalid image region is included as an abnormal image in the output image from the image processing circuit 32.

The image processing device 1 according to the present embodiment detects an abnormal line image including an abnormal image generated by such unlocking of the PLL in the received image.

(Abnormal line image detection processing)
FIG. 5 is a diagram illustrating an example of abnormality detection processing by the image processing circuit 32. Hereinafter, the block diagram of the functional configuration of the image processing circuit 32 shown in FIG. 3 will be described with reference to the appropriate reference.

In FIG. 5, the input FGATE signal is a signal representing the validity period of one page in the received image, and the input LSYNC signal is a signal representing the beginning of each line image included in the received image, as described above.

If the timing at which the PLL lock is released straddles the assert timing of the input LSYNC signal, the LVDS receiver 31 cannot receive the input LSYNC signal, and one line is missing as shown by the alternate long and short dash line 51 in FIG. ..

Therefore, in the embodiment, the internal LSYNC generation unit 3211 generates the internal LSYNC signal, and the internal FGATE generation unit 3212 generates the internal FGATE signal, and these are used as the synchronization signal of the received image to generate the input LSYNC signal. I try not to be affected by the omission.

As shown in FIG. 5, the internal FGATE signal is generated so as to be asserted at a timing 52a that is slightly delayed from the timing 52 of the assertion of the input FGATE signal. The internal LSYNC signal is generated so that it is asserted at a timing 53a slightly delayed from the assert timing 53 of the input LSYNC signal, and in synchronization with the internal FGATE signal. The period 54 indicated by an arrow in the internal LSYNC signal of FIG. 5 indicates a predetermined interval of the internal LSYNC signal, and the internal LSYNC signal is generated according to this interval.

At the timing 52a of the assertion of the internal FGATE signal, the line count unit 3213 starts the line count in response to the assertion of the internal LSYNC signal, and the line count value is incremented. Then, at the timing 55 of negating the internal FGATE signal, the line count unit 3213 is reset and the line count value becomes 0.

When the abnormal line position detection unit 3214 detects the fall of the lock signal during the assert period of the internal FGATE, the abnormal line position detection unit 3214 acquires the line count value at the fall timing from the line count unit 3213. Then, the acquired line count value is output to the abnormal line position resist unit 3215 and held as line position information.

In the example of FIG. 5, the abnormal line position detection unit 3214 acquires the line count value “1” at the timing 56 of the fall of the lock signal, outputs the line count value “1” to the abnormal line position resist unit 3215 at the timing 57, and outputs the line. The line count value "1" is held as the position information. Further, the abnormal line position detection unit 3214 acquires the line count value “3” at the timing 58 of the fall of the lock signal, outputs the line count value “3” to the abnormal line position resist unit 3215 at the timing 59, and outputs the line as line position information. The count value "3" is held.

On the other hand, when the abnormal line number detection unit 3216 detects the rise of the lock signal during the assert period of the internal FGATE, the line count value at the rise timing is acquired from the line count unit 3213 and held in the abnormal line position resist unit 3215. Acquires the line position information of the abnormal line image. Then, the line position information is subtracted from the acquired line count value to acquire the line number information, which is output to the abnormal line number resist unit 3217 and held.

In the example of FIG. 5, the abnormal line number detection unit 3216 acquires the line count value “1” at the rising timing 60 of the lock signal, and the line of the abnormal line image held in the abnormal line position resist unit 3215. Acquire the position information "1". Then, the line position information "1" is subtracted from the count value "1" to acquire the line number information "0", which is output to the abnormal line number resist unit 3217 at the timing 61 and held.

Further, the abnormal line position detection unit 3214 acquires the line count value “4” at the rising timing 62 of the lock signal, and obtains the line position information “3” of the abnormal line image held in the abnormal line position resist unit 3215. get. Then, the line position information "3" is subtracted from the count value "4" to acquire the line number information "1", which is output to the abnormal line number resist unit 3217 at the timing 63 and held.

Abnormal line position From the line position information held in the resist unit 3215 and the line number information held in the abnormal line number resist unit 3217, it is possible to grasp which position and how many lines the abnormal line image has occurred in the received image. can do.

Next, FIG. 6 is a flowchart showing an example of abnormality detection processing by the image processing circuit 32.

First, in step S61, the abnormality detection unit 321 determines whether or not the internal FGATE signal is asserted.

When it is determined in step S61 that the internal FGATE signal is not asserted (step S61, No), the image processing circuit 32 ends the process.

On the other hand, when it is determined in step S61 that the internal FGATE signal is asserted (step S61, Yes), in step S62, the abnormal line position detection unit 3214 detects the fall of the lock signal.

When the falling edge of the lock signal is detected in step S62 (step S62, Yes), in step S63, the abnormal line position detection unit 3214 acquires the line count value from the line count unit 3213, and the abnormal line position resist unit. Output to 3215.

Subsequently, in step S64, the abnormal line position resist unit 3215 holds the input line count value as the line position information of the abnormal line image. After that, the process proceeds to step S61, and the processes after step S61 are executed again.

On the other hand, when the falling edge of the lock signal is not detected in step S62 (step S62, No), the abnormal line number detection unit 3216 detects the rising edge of the lock signal in step S65.

When the rising edge of the lock signal is detected in step S65 (step S65, Yes), in step S66, the abnormal line number detection unit 3216 acquires the line count value from the line count unit 3213.

Subsequently, in step S67, the abnormal line number detection unit 3216 acquires the line position information of the abnormal line image held by the abnormal line position resist unit 3215.

Subsequently, in step S68, the abnormal line number detection unit 3216 subtracts the line position information from the line count value, and outputs the subtracted value to the abnormal line number resist unit 3217.

Subsequently, in step S69, the abnormal line number resist unit 3217 holds the input subtraction value as the line number information of the abnormal line image.

Subsequently, in step S70, the register switching unit 3218 switches between the register included in the abnormal line position resist unit 3215 and the register included in the abnormal line position resist unit 3215. After that, the process proceeds to step S61, and the processes after step S61 are executed again.

On the other hand, if the rise of the lock signal is not detected in step S65 (step S65, No), the process proceeds to step S61, and the processes after step S61 are executed again.

In this way, the image processing circuit 32 can detect the line position and the number of lines of the abnormal line image included in the received image.

(Correction processing of abnormal line image)
Next, FIG. 7 is a diagram illustrating an example of correction processing by the image processing circuit 32, (a) is a diagram showing a received image stored in the local memory 4, and (b) is an abnormality line in (a). It is a figure which shows the line image of image 100 and its vicinity.

In FIG. 7A, each grid shown in the figure shows a pixel in the received image, and the portion shown by the shaded hatching shows the abnormal line images 100, 101 and 102. Each of the abnormal line images 100 and 101 has a number of lines of "1", and the abnormal line image 102 has a number of lines of "2".

The abnormal neighborhood pixel extraction unit 3251 in the image correction unit 325 acquires line position information and line number information of the abnormal line image by referring to the abnormal line position resist unit 3215 and the abnormal line number resist unit 3217. Then, based on this information, the abnormal line images 100, 101 and 102 in the received image stored in the local memory 4 and the image data in the vicinity thereof are extracted and output to the image interpolation unit 3252.

The line image 103 in FIG. 7B is a line image adjacent to the abnormal line image 100 in the negative sub-scanning direction (see FIG. 7A), and the line image 105 is an abnormal line in the positive sub-scanning direction. It is a line image adjacent to the image 100. The anomaly neighborhood pixel extraction unit 3251 extracts line images 103 and 105 as image data in the vicinity of the anomaly line image 100.

The image interpolation unit 3252 uses the pixel data of the nearby pixels A to D of the pixel of interest 104 included in the abnormal line image 100, and uses the following equation (1) based on the bilinear interpolation method to obtain the pixel of the pixel of interest 104. Calculate the data.
Dp = (1-α) ・ (1-α) Da + α ・ (1-β) ・ Db
+ (1-α) ・ β ・ Dc ＋ α ・ β ・ Dd ・ ・ ・ (1)
Here, α and β in Eq. (1) are weighting coefficients, respectively.

The image interpolation unit 3252 replaces the pixel data of the pixel of interest 104 with the pixel data Dp calculated by the equation (1). The image interpolation unit 3252 executes such processing in order for each pixel of the received image along the main scanning direction shown in FIG. 7A, so that all of the abnormal line image 100 is included. The pixel data of the pixels can be replaced with the pixel data Dp, and the abnormal line image 100 can be corrected.

Although the bilinear interpolation method has been described in the above-mentioned example, the method is not limited to this, and other methods such as the spline interpolation method may be used. Further, in the above-mentioned example, the correction using the line image of one line each in the positive and negative directions in the sub-scanning direction has been described, but the correction is not limited to this, and each of the positive and negative lines in the sub-scanning direction is described. Interpolation may be performed using a line image of one or more lines in a direction. Further, the interpolation is not limited to the interpolation using four pixels A to D in the vicinity of the pixel of interest 104, and more pixel data in the vicinity of the pixel of interest 104 may be used. It is preferable to use a wide range of pixel data because high-definition interpolation processing becomes possible.

Similarly, in the case of an abnormal line image extending over two or more lines such as the abnormal line image 102, the same applies.
Using the pixel data of one or more line images adjacent to the abnormal line image 102 in each of the positive and negative directions of the sub-scanning direction, the pixel data of all the pixels included in the abnormal line image 102 is converted into pixel data Dp. It can be replaced and the abnormal line image 102 can be corrected.

<Effect>
In an image processing device such as an MFP (Multifunction Peripheral / Printer / Product) or a printer, when a document is read by a scanner 2 and transferred to an image processing ASIC3, horizontal streaks may occur in the read image. ..

As a result of the analysis by the inventors, one of the causes is that the PLL lock of the LVDS receiver 31 is released due to an external factor such as static electricity in the image processing ASIC3 on the side receiving the image data transferred by LVDS, resulting in horizontal streaks. It turned out to occur.

In the conventional technique, since the image data on the front end side or the rear end side of the line image is lost depending on the timing when the PLL lock is released, the label data used for the abnormality detection cannot be acquired, and the abnormality detection may not be performed properly. ..

In the present embodiment, the abnormality detection unit 321 detects the abnormality line image including the abnormality image among the line images included in the received image based on the lock signal input from the LVDS receiver 31. Since it is based on the lock signal, it is possible to appropriately detect an abnormal line image caused by unlocking the PLL in the received image. Further, a normal image can be obtained by appropriately correcting the abnormal line image detected by the abnormality detecting unit 321.

Further, in the present embodiment, the abnormality detection unit 321 detects the line position in the received image of the abnormality line image based on the falling timing of the lock signal, and determines the number of lines in the abnormality line image starting from the line position. To detect. Since the number of lines is detected together with the line position, even an abnormal line image straddling a plurality of lines can be detected.

Further, when an abnormal line image is detected based on the image data, the circuit scale may be increased by providing a CRC (Cyclic Redundancy Check) confirmation circuit, an 8b10b decoding circuit, or the like, but in the present embodiment, the abnormality is based on the lock signal. Since the line image is detected, the scale of the detection circuit can be reduced.

Further, in the present embodiment, the local memory 4 for accumulating the received image for one page is provided, and the abnormal line image is corrected when reading the received image for one page stored in the local memory 4. Since the correction processing is performed on the accumulated received image, the abnormal line image can be corrected even when the abnormal line image occurs over a plurality of lines.

Further, in the present embodiment, when a plurality of abnormal line images are included in the received image for one page, among the plurality of registers included in the abnormal line position resist unit 3215, the register in which the line position information is held is the register. Switch to another register. Further, among the plurality of registers included in the abnormal line number register unit 3217, the register is switched to a register different from the register in which the line number information is held. As a result, even when a plurality of abnormal line images are included in the received image for one page, the line position and the number of lines information of each abnormal line image can be held in the register and used for the correction processing of the abnormal line image. ..

[Second Embodiment]
Next, the image processing apparatus according to the second embodiment will be described.

In the first embodiment, an example has been described in which a received image is temporarily stored in the local memory 4 and an abnormal line image is corrected when the stored received image is read out.

In the image processing apparatus 1a according to the present embodiment, the image processing ASIC 3 includes a line memory. The image processing ASIC3 detects an abnormal line image in the received image and stores the image data of each line image included in the received image in the line memory. Then, when an abnormal line image is detected, the abnormal line image stored in the line memory is read out and corrected in real time. The details will be described below.

The image processing apparatus 1a according to the present embodiment includes an image processing ASIC 3a, and the image processing ASIC 3a includes an image processing circuit 32a. FIG. 8 is a block diagram illustrating an example of the functional configuration of the image processing circuit 32a.

As shown in FIG. 8, the image processing circuit 32a includes a line memory 326 and a line memory access control unit 327.

The line memory 326 stores the image data of each line image included in the received image. The line memory 326 has a storage capacity (storage capacity) capable of storing at least an abnormal line image and a line image in the vicinity thereof.

The line memory access control unit 327 controls to store the image data of the line image included in the received image in the line memory 326.

In the above-described example, the case where the image processing circuit 32a is provided with the line memory 326 has been described, but the present invention is not limited to this, and the line memory 326 may be provided at another location in the image processing ASIC3. ..

According to the present embodiment, since the abnormal line image and the line image in the vicinity thereof are accumulated at least and the abnormal line image is corrected, the correction processing can be performed at high speed.

Since the other effects are the same as those described in the first embodiment, duplicate explanations will be omitted.

Although the embodiments have been described above, the present invention is not limited to the above-described embodiments specifically disclosed, and various modifications and changes can be made without departing from the scope of claims. is there.

In the embodiment, an example of an MFP or a printer is shown as an image processing device, but it can be widely applied to a device using line synchronous transfer that transfers a line synchronous signal and a reference clock together with image data. Further, in the embodiment, an example in which each functional unit is realized by hardware such as an electronic circuit and an electric circuit has been described, but each functional unit may be realized by software by a CPU.

The embodiment also includes an image processing method. For example, the image processing method includes a step of detecting an abnormal line image in a received image based on a signal indicating a locked state of a phase-locked loop. By such an image processing method, the same effect as that of the image processing apparatus described above can be obtained.

Further, the embodiment also includes a program. For example, the program causes a computer to perform a process of detecting an abnormal line image in a received image based on a signal indicating a locked state of a phase-locked loop. With such a program, the same effect as that of the image processing apparatus described above can be obtained.

Further, each function of the embodiment described above can be realized by one or a plurality of processing circuits. Here, the "processing circuit" in the present specification is a processor programmed to execute each function by software such as a processor implemented by an electronic circuit, or a processor designed to execute each function described above. It shall include devices such as ASIC (Application Specific Integrated Circuit), DSP (digital signal processor), FPGA (field programmable gate array) and conventional circuit modules.

1 Image processing device 2 Scanner 21 CCD
22 A / D conversion circuit 23 LVDS transmitter 3 Image processing ASIC
31 LVDS receiver 32 Image processing circuit 321 Abnormality detection unit 3211 Internal LSYNC generation unit 3212 Internal FIFO generation unit 3213 Line count unit 3214 Abnormal line position detection unit 3215 Abnormal line position registration unit 3216 Abnormal line number detection unit 3217 Abnormal line number registration unit 3218 Register switching unit 322 FIFO processing unit 323 Image processing unit 324 Local memory access control unit 325 Image correction unit 326 Line memory 327 Line memory access control unit 3251 Abnormal neighborhood pixel extraction unit 3252 Image interpolation unit 3253 Corrected image output unit 33 Image transfer I / F
4 local memory 5 controller ASIC
6 chipset 7 CPU
8 Main memory 100 to 102 Abnormal line image

Japanese Unexamined Patent Publication No. 2017-022469

Claims (9)

An image processing device including an abnormality detection unit that detects an abnormality line image in a received image based on a locked state of a phase-locked loop. The abnormality detection unit
The image processing apparatus according to claim 1, wherein the line position of the abnormal line image in the received image is detected based on the falling timing of the lock signal indicating the locked state. The abnormality detection unit
The image processing apparatus according to claim 2, wherein the number of lines of the abnormal line image starting from the line position is detected based on the rising timing of the lock signal. An abnormal line position resist unit that holds the line position information of the abnormal line image,
The abnormal line number resist unit that holds the line number information of the abnormal line image,
A register switching unit for switching registers in each of the abnormal line position resist unit and the abnormal line number resist unit is provided.
The register switching unit is
When a plurality of the abnormal line images are included in the received image for one page, the register is switched to a register different from the register holding the line position information among the plurality of registers included in the abnormal line position register unit. The image processing apparatus according to claim 3, wherein the image processing apparatus is switched to a register other than the register holding the line number information among the plurality of registers included in the abnormal line number resist unit. Based on the line position of the abnormal line image detected by the abnormality detecting unit in the received image and the number of lines of the abnormal line image starting from the line position, the abnormal line image in the received image The image processing apparatus according to any one of claims 1 to 4, further comprising a corrected image output unit that outputs a corrected image corrected by using image data in the vicinity. It is provided with an image storage unit that stores one page of the received image.
The corrected image output unit
The image processing apparatus according to claim 5, wherein the corrected image in which the abnormal line image in the received image for one page is corrected is output. The corrected image output unit
The image processing apparatus according to claim 5 or 6, which outputs the corrected image corrected by interpolation processing using image data in the vicinity of the abnormal line image. An image processing method including a step of detecting an abnormal line image in a received image based on a locked state of a phase-locked loop. Detects an abnormal line image in the received image based on the locked state of the phase-locked loop.
A program that causes a computer to perform processing.

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