JP2020191012A5 - - Google Patents
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- JP2020191012A5 JP2020191012A5 JP2019097073A JP2019097073A JP2020191012A5 JP 2020191012 A5 JP2020191012 A5 JP 2020191012A5 JP 2019097073 A JP2019097073 A JP 2019097073A JP 2019097073 A JP2019097073 A JP 2019097073A JP 2020191012 A5 JP2020191012 A5 JP 2020191012A5
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- image processing
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- 230000015654 memory Effects 0.000 claims description 35
- 238000013528 artificial neural network Methods 0.000 claims description 10
- 238000005070 sampling Methods 0.000 claims 4
- 238000011176 pooling Methods 0.000 claims 3
- 238000003384 imaging method Methods 0.000 claims 2
- 238000003672 processing method Methods 0.000 claims 2
- 238000004364 calculation method Methods 0.000 claims 1
- 238000004590 computer program Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 230000006870 function Effects 0.000 claims 1
Description
本発明の一様態は、階層型ニューラルネットワークの各階層における演算を行う複数の演算部を有する画像処理装置であって、
前記演算部が処理対象とする階層の特徴画像をブロックの２次元配列に分割し、それぞれのブロックを所定個数のメモリのいずれかに格納する格納制御手段と、
前記特徴画像に対する演算に関する情報に基づいて前記メモリからブロックを読み出すパターンであるメモリアクセスパターンを決定する決定手段と、
前記メモリから前記メモリアクセスパターンに従ってブロックを読み出す読み出し手段と
を備え、
前記格納制御手段は、
前記２次元配列に対して、先頭の行／列から、行／列に沿って前記所定個数のメモリを所定の順序で繰り返し割り当てるようにし、２番目以降の行／列では、割り当てを開始するメモリを、前記所定の順序において直前の行／列と一定個数だけずらす
ことを特徴とする。
The uniformity of the present invention is an image processing apparatus having a plurality of arithmetic units that perform arithmetic operations in each layer of a hierarchical neural network.
A storage control means that divides the feature image of the hierarchy to be processed by the arithmetic unit into a two-dimensional array of blocks and stores each block in any of a predetermined number of memories.
A determination means for determining a memory access pattern, which is a pattern for reading a block from the memory, based on information about an operation on the feature image.
A reading means for reading a block from the memory according to the memory access pattern is provided.
The storage control means is
The predetermined number of memories are repeatedly allocated in a predetermined order along the rows / columns from the first row / column to the two-dimensional array, and the memory that starts allocation in the second and subsequent rows / columns. Is shifted by a certain number from the immediately preceding row / column in the predetermined order.
It is characterized by that.
Claims (16)
前記演算部が処理対象とする階層の特徴画像をブロックの２次元配列に分割し、それぞれのブロックを所定個数のメモリのいずれかに格納する格納制御手段と、
前記特徴画像に対する演算に関する情報に基づいて前記メモリからブロックを読み出すパターンであるメモリアクセスパターンを決定する決定手段と、
前記メモリから前記メモリアクセスパターンに従ってブロックを読み出す読み出し手段と
を備え、
前記格納制御手段は、
前記２次元配列に対して、先頭の行／列から、行／列に沿って前記所定個数のメモリを所定の順序で繰り返し割り当てるようにし、２番目以降の行／列では、割り当てを開始するメモリを、前記所定の順序において直前の行／列と一定個数だけずらす
ことを特徴とする画像処理装置。 An image processing device having a plurality of arithmetic units that perform operations in each layer of a hierarchical neural network.
A storage control means that divides the feature image of the hierarchy to be processed by the arithmetic unit into a two-dimensional array of blocks and stores each block in any of a predetermined number of memories.
A determination means for determining a memory access pattern, which is a pattern for reading a block from the memory, based on information about an operation on the feature image.
A reading means for reading a block from the memory according to the memory access pattern is provided.
The storage control means is
The predetermined number of memories are repeatedly allocated in a predetermined order along the rows / columns from the first row / column to the two-dimensional array, and the memory that starts allocation in the second and subsequent rows / columns. Is shifted by a certain number from the immediately preceding row / column in the predetermined order.
An image processing device characterized by this.
前記読み出し手段は、前記メモリアクセスパターンに従って前記所定個数のメモリから１サイクルでブロックを読み出すThe read means reads a block from the predetermined number of memories in one cycle according to the memory access pattern.
ことを特徴とする請求項１に記載の画像処理装置。The image processing apparatus according to claim 1.
前記格納制御手段は、
前記特徴画像において第１方向に並ぶ着目ブロック列をＮ２個のブロックのグループを単位に分割した場合に、それぞれのグループについて、該グループに属するブロック０～（Ｎ２－１）をメモリ０～（Ｎ２－１）のそれぞれに格納した場合、前記着目ブロック列においてメモリｐ（ｐ＝０～（Ｎ２－１））に格納されたブロックの直下のブロックを、メモリｑ（ｑ＝ｍｏｄ（ｐ＋Ｎ，Ｎ２））に格納することを特徴とする請求項３に記載の画像処理装置。 The predetermined number of memories includes memory 0 to memory (N 2-1 ).
The storage control means is
When the block sequence of interest arranged in the first direction in the feature image is divided into groups of N two blocks, the blocks 0 to (N 2-1 ) belonging to the group are stored in the memory 0 to each group. When stored in each of (N 2-1 ), the block immediately below the block stored in the memory p (p = 0 to (N 2-1 )) in the block sequence of interest is stored in the memory q (q = modd). The image processing apparatus according to claim 3 , wherein the image processing apparatus is stored in p + N, N2 )).
請求項１乃至１２の何れか１項に記載の画像処理装置による前記画像に対する演算結果を出力する出力手段と
を備えることを特徴とする撮像装置。 Image input means for acquiring images by imaging,
An image pickup apparatus including an output means for outputting an operation result for the image by the image processing apparatus according to any one of claims 1 to 12 .
前記画像処理装置の格納制御手段が、前記演算部が処理対象とする階層の特徴画像をブロックの２次元配列に分割し、それぞれのブロックを所定個数のメモリのいずれかに格納する格納制御工程と、
前記画像処理装置の決定手段が、前記特徴画像に対する演算に関する情報に基づいて前記メモリからブロックを読み出すパターンであるメモリアクセスパターンを決定する決定工程と、
前記画像処理装置の読み出し手段が、前記メモリから前記メモリアクセスパターンに従ってブロックを読み出す読み出し工程と
を備え、
前記格納制御工程では、
前記２次元配列に対して、先頭の行／列から、行／列に沿って前記所定個数のメモリを所定の順序で繰り返し割り当てるようにし、２番目以降の行／列では、割り当てを開始するメモリを、前記所定の順序において直前の行／列と一定個数だけずらす
ことを特徴とする画像処理方法。 It is an image processing method performed by an image processing device having a plurality of arithmetic units that perform operations in each layer of a hierarchical neural network.
A storage control step in which the storage control means of the image processing device divides the feature image of the hierarchy to be processed by the calculation unit into a two-dimensional array of blocks, and stores each block in any of a predetermined number of memories. ,
A determination step in which the determination means of the image processing device determines a memory access pattern, which is a pattern of reading blocks from the memory based on information regarding operations on the feature image.
The reading means of the image processing device includes a reading step of reading a block from the memory according to the memory access pattern.
In the storage control step,
The predetermined number of memories are repeatedly allocated in a predetermined order along the rows / columns from the first row / column to the two-dimensional array, and the memory that starts allocation in the second and subsequent rows / columns. Is shifted by a certain number from the immediately preceding row / column in the predetermined order.
An image processing method characterized by that.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019097073A JP7278150B2 (en) | 2019-05-23 | 2019-05-23 | Image processing device, imaging device, image processing method |
| US16/876,224 US11775809B2 (en) | 2019-05-23 | 2020-05-18 | Image processing apparatus, imaging apparatus, image processing method, non-transitory computer-readable storage medium |
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| JP2019097073A JP7278150B2 (en) | 2019-05-23 | 2019-05-23 | Image processing device, imaging device, image processing method |
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|---|---|
| JP2020191012A JP2020191012A (en) | 2020-11-26 |
| JP2020191012A5 true JP2020191012A5 (en) | 2022-06-03 |
| JP7278150B2 JP7278150B2 (en) | 2023-05-19 |
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| US11113838B2 (en) * | 2019-03-26 | 2021-09-07 | Nec Corporation | Deep learning based tattoo detection system with optimized data labeling for offline and real-time processing |
| CN114168524B (en) * | 2021-12-07 | 2023-10-20 | 平头哥(上海)半导体技术有限公司 | Line cache unit, acceleration unit, system on chip and line cache configuration method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5171118B2 (en) * | 2007-06-13 | 2013-03-27 | キヤノン株式会社 | Arithmetic processing apparatus and control method thereof |
| JP5184824B2 (en) * | 2007-06-15 | 2013-04-17 | キヤノン株式会社 | Arithmetic processing apparatus and method |
| JP5368687B2 (en) * | 2007-09-26 | 2013-12-18 | キヤノン株式会社 | Arithmetic processing apparatus and method |
| US10175980B2 (en) | 2016-10-27 | 2019-01-08 | Google Llc | Neural network compute tile |
| JP6945986B2 (en) * | 2016-10-28 | 2021-10-06 | キヤノン株式会社 | Arithmetic circuit, its control method and program |
| JP6961011B2 (en) | 2016-12-09 | 2021-11-05 | ベイジン ホライズン インフォメーション テクノロジー カンパニー リミテッド | Systems and methods for data management |
| JP6823495B2 (en) * | 2017-02-27 | 2021-02-03 | 株式会社日立製作所 | Information processing device and image recognition device |
| JP6936592B2 (en) * | 2017-03-03 | 2021-09-15 | キヤノン株式会社 | Arithmetic processing unit and its control method |
| US10387298B2 (en) | 2017-04-04 | 2019-08-20 | Hailo Technologies Ltd | Artificial neural network incorporating emphasis and focus techniques |
| CN107704923A (en) * | 2017-10-19 | 2018-02-16 | 珠海格力电器股份有限公司 | Convolutional neural networks computing circuit |
| JP7391553B2 (en) * | 2019-06-28 | 2023-12-05 | キヤノン株式会社 | Information processing device, information processing method, and program |
| JP7299770B2 (en) * | 2019-07-01 | 2023-06-28 | キヤノン株式会社 | Arithmetic processing device and arithmetic processing method |
| JP7308674B2 (en) * | 2019-07-08 | 2023-07-14 | キヤノン株式会社 | Arithmetic processing device and arithmetic processing method |
| JP2021118403A (en) * | 2020-01-23 | 2021-08-10 | キヤノン株式会社 | Image processing device, control method thereof, program, and image processing system |
| JP2023013004A (en) * | 2021-07-15 | 2023-01-26 | 株式会社ディスコ | Formation method for multilayer device wafer |
| US20220222771A1 (en) * | 2022-03-31 | 2022-07-14 | Intel Corporation | Multi-directional rolling cache and methods therefor |
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