JP2020182168A - Control circuit and controller - Google Patents

Abstract

To protect an electrostatic type transducer from a DC voltage of at least a predetermined value.SOLUTION: A control circuit, protecting an electrostatic type transducer capable of generating vibration, sound or pressure and detecting vibration, sound or pressure from an overvoltage, includes: a timer circuit section for measuring a duration for which a driving voltage for generating vibration, sound or pressure at the electrostatic type transducer is at least a predetermined threshold voltage when the driving voltage is at least the threshold voltage and outputs a pulse signal when the duration is a predetermined first duration, and a voltage output circuit control section for outputting a driving voltage stopping signal for stopping application of a driving voltage to the electrostatic type transducer upon reception of the pulse signal and determining whether or not the driving voltage is at least the threshold voltage at every predetermined first period and when the driving voltage is less than the threshold voltage, stopping an output of the driving voltage stopping signal and applying the driving voltage to the electrostatic type transducer.SELECTED DRAWING: Figure 2

Description

The present invention relates to a control circuit and a control device.

Patent Document 1 describes an electrostatic transducer capable of generating vibration or sound and detecting vibration or sound.

JP-A-2017-183814

In smart rubber actuators that also have a capacitance type actuator function, a pulse-by-pulse type overvoltage protection circuit is provided to protect the load from transient overvoltage. Here, a sine wave or a triangular wave voltage is input to the actuator instead of a DC voltage. Therefore, even when the voltage does not reach the threshold value for protecting the overvoltage protection circuit, it is preferable to apply protection when a high DC voltage is applied to the load.

An object of the present invention is to provide a control circuit and a control device capable of protecting an electrostatic transducer from a DC voltage exceeding a predetermined value.

The control circuit of one aspect of the present invention is a control circuit that protects an electrostatic transducer capable of generating vibration, sound or pressure and detecting vibration, sound or pressure from overvoltage, and is the electrostatic transducer. When the drive voltage for generating vibration, sound, or pressure becomes equal to or higher than a predetermined threshold voltage, the duration at which the drive voltage becomes equal to or higher than the threshold voltage is measured, and the duration is a predetermined number. A timer circuit unit that outputs a pulse signal when the duration reaches one, and a drive voltage stop signal that stops the application of the drive voltage to the electrostatic transducer when the pulse signal is received are output. When the drive voltage stop signal is output, it is determined whether or not the drive voltage is equal to or higher than the threshold voltage every predetermined first cycle, and when the drive voltage is less than the threshold voltage, it is determined. It is provided with a voltage output circuit control unit that stops the output of the drive voltage stop signal and applies the drive voltage to the electrostatic transducer.

Further, in the control circuit, the timer circuit unit starts counting when the drive voltage, the comparator comparing the threshold voltage, and the output signal of the comparator are at the first level, and the output signal is at the second level. It has a timer unit that stops counting when the value becomes, and a pulse signal output unit that outputs the pulse signal when the duration at which the output signal is the first level reaches the first duration. ..

Further, in the control circuit, when the drive voltage stop signal is output, the timer unit continues counting regardless of whether the output signal of the comparator is the first level or the second level, and has a predetermined first cycle. The pulse signal is output each time, and the voltage output circuit control unit determines whether the output signal of the comparator is the first level or the second level each time the pulse signal is output, and outputs the comparator. If the signal is at the first level, the output and count of the drive voltage stop signal are continued, and if the output signal of the comparator is at the second level, the drive stop signal is stopped and the count is stopped. Has a function.

Further, in the control circuit, the voltage output circuit control unit is set or reset when the output signal is at the first level and the pulse signal is output, and the output signal is at the second level. Switching that stops the application of the drive voltage to the electrostatic transducer based on the flip-flop that is reset or set when the pulse signal is output and the drive voltage stop signal that is output from the flip-flop. It has a signal output unit, and the timer unit stops counting when the flip-flop is reset or set.

Further, the flip-flop is a control for switching the first duration, which is the duration until the pulse signal is output, to the second duration, which is longer than the first duration, when the flip-flop is set or reset. The signal is output to the timer unit.

The control device of one aspect of the present invention includes a control circuit of one aspect of the present invention and a voltage output circuit connected to the control circuit and applying a voltage to the electrostatic transducer.

In addition, the control device further includes an inverter.

According to the present invention, the electrostatic transducer can be protected from a DC voltage equal to or higher than a predetermined value.

FIG. 1 is a diagram showing an example of the configuration of the control system according to the first embodiment of the present invention. FIG. 2 is a diagram showing an example of a detailed configuration of a driver for the control system according to the first embodiment of the present invention. FIG. 3 is a diagram showing voltage waveforms at each location in the control system according to the first embodiment of the present invention. FIG. 4 is a flowchart showing an example of a flow of processing in which the control circuit according to the first embodiment of the present invention stops / returns the operation of the voltage output circuit.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to this embodiment, and when there are a plurality of embodiments, the present invention also includes a combination of the respective embodiments.

(First Embodiment)
The configuration of the control system according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing an example of the configuration of the control system according to the first embodiment of the present invention. FIG. 2 is a diagram showing an example of a detailed configuration of a driver for the control system according to the first embodiment of the present invention.

As shown in FIG. 1, the control system 1 includes a driver (control device) 2, a microcomputer 3, a DC power supply 4, and an electrostatic transducer 5.

The driver 2 drives the electrostatic transducer 5 according to the control signal from the output control signal output circuit 31 of the microcomputer 3. The driver 2 converts the electric power received from the DC power supply 4 and applies the converted electric power to the electrostatic transducer 5.

The electrostatic transducer 5 is exemplified by the electrostatic transducer described in Patent Document 1, but the present disclosure is not limited to this. The electrostatic transducer 5 may be referred to as an electrostatic actuator or an electrostatic pressure detecting element. The electrostatic transducer 5 is represented by an equivalent circuit of a resistor 21 and a capacitor 22 connected in series and a resistor 23 connected in parallel to the capacitor 22. When a high voltage (for example, 410 V) is applied, the electrostatic transducer 5 can generate vibration, sound, or pressure by changing the distance between both electrodes of the capacitor 22. When vibration, sound or pressure is applied, the electrostatic transducer 5 can detect vibration, sound or pressure by changing the capacitance by changing the distance between both electrodes of the capacitor 22. ..

The driver 2 according to the first embodiment of the present invention will be described with reference to FIG. The driver 2 includes a voltage output circuit 6 and a control circuit 7.

The voltage output circuit 6 is a flyback type converter, but the present disclosure is not limited thereto. The voltage output circuit 6 may be a forward type converter or an inverter.

The control circuit 7 controls the voltage output circuit 6 under the control of the microcomputer 3. Under the control of the control circuit 7, the voltage output circuit 6 converts the electric power of the DC power supply 4 and applies the converted electric power to the electrostatic transducer 5.

The voltage of the DC power supply 4 is exemplified by 12V, but the present disclosure is not limited to this. The voltage applied to the electrostatic transducer 5 by the voltage output circuit 6 is a voltage that changes in a sinusoidal manner between 0V and 410V, but the present disclosure is not limited to this.

The control circuit 7 operates the voltage output circuit 6 when the electrostatic transducer 5 generates vibration, sound, or pressure.

The control circuit 7 stops the voltage output circuit 6 when the electrostatic transducer 5 detects vibration, sound, or pressure.

The control circuit 7 is a driver IC (Integrated Circuit), but the present disclosure is not limited to this.

(Configuration of voltage output circuit)
The voltage output circuit 6 includes a transformer 11, diodes 12 and 14, N-channel transistors 13 and 15, resistors 16 and 17, and a voltage divider circuit 18.

The voltage dividing circuit 18 outputs the voltage dividing voltage S4 obtained by dividing the voltage of the electrostatic transducer 5 to the control circuit 7. The voltage dividing circuit 18 is exemplified to divide the voltage of the electrostatic transducer 5 to 1/410, but the present disclosure is not limited to this.

In the first embodiment, since the voltage output circuit 6 is a flyback type converter, the primary winding 11a and the secondary winding 11b of the transformer 11 are wound in opposite polarities.

The voltage output circuit 6 is a regenerative type, and the primary side circuit and the secondary side circuit are symmetrical. Although the voltage output circuit 6 is a regenerative type, the present disclosure is not limited to this.

By making the voltage output circuit 6 a regenerative type, the electric power on the electrostatic transducer 5 side can be regenerated to the DC power supply 4 side, so that the power loss can be suppressed.

One end of the primary winding 11a of the transformer 11 is electrically connected to the terminal on the high potential side of the DC power supply 4. The anode of the diode 12 is electrically connected to the terminal on the low potential side of the DC power supply 4. The terminal on the low potential side of the DC power supply 4 is electrically connected to the reference potential. The reference potential is exemplified by the ground potential, but the present disclosure is not limited to this.

The cathode of the diode 12 is electrically connected to the other end of the primary winding 11a of the transformer 11. The drain-source path of the transistor 13 is electrically connected in parallel to the diode 12. A first switching signal S2 is input from the control circuit 7 to the gate of the transistor 13 via a resistor 16.

One end of the secondary winding 11b of the transformer 11 is electrically connected to one end of the electrostatic transducer 5. The anode of the diode 14 is electrically connected to the other end of the electrostatic transducer 5. The other end of the electrostatic transducer 5 is electrically connected to the reference potential.

The cathode of the diode 14 is electrically connected to the other end of the secondary winding 11b of the transformer 11. The drain-source path of the transistor 15 is electrically connected in parallel to the diode 14. A second switching signal S3 is input from the control circuit 7 to the gate of the transistor 15 via a resistor 17.

When the voltage of the electrostatic transducer 5 is increased (for example, when the voltage of the electrostatic transducer 5 is increased in a sinusoidal manner from 0V to 410V), the control circuit 7 sends a first switching signal S2 of PWM (Pulse Width Modulation) to the transistor 13. The output is output to the gate, and the transistor 13 is switched.

While the transistor 13 is in the ON state, energy is stored on the primary winding 11a side of the transformer 11. Energy is released from the secondary winding 11b of the transformer 11 while the transistor 13 is in the off state. The energy released from the secondary winding 11b is rectified by the diode 14 and input to the electrostatic transducer 5.

When the voltage of the electrostatic transducer 5 is lowered (for example, when the voltage is lowered from 410V to 0V in a sinusoidal manner), the control circuit 7 outputs the second PWM switching signal S3 to the gate of the transistor 15. The transistor 15 is switched.

While the transistor 15 is in the ON state, energy is stored on the secondary winding 11b side of the transformer 11. Energy is released from the primary winding 11a of the transformer 11 while the transistor 15 is off. The energy released from the primary winding 11a is rectified by the diode 12 and input to the DC power supply 4.

The capacitor 10 is electrically connected in parallel to the electrostatic transducer 5. The capacitor 10 smoothes the voltage applied to the electrostatic transducer 5.

(Control circuit configuration)
The control circuit 7 includes a timer circuit unit 8 and a voltage output circuit control unit 9.

The timer circuit unit 8 includes a comparator 41, a timer threshold power supply 42, a NOR gate 43, a timer unit 44, a timer capacitor 45, a one-shot pulse circuit 46, and a NOT gate 47.

A voltage dividing circuit 18 is connected to the non-inverting input terminal of the comparator 41. The voltage dividing voltage S4 is input from the voltage dividing circuit 18 to the non-inverting input terminal of the comparator 41.

A timer threshold power supply 42 is connected to the inverting input terminal of the comparator 41. A predetermined timer threshold voltage predetermined from the timer threshold power supply 42 is input to the inverting input terminal of the comparator 41. The timer threshold voltage is a voltage lower than the threshold voltage which is regarded as a transient overvoltage. The timer threshold voltage is set between the maximum output voltage specified in the voltage output circuit 6 (for example, 410V) and the threshold voltage regarded as a transient overvoltage (for example, 450V). The timer threshold voltage is, for example, 420V to 430V when the voltage applied to the electrostatic transducer 5 is 0V to 410V. Specifically, the timer threshold power supply 42 inputs a voltage obtained by dividing 420V to 430V according to the voltage dividing ratio of the voltage dividing circuit 18 as a timer threshold voltage to the inverting input terminal of the comparator 41.

The comparator 41 compares the voltage dividing voltage S4 with the threshold voltage. That is, the comparator 41 determines whether or not a voltage higher than the threshold value regarded as a DC overvoltage is applied to the electrostatic transducer 5. The comparator 41 outputs a high-level output signal to the NOR gate 43 when the voltage dividing voltage S4 exceeds the threshold voltage.

One input terminal of the NOR gate 43 is connected to the output terminal of the comparator 41. The other input terminal of the NOR gate 43 is connected to the Q terminal of the flip-flop 58. The NOR gate 43 outputs a high-level output signal to the T terminal of the timer unit 44 when a low-level output signal is input from both the comparator 41 and the flip-flop 58. When a high-level output signal is input from at least one of the comparator 41 and the flip-flop 58, the NOR gate 43 outputs a low-level output signal to the T terminal of the timer unit 44.

The timer unit 44 starts counting when the first level signal is output from the comparator 41, and measures the duration during which the comparator 41 outputs the first level signal. The timer unit 44 stops counting when a second level signal is output from the comparator 41. In the present embodiment, it is assumed that the first level is a high level and the second level is a low level, but the present invention is not limited thereto.

The timer unit 44 starts counting when a low-level output signal is input from the NOR gate 43. That is, the timer unit 44 measures the duration of application of the overvoltage to the electrostatic transducer 5. Specifically, a timer capacitor 45 connected to a constant current source is connected to the C terminal of the timer unit 44. When a low-level output signal is input to the T terminal of the timer unit 44, the timer capacitor 45 starts charging and then periodically repeats charging and discharging. The timer unit 44 measures the time based on, for example, the time for one cycle of charging and discharging the timer capacitor 45.

If the voltage dividing voltage S4 falls below the threshold voltage while the timer unit 44 is measuring the duration of application of the overvoltage, the comparator 41 outputs a low-level output signal to the NOR gate 43. In this case, since the low level output signal is input to the NOR gate 43 from both the comparator 41 and the flip-flop 58, the high level output signal is input to the T terminal of the timer unit 44. The timer unit 44 resets the count when a high-level output signal is input to the T terminal. After that, when the voltage dividing voltage S4 exceeds the threshold voltage again, the timer unit 44 starts counting again.

The input terminal of the one-shot pulse circuit 46 is connected to the output terminal of the timer unit 44. The one-shot pulse circuit 46 outputs a pulse signal having a predetermined time width to the AND gate 54 when the time when the overvoltage is applied to the electrostatic transducer 5 exceeds a predetermined time.

The NOT gate 47 is arranged between the output terminal of the NOR gate 43 and the input terminal of the AND gate 54. The NOT gate 47 inverts the high-level or low-level output signal output from the NOR gate 43 and outputs it to the AND gate 54.

The voltage output circuit control unit 9 switches the comparator 51, the threshold power supply 52, the error amplifier 53, the AND gate 54, the NAND gate 55, the 3-terminal NAND gate 56, the NOT gate 57, the flip-flop 58, and the like. It includes a signal output unit 59, a buffer 60, and a buffer 61.

A threshold power supply 52 is connected to the inverting input terminal of the comparator 51. A predetermined threshold voltage predetermined from the threshold power supply 52 is input to the inverting input terminal of the comparator 51. The predetermined threshold voltage is a voltage value at which the voltage applied to the electrostatic transducer 5 is regarded as a transient overvoltage. Specifically, when the voltage applied to the electrostatic transducer 5 is 0V to 410V, it is, for example, 450V.

The comparator 51 compares the voltage dividing voltage S4 with the threshold voltage. That is, the comparator 51 determines whether or not a transient overvoltage is applied to the electrostatic transducer 5. The comparator 51 outputs a high-level output signal to the switching signal output unit 59 when the voltage dividing voltage S4 exceeds the threshold voltage. The comparator 51 stops the operation of the voltage output circuit 6 by outputting a high-level output signal to the switching signal output unit 59. That is, the comparator 51 and the threshold power supply 52 function as a pulse-by-pulse type overvoltage protection function.

The output control signal output circuit 31 of the microcomputer 3 is connected to the non-inverting input terminal of the error amplifier 53. The output control signal S1 is input from the output control signal output circuit 31 to the non-inverting input terminal of the error amplifier 53.

A voltage dividing circuit 18 is connected to the inverting input terminal of the error amplifier 53. The voltage dividing voltage S4 is input from the voltage dividing circuit 18 to the inverting input terminal of the error amplifier 53.

The error amplifier 53 outputs a signal corresponding to the difference between the output control signal S1 and the voltage dividing voltage S4 to the switching signal output unit 59. For example, the error amplifier 53 amplifies the difference between the output control signal S1 and the voltage dividing voltage S4, and outputs the difference to the switching signal output unit 59.

The output terminal of the one-shot pulse circuit 46 is connected to one input terminal of the AND gate 54, and the output terminal of the NOT gate 47 is connected to the other input terminal. When both the output signal of the one-shot pulse circuit 46 and the output signal of the NOT gate 47 are high-level, the AND gate 54 transmits the high-level output signal to the NAND gate 55 and the 3-terminal NAND gate 56. Output. When at least one of the output signal of the one-shot pulse circuit 46 and the output signal of the NOT gate 47 is low level, the AND gate 54 sets the low level output signal to the NAND gate 55 and the three-terminal NAND gate 56. Output to.

The output terminal of the comparator 41 is connected to one input terminal of the NAND gate 55, and the output terminal of the AND gate 54 is connected to the other input terminal. The NAND gate 55 outputs a low-level output signal to the S terminal of the flip-flop 58 when both the output signal of the comparator 41 and the output signal of the AND gate 54 are high-level. The NAND gate 55 outputs a high level output signal to the S terminal of the flip-flop 58 when at least one of the output signal of the comparator 41 and the output signal of the AND gate 54 is low level.

The output terminal of the comparator 41 is connected to the first input terminal of the 3-terminal NAND gate 56 via the NOT gate 57. That is, the output signal of the comparator 41 is input to the first input terminal of the 3-terminal NAND gate 56 via the NOT gate 57. The output terminal of the AND gate 54 is connected to the second input terminal of the 3-terminal NAND gate 56. The Q terminal of the flip-flop 58 is connected to the third input terminal of the 3-terminal NAND gate 56. The 3-terminal NAND gate 56 flips a low-level output signal when the output signal of the NOT gate 57, the output signal of the AND gate 54, and the output signal from the Q terminal of the flip-flop 58 are all high-level. Output to the R terminal of the flip-flop 58. The 3-terminal NAND gate 56 outputs a high-level output signal when at least one of the output signal of the NOT gate 57, the output signal of the AND gate 54, and the output signal from the Q terminal of the flip-flop 58 is low level. Output to the R terminal of the flip-flop 58.

The output terminal of the NAND gate 55 is connected to the S terminal of the flip-flop 58. The output terminal of the 3-terminal NAND gate 56 is connected to the R terminal of the flip-flop 58. The Q terminal of the flip-flop 58 is connected to the switching signal output unit 59. The Q bar terminal of the flip-flop 58 is connected to the timer unit 44.

The flip-flop 58 is set when the output signal of the NAND gate 55 is low level, and outputs a high level detection control signal to the switching signal output unit 59. The high-level detection control signal output by the flip-flop 58 is also called a drive voltage stop signal. Further, the flip-flop 58 may be set when the input signal of the S terminal is at a high level. In this case, the NAND gate 55 is replaced with an AND gate and is set when the output signal of the AND gate is at a high level.

The flip-flop 58 is reset when the output signal of the 3-terminal NAND gate 56 is low level, and outputs the low level detection control signal to the switching signal output unit 59.

The flip-flop 58 may be reset when the input signal of the R terminal is at a high level. In this case, the 3-terminal NAND gate 56 is replaced with an AND gate, and is reset when the output signal of the AND gate is at a high level.

The flip-flop 58 outputs a timer control signal, which is an inverted signal of the detection control signal output to the switching signal output unit 59, to the timer unit 44. Specifically, the flip-flop 58 outputs a low-level timer control signal to the timer unit 44 when it is set. When the flip-flop 58 is reset, the flip-flop 58 outputs a high-level timer control signal to the timer unit 44. The flip-flop 58 switches from a normal timer to a long timer by outputting a low-level timer control signal to the timer unit 44. The flip-flop 58 switches from a long timer to a normal timer by outputting a high-level timer control signal to the timer unit 44.

When a high-level output signal is input from the comparator 51, the switching signal output unit 59 stops the operation of the voltage output circuit 6 without outputting the first switching signal S2 and the second switching signal S3. Further, the switching signal output unit 59 operates the voltage output circuit 6 without outputting the first switching signal S2 and the second switching signal S3 even when a high level detection signal is input from the flip-flop 58. Stop it.

(Operation of control circuit)
Next, the operation of the control circuit will be described with reference to FIGS. 2 and 3. FIG. 3 is a diagram showing voltage waveforms at each location in the control system 1.

In FIG. 3, VA is the output signal of the comparator 41, VB is the output signal of the NOR gate 43, VT is the output signal of the timer capacitor 45, VC is the output signal of the timer unit 44, VD is the output signal of the AND gate 54, and VE. Is the output signal of the NAND gate 55, VF is the output signal of the 3-terminal NAND gate 56, and VG is the output signal level of the flip-flop 58. Further, in FIG. 3, “H” means a high level and “L” means a low level.

(Stop processing of voltage output circuit)
First, a process of stopping the operation of the voltage output circuit 6 when an overvoltage is applied to the electrostatic transducer 5 for a predetermined time will be described.

It is assumed that an overvoltage is applied to the electrostatic transducer 5 at the time point t1. In this case, the comparator 41 outputs a high-level output signal to the NOR gate 43. Since the high level output signal is input from the comparator 41 to the NOR gate 43, the low level level output signal is input to the T terminal of the timer unit 44. As a result, the timer unit 44 starts counting the timer by the timer capacitor 45, and measures the time when the overvoltage is applied to the electrostatic transducer 5.

It is assumed that the voltage applied to the electrostatic transducer 5 at the time point t2 falls below the threshold voltage. In this case, since the time T1 from the time point t1 to the time point t2 has not reached the predetermined time, the timer unit 44 resets the count and resets the time measurement.

It is assumed that the overvoltage is applied to the electrostatic transducer 5 again at the time point t3. In this case, the timer unit 44 assumes that the time T2 from the time point t3 to the time point t4 is the first duration of the electrostatic transducer 5. The first duration is the normal timer cycle P1 in which the timer capacitor 45 is the time for one cycle of charging and discharging. When the first duration elapses, the one-shot pulse circuit 46 outputs a pulse signal having a predetermined time width to the AND gate 54. That is, the first duration is the time when the pulse signal is output from the one-shot pulse circuit 46. Specifically, the one-shot pulse circuit 46 periodically outputs a pulse signal each time the first duration elapses.

At time point t4, a pulse signal is input to one of the input terminals of the AND gate 54. At this time, the output signal of the NOR gate 43 is low level, but the output signal is input to the other input terminal of the AND gate 54 via the NOT gate 47. Therefore, a high-level output signal is also input to the other input terminal of the AND gate 54. In this case, the AND gate 54 outputs a high-level output signal to the NAND gate 55 and the 3-terminal NAND gate 56.

At time point t4, a high level output signal is input from the AND gate 54 to one of the input terminals of the NAND gate 55. A high-level output signal is input from the comparator 41 to the other input terminal of the NAND gate 55. As a result, the NAND gate 55 outputs a low-level output signal to the S terminal of the flip-flop 58.

At time point t4, a low-level output signal is input from the NAND gate 55 to the S terminal of the flip-flop 58. The flip-flop 58 is set when a low-level output signal is input to the S terminal, and outputs a high-level detection control signal to the switching signal output unit 59. As described above, the switching signal output unit 59 stops the voltage output circuit 6 when a high-level detection control signal is input.

When the flip-flop 58 is set, the flip-flop 58 outputs a timer control signal for controlling the timer unit 44 to the timer unit 44. The timer control signal is an inverted signal of the detection control signal. That is, the flip-flop 58 outputs a low-level timer control signal to the timer unit 44.

When a low-level timer control signal is input, the timer unit 44 switches the timer count time to a longer timer than usual. Specifically, the timer unit 44 reduces the current of the timer capacitor 45 and lengthens the time for one cycle of charging and discharging the timer capacitor 45. As shown in the VT of FIG. 3, the time for one cycle is lengthened from the normal timer cycle P1 to the long timer cycle P2. The long timer cycle P2 is also referred to as the second duration. When the timer unit 44 is switched to the long timer, even if the comparator 41 outputs a low-level signal, the timer unit 44 does not stop counting and continues to measure the time. Therefore, the one-shot pulse circuit 46 outputs a pulse signal at the timing of one cycle of the long timer cycle P2 until the voltage output circuit 6 is restored. As a result, the accuracy of the overvoltage protection function for the electrostatic transducer 5 is improved. In the present embodiment, the voltage output circuit 6 is kept stopped while the voltage applied to the electrostatic transducer 5 is equal to or higher than the threshold voltage.

(Reset processing of voltage output circuit)
Next, a process of restoring the operation of the voltage output circuit 6 after stopping the voltage output circuit 6 will be described.

The comparator 41 outputs a low-level output signal to the NAND gate 55 at t5 when the voltage dividing voltage S4 falls below the timer threshold voltage. In this case, the NAND gate 55 outputs a high-level output signal to the S terminal of the flip-flop 58. Therefore, the flip-flop 58 is not set.

Further, the comparator 41 inputs a low-level output signal to the first input terminal of the 3-terminal NAND gate 56 via the NOT gate 57. That is, a high-level output signal is input to the first input terminal of the 3-terminal NAND gate 56.

Further, the comparator 41 inputs a low level output signal to the NOR gate 43. The flip-flop 58 inputs a high-level output signal to the NOR gate 43. In this case, the NOR gate 43 outputs a low-level output signal to the T terminal of the timer unit 44. As a result, even if the comparator 41 outputs a low level, the counting is not stopped and the time measurement is continued.

Since the timer unit 44 measures the time based on the long timer cycle P2, the one-shot pulse circuit 46 outputs a pulse signal to the AND gate 54 at the timing of the long timer cycle P2. In the example shown in FIG. 3, the one-shot pulse circuit 46 outputs a pulse signal to the AND gate 54 at the timing of the time point t6.

A high-level output signal is input to one input terminal of the AND gate 54. A low-level output signal output by the comparator 41 is input to the other input terminal of the AND gate 54 via the NOT gate 47. That is, a high-level output signal is input to the other input terminal of the AND gate 54. As a result, the AND gate 54 outputs a high-level output signal to the second input terminal of the NAND gate 55 and the 3-terminal NAND gate 56.

The flip-flop 58 outputs a high-level output signal to the third input terminal of the 3-terminal NAND gate 56.

In the 3-terminal NAND gate 56, a high-level output signal is input to the first input terminal, a high-level output signal is input to the second input terminal, and a high-level output is input to the third input terminal. Since the signal is input, the low level output signal is input to the R terminal of the flip flop 58. As a result, the flip-flop 58 is reset and outputs a low-level detection control signal to the switching signal output unit 59. In this case, the flip-flop 58 outputs a high-level timer control signal to the timer unit 44.

When a low-level detection control signal is input, the switching signal output unit 59 outputs the first switching signal S2 or the second switching signal S3 to the voltage output circuit 6 to restore the operation of the voltage output circuit 6. .. The first switching signal S2 is input to the voltage output circuit 6 via the buffer 60. The second switching signal S3 is input to the voltage output circuit 6 via the buffer 61. Specifically, in the example shown in FIG. 3, the voltage output circuit 6 returns at the timing of the time point t6. That is, in the present embodiment, the voltage output circuit 6 does not recover immediately after the overvoltage is no longer applied to the electrostatic transducer 5, but after a predetermined period of time has elapsed after the overvoltage is no longer applied to the electrostatic transducer 5. Return.

When a high-level timer control signal is input, the timer unit 44 switches the long timer to the normal timer. In the example shown in FIG. 3, the timer unit 44 switches from the long timer cycle P2 to the normal timer cycle P1 at the timing of the time point t6. Specifically, the timer unit 44 determines the time until the pulse signal is output from the one-shot pulse circuit 46 when the high-level timer control signal is input after the low-level timer control signal is input. , The long timer cycle P2 is returned to the normal timer cycle P1 and the count is stopped.

(Flow of stop / return processing of voltage output circuit)
A process in which the control circuit 7 stops and restores the operation of the voltage output circuit 6 will be described with reference to FIG. FIG. 4 is a flowchart showing an example of a processing flow in which the control circuit 7 stops and returns the operation of the voltage output circuit 6.

First, the control circuit 7 determines whether or not an overvoltage is applied to the electrostatic transducer 5 (step S101). If it is determined that an overvoltage is applied to the electrostatic transducer 5 (Yes in step S101), the process proceeds to steps S102 and S103. When it is determined that the overvoltage is not applied to the electrostatic transducer 5 (No in step S101), the process returns to step S101.

The control circuit 7 measures the time when the overvoltage is applied to the electrostatic transducer 5 (step S102). Then, the process proceeds to step S103.

The control circuit 7 determines in step S103 whether or not an overvoltage has been applied to the electrostatic transducer 5 for a predetermined time (step S103). When it is determined that the overvoltage has been applied to the electrostatic transducer 5 for a predetermined time (Yes in step S103), the process proceeds to step S104. When it is determined that the overvoltage has not been applied to the electrostatic transducer 5 for a predetermined time (No in step S103), the process returns to step S101.

The control circuit 7 switches the timer unit 44 to a long time and stops the voltage output circuit 6 (step S104). Then, the process proceeds to step 105.

The control circuit 7 determines whether or not a pulse signal is output from the one-shot pulse circuit 46 (step S105). When it is determined that the pulse signal is output from the one-shot pulse circuit 46 (Yes in step S105), the process proceeds to step S106. When it is determined that the pulse signal is not output from the one-shot pulse circuit 46 (No in step S105), the process returns to step S105.

The control circuit 7 determines whether or not it is determined that the overvoltage applied to the electrostatic transducer 5 has been released (step S106). When it is determined that the overvoltage applied to the electrostatic transducer 5 has been released (Yes in step S106), the process proceeds to step S107. When it is determined that the overvoltage applied to the electrostatic transducer 5 has not been released (No in step S106), the process returns to step S105.

The control circuit 7 switches the timer unit 44 to a normal timer to operate the voltage output circuit 6 (step S107). Then, the process returns to step S101.

As described above, the present embodiment is an electrostatic transducer even when a timer threshold voltage between the maximum output voltage specified in the specifications of the electrostatic transducer 5 and the threshold voltage regarded as an overvoltage is applied for a predetermined time. 5 can be protected. As a result, in this embodiment, it is possible to prevent a high DC voltage from being continuously applied to the electrostatic transducer 5 due to an abnormal operation of the driver 2.

Although the embodiments of the present invention have been described above, the embodiments are not limited by the contents of these embodiments. Further, the above-mentioned components include those that can be easily assumed by those skilled in the art, those that are substantially the same, that is, those having a so-called equal range. Furthermore, the components described above can be combined as appropriate. Further, various omissions, replacements or changes of components can be made without departing from the gist of the above-described embodiment.

1 Control system 2 Driver 3 Microcomputer 4 DC power supply 5 Electrostatic transducer 6 Voltage output circuit 7 Control circuit 8 Timer circuit unit 9 Voltage output circuit control unit 10 Capacitor 31 Output control signal output circuit 41, 51 Comparator 42 Timer threshold power supply 44 Timer section 45 Timer capacitor 46 One-shot pulse circuit 52 Threshold power supply 53 Error amplifier 58 Flip flop 59 Switching signal output section 60, 61 Buffer

Claims (7)

A control circuit that protects an electrostatic transducer that can generate vibration, sound, or pressure and detect vibration, sound, or pressure from overvoltage.
When the drive voltage for generating vibration, sound, or pressure in the electrostatic transducer becomes equal to or higher than a predetermined threshold voltage, the duration at which the drive voltage becomes equal to or higher than the threshold voltage is measured and continued. A timer circuit unit that outputs a pulse signal when the time reaches a predetermined first duration, and
When the pulse signal is received, a drive voltage stop signal for stopping the application of the drive voltage to the electrostatic transducer is output, and when the drive voltage stop signal is output, a predetermined first cycle is output. Each time, it is determined whether or not the drive voltage is equal to or higher than the threshold voltage, and if the drive voltage is less than the threshold voltage, the output of the drive voltage stop signal is stopped and the electrostatic transducer is driven. Voltage output circuit control unit that applies voltage and
A control circuit. The timer circuit unit
A comparator that compares the drive voltage with the threshold voltage,
A timer unit that starts counting when the output signal of the comparator reaches the first level and stops counting when the output signal reaches the second level.
It has a pulse signal output unit that outputs the pulse signal when the duration at which the output signal is the first level reaches the first duration.
The control circuit according to claim 1. The timer unit
When the drive voltage stop signal is output, the output signal of the comparator continues counting regardless of the first level or the second level, and outputs the pulse signal at a predetermined first cycle.
The voltage output circuit control unit
Each time the pulse signal is output, it is determined whether the output signal of the comparator is the first level or the second level, and if the output signal of the comparator is the first level, the output of the drive voltage stop signal is output. And, when the counting is continued and the output signal of the comparator is the second level, it has a function of stopping the driving voltage stop signal and stopping the counting.
The control circuit according to claim 2. The voltage output circuit control unit
It is set or reset when the output signal is at the first level and the pulse signal is output, and is reset or set when the output signal is at the second level and the pulse signal is output. Flip-flop and
It has a switching signal output unit for stopping the application of the drive voltage to the electrostatic transducer based on the drive voltage stop signal output from the flip-flop.
The timer unit stops counting when the flip-flop is reset or set.
The control circuit according to claim 2 or 3. The flip-flop provides a control signal for switching the first duration, which is the duration until the pulse signal is output, to the second duration, which is longer than the first duration, when set or reset. Output to the timer section
The control circuit according to claim 4. The control circuit according to any one of claims 1 to 5.
A voltage output circuit connected to the control circuit and applying a voltage to the electrostatic transducer,
A control device. Including more inverters,
The control device according to claim 6.

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