JP7027615B2 - Control circuits, controls and systems - Google Patents

Description

The present invention relates to control circuits, control devices and systems.

Patent Document 1 describes an electrostatic transducer capable of generating vibration, sound or pressure and detecting vibration, sound or pressure.

By the way, the electrostatic transducer may deteriorate. It is desired that the control circuit that controls the electrostatic transducer can also detect the deterioration of the electrostatic transducer.

Japanese Unexamined Patent Publication No. 2017-183814

It is an object of the present invention to provide a control circuit, a control device and a system capable of detecting deterioration of an electrostatic transducer.

The control circuit of one aspect of the present invention is
A control circuit that controls an electrostatic transducer that can generate vibration, sound or pressure and can detect vibration, sound or pressure.
When the first control signal is at the first level, the voltage output circuit is controlled so that a voltage corresponding to the second control signal is applied between both ends of the electrostatic transducer, and the first control signal is the second. In the case of level, the voltage output circuit control unit that stops the voltage output circuit,
A voltage clamp unit that outputs a clamp voltage that clamps the voltage between terminals of the electrostatic transducer to the first threshold voltage or less.
When the clamp voltage becomes equal to or lower than the second threshold voltage, the first control signal of the second level is output, and when the second control signal becomes higher than the third threshold voltage, the first control signal is output. A control signal output unit that outputs one level of the first control signal,
If the clamp voltage does not exceed the fourth threshold voltage higher than the second threshold voltage for a predetermined number of times continuously during the second level period, the electrostatic transducer deteriorates. A deterioration detection unit that outputs a detection signal indicating that it has been done,
To prepare
It is characterized by that.

In the control circuit
The second control signal is
When vibration, sound or pressure is generated in the electrostatic transducer, it is a signal of an arbitrary waveform to be generated, and when vibration, sound or pressure is detected in the electrostatic transducer, the amplitude is said. A triangular wave signal smaller than a signal of any waveform,
It is characterized by that.

In the control circuit
The control signal output unit is
A first comparator that compares the clamp voltage with the second threshold voltage,
A second comparator that compares the second control signal with the third threshold voltage,
A first flip-flop that is set by the output signal of the first comparator, reset by the output signal of the second comparator, and outputs the first control signal, and
including,
It is characterized by that.

In the control circuit
The control signal output unit is
Within a predetermined period after the change of the first control signal, a mask circuit for masking the output signal of the first comparator is further included.
It is characterized by that.

In the control circuit
The deterioration detection unit is
A third comparator that compares the clamp voltage with the fourth threshold voltage,
The first control signal is set by a first timing signal representing the timing at which the first level changes from the first level to the second level, and is ORed by the logical sum of the output signal of the third comparator and the inversion signal of the first control signal. The second flip-flop to be reset and
A first logical product gate that outputs a logical product of the non-inverting output signal of the second flip-flop and the second timing signal indicating the timing at which the first control signal changes from the second level to the first level. Circuit and
A second logical AND gate circuit that outputs the logical product of the inverted output signal of the second flip-flop and the second timing signal.
When the output signal of the first AND gate circuit is counted, cleared by the output signal of the second logical product gate circuit, and the output signal of the first AND gate circuit is counted a predetermined number of times, the deterioration detection signal is obtained. Output, counter, and
including,
It is characterized by that.

In the control circuit
The deterioration detection unit is
A one-shot circuit that outputs a one-shot first timing signal when the first control signal changes from the first level to the second level is further included.
It is characterized by that.

In the control circuit
The voltage clamp portion is
A drain is connected to the terminal on the high potential side of the electrostatic transducer, a bias voltage is supplied to the gate, and a transistor is included which outputs the clamp voltage from the source.
It is characterized by that.

In the control circuit
The transistor is
A bias voltage is supplied to the gate when the second control signal is equal to or lower than the third threshold voltage, and no bias voltage is supplied to the gate when the second control signal is higher than the third threshold voltage.
It is characterized by that.

In the control circuit
The transistor is
A bias voltage is supplied to the gate when the second control signal is equal to or lower than the fifth threshold voltage higher than the third threshold voltage, and a bias voltage is supplied to the gate when the second control signal is higher than the fifth threshold voltage. Is not supplied,
It is characterized by that.

In the control circuit
When the clamp voltage is equal to or lower than the sixth threshold voltage lower than the first threshold voltage and the first control signal is at the second level, the clamp voltage is output and the clamp voltage is the sixth threshold. Further including a voltage output unit that outputs the sixth threshold voltage when the voltage is higher than the voltage or the first control signal is at the first level.
It is characterized by that.

In the control circuit
The voltage output unit is
Even if the first control signal is at the first level, the clamp voltage is equal to or less than the seventh threshold voltage higher than the second threshold voltage, and the second control signal is equal to or less than the third threshold voltage. When, the clamp voltage is output.
It is characterized by that.

In the control circuit
The electrostatic transducer is an electrostatic actuator or an electrostatic pressure detection element.
It is characterized by that.

In the control circuit
It is a semiconductor integrated circuit,
It is characterized by that.

The control device of one aspect of the present invention is
With the control circuit
With the voltage output circuit
including,
It is characterized by that.

The system of one aspect of the present invention is
With the control device
A signal output unit that outputs the second control signal to the control circuit, and
A voltage change detection unit that detects vibration, sound, or pressure applied to the electrostatic transducer based on the change in the clamp voltage.
The detection signal receiving unit that receives the detection signal and
including,
It is characterized by that.

The control circuit, control device and system of one aspect of the present invention have the effect of being able to detect deterioration of the electrostatic transducer.

FIG. 1 is a diagram showing a configuration of a system using the control device of the first comparative example. FIG. 2 is a diagram illustrating the detection principle of the first comparative example. FIG. 3 is a diagram illustrating the detection principle of the first comparative example. FIG. 4 is a diagram showing a configuration of a system using the control device of the second comparative example. FIG. 5 is a diagram showing signal waveforms of each part of the system of the second comparative example. FIG. 6 is a diagram showing signal waveforms of each part of the system of the second comparative example. FIG. 7 is a diagram showing signal waveforms of each part of the system of the second comparative example. FIG. 8 is a diagram showing signal waveforms of each part of the system of the second comparative example. FIG. 9 is a diagram showing a configuration of a system using the control device of the first embodiment. FIG. 10 is a diagram showing signal waveforms of each part of the system of the first embodiment. FIG. 11 is a diagram showing a configuration of a system using the control device of the second embodiment. FIG. 12 is a diagram showing a configuration of a system using the control device of the third embodiment. FIG. 13 is a diagram showing a configuration of a system using the control device of the fourth embodiment. FIG. 14 is a diagram showing a configuration of a system using the control device according to the fifth embodiment.

Hereinafter, embodiments of the control circuit, control device, and system of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment.

<First Embodiment>
Hereinafter, the first embodiment will be described, but in order to facilitate understanding of the first embodiment, a comparative example will be described first.

(First comparative example)
FIG. 1 is a diagram showing a configuration of a system using the control device of the first comparative example. The system 100 includes a control device 102, a microcomputer 103, a DC power supply 4, an electrostatic transducer 5, and a capacitor 6.

The electrostatic transducer 5 is exemplified by the electrostatic transducer described in Patent Document 1, but the present disclosure is not limited thereto. The electrostatic transducer 5 may be referred to as an electrostatic actuator or an electrostatic pressure detection element.

The electrostatic transducer 5 is represented by an equivalent circuit of a resistor 21 and a capacitor 22 connected in series and a resistor 23 connected in parallel to the capacitor 22.

The resistance value of the resistor 21 is exemplified by about 120Ω (ohm) to 360Ω, but the present disclosure is not limited to this. The capacitance of the capacitor 22 is exemplified by about 100 nF (nanofarado) to 300 nF, but the present disclosure is not limited to this. The resistance value of the resistor 23 is exemplified to be about 12 MΩ (megaohm), but the present disclosure is not limited to this.

When a high voltage (for example, 410 V) is applied, the electrostatic transducer 5 can generate vibration, sound, or pressure by changing the distance between both electrodes of the capacitor 22.

Further, the electrostatic transducer 5 can detect vibration, sound or pressure by changing the distance between both electrodes of the capacitor 22 when vibration, sound or pressure is applied.

The capacitor 6 is electrically connected in parallel to the electrostatic transducer 5. The capacitor 6 smoothes the voltage applied to the electrostatic transducer 5.

2 and 3 are diagrams for explaining the detection principle of the first comparative example.

The switch 203 is turned on and off according to the pulse signal generated by the pulse generation circuit 202.

The switch 203 is turned on when the pulse signal is at a high level. When the switch 203 is turned on, the voltage of the DC power supply 201 is applied to the electrostatic transducer 5, and the electric charge is charged to the capacitor 22. The voltage of the DC power supply 201 is exemplified by 5V, which is a predetermined voltage, but the present disclosure is not limited to this.

The switch 203 is turned off when the pulse signal is at low level. When the switch 203 is turned off, the electric charge charged in the capacitor 22 is discharged via the resistor 205. The voltage detection circuit 204 detects the voltage of the electrostatic transducer 5.

The resistance value of the resistor 205 is exemplified by about 2 MΩ, but the present disclosure is not limited to this.

Referring to FIG. 3, when the switch 203 is turned on between the timing t ₁₀₀ and the timing t ₁₀₁ , the voltage of the electrostatic transducer 5 becomes the same as the voltage of the DC power supply 201.

When the switch 203 is turned off between the timing t ₁₀₁ and the timing t ₁₀₂ , the electric charge charged in the capacitor 22 is discharged. Therefore, the voltage of the electrostatic transducer 5 drops according to the time constants of the resistor 21, the capacitor 22, the resistor 23, and the resistor 205.

The switch 203 is turned on between the timing t ₁₀₃ and the timing t ₁₀₄ . At this time, when vibration, sound, or pressure is applied to the electrostatic transducer 5, the distance between both electrodes of the capacitor 22 becomes short, and the capacitance of the capacitor 22 becomes large. That is, the time constants of the resistor 21, the capacitor 22, the resistor 23, and the resistor 205 become large.

When the switch 203 is turned off between the timing t ₁₀₄ and the timing t ₁₀₅ , the electric charge charged in the capacitor 22 is discharged. At this time, the time constants of the resistor 21, the capacitor 22, the resistor 23, and the resistor 205 are increased. Therefore, the voltage of the electrostatic transducer 5 gradually decreases as compared with the period from the timing t ₁₀₁ to the timing t ₁₀₂ . Thereby, the electrostatic transducer 5 can detect vibration, sound or pressure.

Referring to FIG. 1 again, the control device 102 includes a voltage output circuit 7 and a control circuit 108.

The voltage output circuit 7 is a flyback type converter, but the present disclosure is not limited to this. The voltage output circuit 7 may be a forward type converter or an inverter.

The control circuit 108 controls the voltage output circuit 7 under the control of the microcomputer 103. Under the control of the control circuit 108, the voltage output circuit 7 converts the power of the DC power supply 4 and applies the converted power to the electrostatic transducer 5.

The voltage of the DC power supply 4 is exemplified by 12V, but the present disclosure is not limited to this. The voltage applied to the electrostatic transducer 5 by the voltage output circuit 7 is a voltage that varies between 0V and 410V, but the present disclosure is not limited to this. The waveform of the voltage applied to the electrostatic transducer 5 by the voltage output circuit 7 is an arbitrary waveform desired to be generated from the electrostatic transducer 5. The arbitrary waveform is exemplified by a sine wave or a synthetic wave obtained by superimposing a plurality of sine waves, but the present disclosure is not limited to this.

The control circuit 108 operates the voltage output circuit 7 when the electrostatic transducer 5 generates vibration, sound, or pressure.

The control circuit 108 stops the voltage output circuit 7 when the electrostatic transducer 5 detects vibration, sound, or pressure.

The control circuit 108 is a driver IC (Integrated Circuit), but the present disclosure is not limited to this.

The voltage output circuit 7 includes a transformer 11, diodes 12 and 14, N-channel transistors 13 and 15, resistors 16 and 17, and a voltage divider circuit 18.

The voltage dividing circuit 18 outputs the voltage dividing voltage S ₆ obtained by dividing the voltage S ₇ of the electrostatic transducer 5 to the control circuit 108. The voltage dividing circuit 18 is exemplified to divide the voltage of the electrostatic transducer 5 to 1/410, but the present disclosure is not limited to this.

In the comparative example, since the voltage output circuit 7 is a flyback type converter, the primary winding 11a and the secondary winding 11b of the transformer 11 are wound in opposite polarities.

The voltage output circuit 7 is a regenerative type, and the primary side circuit and the secondary side circuit are symmetrical. Although the voltage output circuit 7 is a regenerative type, the present disclosure is not limited to this.

By making the voltage output circuit 7 a regenerative type, the power on the electrostatic transducer 5 side can be regenerated to the DC power supply 4 side, so that the power loss can be suppressed.

One end of the primary winding 11a of the transformer 11 is electrically connected to the terminal on the high potential side of the DC power supply 4. The anode of the diode 12 is electrically connected to the terminal on the low potential side of the DC power supply 4. The terminal on the low potential side of the DC power supply 4 is electrically connected to the reference potential. The reference potential is exemplified by the ground potential, but the present disclosure is not limited to this.

The cathode of the diode 12 is electrically connected to the other end of the primary winding 11a of the transformer 11. The drain-source path of the transistor 13 is electrically connected in parallel to the diode 12. A first switching signal _S4 is input from the control circuit 108 to the gate of the transistor 13 via the resistor 16.

One end of the secondary winding 11b of the transformer 11 is electrically connected to one end of the electrostatic transducer 5. The anode of the diode 14 is electrically connected to the other end of the electrostatic transducer 5. The other end of the electrostatic transducer 5 is electrically connected to the reference potential.

The cathode of the diode 14 is electrically connected to the other end of the secondary winding 11b of the transformer 11. The drain-source path of the transistor 15 is electrically connected in parallel to the diode 14. A second switching signal _S5 is input from the control circuit 108 to the gate of the transistor 15 via the resistor 17.

When the voltage S 7 of the electrostatic transistor 5 is increased (for example, when the voltage S ₇ is increased in a sinusoidal manner from 0 V to 410 V), the control circuit 108 sends a first switching signal S ₄ of PWM (Pulse Width Modulation). It is output to the gate of the transistor 13 and the transistor 13 is switched.

While the transistor 13 is in the ON state, energy is stored in the primary winding 11a side of the transformer 11. Energy is released from the secondary winding 11b of the transformer 11 while the transistor 13 is in the off state. The energy emitted from the secondary winding 11b is rectified by the diode 14 and input to the electrostatic transducer 5.

The control circuit 108 sends the second PWM switching signal S ₅ to the gate of the transistor 15 when the voltage S 7 of the electrostatic transducer 5 is lowered (for example, when the voltage S ₇ is lowered from 410 V to 0 V in a sinusoidal manner). It outputs and switches the transistor 15.

While the transistor 15 is on, energy is stored on the secondary winding 11b side of the transformer 11. Energy is emitted from the primary winding 11a of the transformer 11 while the transistor 15 is in the off state. The energy released from the primary winding 11a is rectified by the diode 12 and input to the DC power supply 4.

The control circuit 108 includes a voltage output circuit control unit 30, a pulse signal output unit 140, and a voltage clamp unit 50.

The voltage output circuit control unit 30 includes a switching signal output unit 31, an error amplifier 32, and buffers 33 and 34.

The output voltage control signal S ₁₀₂ is input to the non-inverting input terminal of the error amplifier 32 from the output voltage control signal output circuit 122 in the microcomputer 103. The output voltage control signal S ₁₀₂ is a voltage that changes between 0V and 1V, but the present disclosure is not limited to this. The waveform of the output voltage control signal S ₁₀₂ is an arbitrary waveform desired to be generated from the electrostatic transducer 5. The arbitrary waveform is exemplified by a sine wave or a synthetic wave obtained by superimposing a plurality of sine waves, but the present disclosure is not limited to this. The voltage S ₇ applied to the electrostatic transducer 5 by the voltage output circuit 7 is a voltage obtained by multiplying the output voltage control signal S ₁₀₂ by a predetermined gain.

A voltage dividing voltage S ₆ is input from the voltage dividing circuit 18 to the inverting input terminal of the error amplifier 32.

The error amplifier 32 outputs a signal corresponding to the difference between the output voltage control signal S ₁₀₂ and the voltage dividing voltage S ₆ to the switching signal output unit 31. For example, the error amplifier 32 amplifies the difference between the output voltage control signal S ₁₀₂ and the voltage dividing voltage S ₆ and outputs the difference to the switching signal output unit 31.

The detection control signal S ₁₀₁ is input to the switching signal output unit 31 from the detection control signal output circuit 121 in the microcomputer 103.

The detection control signal output circuit 121 outputs the low level (first level) detection control signal S ₁₀₁ to the switching signal output unit 31 when the electrostatic transducer 5 outputs vibration, sound, or pressure.

The detection control signal output circuit 121 outputs a high level (second level) detection control signal S ₁₀₁ to the switching signal output unit 31 when the electrostatic transducer 5 detects vibration, sound, or pressure.

When the detection control signal S ₁₀₁ is at a low level, the switching signal output unit 31 outputs the first switching signal S ₄ or the second switching signal S ₅ to the voltage output circuit 7 based on the output signal of the error amplifier 32. Then, the voltage output circuit 7 is operated.

The switching signal output unit 31 outputs the first PWM switching signal S ₄ to the gate of the transistor 13 via the buffer 33 and the resistor 16. The switching signal output unit 31 outputs the second PWM switching signal S ₅ to the gate of the transistor 15 via the buffer 34 and the resistor 17.

When the detection control signal S ₁₀₁ is at a high level, the switching signal output unit 31 does not output the first switching signal S ₄ and the second switching signal S ₅ to the voltage output circuit 7, and stops the voltage output circuit 7. ..

The pulse signal output unit 140 includes a buffer 141. The pulse signal S ₁₀₃ is input to the buffer 141 from the pulse signal generation circuit 123 in the microcomputer 103. The pulse signal S ₁₀₃ has a low level of 0V and a high level of 5V, but the present disclosure is not limited to this. The buffer 141 outputs the pulse signal S ₁₀₃ to one end of the electrostatic transducer 5 via the diode 9.

The diode 9 is a high withstand voltage type (for example, withstand voltage of 410 V or more). When the voltage of the electrostatic transducer 5 is higher than the output voltage of the buffer 141, the diode 9 is turned off. As a result, it is possible to suppress the application of a high voltage to the buffer 141, and the buffer 141 is protected.

The diode 9 may be provided in the control circuit 108 (driver IC).

The voltage clamp portion 50 includes a DC power supply 51 and an N-channel type transistor 52. The terminal on the low potential side of the DC power supply 51 is electrically connected to the reference potential. The terminal on the high potential side of the DC power supply 51 is electrically connected to the gate of the transistor 52. The output voltage of the DC power supply 51 is exemplified by 8V, but the present disclosure is not limited to this.

The transistor 52 is a high withstand voltage type (for example, withstand voltage of 410 V or more). The voltage threshold VTH between the gate and the source of the transistor 52 is exemplified by 3V. A bias voltage of 8 V is applied to the gate of the transistor 52. Therefore, the source voltage of the transistor 52 is exemplified by a maximum of 5V (= 8V-3V).

The maximum value of the source voltage of the transistor 52 (for example, 5V) corresponds to the "first threshold voltage" of the present disclosure.

The source voltage of the transistor 52 becomes equal to the drain voltage when the drain voltage is 5 V or less. The source voltage of the transistor 52 becomes 5V when the drain voltage is higher than 5V. That is, the transistor 52 outputs the clamp voltage _S8 in which the voltage S7 at one end of the electrostatic transducer 5 is clamped to ₅ V or less to the voltage change detection unit 124 in the microcomputer 103.

The voltage change detection unit 124 can detect vibration, sound, or pressure applied to the electrostatic transducer 5 based on the change in the clamp voltage _S8 based on the detection principle described with reference to FIGS. 2 and 3. .. For example, the voltage change detection unit 124 is applied to the time constant of the electrostatic transducer 5, that is, the electrostatic transducer 5 by measuring the time when the clamp voltage S ₈ drops from 5 V to a predetermined voltage. Vibration, sound or pressure can be detected.

With the above configuration, the control device 102 can control one electrostatic transducer 5 to generate vibration, sound or pressure, and detect vibration, sound or pressure.

(Second comparative example)
FIG. 4 is a diagram showing a configuration of a system using the control device of the second comparative example. The same components as those in the first comparative example are designated by the same reference numerals, and the description thereof will be omitted.

The system 300 includes a control device 302 and a microcomputer 303. The control device 302 includes a control circuit 308. The control circuit 308 does not include the pulse signal output unit 140 as compared with the control circuit 108 (see FIG. 1). Further, the control circuit 308 further includes a control signal output unit 60 as compared with the control circuit 108.

The microcomputer 303 does not include the detection control signal output circuit 121, the output voltage control signal output circuit 122, and the pulse signal generation circuit 123 as compared with the microcomputer 103 (see FIG. 1). Further, the microcomputer 303 further includes an output voltage control signal output circuit 125 as compared with the microcomputer 103.

The control signal output unit 60 includes an RS type flip-flop 61, a comparator 62, a DC power supply 63, a mask circuit 64, a NAND gate circuit 65, a comparator 66, and a DC power supply 67.

The flip-flop 61 corresponds to the "first flip-flop" of the present disclosure. The comparator 66 corresponds to the "first comparator" of the present disclosure. The comparator 62 corresponds to the "second comparator" of the present disclosure.

The flip _- flop 61 is set when the output signal of the NAND gate circuit 65 is low level, and outputs the high level detection control signal S1.

The flip _- flop 61 is reset when the output signal of the comparator 62 is low level, and outputs the low level detection control signal S1.

The detection control signal S ₁ corresponds to the "first control signal" of the present disclosure.

The NAND gate circuit 65 outputs a low-level signal to the inversion set terminal of the flip-flop 61 when the output signal of the comparator 66 is high level and the output signal of the mask circuit 64 is high level. The NAND gate circuit 65 outputs a high-level signal to the inversion set terminal of the flip-flop 61 in other cases.

The clamp voltage _S8 is input to the inverting input terminal of the comparator 66. As described above, the clamp voltage _S8 varies in the range of 0V to 5V.

The voltage of the DC power supply 67 is input to the non-inverting input terminal of the comparator 66. The DC power supply 67 outputs the second threshold voltage Vth ₂ . The second threshold voltage Vth ₂ is exemplified by 1V, but the present disclosure is not limited thereto.

When the clamp voltage S ₈ is equal to or lower than the second threshold voltage Vth ₂ (for example, 1 V), the comparator 66 outputs a high-level signal to one input terminal of the NAND gate circuit 65. When the clamp voltage S ₈ is higher than the second threshold voltage Vth ₂ , the comparator 66 outputs a low-level signal to one input terminal of the NAND gate circuit 65.

The mask circuit 64 outputs the inverting output signal of the flip _- flop 61 (the logic inverting signal of the detection control signal S1) to the other input terminal of the NAND gate circuit 65. However, in the mask circuit 64, even if the comparator 66 outputs a high level within a predetermined period after the inverted output signal of the flip-flop 61 changes from a high level to a low level, the mask circuit 64 of the NAND gate circuit 65. Keep the output at a high level. That is, the mask circuit 64 masks the output signal of the comparator 66. Therefore, the mask circuit 64 can suppress chattering. The mask circuit 64 is exemplified by a one-shot circuit, but the present disclosure is not limited to this.

The output voltage control signal S ₂ is input to the inverting input terminal of the comparator 62 from the output voltage control signal output circuit 125 in the microcomputer 3.

The output voltage control signal S ₂ is a signal that changes in the range of 0V to 1V when vibration, sound, or pressure is generated in the electrostatic transducer 5, but the present disclosure is not limited to this. The waveform of the output voltage control signal S ₂ is an arbitrary waveform desired to be generated from the electrostatic transducer 5. The arbitrary waveform is exemplified by a sine wave or a synthetic wave obtained by superimposing a plurality of sine waves, but the present disclosure is not limited to this.

Further, the output voltage control signal S ₂ is a signal that changes in a triangular wave shape in the range of 0 V to 100 mV when the electrostatic transducer 5 detects vibration, sound, or pressure, but the present disclosure is limited to this. Not done.

The output voltage control signal S ₂ corresponds to the “second control signal” of the present disclosure.

The voltage of the DC power supply 63 is input to the non-inverting input terminal of the comparator 62. The DC power supply 63 outputs the third threshold voltage Vth ₃ . The third threshold voltage Vth ₃ is exemplified by 30 mV, but the present disclosure is not limited to this.

When the output voltage control signal S ₂ is equal to or less than the third threshold voltage Vth ₃ (for example, 30 mV), the comparator 62 outputs a high level signal to the inverting reset terminal of the flip-flop 61. When the output voltage control signal S ₂ is higher than the third threshold voltage Vth ₃ , the comparator 62 outputs a low-level signal to the inverting reset terminal of the flip-flop 61.

Summarizing the above, when the output voltage control signal S ₂ becomes higher than the third threshold voltage Vth ₃ , the flip-flop 61 is reset, so that the control signal output unit 60 outputs the low-level detection control signal S ₁ . .. As a result, the voltage output circuit control unit 30 controls the voltage output circuit 7 so that the voltage corresponding to the _output voltage control signal S2 is applied to the electrostatic transducer 5.

While the output voltage control signal S ₂ is higher than the third threshold voltage Vth ₃ , the control signal output unit 60 continues to output the low-level detection control signal S ₁ . As a result, the voltage output circuit control unit 30 continues to control the voltage output circuit 7 so as to apply the voltage corresponding to the output voltage control signal S ₂ to the electrostatic transducer 5.

After that, when the output voltage control signal S ₂ becomes the third threshold voltage Vth ₃ or less and the clamp voltage S ₈ becomes the second threshold voltage Vth ₂ or less, the flip-flop 61 is set. Therefore, the control signal output unit 60 outputs the high _- level detection control signal S1. As a result, the voltage output circuit control unit 30 stops the voltage output circuit 7.

5 to 8 are diagrams showing signal waveforms of each part of the system of the second comparative example.

FIG. 5 is a diagram showing a waveform 401 of the voltage S7 of the electrostatic transducer ₅ . The period during which the electrostatic transducer 5 detects vibration, sound or pressure is referred to as a "detection period" in the present disclosure. The period from timing t ₂₀₀ to timing t ₂₀₁ is the detection period 411, and the period from timing t ₂₀₂ to timing t ₂₀₃ is the detection period 413.

The period during which the electrostatic transducer 5 generates vibration, sound, or pressure is referred to as a "generation period" in the present disclosure. The occurrence period 412 is from the timing t ₂₀₁ to the timing t ₂₀₂ , and the occurrence period 414 is from the timing t ₂₀₃ to the timing t ₂₀₄ .

During the generation periods 412 and 414, the output voltage control signal S ₂ changes in a sinusoidal manner. Accordingly, during the generation periods 412 and 414, the voltage output circuit 7 applies a sinusoidal voltage S ₇ to the electrostatic transducer 5. For example, in the generation periods 412 and 414, the voltage output circuit 7 applies a sinusoidal voltage S ₇ that changes in the range of about 0 V to 410 V to the electrostatic transducer 5.

Further, during the detection periods 411 and 413, the output voltage control signal S ₂ changes in a triangular wave shape. Accordingly, during the detection periods 411 and 413, the voltage output circuit 7 applies a triangular wave-shaped voltage S ₇ having an amplitude smaller than that of a sine wave to the electrostatic transducer 5. For example, in the detection periods 411 and 413, the voltage output circuit 7 applies a triangular wave-shaped voltage S ₇ that changes in the range of about 1 V to 10 V to the electrostatic transducer 5.

As shown in FIG. 5, the detection period 413 can also be provided in the valley portion (low voltage portion) between the generation period 412 and the generation period 414.

FIG. ₆ is a diagram showing a waveform 401 of the voltage S7 of the electrostatic transducer 5. Specifically, FIG. 6 is an enlarged view of the waveform 401 of the voltage S7 of the electrostatic transducer ₅ in the detection period.

The period in which the voltage output circuit ₇ applies the voltage S7 to the electrostatic transducer 5 within the detection period is referred to as a “detection voltage application period” in the present disclosure. The detection voltage application period 421 is from the timing t ₂₁₀ to the timing t ₂₁₁ .

Within the detection period, the period during which the voltage output circuit ₇ does not apply the voltage S7 to the electrostatic transducer 5 and the voltage change detection unit 124 senses the clamp voltage _S8 is referred to as a “detection sensing period” in the present disclosure. Refer to. The detection sensing period 422 is from the timing t ₂₁₁ to the timing t ₂₁₂ .

In the detection voltage application period 421, the voltage output circuit 7 statically generates a triangular wave-shaped voltage S ₇ that rises with a constant first gradient and then falls with a constant second gradient in response to the output voltage control signal S ₂ . It is applied to the electric transducer 5. The first gradient and the second gradient may be the same or different.

The peak value of the triangular wave-shaped voltage S ₇ applied by the voltage output circuit 7 to the electrostatic transducer 5 is exemplified by, for example, about 10 V, but the present disclosure is not limited thereto. The frequency of the triangular wave-shaped voltage of the output voltage control signal S ₂ , that is, the frequency of the triangular wave-shaped voltage S ₇ applied to the electrostatic transducer 5 by the voltage output circuit 7 is exemplified as about 1 kHz (kilohertz). The present disclosure is not limited to this.

The waveform of the output voltage control signal S ₂ may be saw-like, which is a kind of triangular wave that rises momentarily and then falls with a constant gradient. That is, the voltage output circuit 7 may apply a sawtooth wave voltage S ₇ to the electrostatic transducer 5. However, when the voltage output circuit 7 applies a sawtooth wave voltage S ₇ to the electrostatic transducer 5, a large fluctuation (overshoot) occurs in the voltage S ₇ of the electrostatic transducer 5 near the peak of the sawtooth wave. It may take some time for the fluctuations to converge. Therefore, from the viewpoint of suppressing the time for the fluctuation to converge, the waveform of the output voltage control signal S ₂ is preferably triangular. That is, it is preferable that the voltage output circuit 7 applies a triangular wave-shaped voltage S ₇ to the electrostatic transducer 5.

Further, the waveform of the output voltage control signal S ₂ may be sinusoidal. That is, the voltage output circuit 7 may apply a sinusoidal voltage S ₇ to the electrostatic transducer 5. However, when the voltage output circuit 7 applies a sinusoidal voltage S ₇ to the electrostatic transducer 5, the calculation of the capacitance of the capacitor 22 (described later) becomes complicated. Therefore, from the viewpoint of simplifying the calculation of the capacitance of the capacitor 22, it is preferable that the waveform of the output voltage control signal S ₂ has a triangular wave shape that descends with a constant gradient. That is, it is preferable that the voltage output circuit 7 applies a triangular wave-shaped voltage S ₇ to the electrostatic transducer 5.

FIG. ₇ is a diagram showing a waveform 401 of the voltage S7 of the electrostatic transducer 5. Specifically, FIG. ₇ is an enlarged view of the waveform 401 of the voltage S7 of the electrostatic transducer 5 in the vicinity of the detection sensing period 422.

When vibration, sound, or pressure is applied to the electrostatic transducer 5, the distance between both electrodes of the capacitor 22 changes, so that the capacitance of the capacitor 22 changes. Therefore, when the voltage output circuit 7 ends applying the voltage S ₇ to the electrostatic transducer 5 at the timing t ₂₁₁ , the voltage S ₇ of the electrostatic transducer 5 is static electricity of the capacitor 22 in the detection sensing period 422. The voltage will be adjusted according to the electric capacity. In the detection sensing period 422, the voltage S7 of the electrostatic transducer ₅ has a slight transient state and rises.

In the detection sensing period 422, the smaller the capacitance of the capacitor 22, the lower the voltage S7 of the electrostatic transducer ₅ , and the larger the capacitance of the capacitor 22, the higher the voltage S7 of the electrostatic transducer ₅ . Become. That is, when the waveform of the voltage S7 of the electrostatic transducer ₅ is the waveform 401a, the capacitance of the capacitor 22 is smaller than that of the waveforms 401b and 401c. Further, when the waveform of the voltage S7 of the electrostatic transducer ₅ is the waveform 401c, the capacitance of the capacitor 22 is larger than that of the waveforms 401a and 401b. Further, when the waveform of the voltage S7 of the electrostatic transducer ₅ has the waveform 401b, the capacitance of the capacitor 22 is between the case of the waveform 401a and the case of the waveform 401c.

FIG. 8 is a diagram showing waveforms of signals of each part of the control circuit 8. Specifically, FIG. 8 is an enlarged view of the waveform of the signal of each part of the control circuit 8 in the vicinity of the detection sensing period 422.

Referring to FIG. 8A, the waveform 501 is the waveform of the _output voltage control signal S2. The output voltage control signal S ₂ descends at a constant second gradient, becomes zero within the detection sensing period 422, and then rises at a constant first gradient.

Referring to FIG. ₈ (f), the waveform 506 is the waveform of the detection control signal S1. Since the flip-flop 61 is reset during the detection voltage application periods 421 and 423, the detection control signal S1 is at _a low level. Further, since the flip-flop 61 is set in the detection sensing period 422, the detection control signal S1 is at _a high level. Therefore, the switching signal output unit 31 operates the voltage output circuit 7 in the detection voltage application periods 421 and 423, and stops the voltage output circuit 7 in the detection sensing period 422.

Referring to FIG. 8 (c), the waveform ₅₀₃ is the waveform of the second switching signal S5. Since the detection control signal S1 is at _a low level in the detection voltage application period 421, the switching signal output unit 31 outputs the second PWM switching signal S5 to the gate of the transistor ₁₅ to operate the transistor 15 for switching. As a result, the voltage output circuit 7 lowers the voltage S ₇ of the electrostatic transducer 5 as shown by the waveform 401.

Referring to FIG. 8B, the waveform 502 is a waveform of the voltage of the capacitor 22. The voltage of the capacitor 22 represented by the waveform 502 is higher than the applied voltage (voltage S ₇ ) of the voltage output circuit 7 represented by the waveform 401. Due to the voltage difference between the voltage of the capacitor 22 and the applied voltage of the voltage output circuit 7, a current flows from the capacitor 22 to the voltage output circuit 7 via the resistor 21. That is, the electric charge of the capacitor 22 is drawn to the voltage output circuit 7 via the resistor 21. The current flowing from the capacitor 22 to the voltage output circuit 7 via the resistor 21 is referred to as a “pull-out current” in the present disclosure.

Referring to FIG. 8 (e), the waveform 505 is a waveform of the current flowing through the resistor 21. The direction of flow from the voltage output circuit 7 to the capacitor 22 is positive, and the direction of flow from the capacitor 22 to the voltage output circuit 7 is negative.

The voltage difference between the voltage of the capacitor 22 and the applied voltage of the voltage output circuit 7 (voltage S ₇ ) is equal to the voltage drop in the resistor 21.

The following equation (1) holds between the capacitance C of the capacitor 22, the withdrawal current I, and the applied voltage (voltage S ₇ ) V of the voltage output circuit 7.
I = C × dV / dt ・ ・ ・ (1)

In the second comparative example, since the rate of change dV / dt of the applied voltage (voltage S ₇ ) of the voltage output circuit 7 is constant, the withdrawal current I is constant.

When the waveform of the output voltage control signal S ₂ is sinusoidal, that is, when the voltage output circuit 7 applies the sinusoidal voltage S ₇ to the electrostatic transducer 5, the rate of change of the voltage S ₇ is dV / dt. Is not constant, so the withdrawal current I is also not constant.

At the timing t ₂₁₁ , as shown by the waveform 401, the flip-flop 61 is set when the applied voltage (voltage S ₇ ) of the voltage output circuit 7 becomes the second threshold voltage Vth ₂ or less. Therefore, as shown by the waveform 506, the detection control signal S ₁ becomes a high level. As a result, the switching signal output unit 31 stops the voltage output circuit 7. That is, the voltage output circuit 7 stops the voltage output.

When the voltage output circuit 7 stops the voltage output, no current flows through the resistor 21. This eliminates the voltage drop at the resistor 21. Therefore, in the detection sensing period 422, the voltage S7 of the electrostatic transducer ₅ represented by the waveform 401 is substantially equal to the voltage of the capacitor 22.

The voltage change detection unit 124 senses the voltage S ₇ (clamp voltage S ₈ ) of the electrostatic transducer 5 within the detection sensing period 422 (for example, timing t ₂₁₂ ). The voltage difference between the voltage S ₇ (clamp voltage S ₈ ) of the electrostatic transducer 5 and the second threshold voltage Vth ₂ corresponds to the voltage drop in the resistor 21. The voltage change detection unit 124 can calculate the withdrawal current I by dividing the voltage drop in the resistance 21 by the resistance value of the resistance 21. As a result, in the equation (1), the withdrawal current I and the rate of change dV / dt of the voltage S ₇ become known. Therefore, the voltage change detection unit 124 can calculate the capacitance C of the capacitor 22. As a result, the voltage change detection unit 124 can detect the vibration, sound, or pressure applied to the electrostatic transducer 5.

At the timing t ₂₁₂ , as shown by the waveform 501, when the output voltage control signal S ₂ exceeds the third threshold voltage Vth ₃ , the flip-flop 61 is reset. Therefore, as shown by the waveform 506, the detection control signal S ₁ becomes low level. As a result, the switching signal output unit 31 operates the voltage output circuit 7. That is, the voltage output circuit 7 outputs a voltage.

On the other hand, in the detection sensing period 422, since the voltage output circuit 7 stops the voltage output, the voltage of the voltage output circuit 7 does not become the voltage corresponding to the _output voltage control signal S2. Therefore, the error amplifier 32 is out of the control range (dynamic range). Although not shown, the output of the error amplifier 32 is lowered to a low level during the detection sensing period 422 in order to prevent output overshoot when switching from the detection sensing period 422 to the detection voltage application period 423. As a result, as shown in the waveform 401, the voltage S7 of the electrostatic transducer ₅ temporarily drops. After that, the output voltage control signal S ₂ rises, and the voltage output circuit 7 applies a voltage corresponding to the output voltage control signal S ₂ to the electrostatic transducer 5. The waveform 504 is the waveform of the _first switching signal S4. As a result, the voltage S7 of the electrostatic transducer ₅ also rises.

Similar to the control circuit 108, the control circuit 308 can control one electrostatic transducer 5 to generate vibration, sound or pressure, and detect vibration, sound or pressure.

Further, in the control device 102, the capacitor 22 is spontaneously discharged as described in FIGS. 2 and 3. Therefore, it takes time to discharge the capacitor 22. If the resistance value of the resistor 205 (corresponding to the voltage dividing circuit 18 in FIG. 1) in FIG. 2 is reduced, the time required for the natural discharge of the capacitor 22 can be shortened. However, the resistance 205 is applied with a high voltage of 410 V at the peak. Therefore, if the resistance value of the resistor 205 is reduced, the current flowing through the resistor 205 increases. That is, the resistance 205 can be damaged. Therefore, there is a limit to reducing the resistance value of the resistor 205. That is, there is a limit to shortening the time required for the natural discharge of the capacitor 22.

On the other hand, in the control device 302, the voltage output circuit 7 applies a voltage S ₇ that decreases with a constant gradient to the electrostatic transducer 5, forcibly reducing the voltage of the capacitor 22. That is, the voltage output circuit 7 forcibly discharges the electric charge of the capacitor 22. Therefore, the control device 302 can shorten the time required for discharging the capacitor 22 as compared with the control device 102. As a result, the control device 302 can detect vibration, sound, or pressure in a shorter time than that of the control device 102.

Further, the system 300 can eliminate the need for the detection control signal output circuit 121 and the pulse signal generation circuit 123 as compared with the system 100. As a result, the system 300 can suppress the circuit of the microcomputer 303 and also suppress the wiring between the microcomputer 303 and the control circuit 308.

(First Embodiment)
FIG. 9 is a diagram showing a configuration of a system using the control device of the first embodiment. The same components as those of the first or second comparative example are designated by the same reference numerals, and the description thereof will be omitted.

The system 1 includes a control device 2. The control device 2 includes a control circuit 8. The control circuit 8 further includes a deterioration detection unit 70 as compared with the control circuit 308.

The present inventor has found that when the electrostatic transducer 5 deteriorates, the resistance value of the resistor 21 or 23 decreases. For example, when the resistance value of the resistor 21 becomes smaller, the voltage drop at the resistor 21 becomes smaller. Since the potential difference between the output voltage and the capacitor 22 during the detection voltage application period and the detection sensing period becomes small, the voltage rise due to the voltage drop at the resistance 21 during the detection sensing period becomes small. On the other hand, when the resistance value of the resistor 23 becomes small, the electric charge of the capacitor 22 is discharged via the resistor 23. Therefore, the voltage of the capacitor 22 after the deterioration of the electrostatic transducer 5 is lower than the voltage of the capacitor 22 before the deterioration of the electrostatic transducer 5. The deterioration detection unit 70 can detect the deterioration of the electrostatic transducer 5 by utilizing these phenomena.

The deterioration detection unit 70 includes a one-shot circuit 71, a DC power supply 72, a comparator 73, an OR gate circuit 74, an RS type flip-flop 75, a NOT gate circuit (inverter circuit) 76, an AND gate circuit 77, and an AND gate circuit 77. 78 and a counter 79 are included.

The comparator 73 corresponds to the "third comparator" of the present disclosure. The flip-flop 75 corresponds to the "second flip-flop" of the present disclosure. The AND gate circuit 77 corresponds to the "first AND gate circuit" of the present disclosure. The AND gate circuit 78 corresponds to the "second logic gate circuit" of the present disclosure.

The one-shot circuit 71 outputs a low-level one-shot pulse to the inversion set terminal of the flip-flop 75 when the detection control signal S ₁ changes from low level to high level (timing of the start of the detection sensing period). ..

The output signal of the one-shot circuit 71 corresponds to the "first timing signal" of the present disclosure.

Therefore, the flip-flop 75 is set at the start timing of the detection sensing period.

The DC power supply 72 outputs a fourth threshold voltage Vth ₄ , which is higher than the second threshold voltage Vth ₂ . The fourth threshold voltage Vth ₄ is exemplified by 1.5 V, but the present disclosure is not limited to this.

The clamp voltage _S8 is input to the inverting input terminal of the comparator 73. A fourth threshold voltage Vth ₄ (for example, 1.5V) is input to the non-inverting input terminal of the comparator 73. When the clamp voltage S ₈ is equal to or less than the fourth threshold voltage Vth ₄ , the comparator 73 outputs a high-level signal to one input terminal of the OR gate circuit 74. When the clamp voltage S ₈ is higher than the fourth threshold voltage Vth ₄ , the comparator 73 outputs a low-level signal to one input terminal of the OR gate circuit 74.

An inverting output signal of the flip _- flop 61 (logical inverting signal of the detection control signal S1) is input to the other input terminal of the OR gate circuit 74. The OR gate circuit 74 sends a low-level signal to the inverting reset terminal of the flip-flop 75 when the output signal of the comparator 73 is low _- level and the logic inverting signal of the detection control signal S1 is low-level. Output. The OR gate circuit 74 outputs a high level signal to the inverting reset terminal of the flip-flop 75 in other cases.

Therefore, the flip-flop 75 is reset when the clamp voltage S ₈ becomes higher than the fourth threshold voltage Vth ₄ within the detection sensing period. In other words, the flip-flop 75 maintains the set state if the clamp voltage S ₈ does not become higher than the fourth threshold voltage Vth ₄ within the detection sensing period.

The NOT gate circuit 76 logically inverts the output signal of the mask circuit 64 and outputs it. That is, the NOT gate circuit 76 outputs a high-level signal at the timing when the detection sensing period ends and the voltage output circuit 7 applies the voltage to the electrostatic transducer 5.

The output signal of the NOT gate circuit 76 corresponds to the "second timing signal" of the present disclosure.

The output signal of the NOT gate circuit 76 is input to one input terminal of the AND gate circuit 77. The non-inverting output signal of the flip-flop 75 is input to the other input terminal of the AND gate circuit 77.

Therefore, if the clamp voltage _S8 does not become higher than the fourth threshold voltage Vth ₄ within the immediately preceding detection sensing period, the AND gate circuit 77 sends a high-level signal to the counter 79 at the end timing of the detection sensing period. Output to the count terminal.

The output signal of the NOT gate circuit 76 is input to one input terminal of the AND gate circuit 78. The inverted output signal of the flip-flop 75 is input to the other input terminal of the AND gate circuit 78.

Therefore, when the clamp voltage S ₈ becomes higher than the fourth threshold voltage Vth ₄ within the immediately preceding detection sensing period, the AND gate circuit 78 resets the high level signal to the counter 79 at the end timing of the detection sensing period. Output to the (clear) terminal.

The counter 79 counts the number of times the output signal of the AND gate circuit 77 has reached a high level. Then, the counter 79 determines that the electrostatic transducer 5 has deteriorated when the number of times the output signal of the AND gate circuit 77 has reached the high level reaches four times, and the deterioration detection signal _S9 is used as a switching signal. It is output to the output unit 31 and the deterioration detection signal receiving unit 126.

The counter 79 resets (clears) the counted number of times when the output signal of the AND gate circuit 78 reaches a high level.

Therefore, the counter 79 determines that the electrostatic transducer 5 has deteriorated and detects the deterioration only when the detection sensing period in which the clamp voltage S ₈ does not become higher than the fourth threshold voltage Vth ₄ continues four times. The signal S ₉ is output. On the other hand, for example, in the counter 79, the detection sensing period in which the clamp voltage S ₈ did not become higher than the fourth threshold voltage Vth ₄ continued three times, but the clamp voltage S ₈ was the fourth threshold voltage in the fourth detection sensing period. When it becomes higher than Vth ₄ , the counted number "3" is reset (cleared).

In the first embodiment, the counter 79 counts the output signal of the AND gate circuit 77 four times, but the present disclosure is not limited to this. The counter 79 may count the output signal of the AND gate circuit 77 once, twice, three times, or five times or more.

However, if the counter 79 counts a small number (for example, once), there are the following merits and demerits. The merit is that when the electrostatic transducer 5 is actually deteriorated, the time during which the voltage is applied to the electrostatic transducer 5 from the voltage output circuit 7 can be shortened. The demerit is that if the clamp voltage _S8 does not become higher than the fourth threshold voltage Vth ₄ accidentally due to the influence of noise or the like, it is erroneously determined that the electrostatic transducer 5 is deteriorated. There is a possibility that it will end up.

On the other hand, if the counter 79 counts a large number (for example, 10 times), there are the following merits and demerits. The merit is that if the clamp voltage _S8 does not become higher than the fourth threshold voltage Vth ₄ accidentally due to the influence of noise or the like, it is erroneously determined that the electrostatic transducer 5 has deteriorated. It is possible to suppress the possibility of static electricity. The demerit is that when the electrostatic transducer 5 is actually deteriorated, it takes a long time for the voltage to be applied to the electrostatic transducer 5.

Therefore, it is preferable that the number of times the counter 79 counts is determined by comprehensively considering the above-mentioned advantages and disadvantages. As an example, it is exemplified that the number of times the counter 79 counts is about 3 to 5 times, more preferably 4 times.

The microcomputer 3 further includes a deterioration detection signal receiving unit 126 as compared with the microcomputer 303. When the deterioration detection signal receiving unit 126 receives the deterioration detection signal _S9 , the deterioration detection signal receiving unit 126 may generate a warning sound or turn on the warning light.

The deterioration detection signal S ₉ is also input to the switching signal output unit 31. When the switching signal output unit 31 receives the deterioration detection signal S ₉ , it is preferable to stop the voltage output circuit 7 regardless of the level of the detection control signal S ₁ .

FIG. 10 is a diagram showing signal waveforms of each part of the system of the first embodiment. In FIG. 10, the detection voltage application period 631 is up to the timing t ₁ , and the detection sensing period 632 is from the timing t ₁ to the timing t ₂ . The detection voltage application period 633 is from the timing t ₂ to the timing t ₅ , and the detection sensing period 634 is from the timing t ₅ to the timing t ₆ . The period from timing t ₆ to timing t ₉ is the detection voltage application period 635, and the period from timing t ₉ to timing t ₁₁ is the detection sensing period 636. From the timing _t11 , the detection voltage application period is 637.

Referring to FIG. 10A, the waveform 601 is the waveform of the voltage S7 of the electrostatic transducer ₅ . In the detection voltage application period 631, the voltage output circuit 7 applies a voltage S ₇ that decreases with a constant second gradient to the electrostatic transducer 5.

Referring to FIG. 10B, the waveform 602 is a waveform of the inverted output signal of the flip _- flop 61 (the logical inverted signal of the detection control signal S1). In the detection voltage application period 631, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is at a high level.

Referring to FIG. 10 (e), the waveform 605 is a waveform of the output voltage of the comparator 73. Since the voltage S ₇ (waveform 601) of the electrostatic transducer 5 is higher than the fourth threshold voltage Vth ₄ up to the timing t ₀ , the output signal (waveform 605) of the comparator 73 is low level. At timing t ₀ , when the voltage S ₇ (waveform 601) of the electrostatic transducer 5 becomes the fourth threshold voltage Vth ₄ or less, the output signal (waveform 605) of the comparator 73 changes from low level to high level.

Referring to FIG. 10 (f), the waveform 606 is an output signal of the OR gate circuit 74. Since the inverted output signal (waveform 602) of the flip-flop 61 is at a high level in the detection voltage application period 631, the output signal (waveform 606) of the OR gate circuit 74 is at a high level.

_At the timing t1, the detection voltage application period 631 ends and the detection sensing period 632 starts.

Referring again to FIG. 10A, during the detection sensing period 632, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. Therefore, the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes the voltage of the capacitor 22. When the electrostatic transducer 5 is not deteriorated, the voltage of the capacitor 22 becomes higher than the fourth threshold voltage Vth ₄ .

Referring again to FIG. 10B, during the detection sensing period 632, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is low level.

Referring to FIG. 10 (e) again, at the timing t1, the voltage S ₇ (waveform 601) of the electrostatic transducer ₅ becomes higher than the fourth threshold voltage Vth ₄ , so that the output signal (waveform 605) of the comparator 73 becomes higher. , Changes from high level to low level.

Referring to FIG. 10F again, at timing t1, the inverted output signal (waveform 602) of the flip _- flop 61 changes from high level to low level, and the output signal (waveform 605) of the comparator 73 changes from high level. It changes to a low level. Therefore, the output signal (waveform 606) of the OR gate circuit 74 changes from a high level to a low level.

Referring to FIG. 10D, the waveform 604 is the waveform of the output signal of the one-shot circuit 71. During the detection sensing period 632, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, at the timing t ₁ , the detection control signal S ₁ (logic inversion signal of the waveform 602) changes from a low level to a high level. Therefore, the output signal (waveform 604) of the one-shot circuit 71 becomes a low level for a certain period of time (for example, 100 ns (nanoseconds)).

Referring to FIG. 10 (g), the waveform 607 is the waveform of the non-inverting output signal of the flip-flop 75. At timing t1, a low-level signal (waveform 604) is input from the _one -shot circuit 71 to the inversion set terminal of the flip-flop 75. However, a low level signal (waveform 606) is input from the OR gate circuit 74 to the inverting reset terminal of the flip-flop 75. Therefore, the non-inverting output signal (waveform 607) of the flip-flop 75 maintains a low level.

In general RS type flip-flops, there is a type in which both the set signal and the reset signal are prohibited from being asserted at the same time. However, in the first embodiment, the flip-flop 75 is of a type in which reset is prioritized when both the set signal and the reset signal are asserted at the same time.

_At timing t2, the detection sensing period 632 ends and the detection voltage application period 633 starts.

Referring to FIG. 10A again, in the detection voltage application period 633, the voltage output circuit 7 increases the voltage S ₇ (waveform 601) having a constant first gradient and then decreasing with a constant second gradient. , Applied to the electrostatic transducer 5.

Referring to FIG. 10B again, in the detection voltage application period 633, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is at a high level.

Referring to FIG. 10 (c), the waveform 603 is the waveform of the output signal of the NOT gate circuit 76. In the detection voltage application period 633, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, at the timing t ₂ , the inverted output signal (waveform 602) of the flip-flop 61 changes from a low level to a high level, and the output signal of the mask circuit 64 is a fixed time (for example, from timing t ₂ to timing t ₃ ). 2 μs (microseconds) low level. Therefore, the output signal (waveform 603) of the NOT gate circuit 76 becomes a high level for a certain period of time (for example, 2 μs).

Referring to FIG. 10 (h), the waveform 608 is the waveform of the output signal of the AND gate circuit 77. _At the timing t2, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), but the non-inverting output signal (waveform 607) of the flip-flop 75 maintains a low level. Therefore, the output signal (waveform 608) of the AND gate circuit 77 maintains a low level.

Referring to FIG. 10 (i), the waveform 609 is the waveform of the output signal of the AND gate circuit 78. _At the timing t2, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), and the inverted output signal of the flip-flop 75 (logical inverted signal of waveform 607) becomes high level. .. Therefore, the output signal (waveform 609) of the AND gate circuit 78 becomes a high level for a certain period of time (for example, 2 μs).

Therefore, at the timing t2, the counter 79 does not count ₍ does not increment the count value) because the output signal (waveform 608) of the AND gate circuit 77 is at a low level. At the same time, the counter 79 resets (clears) the count value because the output signal (waveform 609) of the AND gate circuit 78 is at a high level. Therefore, the count value of the counter 79 becomes "0".

Referring to FIG. 10 (e) again, when the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes equal to or less than the _{fourth threshold voltage Vth 4 at} the timing t4, the output signal (waveform 605) of the comparator 73 becomes available. It changes from low level to high level.

_At the timing t5, the detection voltage application period 633 ends and the detection sensing period 634 starts.

Referring again to FIG. 10A, during the detection sensing period 634, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. Therefore, the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes the voltage of the capacitor 22. When the electrostatic transducer 5 is deteriorated (or accidentally due to the influence of noise or the like), the voltage of the capacitor 22 becomes the fourth threshold voltage Vth ₄ or less.

Referring again to FIG. 10B, during the detection sensing period 634, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is low level.

Referring again to FIG. 10 (e), at timing t5, the voltage _S7 (waveform 601) of the electrostatic transducer ₅ is equal to or less than the fourth threshold voltage Vth ₄ , so that the output signal (waveform 605) of the comparator 73 is , Maintain a high level.

Referring to FIG. 10 (f) again, at the timing t5, the inverted output signal ₍ waveform 602) of the flip-flop 61 is low level, but the output signal (waveform 605) of the comparator 73 is high level. Therefore, the output signal (waveform 606) of the OR gate circuit 74 maintains a high level.

Referring again to FIG. 10 (d), during the detection sensing period 632, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, at the timing t ₅ , the detection control signal S ₁ (logic inversion signal of the waveform 602) changes from a low level to a high level. Therefore, the output signal (waveform 604) of the one-shot circuit 71 becomes a low level for a certain period of time (for example, 100 ns).

Referring to FIG. 10 (g) again, at the timing t5, a low level signal (waveform 604) is input from the one _- shot circuit 71 to the inversion set terminal of the flip-flop 75. On the other hand, a high level signal (waveform 606) is input from the OR gate circuit 74 to the inverting reset terminal of the flip-flop 75. Therefore, the flip-flop 75 is set, and the non-inverting output signal (waveform 607) of the flip-flop 75 changes from low level to high level.

At timing t6, the detection sensing period 634 ends and the detection voltage application period ₆₃₅ starts.

Referring to FIG. 10A again, in the detection voltage application period 635, the voltage output circuit 7 increases the voltage S ₇ (waveform 601) having a constant first gradient and then decreasing with a constant second gradient. , Applied to the electrostatic transducer 5.

Referring to FIG. 10B again, in the detection voltage application period 635, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is at a high level.

Referring to FIG. 10 (c) again, in the detection voltage application period 633, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, at the timing t6, the inverted output signal (waveform 602) of the flip-flop ₆₁ changes from the low level to the high level, and the output signal of the mask circuit 64 is used for a certain period of time (for example, from the timing _t6 to the timing _t7 ). 2μs) Low level. Therefore, the output signal (waveform 603) of the NOT gate circuit 76 becomes a high level for a certain period of time (for example, 2 μs).

Referring to FIG. ₁₀ (h) again, at the timing t6, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), and the non-inverting output signal (waveform) of the flip-flop 75. 607) is a high level. Therefore, the output signal (waveform 608) of the AND gate circuit 77 becomes a high level for a certain period of time (for example, 2 μs).

Referring to FIG. ₁₀ (i) again, at the timing t6, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), but the inverted output signal (waveform 607) of the flip-flop 75. The logic invert signal) is low level. Therefore, the output signal (waveform 609) of the AND gate circuit 78 maintains a low level.

Therefore, at the timing _t6 , the counter 79 counts (increments the count value) because the output signal (waveform 608) of the AND gate circuit 77 is at a high level. Further, the counter 79 does not reset (clear) the count value because the output signal (waveform 609) of the AND gate circuit 78 is at a low level. Therefore, the count value of the counter 79 becomes "1".

Referring to FIG. 10 (e) again, when the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes equal to or less than the _{fourth threshold voltage Vth 4 at} the timing t8, the output signal (waveform 605) of the comparator 73 becomes available. It changes from low level to high level.

_At timing t9, the detection voltage application period 635 ends and the detection sensing period 636 starts.

Referring again to FIG. 10A, during the detection sensing period 636, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. Therefore, the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes the voltage of the capacitor 22. When the electrostatic transducer 5 is not deteriorated, the voltage of the capacitor 22 becomes higher than the fourth threshold voltage Vth ₄ .

Referring again to FIG. 10B, during the detection sensing period 636, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is low level.

Referring again to FIG. 10 (d), during the detection sensing period 636, the voltage output circuit 7 does not apply voltage to the electrostatic transducer 5. That is, at the timing t ₉ , the detection control signal S ₁ (logic inversion signal of the waveform 602) changes from a low level to a high level. Therefore, the output signal (waveform 604) of the one-shot circuit 71 becomes a low level for a certain period of time (for example, 100 ns).

Referring to FIG. ₁₀ (e) again, at the timing t10, the voltage _S7 (waveform 601) of the electrostatic transducer 5 becomes higher than the fourth threshold voltage Vth ₄ , so that the output signal (waveform 605) of the comparator 73 becomes higher. , Changes from high level to low level.

Referring to FIG. ₁₀ (f) again, at the timing t10, the inverted output signal (waveform 602) of the flip-flop 61 is at the low level, and the output signal (waveform 605) of the comparator 73 changes from the high level to the low level. .. Therefore, the output signal (waveform 606) of the OR gate circuit 74 changes from a high level to a low level.

Referring to FIG. ₁₀ (g) again, at the timing t9, a low level signal (waveform 604) is input from the one-shot circuit 71 to the inversion set terminal of the flip-flop 75. On the other hand, a high level signal (waveform 606) is input from the OR gate circuit 74 to the inverting reset terminal of the flip-flop 75. Therefore, the non-inverting output signal (waveform 607) of the flip-flop 75 maintains a high level. Next, at the timing t10, a high _- level signal (waveform 604) is input from the one-shot circuit 71 to the inversion set terminal of the flip-flop 75. On the other hand, a low level signal (waveform 606) is input from the OR gate circuit 74 to the inverting reset terminal of the flip-flop 75. Therefore, the non-inverting output signal (waveform 607) of the flip-flop 75 changes from high level to low level.

At the timing _t11 , the detection sensing period 636 ends and the detection voltage application period 637 starts.

Referring to FIG. 10A again, in the detection voltage application period 637, the voltage output circuit 7 applies a voltage S ₇ (waveform 601) rising with a constant first gradient to the electrostatic transducer 5.

Referring to FIG. 10B again, in the detection voltage application period 637, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, the inverted output signal (waveform 602) of the flip-flop 61 is at a high level.

Referring to FIG. 10 (c) again, in the detection voltage application period 637, the voltage output circuit 7 applies the voltage S ₇ to the electrostatic transducer 5. That is, at the timing t ₁₁ , the inverted output signal (waveform 602) of the flip-flop 61 changes from the low level to the high level, and the output signal of the mask circuit 64 is used for a certain period of time (for example, from the timing t ₁₁ to the timing t ₁₂ ). 2 μs (microseconds) low level. Therefore, the output signal (waveform 603) of the NOT gate circuit 76 becomes a high level for a certain period of time (for example, 2 μs).

Referring again to FIG. ₁₀ (h), at timing t11, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), but the non-inverting output signal (waveform) of the flip-flop 75. 607) maintains a low level. Therefore, the output signal (waveform 608) of the AND gate circuit 77 maintains a low level.

Referring to FIG. ₁₀ (i) again, at the timing t11, the output signal (waveform 603) of the NOT gate circuit 76 becomes high level for a certain period of time (for example, 2 μs), and the inverted output signal (waveform 607) of the flip-flop 75 becomes high. The logic invert signal) is at a high level. Therefore, the output signal (waveform 609) of the AND gate circuit 78 becomes a high level for a certain period of time (for example, 2 μs).

Therefore, at the timing _t11 , the counter 79 does not count (does not increment the count value) because the output signal (waveform 608) of the AND gate circuit 77 is at a low level. At the same time, the counter 79 resets (clears) the count value because the output signal (waveform 609) of the AND gate circuit 78 is at a high level. Therefore, the count value of the counter 79 becomes "0".

Summing up the above, the voltage _S7 (voltage of the capacitor 22) of the electrostatic transducer 5 becomes higher than the fourth threshold voltage Vth ₄ in the detection sensing period 632. Therefore, at the timing t2, the counter 79 does not count ₍ does not increment the count value) but resets (clears). Therefore, the count value of the counter 79 becomes "0".

Further, in the detection sensing period 634, the voltage S ₇ (voltage of the capacitor 22) of the electrostatic transducer 5 does not become higher than the fourth threshold voltage Vth ₄ . Therefore, at the timing _t6 , the counter 79 counts (increments the count value) and does not reset (clear). Therefore, the count value of the counter 79 becomes "1".

Further, in the detection sensing period 636, the voltage S ₇ (voltage of the capacitor 22) of the electrostatic transducer 5 becomes higher than the fourth threshold voltage Vth ₄ . Therefore, at the timing _t11 , the counter 79 does not count (does not increment the count value) but resets (clears). Therefore, the count value of the counter 79 becomes "0".

Therefore, the counter 79 determines that the electrostatic transducer 5 has deteriorated and detects the deterioration only when the detection sensing period in which the clamp voltage S ₈ does not become higher than the fourth threshold voltage Vth ₄ continues four times. The signal S ₉ is output. On the other hand, for example, the counter 79 resets (clears) the count value when the detection sensing period in which the clamp voltage S ₈ does not become higher than the fourth threshold voltage Vth ₄ does not continue four times.

(summary)
Similar to the control circuit 308, the control circuit 8 can control one electrostatic transducer 5 to generate vibration, sound or pressure, and detect vibration, sound or pressure.

Further, in the control device 2, the voltage output circuit 7 applies a voltage S ₇ falling with a constant second gradient to the electrostatic transducer 5 to forcibly lower the voltage of the capacitor 22, as in the control device 302. Let me. That is, the voltage output circuit 7 forcibly discharges the electric charge of the capacitor 22. Therefore, the control device 2 can shorten the time required for discharging the capacitor 22 as compared with the control device 102. As a result, the control device 2 can detect vibration, sound, or pressure in a shorter time than that of the control device 102.

Further, the system 1 can eliminate the need for the detection control signal output circuit 121 and the pulse signal generation circuit 123 as compared with the system 100. As a result, the system 1 can suppress the circuit of the microcomputer 3 and also suppress the wiring between the microcomputer 3 and the control circuit 8.

Further, in the deterioration detection unit 70, when the detection sensing period in which the clamp voltage S ₈ does not become higher than the fourth threshold voltage Vth ₄ continues for a predetermined number of times (for example, 4 times), the electrostatic transducer 5 is used. It is determined that the deterioration has occurred, and the deterioration detection signal S ₉ is output. As a result, the control circuit 8 can detect the deterioration of the electrostatic transducer 5.

<Second embodiment>
FIG. 11 is a diagram showing a configuration of a system using the control device of the second embodiment. The same components as those of the first embodiment or the first or second comparative example are designated by the same reference numerals, and the description thereof will be omitted.

System 1A includes control device 2A. The control device 2A includes a control circuit 8A. The control circuit 8A further includes a voltage output unit 80 as compared with the control circuit 8.

The voltage output unit 80 includes a DC power supply 81, a comparator 82, a NAND gate circuit 83, a NOT gate circuit (inverter circuit) 84, and transfer gates 85 and 86.

The DC power supply 81 outputs the sixth threshold voltage Vth ₆ . The sixth threshold voltage Vth ₆ is a voltage (for example, 4.5 V) lower than the first threshold voltage Vth ₁ (for example, 5 V).

A sixth threshold voltage Vth ₆ (for example, 4.5V) is input from the DC power supply 81 to the input terminal of the transfer gate 85. The clamp voltage _S8 is input to the input terminal of the transfer gate 86.

The clamp voltage _S8 is input to the inverting input terminal of the comparator 82. A sixth threshold voltage Vth ₆ (for example, 4.5V) is input to the non-inverting input terminal of the comparator 82. When the clamp voltage S ₈ is equal to or lower than the sixth threshold voltage Vth ₆ , the comparator 82 outputs a high-level signal to one input terminal of the NAND gate circuit 83. When the clamp voltage S ₈ is higher than the sixth threshold voltage Vth ₆ , the comparator 82 outputs a low-level signal to one input terminal of the NAND gate circuit 83.

The detection control signal S1 is input to the _other input terminal of the NAND gate circuit 83. _In the NAND gate circuit 83, when the output signal of the comparator 82 is high level and the detection control signal S1 is high level, the low level signal is transmitted to the input terminal of the NOT gate circuit 84 and the transfer gate 85. Output to the control terminal. In other cases, the NAND gate circuit 83 outputs a high-level signal to the input terminal of the NOT gate circuit 84 and the control terminal of the transfer gate 85.

The NOT gate circuit 84 logically inverts the output signal of the NAND gate circuit 83 and outputs it to the control terminal of the transfer gate 86.

Summarizing the above, the NAND gate circuit 83 has a low level when the clamp voltage S ₈ is equal to or less than the sixth threshold voltage Vth ₆ (for example, 4.5 V) and the detection control signal S ₁ is at a high level. Is output to the control terminal of the transfer gate 85. That is, the NAND gate circuit 83 outputs a low-level signal to the control terminal of the transfer gate 85 when the clamp voltage S ₈ is 4.5 V or less and the voltage output circuit 7 is stopped. As a result, the transfer gate 85 is turned off. On the other hand, the NOT gate circuit 84 outputs a high-level signal to the control terminal of the transfer gate 86. As a result, the transfer gate 86 is turned on. Therefore, the transfer gate 86 outputs the clamp voltage S ₈ as the output voltage S ₁₀ to the voltage change detection unit 124.

On the other hand, the NAND gate circuit 83 outputs a high level signal when the clamp voltage S ₈ is higher than the sixth threshold voltage Vth ₆ (for example, 4.5 V) or the detection control signal S ₁ is low level. , Output to the control terminal of the transfer gate 85. That is, the NAND gate circuit 83 outputs a high-level signal to the control terminal of the transfer gate 85 when the clamp voltage S ₈ is higher than 4.5 V or the voltage output circuit 7 is operating. As a result, the transfer gate 85 is turned on. On the other hand, the NOT gate circuit 84 outputs a low-level signal to the control terminal of the transfer gate 86. As a result, the transfer gate 86 is turned off. Therefore, the transfer gate 85 outputs the sixth threshold voltage Vth ₆ as the output voltage S ₁₀ to the voltage change detection unit 124.

For example, referring to FIG. 8 again, in the detection sensing period 422, the detection control signal S1 represented by the waveform 506 is at a high level, and the clamp voltage S ₈ becomes the _{sixth threshold voltage Vth 6 or} less, so that the NAND gate The circuit 83 outputs a low level signal. Therefore, the voltage output unit 80 outputs the clamp voltage S ₈ as the output voltage S ₁₀ to the voltage change detection unit 124 during the detection sensing period 322. On the other hand, in the detection voltage application periods 421 and 423, since the detection control signal S1 represented by the waveform 506 is low level, the NAND gate circuit 83 outputs _a high level signal. Therefore, the voltage output unit 80 sets the sixth threshold voltage Vth ₆ (for example, 4.5 V) as the output voltage S ₁₀ when the detection voltage application periods 421 and 423, that is, the voltage output circuit 7 is operating. It is output to the voltage change detection unit 124.

Therefore, when the voltage output circuit 7 is operating, the voltage output unit 80 outputs the sixth threshold voltage Vth ₆ (for example, 4.5V) as the output voltage _S10 , so that the output voltage _S10 is unnecessary. Fluctuation can be suppressed. As a result, the voltage change detection unit 124 can stably sense the voltage of the capacitor 22.

<Third embodiment>
FIG. 12 is a diagram showing a configuration of a system using the control device of the third embodiment. The same components as those of the first or second embodiment or the first or second comparative example are designated by the same reference numerals, and the description thereof will be omitted.

System 1B includes control device 2B. The control device 2B includes a control circuit 8B. The control circuit 8B includes a voltage output unit 80B instead of the voltage output unit 80 as compared with the control circuit 8A.

The voltage output unit 80B further includes a DC power supply 87, a comparator 88, and NAND gate circuits 89 and 90 as compared with the voltage output unit 80.

The DC power supply 87 outputs a seventh threshold voltage Vth ₇ , which is higher than the second threshold voltage Vth ₂ (for example, 1V). The seventh threshold voltage Vth ₇ is exemplified by 1.5 V, but the present disclosure is not limited to this.

The clamp voltage _S8 is input to the inverting input terminal of the comparator 88. A seventh threshold voltage Vth ₇ (for example, 1.5V) is input to the non-inverting input terminal of the comparator 88. When the clamp voltage S ₈ is equal to or lower than the seventh threshold voltage Vth ₇ , the comparator 88 outputs a high-level signal to one input terminal of the NAND gate circuit 89. When the clamp voltage S ₈ is higher than the seventh threshold voltage Vth ₇ , the comparator 88 outputs a low-level signal to one input terminal of the NAND gate circuit 89.

The output signal of the comparator 62 is input to the other input terminal of the NAND gate circuit 89. The NAND gate circuit 89 outputs a low level signal to one input terminal of the NAND gate circuit 90 when the output signal of the comparator 88 is high level and the output signal of the comparator 62 is high level. .. The NAND gate circuit 89 outputs a high level signal to one input terminal of the NAND gate circuit 90 in other cases.

An inverting output signal of the flip _- flop 61 (logical inverting signal of the detection control signal S1) is input to the other input terminal of the NAND gate circuit 90. The NAND gate circuit 90 inputs a low level signal to the other input of the NAND gate circuit 83 when the output signal of the NAND gate circuit 89 is high level and the inverted output signal of the flip-flop 61 is high level. Output to the terminal. The NAND gate circuit 90 outputs a high level signal to the other input terminal of the NAND gate circuit 83 in other cases.

Summarizing the above, when the clamp voltage S ₈ is higher than the sixth threshold voltage Vth ₆ (for example, 4.5 V), the voltage output unit 80B outputs the sixth threshold voltage Vth ₆ regardless of other conditions. The voltage S ₁₀ is output to the voltage change detection unit 124.

Next, in the voltage output unit 80B, when the clamp voltage S ₈ is equal to or less than the sixth threshold voltage Vth ₆ (for example, 4.5 V), the detection control signal S ₁ is at a high level (the voltage output circuit 7 is stopped). ), The clamp voltage S ₈ is output to the voltage change detection unit 124 as the output voltage S ₁₀ .

Further, the voltage output unit 80B operates when the clamp voltage S ₈ is equal to or lower than the sixth threshold voltage Vth ₆ (for example, 4.5 V) and the detection control signal S ₁ is at a low level (voltage output circuit 7 operates). Even in the case of), the clamp voltage S ₈ is output to the voltage change detection unit 124 as the output voltage S ₁₀ under the following conditions. That is, in the voltage output unit 80B, the clamp voltage S ₈ is equal to or less than the seventh threshold voltage Vth ₇ (for example, 1.5 V), and the output voltage control signal S ₂ is the third threshold voltage Vth ₃ (for example, 30 mV). In the following cases, the clamp voltage S ₈ is output to the voltage change detection unit 124 as the output voltage S ₁₀ .

Therefore, the timing at which the voltage output unit 80B outputs the clamp voltage S ₈ as the output voltage S ₁₀ is earlier than that of the voltage output unit 80 of the second embodiment. As a result, the voltage change detection unit 124 can start sensing the voltage of the capacitor 22 from an earlier timing as compared with the second embodiment. As a result, the voltage change detection unit 124 can sense the output voltage S ₁₀ more stably.

<Fourth Embodiment>
FIG. 13 is a diagram showing a configuration of a system using the control device of the fourth embodiment. The same components as those of the first, second or third embodiment, or the first or second comparative example are designated by the same reference numerals, and the description thereof will be omitted.

System 1C includes control device 2C. The control device 2C includes a control circuit 8C. The control circuit 8C includes a voltage clamp portion 50C instead of the voltage clamp portion 50 as compared with the control circuit 8A.

The voltage clamp unit 50C further includes a NOT gate circuit (inverter circuit) 53 and transfer gates 54 and 55 as compared with the voltage clamp unit 50.

The output signal of the comparator 62 is input to the input terminal of the NOT gate circuit 53. The NOT gate circuit 53 outputs a high level signal to the control terminal of the transfer gate 54 when the output signal of the comparator 62 is low level. The output signal of the comparator 62 is input to the control terminal of the transfer gate 55.

A reference potential (for example, a ground potential) is input to the input terminal of the transfer gate 54. For example, 8V is input to the input terminal of the transfer gate 55 from the DC power supply 51.

Summarizing the above, when the output voltage control signal S ₂ is equal to or less than the third threshold voltage Vth ₃ (for example, 30 mV), the transfer gate 54 is turned off and the transfer gate 55 is turned on. As a result, a bias voltage (for example, 8V) is applied to the gate of the transistor 52. Therefore, the transistor 52 is turned on, and the voltage clamp unit 50C outputs the clamp voltage _S8 .

On the other hand, when the output voltage control signal S ₂ is higher than the third threshold voltage Vth ₃ , the transfer gate 54 is turned on and the transfer gate 55 is turned off. As a result, the reference potential is applied to the gate of the transistor 52, so that the bias voltage (for example, 8V) is not applied. Therefore, the transistor 52 is turned off, and the voltage clamp portion 50C does not output the clamp voltage _S8 .

Therefore, the transistor 52 is turned on in the period including the detection sensing period, and turned off in the other period (the period not including the detection sensing period). As a result, the voltage clamp portion 50C can suppress the power consumption of the transistor 52.

The fourth embodiment and the third embodiment may be combined. That is, the control circuit 8C may include the voltage output unit 80B instead of the voltage output unit 80.

<Fifth Embodiment>
FIG. 14 is a diagram showing a configuration of a system using the control device according to the fifth embodiment. The same components as those of the first, second, third or fourth embodiment, or the first or second comparative example are designated by the same reference numerals, and the description thereof will be omitted.

System 1D includes control device 2D. The control device 2D includes a control circuit 8D. The control circuit 8D includes a voltage clamp portion 50D instead of the voltage clamp portion 50C as compared with the control circuit 8C.

The voltage clamp unit 50D further includes a DC power supply 56 and a comparator 57 as compared to the voltage clamp unit 50C.

The DC power supply 56 outputs the fifth threshold voltage Vth ₅ . The fifth threshold voltage Vth ₅ is exemplified by a voltage slightly higher than the third threshold voltage Vth ₃ (for example, 30 mV). For example, the fifth threshold voltage Vth ₅ is exemplified to be about 35 mV, but the present disclosure is not limited to this.

The _output voltage control signal S2 is input to the inverting input terminal of the comparator 57. A fifth threshold voltage Vth ₅ (for example, 35 mV) is input to the non-inverting input terminal of the comparator 57. When the output voltage control signal S ₂ is equal to or less than the fifth threshold voltage Vth ₅ , the comparator 57 outputs a high-level signal to the input terminal of the NOT gate circuit 53 and the control terminal of the transfer gate 55. When the output voltage control signal S ₂ is higher than the fifth threshold voltage Vth ₅ , the comparator 57 outputs a low-level signal to the input terminal of the NOT gate circuit 53 and the control terminal of the transfer gate 55.

Summarizing the above, when the output voltage control signal S ₂ is equal to or less than the fifth threshold voltage Vth ₅ (for example, 35 mV), the transfer gate 54 is turned off and the transfer gate 55 is turned on. As a result, a bias voltage (for example, 8V) is applied to the gate of the transistor 52. Therefore, the transistor 52 is turned on, and the voltage clamp unit 50D outputs the clamp voltage _S8 .

On the other hand, when the output voltage control signal S ₂ is higher than the fifth threshold voltage Vth ₅ , the transfer gate 54 is turned on and the transfer gate 55 is turned off. As a result, the reference potential is applied to the gate of the transistor 52, so that the bias voltage (for example, 8V) is not applied. Therefore, the transistor 52 is turned off, and the voltage clamp portion 50D does not output the clamp voltage _S8 .

Therefore, the timing at which the voltage clamp portion 50D starts the output of the clamp voltage _S8 is earlier than that of the voltage clamp portion 50C of the fourth embodiment. Further, the timing at which the voltage clamp portion 50D ends the output of the clamp voltage _S8 is later than that of the voltage clamp portion 50C of the fourth embodiment. As a result, the voltage clamp unit 50D can extend the period for outputting the clamp voltage S ₈ as compared with the fourth embodiment. Therefore, the voltage change detection unit 124 can sense the output voltage S ₁₀ more stably.

The fifth embodiment and the third embodiment may be combined. That is, the control circuit 8D may include the voltage output unit 80B instead of the voltage output unit 80.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention as well as the invention described in the claims and the equivalent scope thereof.

1, 1A, 1B, 1C, 1D system 2, 2A, 2B, 2C, 2D controller 3 Microcomputer 4, 51, 56, 63, 67, 72, 81, 87 DC power supply 5 Electrostatic transducer 6 Condenser 7 Voltage Output circuit 8, 8A, 8B, 8C, 8D Control circuit 30 Voltage output circuit Control unit 31 Switching signal output unit 32 Error amplifier 33, 34 Buffer 50, 50C, 50D Voltage clamp unit 52 Transistor 53, 76, 84 NOT gate circuit 54 , 55, 85, 86 Transfer gate 60 Control signal output unit 61, 75 Flip-flop 57, 62, 66, 73, 82, 88 Comparator 64 Mask circuit 65, 83, 89, 90 NAND gate circuit 70 Deterioration detection unit 71 One shot Circuit 74 OR Gate circuit 77, 78 AND Gate circuit 79 Counter 80, 80B Voltage output unit 124 Voltage change detector 125 Output voltage control signal Output circuit 126 Deterioration detection signal receiver

Claims (15)

A control circuit that controls an electrostatic transducer that can generate vibration, sound or pressure and can detect vibration, sound or pressure.
When the first control signal is at the first level, the voltage output circuit is controlled so that a voltage corresponding to the second control signal is applied between both ends of the electrostatic transducer, and the first control signal is the second. In the case of level, the voltage output circuit control unit that stops the voltage output circuit,
A voltage clamp unit that outputs a clamp voltage that clamps the voltage between terminals of the electrostatic transducer to the first threshold voltage or less.
When the clamp voltage becomes equal to or lower than the second threshold voltage, the first control signal of the second level is output, and when the second control signal becomes higher than the third threshold voltage, the first control signal is output. A control signal output unit that outputs one level of the first control signal,
If the clamp voltage does not exceed the fourth threshold voltage higher than the second threshold voltage for a predetermined number of times continuously during the second level period, the electrostatic transducer deteriorates. A deterioration detection unit that outputs a deterioration detection signal indicating that the product has been used,
To prepare
A control circuit characterized by that. The second control signal is
When vibration, sound or pressure is generated in the electrostatic transducer, it is a signal of an arbitrary waveform to be generated, and when vibration, sound or pressure is detected in the electrostatic transducer, the amplitude is said. A triangular wave signal smaller than a signal of any waveform,
The control circuit according to claim 1, wherein the control circuit is characterized in that. The control signal output unit is
A first comparator that compares the clamp voltage with the second threshold voltage,
A second comparator that compares the second control signal with the third threshold voltage,
A first flip-flop that is set by the output signal of the first comparator, reset by the output signal of the second comparator, and outputs the first control signal, and
including,
The control circuit according to claim 1, wherein the control circuit is characterized in that. The control signal output unit is
Within a predetermined period after the change of the first control signal, a mask circuit for masking the output signal of the first comparator is further included.
The control circuit according to claim 3, wherein the control circuit is characterized in that. The deterioration detection unit is
A third comparator that compares the clamp voltage with the fourth threshold voltage,
The first control signal is set by a first timing signal representing the timing at which the first level changes from the first level to the second level, and is ORed by the logical sum of the output signal of the third comparator and the inversion signal of the first control signal. The second flip-flop to be reset and
A first logical product gate that outputs a logical product of the non-inverting output signal of the second flip-flop and the second timing signal indicating the timing at which the first control signal changes from the second level to the first level. Circuit and
A second logical AND gate circuit that outputs the logical product of the inverted output signal of the second flip-flop and the second timing signal.
When the output signal of the first AND gate circuit is counted, cleared by the output signal of the second logical product gate circuit, and the output signal of the first AND gate circuit is counted a predetermined number of times, the deterioration detection signal is obtained. Output, counter, and
including,
The control circuit according to claim 3, wherein the control circuit is characterized in that. The deterioration detection unit is
A one-shot circuit that outputs a one-shot first timing signal when the first control signal changes from the first level to the second level is further included.
The control circuit according to claim 5. The voltage clamp portion is
A drain is connected to the terminal on the high potential side of the electrostatic transducer, a bias voltage is supplied to the gate, and a transistor is included which outputs the clamp voltage from the source.
The control circuit according to claim 1, wherein the control circuit is characterized in that. The transistor is
A bias voltage is supplied to the gate when the second control signal is equal to or lower than the third threshold voltage, and no bias voltage is supplied to the gate when the second control signal is higher than the third threshold voltage.
The control circuit according to claim 7, wherein the control circuit is characterized in that. The transistor is
A bias voltage is supplied to the gate when the second control signal is equal to or lower than the fifth threshold voltage higher than the third threshold voltage, and a bias voltage is supplied to the gate when the second control signal is higher than the fifth threshold voltage. Is not supplied,
The control circuit according to claim 7, wherein the control circuit is characterized in that. When the clamp voltage is equal to or lower than the sixth threshold voltage lower than the first threshold voltage and the first control signal is at the second level, the clamp voltage is output and the clamp voltage is the sixth threshold. Further including a voltage output unit that outputs the sixth threshold voltage when the voltage is higher than the voltage or the first control signal is at the first level.
The control circuit according to claim 1, wherein the control circuit is characterized in that. The voltage output unit is
Even if the first control signal is at the first level, the clamp voltage is equal to or less than the seventh threshold voltage higher than the second threshold voltage, and the second control signal is equal to or less than the third threshold voltage. When, the clamp voltage is output.
10. The control circuit according to claim 10. The electrostatic transducer is an electrostatic actuator or an electrostatic pressure detection element.
The control circuit according to claim 1, wherein the control circuit is characterized in that. It is a semiconductor integrated circuit,
The control circuit according to claim 1, wherein the control circuit is characterized in that. The control circuit according to claim 1 and
With the voltage output circuit
including,
A control device characterized by that. The control device according to claim 14,
A signal output unit that outputs the second control signal to the control circuit, and
A voltage change detection unit that detects vibration, sound, or pressure applied to the electrostatic transducer based on the change in the clamp voltage.
A detection signal receiving unit that receives the deterioration detection signal, and
including,
A system that features that.

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