JP2020178061A - Electrostatic protection circuit, semiconductor device, and electronic apparatus - Google Patents

Abstract

To stably protect an internal circuit of a semiconductor device.SOLUTION: An electrostatic protection circuit has a first area formed of a p-type silicon, a second area formed of an n-type silicon, a third area provided in contact with the first area between the first area and the second area in plan view and formed of an n-type silicon, a fourth area provided individually in contact with the second area and the third area between the second area and the third area in plan view and formed of a p-type silicon, and a fifth area provided in contact with one area of the third area and the fourth area in plan view, formed of a p-type or an n-type silicon having the same conductivity type as the one area, and having a higher concentration of impurity than the one area. The fifth area is connected to an electrode arranged overlapping the fifth area in plan view, and the electrode is supplied with a trigger voltage.SELECTED DRAWING: Figure 3

Description

The present invention relates to electrostatic protection circuits, semiconductor devices and electronic devices.

A semiconductor device including an integrated circuit configured by using a semiconductor such as silicon is usually provided with an electrostatic discharge protection circuit that protects the integrated circuit from ESD (Electro-Static Discharge). When the integrated circuit is configured by using an SOI (Silicon on Insulator) substrate, for example, the protection element described in Patent Document 1 is used in the conventional electrostatic protection circuit.

In the protective element described in Patent Document 1, a P + type region in which P-type impurities are introduced at a high concentration, an N-type region in which N-type impurities are introduced at a low concentration, and a P-type impurity are introduced at a low concentration. It has a P-type region and an N + -type region in which N-type impurities are introduced at a high concentration. These regions are arranged in this order, and adjacent regions are arranged in contact with each other. Aluminum wiring connected to the signal transmission path is connected to the P + type region. An aluminum wiring connected to the ground potential is connected to the N + type region. When the voltage between the P + type region and the N + type region becomes a predetermined value or more, punch-through occurs in the P type region and the N type region, so that the P + type region and the N + type region become conductive.

JP-A-2002-094010

In the protective element described in Patent Document 1, since the P + type region and the N + type region are in a conductive state due to punch-through in the P-type region and the N-type region, the dimensions of the P-type region or the N-type region, etc. There is a problem that the trigger voltage, which is the voltage at which the conduction state is established, fluctuates due to manufacturing variations. Further, in the protection element described in Patent Document 1, when the trigger voltage is changed, the dose amount of impurities in the P-type region or the N-type region must be changed, so that a new glass mask needs to be prepared separately. As a result, there is also a problem that the manufacturing cost increases.

The electrostatic protection circuit according to one aspect of the present invention protects a circuit using the silicon layer in an SOI substrate in which a substrate made of silicon and a silicon layer made of silicon are bonded via a silicon oxide film from static electricity. This is an electrostatic protection circuit that is provided on the silicon layer and is provided on the silicon layer at a position different from that of the first region formed of P-type silicon and the first region in a plan view. A second region composed of silicon and a second region formed on the silicon layer in contact with the first region between the first region and the second region in a plan view and composed of N-type silicon. It is provided in the silicon layer between the three regions and the second region and the third region in a plan view in contact with each of the second region and the third region, and is composed of P-shaped silicon. The silicon layer has a fourth region and a first contact region that is in contact with only one of the third region and the fourth region in a plan view, and is of the same conductive type as the one region. It is composed of P-type or N-type silicon, has a fifth region having a higher concentration of impurities than the one region, and the first region is connected to a first wiring connected to the circuit.
The second region is connected to a second wiring connected to the circuit, the fifth region is connected to an electrode arranged so as to overlap the fifth region in a plan view, and the electrode is connected to the first. A trigger voltage for passing a current from the first region to the second region via the third region and the fourth region is supplied.

It is a figure which shows the schematic structure of the semiconductor device which concerns on embodiment. It is a figure which shows the electrostatic protection circuit which concerns on 1st Embodiment. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 1st Embodiment has. FIG. 3 is a sectional view taken along line A4-A4 in FIG. It is a figure which shows the electrostatic protection circuit which concerns on 2nd Embodiment. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 2nd Embodiment has. FIG. 6 is a cross-sectional view taken along the line A7-A7 in FIG. It is a figure which shows the electrostatic protection circuit which concerns on 3rd Embodiment. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 3rd Embodiment has. 9 is a cross-sectional view taken along the line A10-A10 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 4th Embodiment has. 11 is a cross-sectional view taken along the line A12-A12 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 5th Embodiment has. FIG. 3 is a cross-sectional view taken along the line A14-A14 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 6th Embodiment has. FIG. 5 is a cross-sectional view taken along the line A16-A16 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 7th Embodiment has. It is sectional drawing of A18-A18 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 8th Embodiment has. It is sectional drawing of A20-A20 in FIG. It is a top view of the thyristor which the electrostatic protection circuit which concerns on 9th Embodiment has. FIG. 21 is a cross-sectional view taken along the line A22-A22 in FIG. It is a figure which shows the electrostatic protection circuit which concerns on 10th Embodiment. It is a figure which shows the electrostatic protection circuit which concerns on 11th Embodiment. It is a figure which shows the electrostatic protection circuit which concerns on 12th Embodiment. It is a graph which shows the voltage-current characteristic of the electrostatic protection circuit which concerns on 12th Embodiment. It is a block diagram which shows the structural example of an electronic device.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the accompanying drawings. In the drawings, the dimensions or scales of each part are appropriately different from the actual ones, and some parts are schematically shown for easy understanding. Further, the scope of the present invention is not limited to these forms unless it is stated in the following description that the present invention is particularly limited.

A. Semiconductor device FIG. 1 is a diagram showing a schematic configuration of a semiconductor device 100 according to an embodiment. The semiconductor device 100 is a device having the integrated circuit shown in the figure. As shown in FIG. 1, the semiconductor device 100 includes power supply terminals P1 and P2, signal terminals P3, power supply wirings 101 and 102, signal wirings 103, internal circuits 104, and diodes 105, which form an integrated circuit. It has 106 and an electrostatic protection circuit 10. In the semiconductor device 100, the illustrated integrated circuit may be composed of a single integrated circuit or a plurality of integrated circuits.

The power supply terminal P1 is a terminal to which the first potential VDD is supplied. The power supply wiring 101, which is an example of the first wiring, is connected to the power supply terminal P1. The power supply wiring 101 has a resistance component RB101. On the other hand, the power supply terminal P2 is a terminal to which the second potential VSS having a lower potential than the first potential VDD is supplied. The power supply wiring 102, which is an example of the second wiring, is connected to the power supply terminal P2. The power supply wiring 102 has a resistance component RB 102. Further, the signal terminal P3 is a terminal that outputs a signal from the internal circuit 104. The signal wiring 103 is connected to the signal terminal P3.

An internal circuit 104 is connected to the power supply wirings 101 and 102 and the signal wiring 103. In the example shown in FIG. 1, the internal circuit 104 includes a transistor QP104 which is a P-channel MOS transistor and a transistor QN104 which is an N-channel MOS transistor. Here, the power supply terminal P1 is connected to the source of the transistor QP104 via the power supply wiring 101. The power supply terminal P2 is connected to the source of the transistor QN104 via the power supply wiring 102. The signal terminal P3 is connected to the drains of the transistors QP104 and QN104 via the signal wiring 103. The signal terminal P3 may be a terminal to which a signal to the internal circuit 104 is input. In this case, the signal terminal P3 is connected to the gates of the transistors QP104 and QN104 via the signal wiring 103.

A diode 105 for connecting the power supply wiring 101 and the signal wiring 103 is provided. The cathode of the diode 105 is connected to the power supply wiring 101, and the anode of the diode 105 is connected to the signal wiring 103. That is, the diode 105 is a diode whose forward direction is from the signal wiring 103 to the power supply wiring 101. Further, a diode 106 for connecting the power supply wiring 102 and the signal wiring 103 is provided. The cathode of the diode 106 is connected to the signal wiring 103, and the anode of the diode 106 is connected to the power supply wiring 102. That is, the diode 106 is a diode whose forward direction is from the power supply wiring 102 to the signal wiring 103. Each of the above diodes 105 and 106 functions as a discharge element that discharges an electric charge due to the excessive positive potential when an excessive positive potential due to static electricity discharge or the like is supplied to the power supply terminal P2.

Specifically, when an excessive positive potential due to electrostatic discharge or the like is supplied to the power supply terminal P2, the charge due to the excessive positive potential is discharged to the signal terminal P3 via the diode 106, or It is discharged to the power supply terminal P1 via the diode 105 as well as the diode 106. Therefore, it is possible to prevent damage to the internal circuit 104 due to the excessive positive potential. One of the diodes 105 and 106 may be omitted, or another discharge element using a transistor or the like may be used instead of one of the diodes 105 and 106.

An electrostatic protection circuit 10 for connecting the power supply wiring 101 and the power supply wiring 102 is provided. Here, the electrostatic protection circuit 10 is connected to the power supply wiring 101 via the node N1 and is connected to the power supply wiring 102 via the node N2. The electrostatic protection circuit 10 is said to be excessive when an excessive positive potential due to static electricity discharge or the like is supplied to the signal terminal P3, or when an excessive negative potential due to static electricity discharge or the like is supplied to the signal terminal P3. It is a circuit that emits electric charge by positive or negative potential.

Specifically, when an excessive positive potential due to static electricity discharge or the like is supplied to the signal terminal P3 while the power supply terminal P2 is grounded, the current due to the excessive positive potential is treated as a surge current by the diode 105. It flows through the power supply wiring 101, the static electricity protection circuit 10, and the power supply wiring 102 in this order. Further, when an excessive negative potential due to electrostatic discharge or the like is supplied to the signal terminal P3 while the power supply terminal P1 is grounded, the current due to the excessive negative potential is treated as a surge current in the power supply wiring 101 and the electrostatic protection circuit. 10. It flows through the power supply wiring 102 and the diode 106 in this order. In either case, the sum of the voltages generated in each part of the element or the like on the path described above is smaller than the breakdown voltage at which the element such as the transistor QP104 or QN104 of the internal circuit 104 is destroyed. Therefore, the static electricity protection circuit 10 can prevent the internal circuit 104 from being destroyed due to static electricity discharge or the like.

The semiconductor device 100 described above includes an electrostatic protection circuit 10 that constitutes an integrated circuit, and an internal circuit 104 that is a circuit that is electrically connected to the electrostatic protection circuit 10. As described in detail below, the static electricity protection circuit 10 can stably protect the internal circuit 104 from static electricity because the fluctuation of the voltage value of the trigger voltage, which is the voltage at which the operation starts, is small. The connection form of the electrostatic protection circuit 10 is not limited to the example shown in FIG. 1. For example, the electrostatic protection circuit 10 may be provided between the power supply wiring 101 and the signal wiring 103, or the electrostatic protection circuit 10 may be provided. May be provided between the power supply wiring 102 and the signal wiring 103. That is, in FIG. 1, the case where the power supply wiring 101 is the first wiring and the power supply wiring 102 is the second wiring is exemplified, but of the two wirings selected from the power supply wirings 101 and 102 and the signal wiring 103. One may be used as the first wiring and the other as the second wiring. In the semiconductor device 100, the electrostatic protection circuit 10 and the internal circuit 104 may be composed of a single integrated circuit or a plurality of integrated circuits. Further, the semiconductor device 100 may be configured to include a discrete transistor or the like in addition to the integrated circuit.

B. Static electricity protection circuit B1. 1st Embodiment FIG. 2 is a figure which shows the electrostatic protection circuit 10 which concerns on 1st Embodiment. As shown in FIG. 2, the electrostatic protection circuit 10 includes a diode 11, a thyristor 12, a resistor 13, and a trigger circuit 14.

The diode 11 is provided between the node N1 and the node N2, the cathode of the diode 11 is connected to the node N1, and the anode of the diode 11 is connected to the node N2. That is, the diode 11 is a diode whose forward direction is from the node N2 to the node N1. The diode 11 described above functions as a discharge element that forms a discharge path in the direction from the node N2 to the node N1.

The thyristor 12 is a discharge circuit provided between the node N1 and the node N2 and forming a discharge path in the direction from the node N1 to the node N2. The thyristor 12 has a transistor QA12 which is a PNP bipolar transistor and a transistor QC12 which is an NPN bipolar transistor.

Here, the base of the transistor QA12 and the collector of the transistor QC12 are connected to each other, and the collector of the transistor QA12 and the base of the transistor QC12 are connected to each other. Then, the emitter of the transistor QA 12 constitutes the anode A of the thyristor 12 and is connected to the node N1. The emitter of the transistor QC12 constitutes the cathode K of the thyristor 12 and is connected to the node N2. The base of the transistor QA12 constitutes the gate G1 of the thyristor 12 and is connected to the node N1 via the resistor 13. In the above thyristor 12, when a current flows through the base of the transistor QA12, a current flows from the emitter side of the transistor QA12 to the collector side, and accordingly, a current flows from the collector side of the transistor QC12 to the emitter side. Therefore, by passing a current through the gate G1 of the thyristor 12, it is possible to form a discharge path for passing a current from the anode side to the cathode side of the thyristor 12. The configuration of the thyristor 12 is not limited to the configuration shown in FIG. 2, and for example, another transistor or resistor may be added.

The resistor 13 functions as a base resistor for the transistor QA12. This function has the effect of reducing malfunction of the thyristor 12 due to external noise.

The trigger circuit 14 is a circuit that turns on the thyristor 12 when a voltage equal to or higher than a predetermined value is applied between the node N1 and the node N2. The trigger circuit 14 is composed of a GGnMOS type transistor QN14. The source and gate of transistor QN14 are connected to node N2. The drain of the transistor QN14 is connected to the gate G1 of the thyristor 12. When a voltage equal to or higher than a predetermined voltage is applied to the drain side of the above transistor QN14, a current starts to flow due to the operation of the NPN parasitic bipolar transistor existing between the drain and the source, and the operating voltage drops sharply. The snapback phenomenon, which is a phenomenon in which a large current flows, occurs. Due to this snapback phenomenon, the trigger circuit 14 turns on the thyristor 12. Therefore, the trigger voltage, which is the voltage at which the thyristor 12 operates, is set according to the voltage at which the snapback phenomenon of the transistor QN 14 occurs.

FIG. 3 is a plan view of the thyristor 12 included in the electrostatic protection circuit 10 according to the first embodiment. FIG. 4 is a sectional view taken along line A4-A4 in FIG. The thyristor 12 is an N-gate type thyristor configured by using the SOI substrate 20. As shown in FIG. 4, the SOI substrate 20 has a substrate 20a made of silicon, a silicon oxide film 20b, and a silicon layer 20c made of silicon, and the substrate 20a and the silicon layer 20c are silicon. It is bonded via the oxide film 20b.

P-type or N-type impurities are appropriately introduced into the silicon layer 20c, and the first region 21, the second region 22, the third region 23, the fourth region 24, and the fifth region 25 are provided. These regions are provided over the entire thickness direction of the silicon layer 20c. In the present embodiment, the first region 21, the third region 23, the fourth region 24, and the second region 22 are arranged side by side in this order from the left side to the right side in FIG. 3, and among these regions, they are adjacent to each other. The two regions come into contact with each other. Here, each of these regions has a longitudinal shape extending in a direction perpendicular to the direction in which these regions are arranged in a plan view. Further, the third region 23 has a frame shape in a plan view of the SOI substrate 20 in the thickness direction, and the fifth region 25 is in contact with the third region 23 inside the third region 23. Be placed. Therefore, in the cross section shown in FIG. 4, from the left side to the right side in FIG. 4, the first region 21, the third region 23, the fifth region 25, the third region 23, the fourth region 24, and the second region 22 are the same. They are arranged side by side in order. The fifth region 25 has a first contact region 25a in contact with the third region 23. The first contact region 25a is a region or a portion of the fifth region 25 that contacts the third region 23, and is provided over the entire circumference of the outer edge of the fifth region 25 in a plan view of the SOI substrate 20 in the thickness direction. .. In the following, the plan view of the SOI substrate 20 viewed from the thickness direction is also simply referred to as "plan view".

The first region 21 and the fourth region 24 are regions made of P-type silicon, respectively. P-type impurities such as boron are introduced into the first region 21 and the fourth region 24, respectively. However, the concentration of the impurity in the first region 21 is higher than the concentration of the impurity in the fourth region 24. That is, the first region 21 is a P-type region having a high concentration of P +, and the fourth region 24 is a P-type region having a low concentration of P−. The concentration of the impurity in the first region 21 is, for example, about 5 × 10 ²⁰ cm ^-3 . The concentration of the impurity in the fourth region 24 is, for example, about 2 × 10 ¹⁶ cm ^-3 . Of the above first region 21 and fourth region 24, the contact 31 is provided in the first region 21. The contact 31 is a part of a wiring made of metal or the like or an electrode such as a conductor post arranged in a contact hole provided in an insulating film (not shown), and is connected to the above-mentioned node N1 via a wiring (not shown). ..

On the other hand, the second region 22, the third region 23, and the fifth region 25 are regions made of N-type silicon, respectively. N-type impurities such as phosphorus are introduced into the second region 22, the third region 23, and the fifth region 25, respectively. However, the concentration of the impurity in each of the second region 22 and the fifth region 25 is higher than the concentration of the impurity in the third region 23. That is, each of the second region 22 and the fifth region 25 is an N-type region having a high concentration of N +, and the third region 23 is an N-type region having a low concentration of N−. The concentration of the impurity in each of the second region 22 and the fifth region 25 is, for example, about 5 × 10 ²⁰ cm ^-3 . The concentration of the impurity in the third region 23 is, for example, about 2 × 10 ¹⁶ cm ^-3 . Of the above-mentioned second region 22, third region 23, and fifth region 25, the contact 32 is provided in the second region 22. The contact 32 is a part of the wiring made of metal or the like connected to the above-mentioned node N2 or a conductor post. A contact 33 is provided in the fifth region 25. The contact 33 is a part of a wire made of metal or the like or an electrode such as a conductor post arranged in a contact hole provided in an insulating film (not shown), and the resistor 13 and the trigger circuit 14 described above are provided via a wire (not shown). Connected to.

Of the above first region 21, second region 22, third region 23, fourth region 24, and fifth region 25, elements other than the second region 22 constitute the above-mentioned transistor QA12, and the first region 21 is excluded. The elements constitute the transistor QC12 described above. That is, the first region 21, the third region 23, the fourth region 24, and the fifth region 25 constitute the transistor QA12 described above, and the second region 22, the third region 23, the fourth region 24, and the fifth region 25 form the transistor QA12. It constitutes the above-mentioned transistor QC12.

As described above, the static electricity protection circuit 10 uses the silicon layer 20c in the SOI substrate 20 in which the substrate 20a made of silicon and the silicon layer 20c made of silicon are bonded via the silicon oxide film 20b. The internal circuit 104, which is a circuit, is protected from static electricity. Here, the static electricity protection circuit 10 has a first region 21, a second region 22, a third region 23, a fourth region 24, and a fifth region 25. The first region 21 is provided in the silicon layer 20c and is composed of P-type silicon. The second region 22 is provided in the silicon layer 20c at a position different from that of the first region 21 in a plan view, and is composed of N-type silicon. The third region 23 is provided in the silicon layer 20c in contact with the first region 21 between the first region 21 and the second region 22 in a plan view, and is composed of N-type silicon. The fourth region 24 is provided in the silicon layer 20c between the second region 22 and the third region 23 in contact with each of the second region 22 and the third region 23 in a plan view, and is composed of P-shaped silicon. Will be done. The fifth region 25 has a first contact region 25a that contacts only the third region 23, which is one of the third region 23 and the fourth region 24 in a plan view, and is provided on the silicon layer 20c. It is composed of the same conductive N-type silicon as the third region 23, and has a higher concentration of impurities than the third region 23. Of the above plurality of regions, the first region 21 is connected to the power supply wiring 101, which is the first wiring connected to the internal circuit 104. The second region 22 is connected to the power supply wiring 102, which is the second wiring connected to the internal circuit 104. The fifth region 25 is connected to a contact 33, which is an electrode arranged so as to overlap the fifth region 25 in a plan view. A trigger voltage for passing a current from the first region 21 to the second region 22 via the third region 23 and the fourth region 24 is supplied to the contact 33.

In the above electrostatic protection circuit 10, by supplying a trigger voltage to the contact 33 connected to the fifth region 25, a current flows from the first region 21 to the second region 22 via the third region 23 and the fourth region 24. Shed. Therefore, it is possible to reduce fluctuations in the trigger voltage due to manufacturing variations such as the dimensions of each region or the concentration of impurities, as compared with the configuration in which the conduction state is obtained by punch-through as in Patent Document 1. Further, the voltage value of the trigger voltage can be set according to the configuration of the trigger circuit 14 that generates the trigger voltage. As a result, when the trigger voltage is changed, it is not necessary to change the dose amount of impurities in each region, and the manufacturing cost can be reduced as compared with the configuration described in Patent Document 1. Here, the fifth region 25 is provided in the silicon layer 20c in contact with the third region 23 in a plan view, is composed of N-type silicon which is the same conductive type as the third region 23, and is more than the third region 23. High concentration of impurities. Therefore, the trigger voltage can be suitably supplied from the contact 33 to the third region 23 via the fifth region 25.

In the present embodiment, since the fifth region 25 is in contact with the third region 23, the electrostatic protection circuit 10 having an N-gate type thyristor structure can be realized. Further, the third region 23 is provided along the outer circumference of the fifth region 25 in a plan view. Therefore, there is an advantage that it is easy to make the potential uniform in the third region 23 as compared with the configuration in which the fifth region 25 is in contact with the outer periphery of the third region 23.

B2. Second Embodiment Next, the second embodiment will be described. The present embodiment is the same as the above-described first embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different and the connection form of each part in the electrostatic protection circuit is different accordingly. In the following description, the second embodiment will be described mainly on the differences from the first embodiment described above, and the same matters will be omitted. Further, in the figure used for the description of the second embodiment, the same reference numerals are given to the same configurations as those of the first embodiment described above.

FIG. 5 is a diagram showing the static electricity protection circuit 10A according to the second embodiment. As shown in FIG. 5, the electrostatic protection circuit 10A includes a diode 11, a thyristor 12A, a resistor 13, and a trigger circuit 14A.

The thyristor 12A has a transistor QA12 which is a PNP bipolar transistor and a transistor QC12 which is an NPN bipolar transistor, like the thyristor 12 of the first embodiment described above, and these are connected to each other. However, in the present embodiment, the base of the transistor QC12 constitutes the gate G2 of the thyristor 12A and is connected to the node N2 via the resistor 13. The emitter of the transistor QA12 is connected to the node N1.

The trigger circuit 14A is composed of a GGnMOS type transistor QN14 as in the trigger circuit 14 of the first embodiment described above. However, the source and gate of the transistor QN14 are connected to the gate G2 of the thyristor 12A. The drain of the transistor QN14 is connected to the node N1.

FIG. 6 is a plan view of the thyristor 12A included in the electrostatic protection circuit 10A according to the second embodiment. FIG. 7 is a cross-sectional view taken along the line A7-A7 in FIG. The thyristor 12A is a P-gate type thyristor. The first embodiment, except that the thyristor 12A has a third region 23A, a fourth region 24A, and a sixth region 26 in place of the third region 23, the fourth region 24, and the fifth region 25 of the first embodiment. It is the same as the thyristor 12 of. The sixth region 26 of the present embodiment has been given a different name from the "fifth region 25" as the "sixth region 26" in order to avoid confusion with the fifth region 25 of the first embodiment. However, it corresponds to the "fifth area" according to claim 1.

In the present embodiment, the first region 21, the third region 23A, the fourth region 24A, and the second region 22 are arranged side by side in this order from the left side to the right side in FIG. 6, of which 2 are adjacent to each other. The two areas come into contact with each other. Here, the fourth region 24A has a frame shape in a plan view of the SOI substrate 20 when viewed from the thickness direction, and inside the fourth region 24A, the sixth region 26 contacts the fourth region 24A. Is placed. Therefore, in the cross section shown in FIG. 7, from the left side to the right side in FIG. 7, the first region 21, the third region 23A, the fourth region 24A, the sixth region 26, the fourth region 24A, and the second region 22 are the same. They are arranged side by side in order. The sixth region 26 has a second contact region 26a in contact with the fourth region 24A. The second contact region 26a is a region or a portion of the sixth region 26 that contacts the fourth region 24A, and is provided over the entire circumference of the outer edge of the sixth region 26 in a plan view.

The third region 23A is a low-concentration N-N-type region composed of N-type silicon. The fourth region 24A is a low-concentration P-P-type region composed of P-type silicon. The sixth region 26 is a high-concentration P + P-type region composed of P-type silicon. A contact 34 is provided in the sixth region 26. The contact 34 is a part of wiring such as metal or a conductor post arranged in a contact hole provided in an insulating film (not shown), and is connected to the resistor 13 and the trigger circuit 14 via a wiring (not shown).

As described above, since the sixth region 26 is in contact with the fourth region 24A, it is possible to realize the electrostatic protection circuit 10A having a P-gate type thyristor structure. The static electricity protection circuit 10A described above also has the same effect as the static electricity protection circuit 10 of the first embodiment described above. Further, in the present embodiment, the fourth region 24A is provided along the outer circumference of the sixth region 26 in a plan view. Therefore, there is an advantage that it is easy to make the potential uniform in the fourth region 24A as compared with the configuration in which the sixth region 26 is in contact with the outer periphery of the fourth region 24A.

B3. Third Embodiment Next, the third embodiment will be described. This embodiment is the same as the above-described first embodiment or second embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different and the connection form of each part in the electrostatic protection circuit is different accordingly. In the following description, the third embodiment will be mainly described as being different from the above-mentioned first and second embodiments, and the same matters will be omitted. Further, in the figure used for the description of the third embodiment, the same reference numerals are given to the same configurations as those of the first embodiment or the second embodiment described above.

FIG. 8 is a diagram showing the static electricity protection circuit 10B according to the third embodiment. As shown in FIG. 12, the electrostatic protection circuit 10B includes a diode 11, a thyristor 12B, a resistor 13, a trigger circuit 14, and a resistor 15.

The thyristor 12B has a transistor QA12 which is a PNP bipolar transistor and a transistor QC12 which is an NPN bipolar transistor, like the thyristor 12 of the first embodiment described above, and these are connected to each other. However, in the present embodiment, the base of the transistor QC12 constitutes the gate G2 of the thyristor 12B and is connected to the node N2 via the resistor 15. The resistor 15 functions as a base resistor for the transistor QC12. With this function, the effect of reducing the malfunction of the thyristor 12B due to external noise can be obtained.

FIG. 9 is a plan view of the thyristor 12B included in the electrostatic protection circuit 10B according to the third embodiment. FIG. 10 is a cross-sectional view taken along the line A10-A10 in FIG. The thyristor 12B is the same as the thyristor 12 of the first embodiment except that it has the fourth region 24A and the sixth region 26 of the second embodiment instead of the fourth region 24 of the first embodiment.

In the above electrostatic protection circuit 10B, as in the first embodiment described above, the fifth region 25 has a first contact region 25a in contact with only the third region 23, and the third region 23 is the fifth in a plan view. It is provided along the outer circumference of the region 25. The fifth region 25 is connected to a contact 33, which is an electrode arranged so as to overlap the fifth region 25 in a plan view. A trigger voltage for passing a current from the first region 21 to the second region 22 via the third region 23 and the fourth region 24 is supplied to the contact 33. Further, in the electrostatic protection circuit 10B of the present embodiment, as in the second embodiment described above, the sixth region 26 has a second contact region 26a that contacts only the fourth region 24A, and the fourth region 24B is a flat surface. It is visually provided along the outer circumference of the sixth region 26. The sixth region 26 is connected to a contact 34, which is an electrode arranged so as to overlap the sixth region 26 in a plan view. A trigger voltage for passing a current from the first region 21 to the second region 22 via the third region 23 and the fourth region 24 is supplied to the contact 34. As described above, it is possible to realize the electrostatic protection circuit 10B having a thyristor structure that can be used for both the P gate type and the N gate type. In this embodiment, the effects of both the above-mentioned first embodiment and the second embodiment can be obtained.

B4. Fourth Embodiment Next, the fourth embodiment will be described. This embodiment is the same as the above-described first embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the fourth embodiment will be described mainly on the differences from the first embodiment described above, and the same matters will be omitted. Further, in the figure used for the description of the fourth embodiment, the same reference numerals are given to the same configurations as those of the first embodiment described above.

FIG. 11 is a plan view of the thyristor 12C included in the electrostatic protection circuit 10C according to the fourth embodiment. FIG. 12 is a cross-sectional view taken along the line A12-A12 in FIG. The thyristor 12C is the same as the thyristor 12 of the first embodiment except that it has a third region 23C and a fifth region 25C in place of the third region 23 and the fifth region 25 of the first embodiment.

In the present embodiment, the fifth region 25C, the first region 21, the third region 23C, the fourth region 24, and the second region 22 are arranged side by side in this order from the left side to the right side in FIG. , Two regions adjacent to each other are in contact with each other. Here, the third region 23C and the fifth region 25C come into contact with each other in a plan view to form a frame shape surrounding the first region 21. In FIG. 11, the third region 23C has a shape having a pair of portions extending toward the fifth region 25C in a plan view. Further, the fifth region 25C has a pair of portions connected to the pair of portions of the third region 23C in a plan view. Therefore, the fifth region 25C has a pair of first contact regions 25b in contact with the third region 23C. Here, the first contact region 25b is provided at a position that does not overlap with the first region 21 in a plan view.

The third region 23C is a low-concentration N-type region composed of N-type silicon. The fifth region 25C is a high-concentration N-type region composed of N-type silicon. A contact 33 is provided in the fifth region 25C.

The static electricity protection circuit 10C described above also has the same effect as the static electricity protection circuit 10 of the first embodiment described above. Further, in the present embodiment, the first region 21 is provided between the third region 23C and the fifth region 25C in a plan view. Therefore, the area of the third region 23A in a plan view can be reduced as compared with the case where the third region 23 is provided along the outer circumference of the fifth region 25 as in the first embodiment. As a result, there is an advantage that the on-resistance of the thyristor 12A can be lowered as compared with the thyristor 12 of the first embodiment.

B5. Fifth Embodiment Next, the fifth embodiment will be described. This embodiment is the same as the above-described second embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the fifth embodiment will be described mainly on the differences between the first and fourth embodiments described above, and the same matters will be omitted. Further, in the drawings used for the description of the fifth embodiment, the same reference numerals are given to the same configurations as those of the first to fourth embodiments described above.

FIG. 13 is a plan view of the thyristor 12D included in the electrostatic protection circuit 10D according to the fifth embodiment. FIG. 14 is a cross-sectional view taken along the line A14-A14 in FIG. The thyristor 12D is the same as the thyristor 12A of the second embodiment except that it has a fourth region 24A and a sixth region 26D in place of the fourth region 24A and the sixth region 26 of the second embodiment. The sixth region 26D of the present embodiment has been given a different name from the "fifth region 25C" as the "sixth region 26D" in order to avoid confusion with the fifth region 25C of the fourth embodiment. However, it corresponds to the "fifth area" according to claim 1.

In the present embodiment, the first region 21, the third region 23A, the fourth region 24D, the second region 22 and the sixth region 26D are arranged side by side in this order from the left side to the right side in FIG. , Two regions adjacent to each other are in contact with each other. Here, the fourth region 24D and the sixth region 26D are in contact with each other in a plan view to form a frame shape surrounding the first region 21. In FIG. 13, the fourth region 24D has a longitudinal shape in a plan view and has a pair of portions extending from both ends thereof toward the sixth region 26D. Further, the sixth region 26D has a pair of portions connected to the above-mentioned pair of portions of the fourth region 24D in a plan view. Therefore, the sixth region 26D has a pair of second contact regions 26b in contact with the fourth region 24D. Here, the second contact region 26b is provided at a position that does not overlap with the second region 22 in a plan view.

The fourth region 24D is a low-concentration P-type region composed of P-type silicon. The sixth region 26D is a high-concentration P-type region composed of P-type silicon. A contact 34 is provided in the sixth region 26D.

The static electricity protection circuit 10D described above also has the same effect as the static electricity protection circuit 10A of the second embodiment described above. Further, in the present embodiment, the second region 22 is provided between the fourth region 24D and the sixth region 26D in a plan view. Therefore, the area of the fourth region 24D in a plan view can be reduced as compared with the case where the fourth region 24A is provided along the outer circumference of the sixth region 26 as in the second embodiment. As a result, there is an advantage that the on-resistance of the thyristor 12D can be lowered as compared with the thyristor 12A of the second embodiment.

B6. Sixth Embodiment Next, the sixth embodiment will be described. This embodiment is the same as the above-described third embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the sixth embodiment will be described mainly on the differences from the first to fifth embodiments described above, and the same matters will be omitted. Further, in the figure used for the explanation of the sixth embodiment, the same reference numerals are given to the same configurations as those of the first to fifth embodiments described above.

FIG. 15 is a plan view of the thyristor 12E included in the electrostatic protection circuit 10E according to the sixth embodiment. FIG. 16 is a cross-sectional view taken along the line A16-A16 in FIG. The thyristor 12E is the same as the thyristor 12C of the fourth embodiment except that it has the fourth region 24D and the sixth region 26D of the fifth embodiment instead of the fourth region 24 of the fourth embodiment.

In the above electrostatic protection circuit 10E, as in the fourth embodiment described above, the fifth region 25C has the first contact region 25b in contact with only the third region 23C, and the first region 21 is the third region 21 in a plan view. It is provided between the area 23C and the fifth area 25C. Further, in the electrostatic protection circuit 10E of the present embodiment, as in the fifth embodiment described above, the sixth region 26D has a second contact region 26b that contacts only the fourth region 24D, and the second region 22 is a flat surface. It is visually provided between the fourth region 24D and the sixth region 26D. Therefore, it is possible to realize the electrostatic protection circuit 10E having a thyristor structure that can be used for both the P-gate type and the N-gate type. In this embodiment, the effects of both the fourth and fifth embodiments described above can be obtained.

B7. Seventh Embodiment Next, the seventh embodiment will be described. This embodiment is the same as the above-described third embodiment or sixth embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the seventh embodiment will be mainly described with respect to the differences between the third embodiment and the sixth embodiment described above, and the same matters will be omitted. Further, in the figure used for the description of the seventh embodiment, the same reference numerals are given to the same configurations as those of the third embodiment or the sixth embodiment described above.

FIG. 17 is a plan view of the thyristor 12F included in the electrostatic protection circuit 10F according to the seventh embodiment. FIG. 18 is a cross-sectional view taken along the line A18-A18 in FIG. The thyristor 12F has a configuration in which two thyristors 12E of the sixth embodiment described above are combined. Specifically, the thyristor 12F has a pair of first region 21, a pair of second region 22, a pair of third region 23C, a pair of fourth region 24F, a pair of fifth region 25C, and a third region. It has 6 regions 26F. Here, the sixth region 26F is arranged between a pair of fifth regions 25C. Then, between each of the fifth region 25C and the sixth region 26F, the second region 22, the fourth region 24F, the third region 23C, and the third region 23C are directed from the sixth region 26F side to the fifth region 25C side. One area 21 is arranged side by side in this order. Two adjacent regions of these regions are in contact with each other.

Each of the pair of fourth regions 24F has a longitudinal shape in a plan view. It has a pair of portions extending from both ends toward the sixth region 26F. Further, the sixth region 26F has a pair of portions connected to the pair of portions of each fourth region 24F in a plan view. In the present embodiment, the pair of portions of the pair of fourth regions 24F come into contact with each other. Therefore, the pair of fourth regions 24F are in contact with each other in a plan view and form a frame shape surrounding the pair of second regions 22 and sixth regions 26F. Therefore, the sixth region 26F has a pair of second contact regions 26c in contact with the fourth region 24F. Here, the second contact region 26c is provided at a position that does not overlap with the second region 22 in a plan view. It can be said that the pair of the fourth region 24F is one frame-shaped fourth region 24F. Further, the pair of portions of the fourth region 24F may be connected to each other via the sixth region 26F.

The fourth region 24F is a low-concentration P-type region composed of P-type silicon. The sixth region 26F is a high-concentration P-type region composed of P-type silicon. A contact 34 is provided in the sixth region 26F.

In the above electrostatic protection circuit 10F, a pair of the fifth region 25C is provided, a pair of the first region 21 is provided between a pair of the fifth region 25C in a plan view, and a third region 23C is provided in a plane view. A pair of first regions 21 are provided, a pair of fourth regions 24F are provided between a pair of third regions 23C in a plan view, and a pair of fourth regions 22 are provided in a plan view. A pair is provided between the regions 24F, and a sixth region 26F is provided between the pair of second regions 22 in a plan view. Here, when a pair of the fourth region 24F is regarded as a frame-shaped fourth region 24F in a plan view, a pair of the second region 22 is provided inside the fourth region 24F in a plan view, and the sixth region 26F is provided. Can be said to be provided between a pair of second regions 22 inside the fourth region 24F in a plan view. With the above pair of first region 21, pair of second region 22, pair of third region 23C, pair of fourth region 24F, pair of fifth region 25C and sixth region 26F, two It is possible to realize an electrostatic protection circuit 10F having a structure in which thyristor structures are connected in parallel. This structure is centered on the sixth region 26F in a plan view.
The structure may be such that the second region 22, the fourth region 24F, the third region 23C, the first region 21, and the fifth region 25C are arranged in pairs on both sides thereof. Here, when a structure in which two thyristor structures are connected in parallel is adopted, the length along the direction perpendicular to the direction in which these regions are arranged in a plan view is reduced as compared with the case where one thyristor structure is adopted. Can be done. Further, since the sixth region 26F is shared by the two thyristor structures, the area of the entire thyristor structure in a plan view should be smaller than that in the case where the sixth region 26F is provided separately for each of the two thyristor structures. Can be done. Further, since the sixth region 26F is shared by the two thyristor structures, there is an advantage that the wiring of the P gate can be easily routed. In the present embodiment, the contact 33 is the first electrode arranged so as to overlap the fifth region 25C in the plan view, and the contact 34 is the second electrode arranged so as to overlap the sixth region 26F in the plan view. .. A trigger voltage for passing a current from the first region 21 to the second region 22 via the third region 23C and the fourth region 24F is supplied to the contact 33 or 34.

B8. Eighth Embodiment Next, the eighth embodiment will be described. This embodiment is the same as the above-described third embodiment or sixth embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the eighth embodiment will be mainly described with respect to the differences between the third embodiment and the sixth embodiment described above, and the same matters will be omitted. Further, in the figure used for the description of the eighth embodiment, the same reference numerals are given to the same configurations as those of the third embodiment or the sixth embodiment described above.

FIG. 19 is a plan view of the thyristor 12G included in the electrostatic protection circuit 10G according to the eighth embodiment. FIG. 20 is a cross-sectional view taken along the line A20-A20 in FIG. The thyristor 12G has a configuration in which two thyristors 12E of the sixth embodiment described above are combined. Specifically, the thyristor 12G has a pair of the first region 21, a pair of the second region 22, a pair of the third region 23G, a pair of the fourth region 24D, and a pair of the fifth region 25G. It has 6 regions 26D. Here, the fifth region 25G is arranged between a pair of sixth regions 26D. Then, between the 5th region 25G and each 6th region 26D, from the 5th region 25G side to each 6th region 26D side, the first region 21, the third region 23G, the fourth region 24D and the third region 26D. The two regions 22 are arranged side by side in this order. Two adjacent regions of these regions are in contact with each other.

Each of the pair of third regions 23G has a longitudinal shape in plan view and has a pair of portions extending from both ends thereof toward the fifth region 25G. Further, the fifth region 25G has a pair of portions connected to the pair of portions of each third region 23G in a plan view. In the present embodiment, the pair of portions of the pair of third regions 23G come into contact with each other. Therefore, the pair of third regions 23G are in contact with each other in a plan view and form a frame shape surrounding the pair of first region 21 and fifth region 25G. Therefore, the fifth region 25G has a pair of first contact regions 25c in contact with the third region 23G. Here, the first contact region 25c is provided at a position that does not overlap with the first region 21 in a plan view. It can be said that the pair of the third region 23G is one frame-shaped third region 23G. Further, the above-mentioned pair of portions of the pair of the third region 23G may be connected to each other via the fifth region 25G.

The third region 23G is a low-concentration N-type region composed of N-type silicon. The fifth region 25G is a high-concentration N-type region composed of N-type silicon. A contact 33 is provided in the fifth region 25G.

In the above electrostatic protection circuit 10G, a pair of sixth regions 26D are provided, a pair of second regions 22 are provided between a pair of sixth regions 26D in plan view, and a pair of fourth region 24D is provided in plan view. A pair is provided between the pair of second regions 22, a pair of third regions 23G is provided between a pair of fourth regions 24D in plan view, and a pair of third regions 21 are provided in plan view. A pair is provided between the regions 23G, and a fifth region 25G is provided between the pair of first regions 21 in a plan view. With the above pair of first region 21, pair of second region 22, pair of third region 23G, pair of fourth region 24D, pair of fifth region 25G and sixth region 26D, two It is possible to realize an electrostatic protection circuit 10G having a structure in which thyristor structures are connected in parallel. In this structure, the fifth region 25G is centered in a plan view, and the first region 21, the third region 23G, the fourth region 24D, the second region 22, and the sixth region 26D are arranged in pairs on both sides thereof. It may be a structure that has been constructed. Here, when a structure in which two thyristor structures are connected in parallel is adopted, the length along the direction perpendicular to the direction in which these regions are arranged in a plan view is reduced as compared with the case where one thyristor structure is adopted. Can be done. Further, since the fifth region 25G is shared by the two thyristor structures, the area of the entire thyristor structure in a plan view should be smaller than that in the case where the fifth region 25G is provided separately for each of the two thyristor structures. Can be done. Further, since the fifth region 25G is shared by the two thyristor structures, there is an advantage that the wiring of the N gate can be easily routed.

B9. Ninth Embodiment Next, the ninth embodiment will be described. This embodiment is the same as the above-described first embodiment or seventh embodiment except that the configuration of the thyristor included in the electrostatic protection circuit is different. In the following description, the ninth embodiment will be mainly described as being different from the above-mentioned first and seventh embodiments, and the same matters will be omitted. Further, in the figure used for the description of the ninth embodiment, the same reference numerals are given to the same configurations as those of the first embodiment or the seventh embodiment described above.

FIG. 21 is a plan view of the thyristor 12H included in the electrostatic protection circuit 10H according to the ninth embodiment. FIG. 22 is a cross-sectional view taken along the line A22-A22 in FIG. The thyristor 12H has a simplified configuration of the thyristor 12F of the seventh embodiment described above. Specifically, the thyristor 12H has a pair of first region 21, a second region 22, a pair of third region 23H, a pair of fourth region 24H, two pairs of fifth region 25H, and a pair of first regions. It has 6 regions 26H. Here, the second region 22 is arranged between a pair of first regions 21. Then, between each of the first region 21 and the second region 22, the fourth region 24H and the third region 23H are arranged side by side in this order from the second region 22 side to the first region 21 side. Will be done. Two adjacent regions of these regions are in contact with each other.

Each of the pair of third regions 23H has a longitudinal shape in plan view and has a pair of portions extending from both ends thereof toward the opposite side of the second region 22. An island-shaped fifth region 25H is connected to each of the pair of portions. Therefore, each fifth region 25H has a first contact region 25d in contact with the third region 23H. Here, the first contact region 25d is provided at a position that does not overlap with the first region 21 in a plan view. The third region 23H is a low-concentration P-type region composed of P-type silicon. The fifth region 25H is a high-concentration P-type region composed of P-type silicon. A contact 33 is provided in each fifth region 25H. It is sufficient that the contact 33 is provided in one of the pair of the fifth region 25H connected to the same third region 23H, but by providing the contact 33 in both of the pair of the fifth region 25H. , The potential of the third region 23H can be stabilized.

Each of the pair of the fourth regions 24H has a longitudinal shape in a plan view, and has a pair of portions extending from both ends thereof toward the second region 22 side. An island-shaped pair of sixth regions 26H is connected to the pair of fourth regions 24H between the pair of portions. Therefore, the pair of the fourth region 24H and the pair of the sixth region 26H form a frame shape surrounding the second region 22 in a plan view. In addition, each sixth region 26H has a pair of second contact regions 26d in contact with a pair of fourth regions 24H. Here, the second contact region 26d is provided at a position that does not overlap with the second region 22 in a plan view. The fourth region 24H is a low-concentration N-type region composed of N-type silicon. The sixth region 26H is a high-concentration N-type region composed of N-type silicon. A contact 34 is provided in each sixth region 26H. It is sufficient that the contact 34 is provided in one of the pair of the sixth region 26H, but the potential of the fourth region 24H is stabilized by providing the contact 34 in both of the pair of the sixth region 26H. Can be done.

The static electricity protection circuit 10H described above also has the same effect as that of the seventh or eighth embodiment described above. Further, the electrostatic protection circuit 10H of the present embodiment has an advantage that it can be downsized as compared with the configuration of the seventh embodiment or the eighth embodiment.

B10. Tenth Embodiment Next, the tenth embodiment will be described. This embodiment is the same as the above-described first embodiment except that the configuration of the trigger circuit in the electrostatic protection circuit is different. In the following description, the tenth embodiment will be mainly described with respect to the differences from the first embodiment described above, and the same matters will be omitted. Further, in the figure used for explaining the tenth embodiment, the same reference numerals are given to the same configurations as those of the first embodiment described above.

FIG. 23 is a diagram showing the static electricity protection circuit 10I according to the tenth embodiment. As shown in FIG. 23, the electrostatic protection circuit 10I includes a diode 11, a thyristor 12, a resistor 13, and a trigger circuit 14I.

The trigger circuit 14I is composed of an SGpMOS type transistor QP14. Here, the source and gate of the transistor QP14 are connected to the gate G1 of the thyristor 12. The drain of the transistor QP14 is connected to the node N2. The static electricity protection circuit 10I described above also has the same effect as that of the first embodiment described above.

B11. Eleventh Embodiment Next, the eleventh embodiment will be described. This embodiment is the same as the above-described first embodiment except that the configuration of the trigger circuit in the electrostatic protection circuit is different. In the following description, the eleventh embodiment will be mainly described with respect to the differences from the first embodiment described above, and the same matters will be omitted. Further, in the figure used for the explanation of the eleventh embodiment, the same reference numerals are given to the same configurations as those of the first embodiment described above.

FIG. 24 is a diagram showing the static electricity protection circuit 10J according to the eleventh embodiment. As shown in FIG. 24, the electrostatic protection circuit 10J includes a diode 11, a thyristor 12, a resistor 13, and a trigger circuit 14J.

The trigger circuit 14J is composed of a diode D14. Here, the cathode of the diode D14 is connected to the gate G1 of the thyristor 12. The anode of diode D14 is connected to node N2. The static electricity protection circuit 10J described above also has the same effect as that of the first embodiment described above.

B12. 12th Embodiment Next, the 12th embodiment will be described. This embodiment is the same as the above-described first embodiment except that the configuration of the trigger circuit in the electrostatic protection circuit is different. In the following description, the twelfth embodiment will be mainly described with respect to the differences from the first embodiment described above, and the same matters will be omitted. Further, in the figure used for the explanation of the twelfth embodiment, the same reference numerals are given to the same configurations as those of the first embodiment described above.

FIG. 25 is a diagram showing an electrostatic protection circuit 10K according to the twelfth embodiment. As shown in FIG. 25, the electrostatic protection circuit 10K includes a diode 11, a thyristor 12, a resistor 13, and a trigger circuit 14K.

The trigger circuit 14K has a resistor R14, a capacitor C14, an inverter IV14, and a transistor QN14. The resistor R14 and the capacitor C14 are provided in series between the node N1 and the node N2. The resistor R14 and the capacitor C14 form a time constant circuit of CR. The inverter IV14 has a P-type transistor QP14a and an N-type transistor QN14 provided between the node N1 and the node N2. The gates of the transistors QP14a and QN14b are connected to the connection node between the resistor R14 and the capacitor C14. The source of the transistor QP14a is connected to the node N1. The source of the transistor QN14b is connected to the node N2. The drains of the transistors QP14a and QN14b are connected to the gate of the transistor QN14. In the above trigger circuit 14K, the trigger voltage can be arbitrarily set according to the setting of the resistance value of the resistor 13 or the transistor size of the transistor QN14. The configuration of the inverter IV14 is not limited to the configuration shown in FIG. 25, and may be at least a configuration capable of outputting an inverted signal of the input signal.

FIG. 26 is a graph showing the voltage-current characteristics of the electrostatic protection circuit 10K according to the twelfth embodiment. FIG. 26 shows the voltage-current characteristics when the channel width of the transistor QN14 is changed while the resistance value of the resistor 13 is fixed. Α in FIG. 26 indicates a case where the channel width is 80 μm, β in FIG. 26 indicates a case where the channel width is 50 μm, and γ in FIG. 26 indicates a case where the channel width is 40 μm. A case is shown, and δ in FIG. 26 shows a case where the channel width is 30 μm. As is clear from FIG. 26, the trigger voltage can be lowered by increasing the channel width. At this time, the trigger current, which is the current flowing when the thyristor 12 is operated, remains almost unchanged at, for example, about 50 mA. The trigger current is set according to the resistance value of the resistor 13. Further, as the trigger current becomes larger, there is an advantage that the effect of preventing malfunction due to noise of the thyristor 12 is enhanced. The above-mentioned static electricity protection circuit 10K also has the same effect as that of the above-described first embodiment.

C. Electronic device FIG. 27 is a block diagram showing a configuration example of the electronic device 200. The electronic device 200 has a processor 201, a memory 202, a display device 203, an input device 204, an output device 205, and a communication device 206, and these are connected to each other so as to be communicable with each other. The processor 201 is a device having a function of controlling each part of the electronic device 200 and a function of processing various data. The processor 201 is configured to include, for example, one or more processors such as a CPU (Central Processing Unit). The memory 202 includes various programs executed by the processor 201 and a hard disk drive or a semiconductor memory for storing various data processed by the processor 201. The processor 201 performs various processes by reading a program from the memory 202 and executing the program. The process is appropriately determined according to the use of the electronic device 200.

The display device 203 is a display device including various display panels such as a liquid crystal display panel or an organic EL (electro-luminescence) display panel that displays various images under the control of the processor 201. The input device 204 is configured to include a pointing device such as a touch pad, a touch panel, or a mouse that accepts operations from the user. The output device 205 is an output device such as a speaker. The communication device 206 is a communication device that communicates wirelessly or by wire with another device. The display device 203, the input device 204, the output device 205, or the communication device 206 may be provided as appropriate or may be omitted.

In the above electronic device 200, the semiconductor device or the electrostatic protection circuit of any of the above-described embodiments is provided in any of the elements constituting the electronic device 200. FIG. 27 shows a case where the semiconductor device 100 of the first embodiment is provided in the processor 201. In the above electronic device 200, the internal circuit 104 of the semiconductor device 100 can be stably protected from static electricity, and as a result, the reliability of the electronic device 200 can be improved.

Examples of electronic devices include personal computers, smartphones, digital still cameras, mobile phones, tablet terminals, watches, body posture detectors, pointing devices, head mount displays, inkjet printers, laptop personal computers, televisions, and videos. Cameras, video tape recorders, navigation devices, pagers, electronic notebooks, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, security TV monitors, electronic binoculars, POS (Point of sale system) terminals , Electronic thermometer, blood pressure monitor, blood glucose meter, electrocardiogram measuring device, ultrasonic diagnostic device, electronic endoscope, fish finder, various measuring devices, instruments, flight simulator and the like.

The electrostatic protection circuit, the semiconductor device, and the electronic device of the present invention have been described above based on the illustrated embodiments, but the present invention is not limited thereto. Further, the configuration of each part of the present invention can be replaced with an arbitrary configuration that exhibits the same function as that of the above-described embodiment, or an arbitrary configuration can be added. Further, the present invention may combine arbitrary configurations of the above-described embodiments.

10 ... Static electricity protection circuit, 10A ... Static electricity protection circuit, 10B ... Static electricity protection circuit, 10C ... Static electricity protection circuit, 10D ... Static electricity protection circuit, 10E ... Static electricity protection circuit, 10F ... Static electricity protection circuit, 10G ... Static electricity protection circuit, 10H ... Static electricity protection circuit, 10I ... Static electricity protection circuit, 10J ... Static electricity protection circuit, 10K ... Static electricity protection circuit, 20 ... SOI substrate, 20a ... Substrate, 20b ... Silicon oxide film, 20c ... Silicon layer, 21 ... First region, 22 ... 2nd region, 23 ... 3rd region, 23A ... 3rd region, 23B ... 3rd region, 23G ... 3rd region, 23H ... 3rd region, 24 ... 4th region, 24B ... 4th region, 24C ... 4th region Region, 24F ... 4th region, 24H ... 4th region, 25 ... 5th region, 25A ... 5th region, 25G ... 5th region, 25H ... 5th region, 26 ... 6th region, 26C ... 6th region, 26F ... 6th region, 26H ... 6th region, 33 ... contact, 34 ... contact, 100 ... semiconductor device, 101 ... power supply wiring, 102 ... power supply wiring, 103 ... signal wiring, 104 ... internal circuit, 200 ... electronic equipment.

Claims (11)

An electrostatic protection circuit that protects a circuit using the silicon layer in an SOI substrate in which a substrate made of silicon and a silicon layer made of silicon are bonded via a silicon oxide film from static electricity.
A first region provided on the silicon layer and composed of P-type silicon,
A second region provided in the silicon layer at a position different from the first region in a plan view and composed of N-type silicon, and a second region.
In a plan view, between the first region and the second region, a third region provided on the silicon layer in contact with the first region and composed of N-type silicon, and a third region.
In a plan view, between the second region and the third region, a fourth region provided on the silicon layer in contact with each of the second region and the third region and composed of P-shaped silicon. ,
The silicon layer is provided with a first contact region that is in contact with only one of the third region and the fourth region in a plan view, and is the same conductive P-type or N-type as the one region. It has a fifth region, which is composed of silicon and has a higher concentration of impurities than one of the regions.
The first region is connected to a first wire connected to the circuit.
The second region is connected to a second wire connected to the circuit.
The fifth region is connected to an electrode arranged so as to overlap the fifth region in a plan view.
A trigger voltage for passing a current from the first region to the second region via the third region and the fourth region is supplied to the electrode.
Static electricity protection circuit. The one region is the third region.
The third region is provided along the outer circumference of the fifth region in a plan view.
The electrostatic protection circuit according to claim 1. The one region is the fourth region.
The fourth region is provided along the outer circumference of the fifth region in a plan view.
The electrostatic protection circuit according to claim 1. It has a second contact region that is in contact with only the fourth region in a plan view, is provided on the silicon layer, is composed of P-type silicon, and has a sixth region having a higher concentration of impurities than the fourth region. ,
The sixth region is connected to an electrode arranged so as to overlap the sixth region in a plan view.
A trigger voltage for passing a current from the first region to the second region via the third region and the fourth region is supplied to the electrode.
The fourth region is provided along the outer circumference of the sixth region in a plan view.
The electrostatic protection circuit according to claim 2. The one region is the third region.
The first region is provided between the third region and the fifth region in a plan view.
The first contact region is provided at a position that does not overlap with the first region in a plan view.
The electrostatic protection circuit according to claim 1. The one region is the fourth region.
The second region is provided between the fourth region and the fifth region in a plan view.
The first contact region is provided at a position that does not overlap with the second region in a plan view.
The electrostatic protection circuit according to claim 1. A sixth region having a second contact region in contact with only the fourth region in a plan view, provided in the silicon layer, composed of P-type silicon, and having a higher concentration of impurities than the fourth region. The sixth region is connected to an electrode arranged so as to overlap the sixth region in a plan view.
A trigger voltage for passing a current from the first region to the second region via the third region and the fourth region is supplied to the electrode.
The second region is provided between the fourth region and the sixth region in a plan view.
The second contact region is provided at a position that does not overlap with the second region in a plan view.
The electrostatic protection circuit according to claim 5. A pair of the fifth regions is provided.
A pair of the first regions are provided between the pair of the fifth regions in a plan view.
A pair of the third regions are provided between the pair of the first regions in a plan view.
A pair of the fourth regions are provided between the pair of the third regions in a plan view.
A pair of the second regions are provided between the pair of the fourth regions in a plan view.
The sixth region is provided between the pair of second regions in a plan view.
The electrostatic protection circuit according to claim 7. A pair of the sixth regions is provided.
A pair of the second regions are provided between the pair of the sixth regions in a plan view.
A pair of the fourth regions are provided between the pair of the second regions in a plan view.
A pair of the third regions are provided between the pair of the fourth regions in a plan view.
A pair of the first regions are provided between the pair of third regions in a plan view.
The fifth region is provided between the pair of first regions in a plan view.
The electrostatic protection circuit according to claim 7. The electrostatic protection circuit according to any one of claims 1 to 9.
It has a circuit that is electrically connected to the electrostatic protection circuit.
Semiconductor device. The semiconductor device according to claim 10.
Electronics.

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