JP2020178032A - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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JP2020178032A
JP2020178032A JP2019079157A JP2019079157A JP2020178032A JP 2020178032 A JP2020178032 A JP 2020178032A JP 2019079157 A JP2019079157 A JP 2019079157A JP 2019079157 A JP2019079157 A JP 2019079157A JP 2020178032 A JP2020178032 A JP 2020178032A
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power semiconductor
circuit pattern
semiconductor element
resin
semiconductor module
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JP6736132B1 (en
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昭雄 杉木
Akio Sugiki
昭雄 杉木
誠 梅木
Makoto Umeki
誠 梅木
岡本　卓也
Takuya Okamoto
卓也 岡本
慧 宮澤
Kei Miyazawa
慧 宮澤
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Oita Device Tech Co Ltd
OITA DEVICE TECHNOLOGY CO Ltd
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Oita Device Tech Co Ltd
OITA DEVICE TECHNOLOGY CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

To provide a compact and lightweight power semiconductor module that does not require a large heat dissipation plate.SOLUTION: In a power semiconductor module 1, the lower surface of a power semiconductor element 4 is die-bonded to a circuit pattern 3 of a substrate 2 by metal particle sintering bonding, and the circuit pattern 3 and the upper surface of the power semiconductor element 4 are connected by ultrasonic wire bonding, and a terminal 7 is connected to the circuit pattern 3 to seal all connection portion with a resin 8. A circuit pattern 9 on the lower surface of the substrate 2 located directly below the power semiconductor element 4 is exposed from the resin 8. All connection portions of the power semiconductor module 1 have a melting point higher than the glass transition point of the sealing resin 8.SELECTED DRAWING: Figure 1

Description

本発明は、パワー半導体素子を基板に実装するとともに樹脂で封止した構造のパワー半導体モジュールに関するものである。 The present invention relates to a power semiconductor module having a structure in which a power semiconductor element is mounted on a substrate and sealed with a resin.

従来より、電力制御等に大電流を流すことができる電子部品としてパワー半導体モジュールが広く利用されている。 Conventionally, power semiconductor modules have been widely used as electronic components capable of passing a large current for power control and the like.

このパワー半導体モジュールの一例として、パワー半導体素子を基板に実装するとともに樹脂で封止した構造のものが知られている（たとえば、特許文献１参照。）。このパワー半導体モジュールでは、内部の接続にはんだを用い、放熱板を設けて放熱を行う構成となっている。 As an example of this power semiconductor module, one in which a power semiconductor element is mounted on a substrate and sealed with a resin is known (see, for example, Patent Document 1). In this power semiconductor module, solder is used for internal connection, and a heat radiating plate is provided to dissipate heat.

特開２００４−１６５４０６号公報Japanese Unexamined Patent Publication No. 2004-165406

上記従来のパワー半導体モジュールでは、内部の接続に封止する樹脂よりも融点が低いはんだを用いているために、稼働時に大電流が内部を流れることで発生した多大な熱によって内部のはんだが溶出して接続部分が破断するおそれがあった。 Since the conventional power semiconductor module uses solder having a melting point lower than that of the resin sealed in the internal connection, the internal solder elutes due to the large amount of heat generated by the large current flowing inside during operation. There was a risk that the connection part would break.

そのため、上記従来のパワー半導体モジュールでは、より多くの熱を放射することができるように大型の放熱板を設ける必要があり、大型で重量なものとなっていた。 Therefore, in the above-mentioned conventional power semiconductor module, it is necessary to provide a large heat radiating plate so that more heat can be radiated, which is large and heavy.

そこで、請求項１に係る本発明では、基板の回路パターンにパワー半導体素子の下面をダイボンディングで接続するとともに、回路パターンとパワー半導体素子の上面とをワイヤーボンディングで接続し、回路パターンに端子を接続し、全ての接続部分を樹脂で封止したパワー半導体モジュールにおいて、前記全ての接続部分が、封止する樹脂のガラス転移点よりも高い融点を有することにした。 Therefore, in the present invention according to claim 1, the lower surface of the power semiconductor element is connected to the circuit pattern of the substrate by die bonding, the circuit pattern and the upper surface of the power semiconductor element are connected by wire bonding, and terminals are attached to the circuit pattern. In a power semiconductor module that is connected and all the connecting portions are sealed with a resin, all the connecting portions have a melting point higher than the glass transition point of the sealing resin.

また、請求項２に係る本発明では、前記請求項１に係る本発明において、前記基板の上面の回路パターンにパワー半導体素子を実装するとともに、パワー半導体素子の直下方に位置する基板の下面の回路パターンを樹脂から露出させることにした。 Further, in the present invention according to claim 2, in the present invention according to claim 1, the power semiconductor element is mounted on the circuit pattern on the upper surface of the substrate, and the lower surface of the substrate located directly below the power semiconductor element is mounted. I decided to expose the circuit pattern from the resin.

また、請求項３に係る本発明では、前記請求項１又は請求項２に係る本発明において、前記回路パターンとパワー半導体素子の下面とを金属粒子焼成結合により接続するとともに、前記回路パターンとパワー半導体素子の上面及び端子とを超音波接合により接続することにした。 Further, in the present invention according to claim 3, in the present invention according to claim 1 or 2, the circuit pattern and the lower surface of the power semiconductor element are connected by metal particle firing coupling, and the circuit pattern and power are connected. We decided to connect the upper surface of the semiconductor element and the terminals by ultrasonic bonding.

そして、本発明では、以下に記載する効果を奏する。 Then, in the present invention, the effects described below are obtained.

すなわち、本発明では、基板の回路パターンにパワー半導体素子の下面をダイボンディングで接続するとともに、回路パターンとパワー半導体素子の上面とをワイヤーボンディングで接続し、回路パターンに端子を接続し、全ての接続部分を樹脂で封止したパワー半導体モジュールにおいて、前記全ての接続部分が、封止する樹脂のガラス転移点よりも高い融点を有することにしているために、大型の放熱板を設ける必要がなくなり、パワー半導体モジュールの小型軽量化を図ることができる。 That is, in the present invention, the lower surface of the power semiconductor element is connected to the circuit pattern of the substrate by die bonding, the circuit pattern and the upper surface of the power semiconductor element are connected by wire bonding, and the terminals are connected to the circuit pattern. In a power semiconductor module in which the connection portion is sealed with a resin, since all the connection portions have a melting point higher than the glass transition point of the resin to be sealed, it is not necessary to provide a large heat dissipation plate. , It is possible to reduce the size and weight of the power semiconductor module.

本発明に係るパワー半導体モジュールを示す断面模式図。The sectional view which shows the power semiconductor module which concerns on this invention. 同製造工程を示す説明図。Explanatory drawing which shows the manufacturing process.

以下に、本発明に係るパワー半導体モジュールの具体的な構成について図面を参照しながら説明する。 The specific configuration of the power semiconductor module according to the present invention will be described below with reference to the drawings.

図１に示すように、パワー半導体モジュール１は、基板２の上面の回路パターン３にパワー半導体素子４の下面をダイアタッチ材５を用いてダイボンディングで接続するとともに、回路パターン３とパワー半導体素子４の上面とをワイヤー６を用いてワイヤーボンディングで接続し、さらに、回路パターン３に端子７を接続し、全ての接続部分を樹脂８で封止している。 As shown in FIG. 1, in the power semiconductor module 1, the lower surface of the power semiconductor element 4 is connected to the circuit pattern 3 on the upper surface of the substrate 2 by die bonding using a die attachment material 5, and the circuit pattern 3 and the power semiconductor element are connected to each other by die bonding. The upper surface of 4 is connected by wire bonding using a wire 6, the terminal 7 is connected to the circuit pattern 3, and all the connecting portions are sealed with resin 8.

このパワー半導体モジュール１では、基板２の上面の回路パターン３にパワー半導体素子４を実装するとともに、パワー半導体素子４の直下方に位置する基板２の下面の回路パターン９を封止した樹脂８から外部に露出させている。 In this power semiconductor module 1, the power semiconductor element 4 is mounted on the circuit pattern 3 on the upper surface of the substrate 2, and the circuit pattern 9 on the lower surface of the substrate 2 located immediately below the power semiconductor element 4 is sealed from the resin 8. It is exposed to the outside.

ここで、基板２は、セラミックス板製で表面（上面及び下面）に銅からなる回路パターン3,9を形成している。 Here, the substrate 2 is made of a ceramic plate, and circuit patterns 3 and 9 made of copper are formed on the surface (upper surface and lower surface).

回路パターン３は、パワー半導体素子４と端子７とを電気的に接続する所要形状の配線パターンを形成している。 The circuit pattern 3 forms a wiring pattern having a required shape that electrically connects the power semiconductor element 4 and the terminal 7.

パワー半導体素子４は、化合物系パワーデバイス等の大電流を流すことができ電力制御に用いられる半導体素子であり、下面にダイボンディング用の電極が形成されるとともに、上面にワイヤーボンディング用の電極が形成されている。 The power semiconductor element 4 is a semiconductor element that can pass a large current such as a compound power device and is used for power control. An electrode for die bonding is formed on the lower surface and an electrode for wire bonding is formed on the upper surface. It is formed.

ダイアタッチ材５は、回路パターン３とパワー半導体素子４とを金属粒子焼成結合させており、ここでは、銅ナノ粒子を用いている。 In the die attach material 5, the circuit pattern 3 and the power semiconductor element 4 are fired and bonded to each other, and copper nanoparticles are used here.

ワイヤー６は、アルミ細線製で端子７が接続される回路パターン３とパワー半導体素子４とを超音波接合（溶接）によって接続している。 The wire 6 is made of thin aluminum wire and connects the circuit pattern 3 to which the terminal 7 is connected and the power semiconductor element 4 by ultrasonic bonding (welding).

端子７は、銅板製のリードフレーム10を樹脂８で封止した後に所定形状に切断して形成しており、回路パターン３に超音波接合（溶接）によって接続している。 The terminal 7 is formed by sealing a lead frame 10 made of a copper plate with a resin 8 and then cutting it into a predetermined shape, and is connected to the circuit pattern 3 by ultrasonic bonding (welding).

樹脂８は、シリコン系封止材やエポキシ系封止材などを用いることができるが、耐熱性を向上させるためにガラス転移点（ガラス転移温度）が高いものが望ましい。 As the resin 8, a silicon-based encapsulant, an epoxy-based encapsulant, or the like can be used, but one having a high glass transition point (glass transition temperature) is desirable in order to improve heat resistance.

回路パターン９は、稼働時に発生するパワー半導体素子４の熱を放射するために基板２の下面に全体的に形成している。 The circuit pattern 9 is formed as a whole on the lower surface of the substrate 2 in order to radiate the heat of the power semiconductor element 4 generated during operation.

パワー半導体モジュール１は、以上に説明したように構成している。 The power semiconductor module 1 is configured as described above.

特に、上記パワー半導体モジュール１では、回路パターン３とパワー半導体素子４の下面との接続部分、及び、回路パターン３とパワー半導体素子４の上面との接続部分、並びに、回路パターン３と端子７との接続部分が、封止する樹脂８のガラス転移点よりも高い融点を有するようにしている。 In particular, in the power semiconductor module 1, the connection portion between the circuit pattern 3 and the lower surface of the power semiconductor element 4, the connection portion between the circuit pattern 3 and the upper surface of the power semiconductor element 4, and the circuit pattern 3 and the terminal 7 The connection portion of the resin 8 has a melting point higher than the glass transition point of the sealing resin 8.

そのため、上記構成のパワー半導体モジュール１では、封止材よりも先に内部の接続が溶断等することが無く、これにより、大型の放熱板を設ける必要もなくなり、パワー半導体モジュール１の小型軽量化を図ることができ、高耐熱性で高信頼性のパワー半導体モジュール１とすることができる。 Therefore, in the power semiconductor module 1 having the above configuration, the internal connection is not blown before the sealing material, which eliminates the need to provide a large heat radiating plate and reduces the size and weight of the power semiconductor module 1. It is possible to obtain a power semiconductor module 1 having high heat resistance and high reliability.

このパワー半導体モジュール１は、以下に説明するようにして製造することができる。 The power semiconductor module 1 can be manufactured as described below.

まず、図２（ａ）に示すように、基板２の上面及び下面に所要形状の回路パターン3,9を形成する。 First, as shown in FIG. 2A, circuit patterns 3 and 9 having a required shape are formed on the upper surface and the lower surface of the substrate 2.

次に、図２（ｂ）に示すように、基板２の上面の回路パターン３の所定位置にダイアタッチ材５を塗布するとともにパワー半導体素子４を載置し、回路パターン３とパワー半導体素子４の下面の電極とを金属粒子焼成結合する。 Next, as shown in FIG. 2B, the die attach material 5 is applied to a predetermined position of the circuit pattern 3 on the upper surface of the substrate 2, and the power semiconductor element 4 is placed, and the circuit pattern 3 and the power semiconductor element 4 are placed. The electrode on the lower surface of the metal particle is fire-bonded.

次に、図２（ｃ）に示すように、パワー半導体素子４の上面の電極と回路パターン３とにワイヤー６の端部をそれぞれ超音波接合する。 Next, as shown in FIG. 2C, the ends of the wires 6 are ultrasonically bonded to the electrodes on the upper surface of the power semiconductor element 4 and the circuit pattern 3.

次に、図２（ｄ）に示すように、基板２の回路パターン３にリードフレーム10の端子７部分先端を超音波接合する。 Next, as shown in FIG. 2D, the tip of the terminal 7 portion of the lead frame 10 is ultrasonically bonded to the circuit pattern 3 of the substrate 2.

次に、図２（ｅ）に示すように、基板２の下面の回路パターン９を露出させた状態で、回路パターン３とパワー半導体素子４の下面との接続部分、及び、回路パターン３とパワー半導体素子４の上面との接続部分、並びに、回路パターン３と端子７との接続部分を樹脂８で成形封止する。 Next, as shown in FIG. 2E, with the circuit pattern 9 on the lower surface of the substrate 2 exposed, the connection portion between the circuit pattern 3 and the lower surface of the power semiconductor element 4 and the circuit pattern 3 and the power The connection portion with the upper surface of the semiconductor element 4 and the connection portion between the circuit pattern 3 and the terminal 7 are molded and sealed with the resin 8.

最後に、図２（ｆ）に示すように、リードフレーム10から端子７を切断して、パワー半導体モジュール１を製造する。 Finally, as shown in FIG. 2 (f), the terminal 7 is cut from the lead frame 10 to manufacture the power semiconductor module 1.

１ パワー半導体モジュール ２ 基板
３ 回路パターン ４ パワー半導体素子
５ ダイアタッチ材 ６ ワイヤー
７ 端子 ８ 樹脂
９ 回路パターン 10 リードフレーム 1 Power semiconductor module 2 Substrate 3 Circuit pattern 4 Power semiconductor element 5 Diaattach material 6 Wire 7 Terminal 8 Resin 9 Circuit pattern 10 Lead frame

そこで、請求項１に係る本発明では、基板の回路パターンにパワー半導体素子の下面をダイボンディングで接続するとともに、回路パターンとパワー半導体素子の上面とをワイヤーを用いてワイヤーボンディングで接続し、回路パターンに端子を接続し、全ての接続部分を樹脂で封止したパワー半導体モジュールにおいて、前記全ての接続部分が、前記パワー半導体素子と前記ワイヤーと前記全ての接続部分とを封止する樹脂のガラス転移点よりも高い融点を有して、前記樹脂のガラス転移よりも先に前記接続部分が溶断しないことにした。 Therefore, in the present invention according to claim 1, the lower surface of the power semiconductor element is connected to the circuit pattern of the substrate by die bonding, and the circuit pattern and the upper surface of the power semiconductor element are connected by wire bonding using a wire to form a circuit. In a power semiconductor module in which terminals are connected to a pattern and all connection portions are sealed with resin, all the connection portions are resin glass that seals the power semiconductor element, the wire, and all the connection portions. and have a melting point higher than the transition point, the connecting portion prior to the glass transition of the resin was not blown.

Claims (3)

基板の回路パターンにパワー半導体素子の下面をダイボンディングで接続するとともに、回路パターンとパワー半導体素子の上面とをワイヤーボンディングで接続し、回路パターンに端子を接続し、全ての接続部分を樹脂で封止したパワー半導体モジュールにおいて、
前記全ての接続部分が、封止する樹脂のガラス転移点よりも高い融点を有することを特徴とするパワー半導体モジュール。 The lower surface of the power semiconductor element is connected to the circuit pattern of the board by die bonding, the circuit pattern and the upper surface of the power semiconductor element are connected by wire bonding, the terminals are connected to the circuit pattern, and all the connecting parts are sealed with resin. In the stopped power semiconductor module
A power semiconductor module characterized in that all the connection portions have a melting point higher than the glass transition point of the resin to be sealed. 前記基板の上面の回路パターンにパワー半導体素子を実装するとともに、パワー半導体素子の直下方に位置する基板の下面の回路パターンを樹脂から露出させたことを特徴とする請求項１に記載のパワー半導体モジュール。 The power semiconductor according to claim 1, wherein the power semiconductor element is mounted on the circuit pattern on the upper surface of the substrate, and the circuit pattern on the lower surface of the substrate located immediately below the power semiconductor element is exposed from the resin. module. 前記回路パターンとパワー半導体素子の下面とを金属粒子焼成結合により接続するとともに、前記回路パターンとパワー半導体素子の上面及び端子とを超音波接合により接続したことを特徴とする請求項１又は請求項２に記載のパワー半導体モジュール。 Claim 1 or claim characterized in that the circuit pattern and the lower surface of the power semiconductor element are connected by metal particle firing coupling, and the circuit pattern and the upper surface and terminals of the power semiconductor element are connected by ultrasonic bonding. 2. The power semiconductor module according to 2.
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JP2003128875A (en) * 2001-08-16 2003-05-08 Shin Etsu Chem Co Ltd Liquid epoxy resin composition and semiconductor device
JP2004128420A (en) * 2002-10-07 2004-04-22 Fuji Electric Fa Components & Systems Co Ltd Semiconductor module and manufacturing method thereof
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