JP2020173691A - Semiconductor apparatus, photoelectric conversion apparatus, photoelectric conversion system, and mobile body - Google Patents

Abstract

To provide a semiconductor apparatus in which characteristic change resulting from an external force is reduced.SOLUTION: A semiconductor apparatus according to the present invention has: a first transistor of a first conductive type; a second transistor of a second conductive type different from the first conductive type; and an output terminal for outputting a third current obtained by adding a first current generated based on a current flowing among main electrodes of the first transistor and a second current generated based on a current among main electrodes of the second transistor.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices, photoelectric conversion devices, photoelectric conversion systems and mobile bodies.

Patent Document 1 describes a solid-state image sensor having a plurality of pixels arranged in a matrix, vertical signal lines provided for each row, and load transistors provided for each row corresponding to the vertical signal lines. It is disclosed. The load transistor and the reference transistor in each row form a current mirror circuit.

Non-Patent Document 1 discloses that the electrical characteristics of a transistor change when the transistor is stressed. Further, Non-Patent Document 1 discloses that the tendency of the characteristic change with respect to stress is opposite between the N-channel MOS transistor and the P-channel MOS transistor.

Japanese Unexamined Patent Publication No. 2011-61270

Toshiro Hiramoto et al., "Integrated Nanodevices", Maruzen Co., Ltd., November 2009, p.96

When an external force is applied to the semiconductor substrate, the characteristics of the transistors formed on the semiconductor substrate may change. Therefore, an object of the present invention is to provide a semiconductor device, a photoelectric conversion device, a photoelectric conversion system, and a moving body in which characteristic changes due to external forces are reduced.

According to one aspect of the present invention, it is based on the current flowing between the first conductive type first transistor, the second conductive type second transistor different from the first conductive type, and the main electrode of the first transistor. It is characterized by having an output terminal for outputting a third current, which is the sum of a first current generated by the above and a second current generated based on a current flowing between the main electrodes of the second transistor. A semiconductor device is provided.

According to the present invention, it is possible to provide a semiconductor device, a photoelectric conversion device, a photoelectric conversion system, and a mobile body in which a characteristic change due to an external force is reduced.

It is a circuit diagram which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a block diagram which shows the schematic structure of the image pickup apparatus which concerns on 3rd Embodiment. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 3rd Embodiment. It is a timing diagram which shows the operation of the image pickup apparatus which concerns on 3rd Embodiment. It is a block diagram which shows the modification of the current source circuit of 3rd Embodiment. It is a block diagram which shows the structural example of the imaging system which concerns on 4th Embodiment. It is a figure which shows the structural example of the image pickup system and the moving body which concerns on 5th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same element or the corresponding element has a common reference numeral across a plurality of drawings, and the description thereof may be omitted or simplified.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor device according to the first embodiment. The semiconductor device of this embodiment is a current supply circuit for supplying a current to another circuit. The semiconductor device of the present embodiment can be used, for example, as a current source for reading a photoelectric conversion device such as an image pickup device, but the present invention is not limited to this.

The semiconductor device has a bias generation unit 110, a reference current generation unit 120, and current supply units 141 and 142. Each of these parts is formed on a semiconductor substrate. In FIG. 1, two current supply units 141 and 142 are shown, but the number of current supply units is not particularly limited, and may be, for example, one or three or more. May be good. Further, the number of reference current generation units 120 may be plural.

The bias generation unit 110 includes transistors PM1, NM1, NM2, and a constant current source IS. The reference current generation unit 120 includes transistors PM2, NM3, a capacitor C1 and a switch S1. The current supply unit 141 includes transistors NM4, NM5, a capacitor C2, and a switch S2. The current supply unit 142 includes transistors NM6, NM7, a capacitor C3, and a switch S3. In the description of each transistor, the source or drain may be referred to as a main electrode, and the gate may be referred to as a control electrode.

The transistors PM1 and PM2 are P-channel MOS transistors, and the transistors NM1, NM2, NM3, NM4, NM5, NM6, and NM7 are N-channel MOS transistors. In the present specification, the P-channel MOS transistor may be referred to as a first conductive type transistor, and the N-channel MOS transistor may be referred to as a second conductive type transistor. The switches S1, S2, and S3 are composed of a MOS transistor and the like. The switches S1, S2, and S3 are controlled on or off by, for example, a control signal from a control device external to the semiconductor device.

The drain of the transistor NM1 is connected to the constant current source IS. The connection node between the drain of the transistor NM1 and the constant current source IS is connected to the gate of the transistors NM1 and NM2 and one terminal of the switches S2 and S3. The source of the transistor NM1 and the source of the transistor NM2 are connected to the ground potential line. The drain of the transistor NM2 is connected to the drain and the gate of the transistor PM1. The source of the transistor PM1 is connected to the power potential line. The transistor NM1 and the transistor NM2 form a current mirror circuit. Therefore, the current flowing from the constant current source IS to the transistor NM1 is duplicated by the current mirror circuit. The replicated current flows between the main electrodes of the transistor PM1 and between the main electrodes of the transistor NM2.

The gate of the transistor PM1 is connected to one terminal of the switch S1. The other terminal of the switch S1 is connected to the gate of the transistor PM2 (first transistor) and one terminal of the capacitor C1. The other terminal of the capacitor C1 and the source of the transistor PM2 are connected to the power potential line. The drain of the transistor PM2 is connected to the drain and the gate of the transistor NM3 and the gate of the transistors NM5 and NM7. The sources of the transistors NM3, NM5, and NM7 are connected to the ground potential line. The transistor NM3 (third transistor), the transistor NM5 (fourth transistor), and the transistor NM7 form a current mirror circuit. Therefore, the current flowing between the main electrodes of the transistor NM3 is replicated to each of the transistor NM5 and the transistor NM7 by the current mirror circuit. The replicated current flows between the main electrodes of the transistor NM5 and between the main electrodes of the transistor NM7.

The other terminal of the switch S2 is connected to the gate of the transistor NM4 (second transistor) and one terminal of the capacitor C2. The source of the transistor NM4 and the other terminal of the capacitor C2 are connected to the ground potential line. The source of the transistor NM5 is connected to the ground potential line. The drain of the transistor NM4 and the drain of the transistor NM5 are connected at the node N1.

The other terminal of the switch S3 is connected to the gate of the transistor NM6 and one terminal of the capacitor C3. The source of the transistor NM6 and the other terminal of the capacitor C3 are connected to the ground potential line. The source of the transistor NM7 is connected to the ground potential line. The drain of the transistor NM6 and the drain of the transistor NM7 are connected at the node N2.

The switch S1 and the capacitor C1 form a sample hold circuit (first sample hold circuit) that holds the gate voltage of the transistor PM2. The switch S2 and the capacitor C2 form a sample hold circuit (second sample hold circuit) for holding the gate voltage of the transistor NM4. The switch S3 and the capacitor C3 form a sample hold circuit for holding the gate voltage of the transistor NM6.

The semiconductor device of the present embodiment can be operated by a sampling state in which the switches S1, S2, and S3 are all on and a hold state in which the switches S1, S2, and S3 are all off. In the hold state, the gate voltage in the sampling state is held in the capacitors C1, C2, and C3.

First, the operation of the semiconductor device in the sampling state will be described. In the sampling state, since the switch S1 is on, the gate of the transistor PM1, the drain of the transistor PM1 and the gate of the transistor PM2 are connected. As a result, the transistor PM1 and the transistor PM2 form a current mirror circuit. Therefore, the current flowing between the main electrodes of the transistor PM1 is duplicated by the current mirror circuit. The replicated current flows between the main electrodes of the transistor PM2 and between the main electrodes of the transistor NM3.

Further, in the sampling state, the switches S2 and S3 are also on. Therefore, the gate of the transistors NM1, NM4 and NM6 and the drain of the transistor NM1 are connected. As a result, the transistor NM1, the transistor NM4, and the transistor NM6 form a current mirror circuit. Therefore, the current flowing between the main electrodes of the transistor NM1 is duplicated by the current mirror circuit. The replicated current flows between the main electrodes of the transistor NM4 and between the main electrodes of the transistor NM6, respectively.

After the gate voltage of the transistor corresponding to the capacitors C1, C2, and C3 is charged in the sampling state, the switches S1, S2, and S3 are all turned off. As a result, the semiconductor device shifts to the hold state. At this time, a current corresponding to the gate voltage held in the capacitors C1, C2, and C3 in the sampling state flows between the main electrodes of the transistors PM2, NM4, and NM6, respectively.

Assuming that the current flowing into the node N1 is I1 (third current), the current flowing between the main electrodes of the transistor NM4 is I1a (second current), and the current flowing between the main electrodes of the transistor NM5 is I1b (first current). There is a relationship of Eq. (1) between the currents of.
I1 = I1a + I1b (1)

Further, assuming that the current flowing into the node N2 is I2, the current flowing between the main electrodes of the transistor NM6 is I2a, and the current flowing between the main electrodes of the transistor NM7 is I2b, there is a relationship of the equation (2) between these currents. ..
I2 = I2a + I2b (2)

The nodes N1 and N2 are connected to a circuit outside the semiconductor device. In other words, the nodes N1 and N2 are output terminals of the current supply units 141 and 142 configured to supply the currents I1 and I2 to the external circuit, respectively. As described above, the semiconductor device of the present embodiment can output a plurality of currents. For example, when the semiconductor device of the present embodiment is a readout circuit of the image pickup device, the nodes N1 and N2 are connected to the output terminals of the pixels in the image pickup device.

The effect of the semiconductor device of this embodiment will be described. When an external force is applied to the semiconductor substrate on which the semiconductor device is formed, the characteristics of the transistor formed in the semiconductor device may change. The cause of this characteristic change is a change in electron mobility or hole mobility.

When a transistor is saturated, the temporary approximation of the current I flowing between the main electrodes of that transistor is that the mobility is μ, the gate voltage is Vg, the threshold voltage is Vth, the gate capacitance is Cox, and the channel length is L. , When the channel width is W, it is expressed by the equation (3).
I = (μ ・ Cox / 2) ・ (W / L) ・ (Vg-Vth) ^ 2 (3)

From the equation (3), it can be seen that if the gate voltage Vg is constant, the current I changes in proportion to the amount of change in the mobility μ when an external force is applied to the semiconductor device to change the mobility μ. The mobility μ in the equation (3) means the hole mobility μp in the case of the P-channel MOS transistor and the electron mobility μn in the case of the N-channel MOS transistor. When the P-channel MOS transistor and the N-channel MOS transistor receive the same external force, the tendency of the characteristic change with respect to stress is opposite. It is considered that this is because the change in the hole mobility μp and the change in the electron mobility μn with respect to the external force are in opposite directions.

In the hold state, the voltage held by the capacitor C2 is applied to the gate of the transistor NM4. That is, a constant voltage is applied to the gate of the transistor NM4. At this time, assuming that the electron mobility μn changes by + 1% due to an external force, the current I1a flowing between the main electrodes of the transistor NM4 changes by + 1%.

Further, in the hold state, the voltage held by the capacitor C1 is applied to the gate of the transistor PM2. That is, a constant voltage is applied to the gate of the transistor PM2. At this time, when the transistor PM2 receives an external force similar to that of the transistor NM4, the sign of the change in the hole mobility μp is opposite to the sign of the change in the electron mobility μn. Assuming that the hole mobility μp changes by -1% due to an external force, the current flowing between the main electrodes of the transistor NM4 changes by -1%. The current flowing between the main electrodes of the transistor PM2 is replicated in the transistor NM5 by the current mirror circuit. Therefore, the current I1b flowing between the main electrodes of the transistor NM5 changes by -1%.

From the formula (1), the current I1 supplied to the outside from the current supply unit 141 is the sum of the current I1a flowing between the main electrodes of the transistor NM4 and the current I1b flowing between the main electrodes of the transistor NM5. As described above, since the change in the current I1a and the current I1b when the external force is applied have opposite codes, the change in the current due to the external force is canceled out. As a result, the change in the supply current due to the external force applied to the semiconductor device is reduced. As described above, according to the present embodiment, the semiconductor device in which the characteristic change due to the external force is reduced is provided.

If the effects on each transistor when an external force is applied to the semiconductor substrate are the same, the effect of canceling the change in current is further improved. Therefore, it is preferable that the transistors PM2, NM4, and NM5 are arranged so that the external forces applied to them are about the same. Specifically, it is preferable that the transistors PM2, NM4, and NM5 are arranged at close positions in the semiconductor substrate. Further, it is preferable that the channels of the transistors PM2, NM4, and NM5 have the same channel direction.

Although it has been explained that the influence of the external force is reduced for the current I1 supplied from the current supply unit 141, the same applies to the current I2 supplied from the current supply unit 142. Further, even when three or more current supply units are provided, the influence of the external force is similarly reduced for each current supply unit.

[Second Embodiment]
The configuration of the semiconductor device according to the second embodiment will be described. This embodiment is a modification of the circuit configuration of the semiconductor device of the first embodiment. In the following, the description overlapping with the first embodiment may be omitted as appropriate.

FIG. 2 is a circuit diagram showing the configuration of the semiconductor device according to the second embodiment. The semiconductor device has a bias generation unit 210, a reference current generation unit 220, and a current supply unit 241 and 242. Each of these parts is formed on a semiconductor substrate.

In the present embodiment, the transistors PM1 and NM2 are omitted, and the switches S4, S5, and S6 are added as compared with the semiconductor device of the first embodiment. The bias generation unit 210 has a transistor NM1 and a constant current source IS. The reference current generation unit 220 includes transistors PM2, NM3, capacitors C1 and switches S1 and S4. The current supply unit 241 includes transistors NM4 and NM5, capacitors C2, and switches S2 and S5. The current supply unit 242 includes transistors NM6 and NM7, capacitors C3, and switches S3 and S6.

The drain of the transistor NM1 is connected to the constant current source IS. The connection node between the drain of the transistor NM1 and the constant current source IS is connected to the gate of the transistor NM1 and one terminal of the switches S2 and S3. The source of the transistor NM1 is connected to the ground potential line.

The drain of the transistor PM2 is connected to one terminal of the switches S1 and S4 and the drain of the transistor NM3. The gate of the transistor PM2 is connected to the other terminal of the switch S1 and one terminal of the capacitor C1. The other terminal of the capacitor C1 and the source of the transistor PM2 are connected to the power potential line. The source of the transistor NM3 is connected to the ground potential line. The other terminal of the switch S4 is connected to the gate of the transistors NM3, NM5, NM7 and one terminal of the switches S5, S6.

The other terminal of the switch S2 is connected to the other terminal of the switch S5, the gate of the transistor NM4, and one terminal of the capacitor C2. The source of the transistor NM4 and the other terminal of the capacitor C2 are connected to the ground potential line. The source of the transistor NM5 is connected to the ground potential line. The drain of the transistor NM4 and the drain of the transistor NM5 are connected at the node N1.

The other terminal of the switch S3 is connected to the other terminal of the switch S6, the gate of the transistor NM6, and one terminal of the capacitor C3. The source of the transistor NM6 and the other terminal of the capacitor C3 are connected to the ground potential line. The source of the transistor NM7 is connected to the ground potential line. The drain of the transistor NM6 and the drain of the transistor NM7 are connected at the node N2.

The semiconductor device of the present embodiment can operate in the sampling state and the hold state as in the first embodiment. The semiconductor device is in the sampling state when the switches S1, S2, S3, S5, and S6 are all on and the switch S4 is off. Further, when the switches S1, S2, S3, S5, and S6 are all off and the switch S4 is on, the hold state is set.

First, the operation of the semiconductor device in the sampling state will be described. In the sampling state, switches S1, S2, S3, S5, and S6 are on, and switch S4 is off. Therefore, the gates of the transistors NM1, NM3, NM4, NM5, NM6, and NM7 and the drain of the transistor NM1 are connected. As a result, the transistors NM1, NM3, NM4, NM5, NM6, and NM7 form a current mirror circuit. Therefore, the current flowing between the main electrodes of the transistor NM1 is duplicated by the current mirror circuit. The replicated current flows between the main electrodes of the transistors NM3, NM4, NM5, NM6, and NM7, respectively.

Further, in the sampling state, since the switch S1 is on, the drain of the transistor PM2 and the gate of the transistor PM2 are connected. At this time, since the switch S4 is off, the current flowing between the main electrodes of the transistor PM2 coincides with the current flowing between the main electrodes of the transistor NM3.

After the gate voltage of the transistor corresponding to the capacitors C1, C2, and C3 is charged in the sampling state, the switches S1, S2, S3, S5, and S6 are all turned off, and the switch S4 is turned on. As a result, the semiconductor device shifts to the hold state. At this time, a current corresponding to the gate voltage held in the capacitors C1, C2, and C3 in the sampling state flows between the main electrodes of the transistors PM2, NM4, and NM6, respectively. Further, the transistors NM3, NM5, and NM7 form a current mirror circuit.

In the hold state, the change in the supply current due to the external force applied to the semiconductor device is reduced by the same mechanism as in the first embodiment. Therefore, also in the present embodiment, a semiconductor device in which the characteristic change due to the external force is reduced is provided.

[Third Embodiment]
The configuration of the image pickup apparatus according to the third embodiment will be described. In this embodiment, the semiconductor device of the first embodiment is used as a current source circuit. In the following, the description overlapping with the first embodiment may be omitted as appropriate. The imaging device described in this embodiment is an example of a photoelectric conversion device, and the semiconductor device of the first embodiment can be similarly applied to a photoelectric conversion device other than the imaging device. An example of a photoelectric conversion device other than the image pickup device is a distance measuring device.

FIG. 3 is a block diagram showing a schematic configuration of an imaging device according to the present embodiment. The image pickup apparatus includes a pixel array 20, a vertical scanning circuit 30, a column amplifier circuit 40, a horizontal scanning circuit 50, a control circuit 60, and an output circuit 70. Further, the image pickup apparatus includes the current source circuit 100 which is the semiconductor apparatus described in the first embodiment. The current source circuit 100 includes a bias generation unit 110, a reference current generation unit 120, and current supply units 141 and 142. Further, the imaging device has a current supply unit 143 having the same configuration as the current supply units 141 and 142. These circuits can be formed on one or more semiconductor substrates. In FIG. 3, since only three rows of the pixel array 20 are illustrated by way of illustration, only three current supply units are shown, but the current supply unit is each row of the pixel array 20. It is not limited to three because it can be provided corresponding to.

The pixel array 20 has a plurality of pixels 10 arranged so as to form a plurality of rows and a plurality of columns. The vertical scanning circuit 30 is a scanning circuit that supplies a control signal for controlling the transistor included in the pixel 10 to be turned on or off via a control signal line 6 provided corresponding to each line of the pixel 10. Here, since the control signal supplied to each of the plurality of pixels 10 may include a plurality of types of control signals, the control signal line 6 of each line may be configured as a set of a plurality of drive wirings. Further, the image pickup apparatus is provided with row signal lines 5 corresponding to each row of pixels 10, and signals from the pixels 10 are read out to the row signal lines 5 for each row.

One of a plurality of current supply units 141, 142, and 143 is connected to the row signal line 5 of each row. The current supply units 141, 142, and 143 supply current to the row signal line 5 of the corresponding row. A control signal φ1 is input from the control circuit 60 to the reference current generation unit 120 and the current supply units 141, 142, and 143. The control signal φ1 switches between a sampling state and a hold state by controlling a plurality of switches shown in FIG. 1 to be on or off.

The column amplifier circuit 40 performs processing such as amplification and correlation double sampling processing on the signal output to the column signal line 5. The horizontal scanning circuit 50 supplies a control signal for sequentially outputting signals corresponding to each row from the row amplifier circuit 40 to the output circuit 70. This control signal controls the switch provided in the column amplifier circuit 40 to be turned on or off. The output circuit 70 is composed of a buffer amplifier, a differential amplifier, and the like, and outputs a signal from the column amplifier circuit 40 to a signal processing unit outside the image pickup apparatus. The imaging device may further include an AD conversion unit, in which case the imaging device can output a digital signal. For example, the column amplifier circuit 40 may include an AD conversion unit. Further, the output circuit 70 may be configured to include an AD conversion unit. The control circuit 60 controls the operation timing of the vertical scanning circuit 30, the column amplifier circuit 40, the horizontal scanning circuit 50, and the like, and outputs a control signal φ1.

FIG. 4 is a circuit diagram showing a circuit configuration of the pixel 10. The pixel 10 includes a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. These transistors can be N-channel MOS transistors. A control signal PTX is input from the vertical scanning circuit 30 to the gate of the transfer transistor M1. A control signal PRESS is input from the vertical scanning circuit 30 to the gate of the reset transistor M2. The control signal PSEL is input from the vertical scanning circuit 30 to the gate of the selection transistor M4.

The photoelectric conversion element PD generates an electric charge according to the incident light by photoelectric conversion and accumulates the electric charge. The photoelectric conversion element PD can be a photodiode. In the following description, it is assumed that the photoelectric conversion element PD is a photodiode having an anode and a cathode. The anode of the photoelectric conversion element PD is connected to the ground potential line. The cathode of the photoelectric conversion element PD is connected to the source of the transfer transistor M1.

The connection node of the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 constitutes a floating diffusion FD. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to the power supply potential line. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the column signal line 5. A current supply unit 141 (or current supply units 142, 143) is connected to the column signal line 5. When the selection transistor M4 is turned on, the amplification transistor M3 and the current supply unit 141 form a source follower circuit, and a voltage corresponding to the potential of the floating diffusion FD is output to the column signal line 5.

FIG. 5 is a timing diagram showing the operation of the image pickup apparatus according to the third embodiment. FIG. 5 shows the level of each control signal in reading a signal from a row of pixels 10. Each transistor shall be turned on when the level of each control signal is high level and turned off when the level of each control signal is low level. Further, the current source circuit 100 is assumed to be in a sampling state when the control signal φ1 is at a high level and in a hold state when the control signal φ1 is at a low level.

At time t1, the control signals φ1, PRES, and PSEL become high levels. As a result, the reset transistor M2 and the selection transistor M4 are turned on, and the potential (N signal) in the reset state of the floating diffusion FD is output to the column signal line 5. Further, the current source circuit 100 is in the sampling state, and the same voltage as the gate voltage of the transistor that generates the current is applied to the capacitor.

At time t2, the control signal φ1 becomes low level, the current source circuit 100 shifts to the hold state, and the gate voltage applied in the sampling state is held in the capacitor.

At time t3, the control signal PRESS goes low and the reset transistor M2 turns off. As a result, the reset state of the floating diffusion FD is released. During the period from time t3 to time t4, the N signal is read out.

At time t4, the control signal PTX goes high and the transfer transistor M1 turns on. After that, at time t5, the control signal PTX becomes low level and the transfer transistor M1 is turned off. By these operations, the electric charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion FD. The potential of the floating diffusion FD changes to a potential corresponding to this charge. A potential (S signal) corresponding to the electric charge transferred to the floating diffusion FD is output to the column signal line 5. After that, the S signal is read out during the period from time t5 to time t6.

At time t6, the control signal PSEL goes low and the selection transistor M4 turns off. As a result, the reading from the pixel 10 of the row is completed. The CDS (correlation double sampling) circuit in the column amplifier circuit 40, the signal processing circuit outside the imaging device, or the like performs CDS processing on the S signal and N signal read by this processing to generate an image signal. To do.

As described above, the current source circuit 100 is in the hold state during the period in which the N signal and the S signal are read out. In the hold state, as described in the first embodiment, the change caused by the external force of the supply current from the current source circuit 100 is reduced. Therefore, according to the present embodiment, there is provided an imaging device capable of acquiring a signal with higher accuracy.

In this embodiment, the semiconductor device of the first embodiment has been described as being used for the current source circuit 100, but the present embodiment is not limited to this. For example, the semiconductor device of the second embodiment may be used for the current source circuit 100, or circuit configurations other than those of the first embodiment and the second embodiment may be used. Further, the structure of the pixel array 20 is not limited to the one shown in the drawing, and for example, the pixels 10 may be arranged one-dimensionally.

[Modified example of the third embodiment]
In the above description of the third embodiment, one reference current generation unit 120 is provided in the current source circuit 100, but the number of reference current generation units 120 may be plural. FIG. 6 shows a modified example when the number of reference current generating units 120 is plural. The current source circuit 100 of this modification has a plurality of circuits in which one reference current generation unit 120 supplies current to a plurality of current supply units 141 and 142. The number of reference current generators 120 is not limited to 2. It is assumed that the number of reference current generation units 120 is n and the number of current supply units 141 and 142 is m (n and m are natural numbers). At this time, it is sufficient that the relationship of 1 <n ≦ m is satisfied.

In this modification, even when the number of current supply units 141 and 142 is large, the distance between the reference current generation unit 120 and the current supply units 141 and 142 can be arranged at close positions in the semiconductor substrate. Changes in the supply current due to external force can be further reduced. Typically, the ratio m / n of m and n described above can be about 10.

[Fourth Embodiment]
Next, an example of an apparatus to which the imaging apparatus according to the above-described embodiment is applied will be described. FIG. 7 is a block diagram showing the configuration of the imaging system 900 according to the present embodiment. The image pickup device 930 shown in FIG. 7 is the image pickup device described in the third embodiment described above. Examples of the imaging system 900 to which the imaging device can be applied include a digital camera, a digital camcorder, and a surveillance camera. FIG. 7 shows a configuration example of a digital camera to which the image pickup apparatus described in the above embodiment is applied.

The imaging system 900 illustrated in FIG. 7 is for protecting the imaging device 930, the lens 902 for forming an optical image of a subject on the imaging device 930, the aperture 904 for changing the amount of light passing through the lens 902, and the lens 902. Has a barrier 906. The lens 902 and the aperture 904 are optical systems that collect light on the image pickup apparatus 930.

The imaging system 900 also has a signal processing unit 908 that processes an output signal output from the imaging device 930. The signal processing unit 908 performs a signal processing operation of performing various corrections and compressions on the input signal and outputting the input signal as needed.

The imaging system 900 further includes a buffer memory unit 910 for temporarily storing image data and an external interface unit (external I / F unit) 912 for communicating with an external computer or the like. Further, the imaging system 900 includes a recording medium 914 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 916 for recording or reading on the recording medium 914. Has. The recording medium 914 may be built in the imaging system 900 or may be detachable.

Further, the image pickup system 900 has an overall control / calculation unit 918 that performs various calculations and controls the entire digital camera, and a timing generation unit 920 that outputs various timing signals to the image pickup device 930 and the signal processing unit 908. Here, a timing signal or the like may be input from the outside, and the imaging system 900 may have at least an imaging device 930 and a signal processing unit 908 that processes an output signal output from the imaging device 930. The overall control / calculation unit 918 and the timing generation unit 920 may be configured to execute some or all of the functions related to the control of the photoelectric conversion device such as the generation of the control signal and the generation of the reference voltage in the above-described embodiment. Good.

The image pickup apparatus 930 outputs an image signal to the signal processing unit 908. The signal processing unit 908 performs predetermined signal processing on the image signal output from the image pickup apparatus 930 and outputs the image data. In addition, the signal processing unit 908 uses the image signal to generate an image.

As described above, the imaging system 900 of the present embodiment includes the imaging device 930 according to the third embodiment. As a result, it is possible to realize an imaging system 900 capable of higher quality imaging.

[Fifth Embodiment]
8 (A) and 8 (B) are diagrams showing the configuration of the imaging system 1000 and the moving body according to the present embodiment. FIG. 8A shows an example of the imaging system 1000 relating to the in-vehicle camera. The imaging system 1000 has the imaging device according to the third embodiment described above.

The image pickup system 1000 has an image processing unit 1030 that performs image processing on a plurality of image data acquired by the image pickup device 1010. Further, the imaging system 1000 has a parallax acquisition unit 1040 that calculates parallax information (phase difference of the parallax image, etc.) from a plurality of image data acquired by the imaging device 1010. Further, the imaging system 1000 includes a distance acquisition unit 1050 that calculates the distance to the object based on the calculated parallax information, and a collision determination unit that determines whether or not there is a possibility of collision based on the calculated distance. It has 1060 and. Here, the parallax acquisition unit 1040 and the distance acquisition unit 1050 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information on parallax, defocus amount, distance to an object, and the like. The collision determination unit 1060 may determine the possibility of collision by using any of these distance information. The distance information acquisition means may be realized by specially designed hardware or may be realized by a software module. Further, it may be realized by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or may be realized by a combination thereof. The above-mentioned parallax calculation is performed using signals read from a plurality of electrodes in the image pickup apparatus 1010.

The imaging system 1000 is connected to the vehicle information acquisition device 1310, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the image pickup system 1000 is connected to a control ECU 1410 which is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination unit 1060. That is, the control ECU 1410 is an example of a moving body control means that controls a moving body based on distance information. The imaging system 1000 is also connected to an alarm device 1420 that issues an alarm to the driver based on the determination result of the collision determination unit 1060. For example, when the collision determination unit 1060 has a high possibility of collision, the control ECU 1410 controls the vehicle to avoid the collision and reduce the damage by applying the brake, returning the accelerator, suppressing the engine output, and the like. The alarm device 1420 warns the user by sounding an alarm such as a sound, displaying alarm information on the screen of a car navigation system or the like, or giving vibration to the seat belt or steering wheel.

In the present embodiment, the periphery of the vehicle, for example, the front or the rear, is imaged by the imaging system 1000. FIG. 8B shows an imaging system 1000 for imaging the front of the vehicle (imaging range 1510). The vehicle information acquisition device 1310 sends an instruction to operate the imaging system 1000 to perform imaging. The imaging system 1000 of the present embodiment including the imaging device 1010 according to the third embodiment can further improve the accuracy of distance measurement.

In the above explanation, an example of controlling so as not to collide with another vehicle has been described, but it can also be applied to control for automatically driving following another vehicle, control for automatically driving so as not to go out of the lane, and the like. is there. Further, the imaging system can be applied not only to a vehicle such as a own vehicle but also to a moving body (moving device) such as a ship, an aircraft, or an industrial robot. In addition, it can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[Other Embodiments]
It should be noted that the above-described embodiments are merely examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features. For example, an embodiment in which a part of the configuration of any of the embodiments is added to another embodiment or a part of the configuration of another embodiment is replaced is also an embodiment to which the present invention can be applied. Should be understood.

Since the configuration of the imaging device of the third embodiment can be generally applied by the photoelectric conversion device, the imaging systems of the fourth embodiment and the fifth embodiment described above are also more generally applied to the photoelectric conversion system. It is extensible. That is, the technical ideas of the fourth embodiment and the fifth embodiment are not limited to the imaging system using the imaging device. For example, when the photoelectric conversion device is a distance measuring device, the photoelectric conversion system can be a distance measuring system.

In the above-described embodiment, the circuit configuration and the like can be changed as appropriate. For example, the circuit configuration may be modified so that the conductive types of the P-channel MOS transistor and the N-channel MOS transistor are reversed.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

N1, N2 node NM1-NM7 (N channel MOS) transistor PM1-PM2 (P channel MOS) transistor

Claims (14)

The first conductive type first transistor and
A second transistor of the second conductive type different from the first conductive type,
A third current obtained by adding a first current generated based on the current flowing between the main electrodes of the first transistor and a second current generated based on the current flowing between the main electrodes of the second transistor. Output terminal to output
A semiconductor device characterized by having. It further has a first sample hold circuit that holds the potential applied to the control electrode of the first transistor.
The semiconductor device according to claim 1. The output terminal outputs the third current when the first sample hold circuit is in the hold state.
The semiconductor device according to claim 2. It further has a second sample hold circuit that holds the potential applied to the control electrode of the second transistor.
The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is characterized by the above. The output terminal outputs the third current when the second sample hold circuit is in the hold state.
The semiconductor device according to claim 4, wherein the semiconductor device is characterized by the above. With the second conductive type third transistor,
With the second conductive type fourth transistor,
With more
The third transistor and the fourth transistor form a current mirror circuit.
The current mirror circuit generates the first current by replicating the current flowing between the main electrodes of the first transistor.
The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is characterized by the above. The first transistor and the second transistor are formed on the same semiconductor substrate.
The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is characterized by the above. Having a plurality of said second transistors corresponding to one said first transistor,
It is possible to output a plurality of the third currents.
The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is characterized by the above. It has a plurality of circuit groups including one said first transistor and a plurality of said second transistors corresponding to the one said first transistor.
The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is characterized by the above. The first transistor is a P-channel MOS transistor.
The second transistor is an N-channel MOS transistor.
The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is characterized by the above. The direction of the channel of the first transistor and the direction of the channel of the second transistor are the same.
The semiconductor device according to claim 10. A pixel containing a photoelectric conversion element that generates an electric charge according to the incident light by photoelectric conversion, and
The semiconductor device according to any one of claims 1 to 11.
Have,
The semiconductor device supplies the third current to the pixel.
A photoelectric conversion device characterized by this. The photoelectric conversion device according to claim 12,
A signal processing unit that processes the signal output from the photoelectric conversion device, and
A photoelectric conversion system characterized by having. It ’s a mobile body,
The photoelectric conversion device according to claim 12,
A distance information acquisition means for acquiring distance information to an object from parallax information based on a signal from the photoelectric conversion device, and
A control means for controlling the moving body based on the distance information,
A mobile body characterized by having.

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