JP6871797B2 - Photoelectric converter - Google Patents

Description

The present invention relates to a photoelectric conversion device.

Patent Document 1 discloses a photoelectric conversion device including a plurality of pixels arranged in a row direction and a column direction, and a readout circuit provided for each column. The read-out circuit is provided with a holding unit that holds a reference voltage input from the outside and an arithmetic amplification unit that receives a reference voltage. Further, the read circuit includes a switch unit that electrically cuts off between the outside and the holding unit when the arithmetic amplification unit amplifies the signal output from the pixel. According to Patent Document 1, since the temporal fluctuation of the reference voltage can be suppressed, it is described that the horizontal striped random noise appearing in the image due to the disturbance noise of the reference voltage can be reduced.

Japanese Unexamined Patent Publication No. 2008-85994

However, in the case where the holding portion is provided for each row as shown in FIG. 6 of Patent Document 1, if a leak exists in the circuit around the holding capacitance constituting the holding portion, the reference voltage held in the hold capacitance becomes It can fluctuate during the read period. If the reading is performed with different reference voltages among the plurality of columns, vertical stripe noise may occur in the acquired image.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a photoelectric conversion device capable of reducing vertical stripe noise.

According to one aspect of the present invention, there is a pixel array in which a plurality of pixels are arranged so as to form a plurality of rows, and a plurality of pixels arranged corresponding to the plurality of rows in the pixel array and reading signals from the pixels. Each of the plurality of column read circuits includes a reading unit in which row reading circuits are arranged, and a holding unit that holds a reference voltage supplied from a reference voltage line, and the reference voltage held by the holding unit. When the amplification unit amplifies the signal output from the pixel and the amplification unit amplifies the signal output from the pixel, the reference voltage line and the holding unit are electrically disconnected from each other. The holding portion of the first row read circuit and the holding portion of the second row read circuit different from the first row read circuit, including the switch unit, do not pass through the reference voltage line. Provided is a photoelectric conversion device further comprising a configuration which is connected or can be connected without using the reference voltage line.

It is possible to provide a photoelectric conversion device capable of reducing vertical striped noise.

It is a circuit block diagram of the photoelectric conversion apparatus which concerns on 1st Embodiment of this invention. It is a timing chart of the photoelectric conversion apparatus which concerns on 1st Embodiment of this invention. It is a circuit block diagram of the photoelectric conversion apparatus which concerns on 2nd Embodiment of this invention. It is a circuit block diagram of the photoelectric conversion apparatus which concerns on 3rd Embodiment of this invention. It is a block diagram of the image pickup system which concerns on 4th Embodiment of this invention. It is a block diagram of the image pickup system and the moving body which concerns on 5th Embodiment of this invention.

[First Embodiment]
FIG. 1 is a circuit configuration diagram of a photoelectric conversion device according to a first embodiment of the present invention. The photoelectric conversion device includes a pixel array 10, a reading unit 20, a horizontal transfer circuit 30, a vertical scanning circuit 40, and a horizontal scanning circuit 50.

The pixel array 10 includes a plurality of pixel PXs arranged so as to form a plurality of rows and a plurality of columns. FIG. 1 shows a pixel array 10 in which pixels PX are arranged in a matrix of 2 rows and 4 columns for the sake of simplification of description, but the number of rows and columns is not particularly limited. Further, in FIG. 1, for convenience of explanation, the row number is m and the column number is n, and a code of PXmn is added to each pixel (m and n are natural numbers). For example, the pixel PX located in the first row and the second column is described as PX12.

The circuit configuration of each pixel PX will be described. The pixel PX includes a photoelectric conversion element 11, a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15. The photoelectric conversion element 11 is, for example, a photodiode. The anode of the photoelectric conversion element 11 is grounded, and the cathode of the photoelectric conversion element 11 is connected to the source of the transfer transistor 12. The drain of the transfer transistor 12 is connected to the source of the reset transistor 13 and the gate of the amplification transistor 14. The drain of the transfer transistor 12, the source of the reset transistor 13, and the connection node of the gate of the amplification transistor 14 form a floating diffusion region (hereinafter, referred to as “FD region”). The drain of the reset transistor 13 and the drain of the amplification transistor 14 are connected to a power supply voltage line that supplies the power supply voltage VDD. The source of the amplification transistor 14 is connected to the drain of the selection transistor 15.

The names of the source and drain of the transistor may differ depending on the conductive type of the transistor, the function of interest, and the like, and the above-mentioned source and drain may be referred to by the opposite names. In addition, the source and drain are sometimes collectively referred to as main electrodes.

A vertical output line 16 extending in the column direction is arranged in each row of the pixel array 10. The vertical output lines 16 are connected to the sources of the selection transistors 15 of the plurality of pixel PXs arranged in the column direction, and form a common signal line for the pixel PXs in the same row. A current source (not shown) is connected to the vertical output line 16. As a result, the amplification transistor 14 and the current source form a source follower circuit that outputs a voltage corresponding to the potential in the FD region to the vertical output line 16.

A plurality of control signal lines extending in the row direction are arranged in each row of the pixel array 10. Each control signal line forms a common control signal line for the pixels PXmn arranged in the row direction, and is connected to the vertical scanning circuit 40. Each control signal line includes a reset signal line for transmitting the control signal P1, a transfer signal line for transmitting the control signal P2, and a line selection signal line for transmitting the control signal P3. The vertical scanning circuit 40 outputs the control signal P2 to the gate of the transfer transistor 12 in the corresponding line via the transfer signal line. Further, the vertical scanning circuit 40 outputs the control signal P1 to the gate of the reset transistor 13 in the corresponding row via the reset signal line. Further, the vertical scanning circuit 40 outputs the control signal P3 to the gate of the selection transistor 15 in the corresponding row via the selection signal line.

The reading unit 20 has a row reading circuit R provided corresponding to each row of the pixel array 10. In FIG. 1, for convenience of explanation, a column number is set to n, and a code of Rn is added to each column reading circuit. For example, the column reading circuit R located in the first column is described as R1.

The circuit configuration of each column readout circuit R will be described. The column readout circuit R includes a clamp capacitance 21, a breaking transistor 22, a reference voltage holding capacitance 23, an operational amplifier 24, a feedback capacitance 25, a clamp transistor 26, a sample hold transistor (SH transistor) 27, and a sample hold capacitance (SH capacitance) 28. Be prepared. A plurality of control signal lines extending in the row direction and one reference voltage line are arranged in each column readout circuit R. Control signals P4, P5, and P6 are supplied to the plurality of control signal lines from a control unit or the like outside the photoelectric conversion device. A reference voltage V1 is supplied to the reference voltage line from the control unit or the like.

The vertical output line 16 of each row is connected to one end of the clamp capacitance 21 of the row reading circuit R of the corresponding row. The other end of the clamp capacitance 21 is connected to the inverting input terminal of the operational amplifier 24, one end of the feedback capacitance 25, and one main electrode of the clamp transistor 26. The other end of the feedback capacitance 25 and the other main electrode of the clamp transistor 26 are connected to the output terminal of the operational amplifier 24. A control signal P4 is input to the gate of the clamp transistor 26 via a control signal line.

The non-inverting input terminal of the operational amplifier 24 is connected to one end of the reference voltage holding capacitance 23 and one main electrode of the breaking transistor 22. The other end of the reference voltage holding capacity 23 is grounded. A reference voltage V1 is supplied from the reference voltage line to the other main electrode of the breaking transistor 22. The control signal P5 is input from the control signal line to the gate of the cutoff transistor 22. The other end of the reference voltage holding capacity 23 may be connected to a low impedance wiring having a fixed potential, and the potential is not limited to the ground potential. For example, the other end of the reference voltage holding capacity 23 may be connected to the wiring to which the power supply potential is supplied. The reference voltage holding capacity 23 has a function as a holding unit for holding the reference voltage V1 supplied from the reference voltage line. The operational amplifier 24 has a function as an amplification unit that amplifies the signal output from the pixel PX with reference to the reference voltage V1 held in the reference voltage holding capacity 23. The breaking transistor 22 has a function as a switch unit that electrically disconnects the reference voltage line and the reference voltage holding capacity 23 when the operational amplifier 24 amplifies the signal output from the pixel PX.

Further, one end of the reference voltage holding capacity 23 of the column reading circuit R1 in the first row is connected to one end of the reference voltage holding capacity 23 of the adjacent row reading circuit R2 in the second row by wiring W. Further, one end of the reference voltage holding capacity 23 of the row reading circuit R2 in the second row is further connected to one end of the reference voltage holding capacity 23 of the adjacent row reading circuit R3 in the third row by wiring W. In this way, in the example of the present embodiment, one end of the reference voltage holding capacity 23 of all the rows is connected by the wiring W which is a path different from the breaking transistor 22. By connecting the reference voltage holding capacity 23 in the adjacent row with the wiring W, it is possible to connect with a low impedance, and the potentials of the connected reference voltage holding capacity 23 can be brought close to the same.

It is not essential that one end of the reference voltage holding capacity 23 in all columns is connected. At least the reference voltage holding capacity 23 of one row reading circuit (first row reading circuit) and the reference voltage holding of another row reading circuit (second row reading circuit) different from the first row reading circuit. It suffices if the capacity 23 is connected.

In FIG. 1, the reference voltage holding capacities 23 in adjacent columns are connected to each other, but the reference voltage holding capacities 23 in adjacent columns are not connected to each other, but the reference voltage holding capacities 23 in separate rows are connected to each other. It may be a configuration. This configuration example will be described in the third embodiment.

The output terminal of the operational amplifier 24 is further connected to one main electrode of the SH transistor 27. One end of the SH capacitance 28 is connected to the other main electrode of the SH transistor 27. The control signal P6 is input from the control signal line to the gate of the SH transistor 27. The other end of the SH capacity 28 is grounded. The SH transistor 27 and the SH capacitance 28 form a sample hold circuit.

The horizontal transfer circuit 30 includes a horizontal transfer transistor 31, a horizontal transfer line 32, a transistor 33, and a differential amplifier 34 arranged corresponding to the column read-out circuit R of each row. One main electrode of each horizontal transfer transistor 31 is connected to one end of the SH capacitance 28 of the row readout circuit R of the corresponding row. The other main electrode of each horizontal transfer transistor 31 is connected to the horizontal transfer line 32. A control signal Hn (n is a column number) output from the horizontal scanning circuit 50 is input to the gate of the horizontal transfer transistor 31 in each row. The horizontal transfer line 32 is connected to the non-inverting input terminal of the differential amplifier 34 and one main electrode of the transistor 33. The inverting input terminal and the output terminal of the differential amplifier 34 are connected, and the differential amplifier 34 constitutes a voltage follower that outputs the potential of the horizontal transfer line 32 as an output signal OUT. A reset voltage V2 is input to the other main electrode of the transistor 33 from an external control unit or the like. A control signal P7 is input to the gate of the transistor 33 from an external control unit or the like. When the transistor 33 is turned on in response to the control signal P7, the horizontal transfer line 32 is reset to the reset voltage V2.

FIG. 2 is a timing chart of the photoelectric conversion device according to the first embodiment. The reading operation for one line of the photoelectric conversion device will be described with reference to FIG. Immediately before the time T1, the control signal P5 is at a high level and the cutoff transistor 22 is in the ON state. As a result, the reference voltage holding capacity 23 is reset at the reference voltage V1. At the same time, the control signals P1, P2, P3, P4, and P6 are all at low levels, and the reset transistor 13, the transfer transistor 12, the selection transistor 15, the clamp transistor 26, and the SH transistor 27 are all turned off. There is.

At time T1, the control signal P5 goes low and the cutoff transistor 22 goes off. As a result, the reference voltage line and the reference voltage holding capacity 23 are electrically disconnected, and the reference voltage V1 is held in the reference voltage holding capacity 23.

At time T2, the control signals P1 and P3 go high, and the reset transistor 13 and the selection transistor 15 turn on. As a result, the FD region is reset by the power supply voltage VDD, and the voltage based on the reset state of the FD region is output to the vertical output line 16. At the same time, the control signal P4 becomes high level and the clamp transistor 26 also turns on. As a result, the inverting input terminal and the output terminal of the operational amplifier 24 are connected to form a voltage follower circuit. Therefore, the nodes of the inverting input terminal and the output terminal of the operational amplifier 24 are reset to the reference voltage V1.

At time T3, the control signal P1 goes low and the reset transistor 13 goes off. As a result, the FD region becomes a floating state. At time T4, the control signals P3 and P4 are at a low level, and the selection transistor 15 and the clamp transistor 26 are turned off. At this time, the voltage based on the reset state of the FD region is clamped to the clamp capacity 21. Further, the output of the operational amplifier 24 is fed back to the inverting input terminal via the feedback capacitance 25. As described above, the operational amplifier 24, the clamp capacitance 21, and the feedback capacitance 25 perform an amplification operation with a gain corresponding to the capacitance ratio of the clamp capacitance 21 to the feedback capacitance 25 with reference to the reference voltage V1.

At time T5, the control signals P2 and P3 go high, and the transfer transistor 12 and the selection transistor 15 turn on. As a result, the electric charge accumulated in the photoelectric conversion element 11 within a predetermined exposure period is transferred to the FD region. Due to the change in the potential in the FD region at this time, the voltage generated in the vertical output line 16 is such that the potential change in the FD region based on the electric charge generated by the incident light is superimposed on the voltage in the reset state. Since the voltage based on the reset state of the FD region is clamped to the clamp capacitance 21, the component of the reset state is canceled, and the operational amplifier 24 performs the amplification operation with respect to the optical signal voltage corresponding to the incident light.

At time T6, the control signal P2 goes low and the transfer transistor 12 turns off. This completes the charge transfer. At time T7, the control signal P3 goes low and the selection transistor 15 turns off. At this time, the electrical connection between the pixel PX and the vertical output line 16 is released.

During the period from time T8 to time T9, the control signal P6 is temporarily raised to a high level, and the SH transistor 27 is turned on. As a result, the signal output from the operational amplifier 24 is held in the SH capacity 28. At time T10, the control signal P5 goes high and the cutoff transistor 22 turns on. As a result, the reference voltage holding capacity 23 is reset again at the reference voltage V1.

By the above operation, the signal from the pixel PX for one line is read out and held in the SH capacity 28. After that, although not shown in FIG. 2, the control signals H1, H2, H3, ... Are sequentially set to high levels, and the horizontal transfer transistors 31 are sequentially turned on. As a result, the signal held in the SH capacity 28 of each row is serially output to the outside of the photoelectric conversion device as an output signal OUT.

In the present embodiment, the reference voltage holding capacity 23 of the row reading circuit R of each row is electrically connected by the wiring W. If there is a leak in the circuit around the reference voltage holding capacity 23, the reference voltage V1 held in the reference voltage holding capacity 23 may fluctuate during the read period. If the reading is performed with the reference voltage V1 being different among the plurality of columns, vertical stripe noise may occur in the acquired image. The change ΔV of the output voltage from the column readout circuit R due to the leak is expressed by the following equation 1.

Here, _{I L} is the leakage current. T is the time from when the reference voltage V1 is held until the reading is completed. In the example shown in FIG. 2, T corresponds to the time from time T1 to time T9. G is the gain of the column reading circuit R, and is a value corresponding to the capacitance ratio of the clamp capacitance 21 to the feedback capacitance 25. k is the number of reference voltage holding capacities 23 electrically connected. C is the capacity value of the reference voltage holding capacity 23.

As can be understood from Equation 1, the change ΔV of the output voltage is inversely proportional to the number of reference voltage holding capacities 23 connected. Therefore, in the configuration of the present embodiment, the change ΔV of the output voltage is smaller than that in the case where the reference voltage holding capacity 23 of each column as shown in FIG. 6 of Patent Document 1 is not connected (k = 1 in Equation 1). Become. Therefore, according to the present embodiment, it is possible to provide a photoelectric conversion device capable of reducing vertical striped noise. Further, the photoelectric conversion device of the present embodiment has little influence on the image quality even if there is a slight leak in the circuit around the reference voltage holding capacity 23 due to manufacturing factors, and is unlikely to be defective. , Yield can be improved.

According to Equation 1, the larger the number k of the connected reference voltage holding capacities 23, the smaller the change ΔV of the output voltage. However, when the signal levels differ greatly in the horizontal direction (horizontal direction in FIG. 1) as in the case where the contrast of the subject is large, the current consumption, operating state, etc. of the operational amplifier 24 may differ greatly for each column. is there. In such a case, the influence of the difference in each column such as the current consumption of the operational amplifier 24 and the operating state may crosstalk to the surrounding pixels PX. Further, if the number k of the connected reference voltage holding capacities 23 is made too large, the influence of crosstalk becomes remarkable. In order to sufficiently reduce the influence of crosstalk, the number k of the connected reference voltage holding capacities 23 should be (n / 100) or less, where n is the number of rows of the pixel array 10. desirable. Further, in order to obtain the effect of reducing noise due to the above-mentioned leak, at least two reference voltage holding capacities 23 need to be connected. Considering these, it is desirable that the number k of the connected reference voltage holding capacities 23 is 2 or more and (n / 100) or less.

In the circuit configuration shown in FIG. 1, the breaking transistors 22 are provided in each of the column readout circuits R, but if they are configured so that the reference voltage V1 can be applied from other rows via wiring, a part of them The cutoff transistor 22 in the line of may be omitted. Further, the circuit used for the column readout circuit R is not limited to the one using the operational amplifier 24, and may be an amplifier having another configuration as long as the reference voltage can be input. For example, the operational amplifier 24 may be a comparator.

[Second Embodiment]
Next, the photoelectric conversion device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram of the photoelectric conversion device according to the second embodiment. In the present embodiment, the difference from the first embodiment is that the reference voltage holding capacity 23 is connected to the reference voltage holding capacity 23 in the adjacent row via the connecting transistor 29. Since other points are the same as those in the first embodiment, the description thereof will be omitted.

The column read-out circuit R of each column further includes a connection transistor 29. One main electrode (first main electrode) of the connection transistor 29 of the column read circuit R1 is connected to the reference voltage holding capacity 23 of the column read circuit R1. The other main electrode (second main electrode) of the connection transistor 29 of the column read circuit R1 is connected to the reference voltage holding capacity 23 of the column read circuit R2. Similarly, for the other rows, the reference voltage holding capacities 23 of the adjacent rows are connected to each other via the connection transistor 29. A control signal P8 is input to the gate of the connection transistor 29. When the control signal P8 is at a high level, the connection transistor 29 is in the ON state, and the reference voltage holding capacities 23 in the adjacent rows are electrically connected to each other. Further, when the control signal P8 is at a low level, the connection transistor 29 is in the off state, and the reference voltage holding capacities 23 in the adjacent rows are electrically disconnected from each other.

Whether or not to turn on the connection transistor 29 can be determined based on whether or not there is a leak in the circuit around the reference voltage holding capacity 23. Whether or not a leak is present can be determined, for example, based on the results of a shipping inspection or adjustment step of the photoelectric conversion device. When it is determined that a leak exists in the circuit around the reference voltage holding capacity 23, the control signal P8 is maintained at a high level and the reference voltage holding capacities 23 in the adjacent rows are electrically connected to each other. , Noise can be reduced. If it is determined that there is no leakage, the influence of crosstalk is reduced by maintaining the control signal P8 at a low level and electrically disconnecting the reference voltage holding capacities 23 in the adjacent rows. be able to. As described above, in the present embodiment, by providing the connection transistor 29, it is possible to change whether or not the reference voltage holding capacities 23 in the adjacent rows are electrically connected depending on the presence or absence of the leak, which is more effective. Noise can be reduced.

[Third Embodiment]
Next, the photoelectric conversion device according to the third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of the photoelectric conversion device according to the third embodiment. In the present embodiment, the difference from the second embodiment is that the reference voltage holding capacity 23 in one column is not connected to the reference voltage holding capacity 23 in the adjacent row, and the reference voltage holding capacity 23 in the next row is not connected. It is a point that is connected to 23 via a connection transistor 29. Since other points are the same as those in the second embodiment, the description thereof will be omitted.

One main electrode of the connection transistor 29 of the column read circuit R1 is connected to the reference voltage holding capacity 23 of the column read circuit R1, and the other main electrode of the connection transistor 29 of the column read circuit R1 is the column read circuit R3. It is connected to the reference voltage holding capacity 23 of. One main electrode of the connection transistor 29 of the column read circuit R2 is connected to the reference voltage holding capacity 23 of the column read circuit R2, and the other main electrode of the connection transistor 29 of the column read circuit R2 is the column read circuit R4. It is connected to the reference voltage holding capacity 23 of. In this way, the reference voltage holding capacities 23 of the rows other than the adjacent rows are connected to each other via the connection transistor 29.

In this way, by configuring the reference voltage holding capacities 23 of rows other than the adjacent rows to be electrically connected to each other, the influence of crosstalk between adjacent rows is reduced, and noise due to the influence of crosstalk is generated. It becomes difficult. In FIG. 4, the reference voltage holding capacities 23 can be connected to each other in every other row, but the reference voltage holding capacities 23 may be connected to each other with two or more rows open.

[Fourth Embodiment]
Next, an example of an apparatus to which the solid-state image sensor according to the above-described embodiment is applied will be described. FIG. 5 is a block diagram showing the configuration of the imaging system 500 according to the present embodiment. The solid-state image sensor 400 shown in FIG. 5 is a solid-state image sensor using any of the photoelectric conversion devices described in the first to third embodiments described above. Examples of the image pickup system 500 to which the solid-state image pickup device 400 can be applied include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 5 shows a configuration example of a digital still camera to which the solid-state image sensor 400 described in the above embodiment is applied.

The image pickup system 500 illustrated in FIG. 5 includes a solid-state image pickup device 400, a lens 502 for forming an optical image of a subject on the solid-state image pickup device 400, an aperture 504 for varying the amount of light passing through the lens 502, and protection of the lens 502. Has a barrier 506 for. The lens 502 and the aperture 504 are optical systems that focus light on the solid-state image sensor 400.

The image pickup system 500 also has a signal processing unit 508 that processes an output signal output from the solid-state image pickup device 400. The signal processing unit 508 performs a signal processing operation of performing various corrections and compressions on the input signal as necessary and outputting the signal. The signal processing unit 508 may have a function of performing AD (Analog-to-Digital) conversion processing on the output signal output from the solid-state image sensor 400. In this case, it is not always necessary to have an AD conversion circuit inside the solid-state image sensor 400.

The image pickup system 500 further includes a buffer memory unit 510 for temporarily storing image data, and an external interface unit (external I / F unit) 512 for communicating with an external computer or the like. Further, the imaging system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 516 for recording or reading on the recording medium 514. Has. The recording medium 514 may be built in the image pickup system 500 or may be detachable.

Further, the image pickup system 500 includes an overall control / calculation unit 518 that performs various calculations and controls the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the solid-state image sensor 400 and the signal processing unit 508. Here, a timing signal or the like may be input from the outside, and the imaging system 500 may have at least a solid-state imaging device 400 and a signal processing unit 508 that processes an output signal output from the solid-state imaging device 400. .. The overall control / calculation unit 518 and the timing generation unit 520 may be configured to execute some or all of the functions related to the control of the photoelectric conversion device such as the generation of the control signal and the generation of the reference voltage in the above-described embodiment. Good.

The solid-state image sensor 400 outputs an image signal to the signal processing unit 508. The signal processing unit 508 performs predetermined signal processing on the image signal output from the solid-state image sensor 400, and outputs the image data. Further, the signal processing unit 508 uses the image signal to generate an image.

By configuring the image pickup system including the solid-state image pickup device 400 using the photoelectric conversion device according to the first to third embodiments, it is possible to realize an image pickup system with further reduced noise.

[Fifth Embodiment]
6 (a) and 6 (b) are diagrams showing the configuration of the imaging system 600 and the moving body according to the present embodiment. FIG. 6A shows an example of the image pickup system 600 relating to the vehicle-mounted camera. The image pickup system 600 includes a solid-state image pickup device 400. The solid-state image sensor 400 is a solid-state image sensor using the photoelectric conversion device according to any one of the first to third embodiments described above. The image pickup system 600 has an image processing unit 612 that performs image processing on a plurality of image data acquired by the solid-state image pickup device 400, and a parallax (phase difference of the parallax image) from the plurality of image data acquired by the image pickup system 600. It has a parallax calculation unit 614 for calculating the above. Further, the imaging system 600 includes a distance measuring unit 616 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 618 that determines whether or not there is a possibility of collision based on the calculated distance. And have. Here, the parallax calculation unit 614 and the distance measurement unit 616 are examples of distance information acquisition means for acquiring distance information to an object. That is, the distance information is information on parallax, defocus amount, distance to an object, and the like. The collision determination unit 618 may determine the possibility of collision by using any of these distance information. The distance information acquisition means may be realized by specially designed hardware or may be realized by a software module. Further, it may be realized by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or may be realized by a combination thereof.

The imaging system 600 is connected to the vehicle information acquisition device 620, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the image pickup system 600 is connected to a control ECU 630 which is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination unit 618. That is, the control ECU 630 is an example of a moving body control means that controls a moving body based on distance information. The imaging system 600 is also connected to an alarm device 640 that issues an alarm to the driver based on the determination result of the collision determination unit 618. For example, when there is a high possibility of a collision as a result of the collision determination unit 618, the control ECU 630 controls the vehicle to avoid the collision and reduce the damage by applying the brake, returning the accelerator, suppressing the engine output, and the like. The alarm device 640 warns the user by sounding an alarm such as a sound, displaying alarm information on the screen of a car navigation system or the like, or giving vibration to the seat belt or steering wheel.

In the present embodiment, the periphery of the vehicle, for example, the front or the rear, is imaged by the image pickup system 600. FIG. 6B shows an imaging system 600 for imaging the front of the vehicle (imaging range 650). The vehicle information acquisition device 620 sends an instruction to operate the imaging system 600 to perform imaging. The image pickup system 600 of the present embodiment including the solid-state image pickup device 400 using the photoelectric conversion device according to the first to third embodiments can further improve the accuracy of distance measurement.

In the above explanation, an example of controlling so as not to collide with another vehicle has been described, but it can also be applied to control for automatic driving following other vehicles, control for automatic driving so as not to go out of the lane, and the like. is there. Further, the imaging system can be applied not only to a vehicle such as a own vehicle but also to a moving body (moving device) such as a ship, an aircraft, or an industrial robot. In addition, it can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[Other Embodiments]
It should be noted that the above-described embodiments are merely examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features. For example, an embodiment in which a part of the configuration of any of the embodiments is added to another embodiment or a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment to which the present invention can be applied. Should be understood.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

10 Pixel array 20 Read section 22 Interruption transistor 23 Reference voltage holding capacity 24 Operational amplifier PX pixel R column Read circuit V1 Reference voltage

Claims (8)

A pixel array in which multiple pixels are arranged in multiple rows, and
A reading unit provided corresponding to the plurality of rows in the pixel array and in which a plurality of row reading circuits for reading signals from the pixels are arranged.
With
Each of the plurality of column readout circuits
A holding unit that holds the reference voltage supplied from the reference voltage line,
An amplification unit that amplifies the signal output from the pixel with reference to the reference voltage held in the holding unit.
A switch unit that electrically disconnects the reference voltage line and the holding unit when the amplification unit amplifies a signal output from the pixel.
Including
The holding portion of the first row reading circuit and the holding portion of the second row reading circuit different from the first row reading circuit are connected without the reference voltage line, or the reference. Further equipped with a configuration that can be connected without going through a voltage line ,
A photoelectric conversion device characterized by this. The first aspect of the present invention, wherein the holding portion of the first row read circuit and the holding portion of the second row read circuit are connected by a wiring different from that of the reference voltage line. Photoelectric conversion device. The connectable configuration further includes a connecting transistor having a first main electrode and a second main electrode.
The holding portion of the first row readout circuit is connected to the first main electrode of the connecting transistor, and the holding portion of the second row readout circuit is connected to the second main electrode of the connecting transistor. Being done
Claim 1 is characterized in that, when the connection transistor is turned on, the holding portion of the first row read circuit and the holding portion of the second row read circuit are electrically connected. The photoelectric conversion device according to the above. The photoelectric conversion device according to any one of claims 1 to 3, wherein the row corresponding to the first row read circuit and the row corresponding to the second row read circuit are adjacent to each other. The photoelectric conversion device according to any one of claims 1 to 3, wherein the row corresponding to the first row read circuit and the row corresponding to the second row read circuit are not adjacent to each other. When the number of rows of the pixel array is n,
The number of the holding parts that can be connected to the holding part of the first row reading circuit without going through the reference voltage line or can be connected through the connectable configuration is the number of the holding parts that can be connected to the first row reading circuit. Any one of claims 1 to 5, wherein the number of the holding portion of the circuit and the holding portion of the second row reading circuit is two or more and (n / 100) or less. The photoelectric conversion device according to the section. The photoelectric conversion device according to any one of claims 1 to 6.
An imaging system including a signal processing unit that processes a signal output from the photoelectric conversion device. It ’s a mobile body,
The photoelectric conversion device according to any one of claims 1 to 6.
A distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device, and
A moving body including a moving body control means for controlling the moving body based on the distance information.

Images