JP2020170377A - Power source control circuit, power management circuit, and electronic apparatus - Google Patents

Abstract

To provide a power source control circuit and PMIC with enhanced robustness.SOLUTION: A power source control circuit 200 controls states of a plurality of power sources 101_1 to 101_4. A non-volatile memory 210 stores a plurality of instruction groups corresponding to a plurality of events. A PMU 220 executes, when one of the plurality of events occurs, a group of instructions corresponding to the event and controls the plurality of power sources 101_1 to 101_4. An interface circuit 230 is provided to access a register block 240 from an outside. The power supply control circuit 200 can control states of the plurality of power sources 101_1 to 101_4 by changing a value of the register block 240 from the outside, and the PMU220 is configured to be able to execute an instruction to change the value of the register block 240.SELECTED DRAWING: Figure 2

Description

The present invention relates to a power management technique for managing and controlling a plurality of power sources.

Mobile phones, tablet terminals, notebook personal computers (PCs), desktop PCs, and game devices are provided with microprocessors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) that perform arithmetic processing.

Electronic devices equipped with microprocessors are subdivided into dozens of circuit blocks due to the miniaturization of semiconductor manufacturing processes, the increase in peripheral circuits to be mounted, and the demand for low power consumption, and each circuit block is independent. The power supply voltage can be controlled.

In such equipment, power control circuits are used to control dozens of power grids corresponding to dozens of circuit blocks. The power supply control circuit is required to reliably control the on / off of a plurality of power supplies according to a predetermined sequence.

The power control circuit includes a state machine capable of transitioning a plurality of states. Each state has a different combination of power on / off and output voltage level. When a predetermined event occurs, the sequencer executes an instruction corresponding to the event and changes the state of the state machine. Instructions include turning each power supply on and off, changing the output voltage setting, and so on.

Japanese Unexamined Patent Publication No. 2013-089600 JP 2015-195690

There is a demand that a designer of an electronic device (set) equipped with a power supply control circuit wants to dynamically use a state different from a predetermined state in the power supply control circuit.

In order to meet this demand, the present inventor has studied an architecture in which a plurality of power supply states (for example, on, off, and voltage level) can be changed by external register access, apart from control by a sequencer.

For example, it is assumed that the set value of the output voltage of an arbitrary power supply can be changed by register access (user control) from the outside. In this case, the following problems occur.

FIG. 1 is a diagram for explaining problems associated with user control. Consider the following two states. For the sake of simplicity, it is assumed that there are two power supplies A and B, and the three states S0, S1 and S2 are defined as follows.
S0 = 2 power supplies A and B are off (disabled)
S1 = Only power supply A is on (enabled)
S2 = Both power supplies A and B are on

Further, it is assumed that the on / off of each of the power supplies A and B and the set value of the output voltage of the power supply A in the state S1 can be controlled by register access (user control). The register that specifies the output voltage of the power supply A in S1 is referred to as VOUT_A1.

Is the state S0 is prior to the time _{T 0.} At time T _0, an event which is a transition trigger to the state S1 occurs, the sequencer turns on the power supply A. At this time, the output voltage of the power supply A is the initial value (1.0V) of the set value stored in the register VOUT_A1.

At time T _1, the register access from the outside, the value of the setting register of the output voltage of the power supply A is changed (1.1V). As a result, the voltage level of the output voltage of the power supply A changes to 1.1V. This state is referred to as S1'.

At time T _2, when the event that the transition trigger to the state S2 occurs, the sequencer further to turn on the power B. The voltage level of the output voltage of the power supply A is changed to the set value (1.2V) in the state S2.

At time T _3, the event to be a transition trigger from state S2 to S1 is generated. The sequencer turns off the power supply B and changes the output voltage of the power supply A to the set value of the register VOUT_A1, but since the set value at this time is 1.1 V, the state after the transition should be S1. , S1'instead of S1, resulting in inconsistency.

In this way, if user control and event-driven state transitions coexist, the correct voltage cannot be supplied to the load.

The present invention has been made in such a situation, and one of the exemplary purposes of an embodiment thereof is to provide a power control circuit and a PMIC with enhanced robustness.

One aspect of the present invention relates to a power supply control circuit. The power supply control circuit controls the state of a plurality of power supplies. The power supply control circuit includes a non-volatile memory that stores multiple instruction groups corresponding to multiple events, a sequencer that executes the corresponding instruction groups when one of the multiple events occurs, and controls multiple power supplies. It includes a register block and an interface circuit for accessing the register block from the outside. The power supply control circuit is configured so that the state of a plurality of power supplies can be controlled by changing the value of the register block from the outside, and the sequencer can execute an instruction for changing the value of the register block.

According to this aspect, assuming that the register value is changed by the register block from the outside, the value of the register is written back to the expected value in the state after the transition in the instruction group corresponding to each event. Instructions can be included. As a result, conflicts and inconsistencies between user control and sequence control due to register access can be resolved, and robustness can be improved.

The register block may include a voltage setting register to specify the voltage level of a particular power supply in a particular state. The power control circuit may support an instruction to change the value of the voltage setting register.

The register block may include an enable setting register for designating a specific power on / off. The power control circuit may support an instruction to change the value of the enable setting register.

The power supply control circuit may be configured to be switchable between a mode in which a specific power supply is turned on and off based on the value of the enable setting register and a mode in which the power supply is controlled by a sequencer. The register block may include a mode setting register for designating a mode. The power control circuit may support an instruction to change the value of the mode setting register.

The sequencer includes at least a first state in which the plurality of power supplies are all off, a second state in which some of the power supplies are on, and a third state in which the power supplies are all on. It may include a state machine.

Another aspect of the invention relates to a power management circuit. The power management circuit includes a plurality of power supplies and any of the above-mentioned power management circuits that control the plurality of power supplies. The power management circuit may be integrally integrated on one semiconductor substrate.

Another aspect of the invention relates to electronic devices. The electronic device includes a processor having a plurality of power supply terminals and the above-mentioned power management circuit for supplying a power supply voltage to the plurality of power supply terminals of the processor.

Another aspect of the invention relates to electronic devices. The electronic device may include a processor having a plurality of power supply terminals and the above-mentioned power management circuit for supplying a power supply voltage to the plurality of power supply terminals of the processor.

It should be noted that any combination of the above components and those in which the components and expressions of the present invention are mutually replaced between methods, devices, systems and the like are also effective as aspects of the present invention.

According to an aspect of the present invention, the robustness of the power supply control circuit and the PMIC can be enhanced.

It is a figure explaining the problem with user control. FIG. 5 is a block diagram of a power management circuit including a power control circuit according to the first embodiment. It is a state transition diagram of PMU of FIG. It is a time chart at the time of power-on. It is a time chart when the power is turned off. It is a time chart when transitioning in the order of the third state S3-second state S2-third state S3. It is a time chart when a user control occurs during the transition in the order of the third state S3-second state S2-third state S3. It is a block diagram of the PMIC which concerns on Embodiment 2. FIG. It is a time chart explaining the operation of the PMIC of FIG. It is a perspective view of the electronic device provided with a PMIC.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via another member that does not affect the connection state. Further, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also an electrical connection. It also includes the case of being indirectly connected via other members that do not affect the state.

(Embodiment 1)
FIG. 2 is a block diagram of a power management circuit (hereinafter, referred to as PMIC: Power Management IC) 100 including the power control circuit 200 according to the first embodiment. The PMIC 100 is a functional IC including a plurality of (N) power supplies 101_1 to 101_N and a power supply control circuit 200 for controlling them, and the main parts thereof are integrated on one semiconductor substrate. Some of the plurality of power supplies 101 are step-down, step-up or buck-boost type DC / DC converters, and some of the plurality of power supplies 101 are LDO regulators. Hereinafter, assuming that N = 4, the power supplies 101_1 and 101_2 are referred to as DCDC1, DCDC2, and the power supplies 101_3, 101_4 are referred to as LDO1 and LDO2.

The inductor, output capacitor, switching transistor, and synchronous rectifying transistor, which are components of the DC / DC converter, may be externally attached to the PMIC 100. The output capacitor, which is a component of the LDO regulator, may be externally attached to the PMIC 100.

The power control circuit 200 includes a non-volatile memory 210, a memory 212, a power management unit (PMU: Power Manegement Unit) 220, an interface circuit 230, and a register block 240.

The power supply control circuit 200 supports state control (user control) by register access in addition to state transition by event drive.

The non-volatile memory 210 stores a plurality of instruction groups (also referred to as sequences) corresponding to a plurality of events that trigger state transitions. This instruction group is loaded into the memory 212 and can be executed by the PMU 220.

The instruction group is programmed by the designer, compiled, and written to the non-volatile memory 210 at the design stage of the PMIC 100. The non-volatile memory 210 may be a mask ROM, an OTP (One Time Programmable) ROM such as a fuse ROM (Read Only Memory) or an anti-fuse ROM, or an EPROM (Erasable Programmable Read Only Memory). It may be.

The PMU 220 includes a sequencer and a state machine. When one of the plurality of events occurs, the sequencer of the PMU 220 executes a group of instructions corresponding to the event and controls a plurality of power supplies 101_1 to 101_N.

In the following description, it is assumed that the PMIC 100 includes two systems of DC / DC converters DCDC1 and DCDC2 and two systems of LDO regulators LDO1 and LDO2.

Further, the state machine of the PMU 220 can take the following three states.
・ First state S1
All power supplies 101_1 to 101_4 are off

・ Second state S2
Power supply 101_1, 101_2 is on, 101_3, 101_4 is off

・ Third state S3
Power supplies 101_1 to 101_4 are all on

The PMU 220 may support more states.

FIG. 3 is a state transition diagram of the PMU 220 of FIG. The event that triggers the transition from the i-th state Si to the j-th state Sj (i, j ∈ (1, 2, 3), i ≠ j) is expressed as EVTij. Further, the instruction group executed when transitioning from the i-th state Si to the j-th state Sj (i, j ∈ (1, 2, 3), i ≠ j) is expressed as SEQij.

Return to FIG. The register block 240 includes a plurality of registers. The register block 240 can include a register for storing a set value of an output voltage in a predetermined state for each of the plurality of power supplies 101_1 to 101_4.

In the present embodiment, the register block 240 includes voltage setting registers DCDC1_VOLT_S2 and DCDC1_VOLT_S3 that store voltage setting values of the DC / DC converter DCDC1 in the second state S2 and the third state S3.

The register block 240 includes voltage setting registers LDO1_VOLT_S3 and LDO2_VOLT_S3 that store voltage setting values of the LDO regulators LDO1 and LDO2 in the third state S3.

The electronic device 300 incorporating the PMIC 100 is provided with a user interface 302 and a host controller 304. The host controller 304 is a CPU (Central Processing Unit) or a microcomputer that integrally controls the electronic device 300. The user interface 302 may include a power button, a reset button, and the like of the electronic device 300.

The user interface 302 and the host controller 304 generate an event that triggers the state transition. For example, pressing the power button or reset button can be an event that triggers a state transition.

The interface circuit 230 is provided to access the register block 240 from the external host controller 304. The type of interface is not particularly limited, but for example, an I ² C (Inter IC) interface or an SPI (Serial Peripheral Interface) may be used.

The register block 240 may include a register (referred to as a trigger register) that triggers a state transition. The PMU 220 monitors the register block 240, and the fact that the host controller 304 changes the value of the trigger register (event) can be used as a trigger for the state transition.

Further, the host controller 304 knows the addresses of the voltage setting registers DCDC1_VOLT_S2, DCDC1_VOLT_S3, LDO1_VOLT_S3, LDO2_VOLT_S3 of the register block 240, and can rewrite those values (user control).

In this way, the power supply control circuit 200 can control the states of the plurality of power supplies 101_1 to 101_N by changing the value of the register block 240 by the external host controller 304.

Subsequently, the instructions supported by the power supply control circuit 200 will be described.

-Enable instruction (turn-on instruction)
This is an instruction to turn on each power supply after the lapse of the specified time t. As described here, a separate enable instruction may be prepared for each power supply.
・ ON_DCDC1 (t0)
After t0 has elapsed, the DC / DC converter DCDC1 (101_1) is turned on. ・ ON_DCDC2 (t1)
After t1 has elapsed, the DC / DC converter DCDC2 (101_2) is turned on. ・ ON_LDO1 (t3)
After t3 has elapsed, the LDO regulator LDO1 (101_3) is turned on. ・ ON_LDO2 (t4)
After t4, turn on the LDO regulator LDO2 (101_4).

-Disable instruction (turn-off instruction)
This is a command to turn off each power supply after the specified time has elapsed. As shown here, a separate disable instruction may be prepared for each power supply.
・ OFF_DCDC1 (t9)
After t9 has elapsed, the DC / DC converter DCDC1 (101_1) is turned off. ・ OFF_DCDC2 (t8)
After t8 has elapsed, the DC / DC converter DCDC2 (101_2) is turned off. ・ OFF_LDO1 (t6)
After t6 has elapsed, the LDO regulator LDO1 (101_3) is turned off. ・ OFF_LDO2 (t5)
After t5, turn off the LDO regulator LDO2 (101_4).

The enable instruction and disable instruction may be common to all power supplies, and the power supply identification number may be given as an argument (parameter). Further, the standby time setting may be separated from the enable instruction and the disable instruction, and a separate standby instruction may be prepared.

-Voltage change command In this example, the voltage of the DC / DC converter DCDC1 is set separately in the second state S2 and the third state S3. Therefore, in the state transition between them, an instruction to change the voltage value of the DC / DC converter DCDC1 is prepared.
・ CHANGE_DCDC1_S3 (t2)
After t2 has elapsed, the output voltage of the DC / DC converter DCDC1 is changed to the value of the voltage setting register DCDC1_VOLT_S3.

・ CHANGE_DCDC1_S2 (t7)
After t7 elapses, the output voltage of the DC / DC converter DCDC1 is changed to the value of the voltage setting register DCDC1_VOLT_S2.

-Register change instruction This is an instruction to write the specified value to a specific register. The register change instruction may be prepared for each specific register. Alternatively, a general-purpose instruction may be prepared so that the value of an arbitrary register can be changed by giving the address of a register as an argument. By supporting this register change instruction, the power supply control circuit 200 allows the PMU 220 to change the value of the register block 240.

In this embodiment, an instruction to change the values of the voltage setting registers DCDC1_VOLT_S2, DCDC1_VOLT_S3, LDO1_VOLT_S3, and LDO2_VOLT_S3 is supported.
-SET_DCDC1_VOLT_S2 (v1)
Change the value of DCDC1_VOLT_S2 to v1 ・ SET_DCDC1_VOLT_S3 (v2)
Change the value of DCDC1_VOLT_S3 to v2 ・ SET_LDO1_VOLT_S3 (v3)
Change the value of LDO1_VOLT_S3 to v3 ・ SET_LDO2_VOLT_S3 (v4)
Changed the value of LDO2_VOLT_S3 to v4

The above is the configuration of the PMIC 100. Next, the operation will be described.

FIG. 4 is a time chart when the power is turned on. The initial state is the first state S1 in which all power supplies are off. At time T _1, an event that triggers a transition to state S2 occurs. As a result, the instruction group SEQ12 for transitioning from the state S1 to S2 is executed. This instruction group SEQ12 includes the following instructions.

(I) SET_DCDC1_VOLT_S2 (V1)
By this instruction, it is guaranteed that the output voltage of the DC / DC converter DCDC1 becomes the default set value v1 before the transition to the second state S2.
(Ii) ON_DCDC1 (t0)
By this instruction, the DC / DC converter DCDC1 is turned on after the lapse of time t0.
(Iii) ON_DCDC2 (t1)
By this instruction, the DC / DC converter DCDC2 is turned on after the lapse of time t1.
When the execution of the instruction group SEQ12 is completed, the second state S2 is entered.

Events that trigger the transition to the state S3 occurs at time T _2. As a result, the instruction group SEQ23 for transitioning from the state S2 to S3 is executed. This instruction group SEQ23 includes the following enable instructions.
(2) Instruction group SEQ23 when transitioning from the second state S2 to the third state S3
(I) SET_DCDC1_VOLT_S3 (v2)
(Ii) SET_LDO1_VOLT_S3 (v3)
(Iii) SET_LDO2_VOLT_S3 (v4)
These instructions guarantee that the output voltages of the DC / DC converter DCDC1, the LDO regulators LDO1 and the LDO2 will be their default set values v2 to v4 before transitioning to the third state S3.
(Iv) CHANGE_DCDC1_S3 (t2)
By this instruction, after the lapse of time t2, the output voltage of the DC / DC converter DCDC1 is changed to a voltage level corresponding to DCDC1_VOLT_S3.
(V) ON_LDO1 (t3)
After the elapse of t3, the LDO regulator LDO1 is turned on.
(Vi) ON_LDO2 (t4)
When the execution of the instruction group SEQ23 is completed, the third state S3 is set. The above is the sequence when the power is turned on.

FIG. 5 is a time chart when the power is turned off. The initial state is the third state S3 in which all power is on. At time T _1, an event that triggers a transition to state S2 occurs. As a result, the instruction group SEQ 32 for transitioning from the state S3 to S2 is executed. This instruction group SEQ 32 includes the following instructions.
(I) SET_DCDC1_VOLT_S2 (v1)
By this instruction, it is guaranteed that the output voltage of the DC / DC converter DCDC1 becomes the default set value v1 before the transition to the second state S2.
(Ii) OFF_LDO2 (t5)
(Iii) OFF_LDO1 (t6)
By these commands, the LDO regulator LDO2 is turned off after the lapse of time t5, and the LDO regulator LDO1 is turned off after the lapse of time t6.
(Iv) CHANGE_DCDC1_S2 (t7)
By this instruction, after the lapse of time t7, the output voltage of the DC / DC converter DCDC1 is changed to a voltage level corresponding to DCDC1_VOLT_S2.
When the execution of the instruction group SEQ 32 is completed, the second state S2 is entered.

At time T _2, the event that triggers a transition to state S1 is generated. As a result, the instruction group SEQ21 for transitioning from the state S2 to S1 is executed. This instruction group SEQ21 includes the following instructions.
(I) OFF_DCDC2 (t8)
(Ii) OFF_DCDC1 (t9)
By these instructions, the DC / DC converter DCDC2 is turned off after the lapse of time t8, and then the DC / DC converter DCDC1 is turned off after the lapse of time t9. When the execution of the instruction group SEQ21 is completed, the first state S1 is set.

FIG. 6 is a time chart when transitioning in the order of the third state S3-second state S2-third state S3. The initial state is the third state S3. At time T _1, an event that triggers a transition to state S2 occurs. As a result, the instruction group SEQ 32 for transitioning from the state S3 to S2 is executed. At time T _2, the event that triggers the transition to the state S3 occurs. As a result, the instruction group SEQ23 for transitioning from the state S2 to S3 is executed.

FIG. 7 is a time chart when user control occurs during the transition in the order of the third state S3-second state S2-third state S3. At time T ₀ , the value of the voltage setting register DCDC1_VOLT_S2 is rewritten from 1.2V to 1.3V by user control (register access from the host controller 304). In response, the PMU 220 changes the output voltage of the DC / DC converter DCDC1 to a voltage level of 1.3V according to DCDC1_VOLT_S2.

Instructions SEQ32 time _{T 1} is being executed, a transition to the second state S2. Are instructions SEQ23 to time _{T 2,} is executed by the instruction SET_DCDC1_VOLT_S2 (V1) it contains, the value of DCDC1_VOLT_S3 is reset to the default value 1.2V. Then, the instruction CHANGE_DCDC1_S3 (t2) executed after the lapse of time t2 guarantees that the output voltage of the DC / DC converter DCDC1 returns to the correct voltage value of 1.2V.

The above is the operation of the PMIC 100. According to this PMIC 100, when the voltage value of a certain power supply is changed by user access in a certain state and then returns to the original state after transitioning to another state, the voltage value of the power supply returns to the correct state. We can guarantee that.

(Embodiment 2)
In the first embodiment, the voltage set value can be changed by user control. In the second embodiment, on or off of each power source can be controlled by user control instead of or in addition to it. FIG. 8 is a block diagram of the PMIC 100A according to the second embodiment. The basic configuration of the PMIC 100A is the same as that of the PMIC 100 of FIG.

In the second embodiment, the register block 240A includes enable setting registers USER_EN1 to USER_EN4 for designating on / off of a specific power supply 101_1 to 101_4.

In addition, for each power supply, it is possible to switch between a register control mode that switches on and off based on the value of the enable setting register USER_EN, and a PMU control mode that specifies whether to switch on and off by a control signal from the PMU 220. Mode setting registers MODE1 to MODE4 for designating each control mode of the power supplies 101_1 to 101_4 are prepared.

The PMU 220 generates control signals PMU_EN1 to PMU_EN4 for designating on and off of the plurality of power supplies 101_1 to 101_4, respectively.

The power control circuit 200A includes multiplexers 250_1 to 250_4. The multiplexer 250_ # receives the control signal PMU_EN # generated by the PMU 220 and the corresponding register USER_EN # of the register block 240A, and selects one according to the value of the corresponding mode setting register MODE #.

The PMIC 100A supports an instruction SET_USER_EN # that changes the value of the enable setting register USER_EN # and an instruction SET_MODE # that changes the value of the mode setting register MODE #. Any instruction group can include these instructions.

FIG. 9 is a time chart illustrating the operation of the PMIC 100A of FIG. Here, attention is paid to the operation of the power supply 101_3 (LDO1).

At time T _1, an event that triggers a transition to state S2 occurs. As a result, the instruction group SEQ 32 for transitioning from the state S3 to S2 is executed. The power supply 101_3 is turned off by this instruction group SEQ32.

In the second state S2 subsequent user control occurs at time _{T 2,} power 101_3 is switched on.

At time T _3, the event that triggers a transition to state S1 is generated. As a result, the instruction group SEQ21 for transitioning from the state S2 to S1 is executed. This instruction group SEQ21 includes an instruction to reset the registers MODE3 and USER_EN3 to zero. The reset instruction, when executed at time _{T 4,} the control power supply 101_3 is delegated to PMU 220, the power supply 101_3 is guaranteed to be off.

Time T ₅ after is a start sequence described above, the transition in order until the third state S3.

The above is the operation of the power supply control circuit 200A. According to this power supply control circuit 200A, it is possible to prevent inconsistency between power on and off.

(Use)
Finally, the use of the PM controller 100 will be described. FIG. 10 is a perspective view of an electronic device 500 including the PMIC 200. The electronic device 500 is, for example, a tablet terminal or a smartphone. The housing 520 contains a CPU 502, a RAM 504, an HDD 506, a battery 508, and a PMIC 200. In the PMIC 200, the display panel 510 may supply a power supply voltage to its driver, audio circuit, and the like. The electronic device 500 may be a notebook PC, a console game device, a portable game device, a wearable PC, a portable audio player, a digital camera, or the like.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

300 Electronic Equipment 302 User Interface 304 Host Controller 100 PMIC
101 power supply 200 power supply control circuit 210 non-volatile memory 212 memory 220 PMU
230 Interface Circuit 240 Register Block 250 Multiplexer 500 Electronic Equipment 502 CPU
504 RAM
506 HDD
508 battery

Claims (8)

A power supply control circuit that controls the state of multiple power supplies.
Non-volatile memory that stores multiple instruction groups corresponding to multiple events,
When one of the plurality of events occurs, the sequencer that executes the corresponding instruction group and controls the plurality of power supplies,
Register block and
An interface circuit for accessing the register block from the outside,
With
The power supply control circuit can control the state of the plurality of power supplies by changing the value of the register block from the outside, and the sequencer can execute an instruction for changing the value of the register block. A power control circuit characterized by being configured. The register block includes a voltage setting register for specifying a voltage level of a particular power supply in a particular state.
The power supply control circuit according to claim 1, wherein the power supply control circuit supports an instruction for changing a value of the voltage setting register. The register block contains an enable setting register for designating a specific power on / off.
The power supply control circuit according to claim 1, wherein the power supply control circuit supports an instruction for changing the value of the enable setting register. The power supply control circuit is configured to be switchable between a mode in which the specific power supply is turned on and off based on the value of the enable setting register and a mode in which the sequencer controls the power supply.
The register block includes a mode setting register for designating the mode.
The power supply control circuit according to claim 3, wherein the power supply control circuit supports an instruction for changing the value of the mode setting register. The sequencer is at least
The first state in which all of the plurality of power supplies are off, and
A second state in which some of the plurality of power supplies are on, and
The third state in which the plurality of power supplies are all on, and
The power supply control circuit according to any one of claims 1 to 4, further comprising a state machine that transitions between. With multiple power supplies
The power supply control circuit according to any one of claims 1 to 5, which controls the plurality of power supplies.
A power management circuit characterized by being equipped with. The power management circuit according to claim 6, wherein the power management circuit is integrally integrated on one semiconductor substrate. With a processor that has multiple power terminals,
The power management circuit according to claim 6 or 7, which supplies a power supply voltage to a plurality of power supply terminals of the processor.
An electronic device characterized by being equipped with.

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