JP2020161738A - Group iii nitride semiconductor element and manufacturing method of the same - Google Patents

Abstract

To provide a group iii nitride semiconductor element with a high breakdown voltage performance.SOLUTION: A group iii nitride semiconductor element comprises: a substrate 101 formed by a single crystal substance expressed by a general formula of RAMO4; a M containing layer 102 positioned on the substrate 101 and containing an element expressed by M in the generation formula; an n-type layer 103 positioned on the M containing layer 102; and a drain electrode 112 penetrating the substrate 101. In the general formula, R expresses one or a plurality of trivalent elements selected from a group of Sc, In, Y, and lanthanoid element, A expresses one or the plurality of trivalent elements selected from a group of Fe(III), Ga, and Al, and M is one or a plurality of bivalent elements selected from a group of Mg, Mn, Fe(II), Co, Cu, Zn, and Cd.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a group III nitride semiconductor device and a method for manufacturing the same.

Group III nitride compound semiconductors represented by gallium nitride (GaN), so-called nitride semiconductors, are attracting attention as materials for new devices such as light emitting diodes (LEDs) and laser diodes (LDs), as well as power devices. .. Nitride semiconductor, for example, the general formula of _{In x Ga y Al 1-x} -y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1), a group III element indium ( It is a compound semiconductor composed of In), gallium (Ga), aluminum (Al), and nitrogen (N), which is a group V element. Hereinafter, the multi-element mixed crystal is abbreviated as an arrangement of each constituent element symbol, for example, AlInN, GaInN, AlGaInN, and the like.

Among them, GaN and AlN are wide-gap semiconductors having a large bandgap of 3.4 eV and 6.2 eV at room temperature, respectively, a large dielectric breakdown electric field, and a compound semiconductor such as GaAs or a Si semiconductor having an electron saturation drift rate. It has the feature that it is larger than the above. For this reason, research and development of a power transistor using a nitride semiconductor which is advantageous for high output and high withstand voltage is currently being actively carried out (see, for example, Patent Document 1 or Patent Document 2).

Japanese Unexamined Patent Publication No. 2012-84417 International Publication No. 2015/122135

In a vertical GaN transistor, the through-dislocation density of the nitride semiconductor layer due to the underlying substrate (also referred to as a seed substrate) may correlate with the withstand voltage of the device. Therefore, a base substrate capable of forming a higher quality nitride semiconductor layer is desired.

In view of the above problems, it is an object of the present disclosure to provide a group III nitride semiconductor device having high withstand voltage performance and a method for manufacturing the same.

Group III nitride semiconductor device according to an embodiment of the present disclosure includes a RAMO ₄ substrate made of single crystal represented by the general formula RAMO _4, located in the RAMO ₄ substrate, represented by M in the general formula It is provided with an M-containing group III nitride layer containing the element, an n-type group III nitride layer located on the M-containing group III nitride layer, and an electrode penetrating the RAMO ₄ substrate. In the above general formula, R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, and A is the group consisting of Fe (III), Ga and Al. Represents one or more trivalent elements selected from, where M is one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd. Represents an element.

Further, in the method for manufacturing a group III nitride semiconductor element according to one aspect of the present disclosure, an element represented by M in the general formula is placed on a RAMO ₄ substrate made of a single crystal represented by the general formula RAMO _4. A step of sequentially laminating an M-containing group III nitride layer contained therein and an n-type group III nitride layer located on the M-containing group III nitride layer, and etching a through hole penetrating the RAMO ₄ substrate. A step of removing the M-containing group III nitride layer exposed in the through hole by etching, and an electrode connected to the n-type group III nitride layer through the through hole. Including the step of forming. In the above general formula, R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, and A is the group consisting of Fe (III), Ga and Al. Represents one or more trivalent elements selected from, where M is one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd. Represents an element.

According to the present disclosure, it is possible to provide a group III nitride semiconductor device having high withstand voltage performance and a method for manufacturing the same.

FIG. 1 is a schematic cross-sectional view showing the structure of the vertical field effect transistor according to the first embodiment. FIG. 2 is a diagram showing a crystal structure of ScAlMgO ₄ . FIG. 3 is a diagram showing the relationship between the lattice mismatch of each material based on GaN and the difference in the coefficient of thermal expansion. FIG. 4 is a diagram showing the relationship between the type of the substrate and the penetration dislocation density of the GaN growth layer. FIG. 5 is a diagram showing the relationship between the cost of the base substrate and the penetration dislocation density of the GaN growth layer. FIG. 6 is a diagram showing the relationship between the through-dislocation density and the withstand voltage in a GaN-based vertical field effect transistor. FIG. 7 is a diagram showing an impurity concentration profile of the nitride semiconductor layer and the underlying substrate in the field effect transistor according to the embodiment. FIG. 8A is a diagram showing the relationship between the impurity concentration in GaN and the lattice constant of GaN. Figure 8B is a diagram showing the relationship between lattice mismatch with respect to the impurity concentration and ScAlMgO ₄ in GaN. FIG. 9 is a TEM image of the vicinity of the interface between ScAlMgO ₄ and the Mg-containing GaN layer. FIG. 10 is a schematic cross-sectional view showing the structure of the group III nitride semiconductor element according to the modified example of the embodiment.

(Summary of this disclosure)
Group III nitride semiconductor device according to an embodiment of the present disclosure includes a RAMO ₄ substrate made of single crystal represented by the general formula RAMO _4, located in the RAMO ₄ substrate, represented by M in the general formula It includes an M-containing group III nitride layer containing the elements, an n-type group III nitride layer located on the M-containing group III nitride layer, and an electrode penetrating the RAMO ₄ substrate. In the above general formula, R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, and A is the group consisting of Fe (III), Ga and Al. Represents one or more trivalent elements selected from, where M is one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd. Represents an element.

With this configuration, a high-quality nitride semiconductor layer can be formed on the RAMO ₄ substrate, and a group III nitride semiconductor element having a high withstand voltage can be realized. The group III nitride semiconductor device is, for example, a GaN-based vertical field effect transistor.

It should be noted that the cost of the GaN substrate itself is very high for the vertical GaN transistor using the conductive GaN substrate having the conventional configuration, and the price of the device chip does not fall into the popular price range. There is a problem that the usage does not spread. Efforts to reduce the cost of the GaN substrate itself are being energetically carried out mainly by substrate manufacturers, but it takes a considerable amount of time to significantly reduce the cost. Therefore, there is a demand for group III nitride semiconductor devices by using a base substrate other than the GaN substrate.

On the other hand, in one aspect of the present disclosure, the RAMO ₄ substrate is used as the substrate. As a result, it is possible to realize a group III nitride semiconductor device that can achieve both cost reduction and improvement in withstand voltage performance.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, even if the electrode penetrates the M-containing group III nitride layer and is connected to the n-type group III nitride layer. Good.

With this configuration, a GaN-based vertical field effect transistor in which a current flows in the vertical direction can be realized.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the R may be Sc, the A may be Al, and the M may be Mg.

This configuration, the ScAlMgO ₄ substrate closer to GaN in lattice constant by using as a base substrate, can be realized vertical GaN-based FET of low dislocation density.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the M-containing group III nitride layer has a region in which the content concentration of the element represented by M is 10 ²⁰ cm- ³ units. May include.

This configuration makes it possible to further reduce the lattice mismatch between the ScAlMgO ₄ substrate and the nitride semiconductor layer, it is possible to realize a GaN-based vertical field effect transistor of the low dislocation density.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the thickness of the M-containing group III nitride layer is 50 nm or more and 2000 nm or less, and the M-containing group III nitride layer is p. It may be a type conductive layer or a high resistance layer.

This configuration makes it possible to form an electrode which penetrates the M-containing III-nitride layer can be realized vertical GaN-based field effect transistor with ScAlMgO ₄ substrate having no conductivity.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the n-type III nitride layer contains Si or O as an n-type dopant, and the n-type III nitride layer contains Si or O as an n-type dopant. The content concentration of the n-type dopant may be larger than the content concentration of the element represented by M.

With this configuration, the n-type group III nitride layer can be made into a low-resistance n-type conductive layer, and a high-performance GaN-based vertical field-effect transistor can be realized.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the thickness of the RAMO ₄ substrate may be 50 μm or more and 400 μm or less.

With this configuration, the strength of the device chip can be maintained while forming an electrode penetrating the RAMO ₄ substrate, and a high-performance GaN-based vertical field effect transistor can be realized.

Further, for example, in the group III nitride semiconductor device according to one aspect of the present disclosure, the through-dislocation density on the outermost surface of the nitride semiconductor layer including the n-type group III nitride layer is 1 × 10 ⁸ cm- ^2. It may be as follows.

Since the through-dislocation density is reduced by this configuration, a GaN-based vertical field effect transistor having high withstand voltage performance can be realized.

Further, the method for manufacturing a group III nitride semiconductor device according to one aspect of the present disclosure includes an element represented by M in the general formula on a substrate made of a single crystal represented by the general formula RAMO _4. A step of sequentially laminating an M-containing group III nitride layer and an n-type III-nitride layer located on the M-containing group III nitride layer, and forming a through hole penetrating the RAMO ₄ substrate by etching. The step of removing the M-containing group III nitride layer exposed in the through hole by etching, and forming an electrode connected to the n-type group III nitride layer through the through hole. Includes steps.

With this configuration, a high-quality nitride semiconductor layer can be formed on the RAMO ₄ substrate, and a group III nitride semiconductor element having a high withstand voltage can be manufactured. For example, even in the case of using ScAlMgO ₄ substrate having no conductivity, it is possible to realize a vertical GaN-based field effect transistor.

Further, for example, in the method for producing a group III nitride semiconductor device according to one aspect of the present disclosure, in the step of forming the through holes by etching, a mixed solution of sulfuric acid and hydrogen peroxide solution was heated to 50 ° C. or higher. The step of performing the etching may be performed by immersing the RAMO ₄ substrate in the etching solution.

With this configuration, a through hole is formed in the thick RAMO ₄ substrate, and a GaN-based vertical field effect transistor can be realized.

Hereinafter, embodiments will be specifically described with reference to the drawings.

It should be noted that all of the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, manufacturing processes, order of manufacturing processes, etc. shown in the following embodiments are examples, and are not intended to limit the present disclosure. Further, among the components in the following embodiments, the components not described in the independent claims will be described as arbitrary components.

Further, each figure is a schematic view and is not necessarily exactly illustrated. Therefore, for example, the scales and the like do not always match in each figure. Further, in each figure, substantially the same configuration is designated by the same reference numerals, and duplicate description will be omitted or simplified.

Further, in the present specification, a term indicating a relationship between elements such as parallel, coincident or uniform, a term indicating an element shape such as a rectangle or a trapezoid, and a numerical range are expressions expressing only strict meanings. Rather, it is an expression that means that a substantially equivalent range, for example, a difference of about several percent is included.

Further, in the present specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking configuration. It is used as a term defined by the relative positional relationship with. Also, the terms "upper" and "lower" are used not only when the two components are spaced apart from each other and another component exists between the two components, but also when the two components It also applies when the two components are placed in close contact with each other and touch each other.

(Embodiment)
[Constitution]
First, the configuration of the group III nitride semiconductor device according to the embodiment will be described with reference to FIG.

FIG. 1 is a schematic cross-sectional view showing the structure of the vertical field effect transistor 100 according to the embodiment. The field effect transistor 100 is an example of a group III nitride semiconductor device. As shown in FIG. 1, the field effect transistor 100 includes a substrate 101, an M-containing layer 102, an n-type layer 103, a drift layer 104, a first base layer 105, a second base layer 106, and a second base layer 106. 3 Underlayer 107, 1st regrowth layer 108, 2nd regrowth layer, 3rd regrowth layer 109, gate electrode 110, source electrode 111, drain electrode 112, gate opening 113, It is provided with a through hole 114. In FIG. 1, the second regrowth layer is located between the first regrowth layer 108 and the third regrowth layer 109, but its description is omitted because the layer thickness is thin.

The field effect transistor 100 is a device having a laminated structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the field effect transistor 100 has a heterostructure of an AlGaN film and a GaN film.

In the heterostructure of the AlGaN film and the GaN film, a high concentration of two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is generated at the hetero interface by spontaneous polarization or piezo polarization on the (0001) plane. Therefore, even in the undoped state, the interface has a characteristic that a sheet carrier concentration of 1 × 10 ¹³ cm- ² or more can be obtained.

The field effect transistor 100 according to the present embodiment is a field effect transistor (FET) that utilizes the two-dimensional electron gas layer 115 generated at the hetero interface of AlGaN / GaN as a channel. Specifically, the field effect transistor 100 is a so-called vertical FET.

For example, the field effect transistor 100 is a normally-off type FET. For example, the source electrode 111 is grounded (that is, the potential is 0 V), and the drain electrode 112 is given a positive potential. The potential given to the drain electrode 112 is, for example, 100 V or more and 1200 V or less, but is not limited to this. When the field effect transistor 100 is in the off state, a zero potential (0V) is applied to the gate electrode 110. When the field effect transistor 100 is in the ON state, a positive potential (for example, + 5V) is applied to the gate electrode 110.

Hereinafter, the details of each component included in the field effect transistor 100 according to the present embodiment will be described.

The substrate 101 is a RAMO ₄ substrate made of a single crystal represented by the general formula RAMO ₄ . The main surface of the substrate 101 coincides with the c-plane ((0001) plane). The thickness of the substrate 101 is, for example, 50 μm or more and 400 μm or less, and 100 μm as an example. The plan view shape of the substrate 101 is, for example, a rectangle, but is not particularly limited. The substrate 101 does not have conductivity. That is, the substrate 101 is an insulating substrate having a sufficiently higher electrical resistance than the n-type layer 103 and the drift layer 104.

In the general formula RAMO ₄ , R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements. A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al. M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd.

In this embodiment, a ScAlMgO ₄ substrate is used as the substrate 101. That is, R is Sc, A is Al, and M is Mg. ScAlMgO ₄ is one of the oxide crystals represented by the general formula RAMO ₄ , and is a trigonal crystal belonging to the space group R-3m.

The M-containing layer 102 is an example of an M-containing group III nitride layer located on the ScAlMgO ₄ substrate 101 and containing an element represented by M in the general formula RAMO ₄ . That is, the M-containing layer 102 contains the same element as one of the plurality of elements contained in the substrate 101. In the present embodiment, since M is Mg, the M-containing layer 102 is an Mg-containing layer containing Mg. The thickness of the M-containing layer 102 is, for example, 50 nm or more and 2000 nm or less, for example, 0.5 μm (= 500 nm). The M-containing layer 102 includes a region in which the content concentration of the element represented by M is 10 ²⁰ cm- ³ units. The M-containing layer 102 is a p-type conductive layer or a high resistance layer. In addition, 10 ²⁰ cm- ³ units means a range of 10 ²⁰ cm ^-3 or more and less than 10 ²¹ cm ^-3 .

The n-type layer 103 is an example of an n-type Group III nitride layer located on the M-containing layer 102. The n-type layer 103 contains Si or O as an n-type dopant. In the n-type layer 103, the content concentration of the n-type dopant is larger than the content concentration of the element represented by M. The n-type layer 103 is, for example, a layer made of n-type GaN having a thickness of 10 μm and a carrier concentration of 5 × 10 ¹⁸ cm ^-3 .

The drift layer 104 is an n-type nitride semiconductor layer located on the n-type layer 103. The drift layer 104 is, for example, a layer made of n-type GaN having a thickness of 5 μm and a carrier concentration of 1 × 10 ¹⁶ cm ^-3 .

The first base layer 105 is an example of a p-type nitride semiconductor layer located on the drift layer 104. The first base layer 105 is, for example, a layer made of p-type GaN having a thickness of 400 nm and a carrier concentration of 1 × 10 ¹⁷ cm ^-3 . The first base layer 105 suppresses a leak current between the source electrode 111 and the drain electrode 112. For example, when a reverse voltage is applied to the pn junction formed by the first base layer 105 and the drift layer 104, specifically, when the drain electrode 112 has a higher potential than the source electrode 111. In addition, a depletion layer extends to the drift layer 104. This makes it possible to increase the withstand voltage of the field effect transistor 100.

The second base layer 106 is an example of a nitride semiconductor layer located on the first base layer 105. The second base layer 106 has a higher resistance than the first base layer 105. Specifically, the second base layer 106 is formed of an insulating or semi-insulating nitride semiconductor. The second base layer 106 is, for example, a layer made of C (carbon) -doped high-resistance GaN having a thickness of 200 nm.

The third base layer 107 is an example of a nitride semiconductor layer located on the second base layer 106. The third base layer 107 is, for example, a layer made of undoped GaN having a thickness of 200 nm. The term "undoped" means that a dopant such as Si or Mg that changes the polarity of GaN to n-type or p-type is not intentionally doped.

In the second base layer 106 and the third base layer 107, a parasitic npn structure is formed by the first regrowth layer 108 including the channel, the p-type first base layer 105, and the n-type drift layer 104. Suppress. As a result, it is possible to suppress the occurrence of malfunction of the field effect transistor 100.

The gate opening 113 is an opening that reaches the drift layer 104 from the upper surface side of the third base layer 107 through the third base layer 107, the second base layer 106, and the first base layer 105 in this order. The gate opening 113 is formed so that the opening area becomes larger as the distance from the substrate 101 increases. Specifically, the side surface of the gate opening 113 is inclined obliquely with respect to the main surface of the substrate 101. That is, the cross-sectional shape of the gate opening 113 has an inverted trapezoidal shape as shown in FIG. The cross-sectional shape of the gate opening 113 may be rectangular.

The first regrowth layer 108 is a nitride semiconductor layer provided along the bottom surface and side surfaces of the gate opening 113 so as to cover the gate opening 113. Specifically, the first regrowth layer 108 is formed inside the gate opening 113 and on the third base layer 107 with a uniform thickness so as to follow the shape of the inner surface of the gate opening 113. For example, the first regrowth layer 108 is a layer made of undoped GaN having a thickness of 100 nm.

The second regrowth layer is a nitride semiconductor layer located on the first regrowth layer 108. The second regrowth layer is provided on the first regrowth layer 108 with a uniform thickness so as to follow the shape of the upper surface of the first regrowth layer 108. The second regrowth layer is, for example, a layer made of undoped AlN having a thickness of 1 nm. The second regrowth layer can suppress alloy scattering and improve the mobility of the channel. The field effect transistor 100 does not have to include the second regrowth layer.

The third regrowth layer 109 is a nitride semiconductor layer located on the second regrowth layer. The third regrowth layer 109 is provided on the second regrowth layer with a uniform thickness so as to follow the shape of the upper surface of the second regrowth layer. The third regrowth layer 109 is, for example, a layer made of undoped Al _0.2 Ga _0.8 N having a thickness of 50 nm.

A two-dimensional electron gas layer 115 is formed at the interface between the first regrowth layer 108 and the second regrowth layer. The two-dimensional electron gas layer 115 forms an electron traveling layer (channel layer) of the field effect transistor 100. The third regrowth layer 109 functions as an electron supply layer that supplies electrons to the channel layer. The main surface and the inclined surface of the first regrowth layer 108, the second regrowth layer, and the third regrowth layer 109 are parallel to each other.

The gate electrode 110 is located on the third regrowth layer 109 so as to cover the gate opening 113. As shown in FIG. 1, the width of the gate electrode 110 is larger than the width of the gate opening 113. Specifically, in top view, the gate electrode 110 completely covers the gate opening 113. The gate electrode 110 is formed by using a metal material such as Pd. As the material used for the gate electrode 110, a material that is Schottky-connected to the n-type semiconductor can be used, and for example, a nickel (Ni) -based material, a tungsten silicide (WSi), a gold (Au), or the like can be used. Can be done. The gate electrode 110 is shot key connected to the third regrowth layer 109.

The source electrode 111 is located so as to sandwich the gate electrode 110. Specifically, an opening that penetrates the third regrowth layer 109, the second regrowth layer, the first regrowth layer 108, the third base layer 107, and the second base layer 106 and reaches the first base layer 105. The source electrode 111 is formed so as to fill the opening. The source electrode 111 has, for example, a laminated structure of Ti and Al. As the material used for the source electrode 111, a material that is ohmic-connected to the n-type semiconductor can be used. The source electrode 111 is ohmic-connected to the two-dimensional electron gas layer 115.

The through hole 114 penetrates the substrate 101. Specifically, the through hole 114 penetrates the substrate 101 and the M-containing layer 102 from the lower surface of the substrate 101 and reaches the n-type layer 103. That is, the n-type layer 103 is exposed as the bottom surface in the through hole 114. As shown in FIG. 1, the width of the through hole 114 is larger than the width of the gate opening 113. Further, the width of the through hole 114 is larger than the width of the gate electrode 110. Specifically, in the bottom view, the entire gate opening 113 and the gate electrode 110 are located inside the through hole 114. The bottom view shape of the through hole 114 may match the bottom view shape of the gate electrode 110 or the gate opening 113. Alternatively, in bottom view, the entire through hole 114 may be located inside the gate electrode 110 or the gate opening 113.

The drain electrode 112 is an electrode that penetrates the substrate 101. Specifically, the drain electrode 112 penetrates the substrate 101 and the M-containing layer 102. More specifically, the drain electrode 112 is provided along the inner surface of the through hole 114, and is connected to the n-type layer 103 exposed in the through hole 114. The drain electrode 112 has, for example, a laminated structure of Ti and Au. As the material used for the drain electrode 112, a material that is ohmic-connected to the n-type semiconductor can be used. The drain electrode 112 is ohmic-connected to the n-type layer 103.

An example of the configuration of the substrate and each semiconductor layer included in the field effect transistor 100 shown in FIG. 1 is shown in Table 1 below.

In the present specification, the “nitride semiconductor” means a structure composed of any one of GaN, AlN and InN, or a mixture thereof. The main surface of each nitride semiconductor layer formed by crystal growth from the substrate 101 is the c-plane. Further, for each of the above semiconductor layers, the n-type conductive type is formed by adding Si or O. The p-type conductive type is formed by adding Mg.

[Crystal structure of ScAlMgO ₄ ]
As described above, in the present embodiment, as the substrate 101, a substrate made of ScAlMgO _4, which is an example of a single crystal represented by the general formula RAMO ₄ , is used. Here, the crystal structure of ScAlMgO ₄ will be described with reference to FIG.

FIG. 2 is a diagram showing a crystal structure of ScAlMgO ₄ . As shown in FIG. 2, the ScAlMgO ₄ has a structure in which Sc—O layers and Al / Mg—O layers are alternately laminated. The lattice constant in the c-axis direction is 25.15 Å, and the lattice constant in the a-axis direction is 3.236 Å.

As will be described in detail later, the lattice mismatch between the c-plane GaN and ScAlMgO ₄ and represented by {(GaN lattice constant-ScAlMgO ₄ lattice constant) / GaN lattice constant} is As small as -1.5%. Therefore, ScAlMgO ₄ substrate, fewer defects high-quality group III nitride semiconductor multilayer is achieved.

According to the study by the inventors of the present application, the penetration dislocation density is about 1/5 or less of that of c-plane sapphire (Al ₂ O ₃ ), which has a very large lattice mismatch with GaN of 16%, which is 5 × 10 ⁷ cm ^{−. It} has been clarified that it can be reduced to ² or less. In this manner, by using the ScAlMgO ₄ substrate, it can achieve a low nitride semiconductor layer structure of the threading dislocation density. The same is true for RAMO ₄ other than ScAlMgO _4.

[Production method]
Next, a method of manufacturing the vertical field effect transistor 100 according to the present embodiment will be described in detail.

First, a substrate made of ScAlMgO ₄ whose main surface is the (0001) surface is prepared. As an example, a ScAlMgO ₄ substrate having a thickness of 400 μm is used. The ScAlMgO ₄ substrate is a flat plate on which the through holes 114 have not yet been formed. Further, as will be described later, the back surface of the ScAlMgO ₄ substrate is ground and polished to reduce the thickness. The ScAlMgO ₄ substrate may be an off-angle substrate whose main surface is inclined by about 0 ° to 10 ° with respect to the (0001) surface.

Next, the crystal growth of the nitride semiconductor is carried out by using the metalorganic vapor deposition (MOCVD: Metalorganic Chemical Vapor Deposition). Trimethylgallium (TMG) and / or trimethylaluminum (TMA) is used as the group III raw material, and ammonia (NH ₃ ) gas is used as the group V raw material. Hydrogen (H ₂ ) and nitrogen (N ₂ ) are used as the carrier gas. Monosilane (SiH ₄ ) is used as the n-type donor impurity. As the p-type acceptor impurity, biscyclopentadienyl magnesium (Cp ₂ Mg) is used.

First, ScAlMgO ₄ substrate introduced into the furnace of the MOCVD apparatus, for 10 minutes at about 1000 ° C., for thermal cleaning in a hydrogen atmosphere. As a result, carbon-based stains and the like adhering to the surface of the ScAlMgO ₄ substrate are removed. Then, the temperature is lowered to 450 ° C., and a low temperature buffer layer (not shown in FIG. 1) made of amorphous GaN is deposited at about 30 nm. The film thickness of the buffer layer can be adjusted by the growth time, the growth temperature, and the ratio of the group III raw materials to be supplied. After the buffer layer grows, the substrate temperature is raised again to about 1000 ° C. and the buffer layer is recrystallized to form crystal nuclei for the main growth.

Then, the M-containing layer 102 and the n-type layer 103 are laminated in this order at 1000 ° C to 1100 ° C. For example, using the conditions of a growth temperature of 1050 ° C., a growth rate of 3 μm / h, and a V / III ratio of 2000, an Mg-containing GaN layer having a thickness of 0.5 μm is formed as an M-containing layer 102, followed by a thickness of 10 μm. The n-type GaN layer is formed as the n-type layer 103. The n-type dopant to be doped in the n-type layer 103, _{N 2} diluted _SiH 4 used (10 ppm). As a result, the n-type layer 103 is doped with Si by about 5 × 10 ¹⁸ cm ^-3 . Here, the Mg contained in the M-containing layer 102 is due to diffusion from the ScAlMgO ₄ substrate. Therefore, the content of Mg contained in the M-containing layer 102 can be controlled by the growth conditions. The effect of the M-containing layer 102 will be described in detail later.

Next, after forming a drift layer 104 doped with Si by about 1 × 10 ¹⁶ cm ^-3 to a thickness of 5 μm, a first base layer 105 composed of a p-type GaN layer having a thickness of 400 nm and a C-doped high resistance GaN having a thickness of 200 nm. A second base layer 106 composed of layers and a third base layer 107 composed of an undoped GaN layer having a thickness of 150 nm are formed in this order. Then, the temperature is lowered to room temperature to obtain a wafer in which a nitride semiconductor layer is laminated. In the p-type GaN layer, Mg is doped as an acceptor impurity at a concentration of 1 × 10 ¹⁸ cm ^-3 , and the carrier concentration is 1 × 10 ¹⁷ cm ^-3 . The C-doped high-resistance GaN layer is doped with a C concentration of 3 × 10 ¹⁸ cm ^-3 by controlling the amount of trimethyl group C such as TMG incorporated into GaN according to the growth conditions. , The resistance is increased by compensating for the n-type carriers that naturally exist in GaN.

Next, the third base layer 107, the second base layer 106, and the first base layer 105 are penetrated in this order to form the gate opening 113 that reaches the drift layer 104. For the formation of the gate opening 113, resist patterning by photolithography and ICP (Inductively Coupled Plasma) dry etching using Cl ₂ gas are used.

Then, the MOCVD method is used again to form a regrowth layer made of a nitride semiconductor. In the present embodiment, the first regrowth layer 108 made of undoped GaN having a thickness of 100 nm, the second regrowth layer made of undoped AlN having a thickness of 1 nm, and the third layer made of undoped Al _0.2 GaN _0.8 N having a thickness of 50 nm. The regrowth layer 109 is formed in order. Then, the temperature is lowered to room temperature to obtain a wafer in which a nitride semiconductor layer is laminated.

Next, the portion of each of the third regrowth layer 109, the second regrowth layer, and the first regrowth layer 108 that forms the source electrode 111 is removed by ICP dry etching to form the first base layer 105. Form an exposed opening. The source electrode 111 composed of Ti and Al is formed so as to fill the formed opening and contact the first base layer 105. The source electrode 111 is formed, for example, by forming a metal film by sputtering or vapor deposition, and patterning the formed metal film into a predetermined shape. Patterning is performed, for example, by etching or lift-off.

Further, a gate electrode 110 made of Pd is formed so as to cover the gate opening 113. The gate electrode 110 is formed, for example, by forming a metal film by sputtering, vapor deposition, or the like, and patterning the formed metal film into a predetermined shape. Patterning is performed, for example, by etching or lift-off. Either the gate electrode 110 or the source electrode 111 may be formed first.

Thereafter, the back surface of ScAlMgO ₄ substrate, the thickness is thinned by grinding and polishing to a 100 [mu] m. The back surface of the substrate is the surface opposite to the surface on which the nitride semiconductor layer is grown, and is the surface on which the drain electrode 112 is provided.

After that, a SiO ₂ film is formed on the polished surface of the ScAlMgO ₄ substrate by plasma CVD (Chemical Vapor Deposition). Further, an opening is formed in the portion of the SiO ₂ film facing the gate opening 113 by photolithography. Then, using the SiO ₂ film as a mask, a through hole 114 penetrating the ScAlMgO ₄ substrate is formed by wet etching. Etching of ScAlMgO ₄ substrate is carried out by immersing the ScAlMgO ₄ substrate solution heated SPM is a mixture of sulfuric acid (in particular concentrated sulfuric acid) and hydrogen peroxide solution at about 80 ° C.. If the temperature of the etching solution is 50 ° C. or higher, a practical etching rate can be obtained. For example, the temperature of the etching solution may be in the range of 50 ° C. or higher and 100 ° C. or lower. The temperature of the etching solution may be 70 ° C. or higher and 100 ° C. or lower. The etching for forming the through hole 114 may be dry etching.

Then, the M-containing layer 102 exposed in the through hole 114 is removed by etching. For example, the M-containing layer 102 is removed by wet etching with KOH (potassium hydroxide aqueous solution). As a result, the n-type layer 103 is exposed.

A drain electrode 112 composed of Ti and Au is formed so as to cover the finally formed through hole 114. The drain electrode 112 is formed by, for example, forming a metal film by sputtering, vapor deposition, or the like, and patterning the metal film into a predetermined shape as needed. Patterning is performed, for example, by etching or lift-off.

Through the above steps, the vertical field effect transistor 100 shown in FIG. 1 can be manufactured.

[Effects, etc.]
Hereinafter, the characteristics and effects of the field effect transistor 100 according to the present embodiment will be described.

FIG. 3 is a diagram showing the relationship between the lattice mismatch of each material based on GaN and the difference in the coefficient of thermal expansion. As shown in FIG. 3, in the ScAlMgO ₄ substrate (SCAMO in the figure) used as the substrate 101 of the field effect transistor 100 according to the present embodiment, the lattice with the lattice constant (3.1876Å) in the a-axis direction of GaN. The inconsistency is -1.5%. This is smaller than the lattice mismatch of sapphire substrates, Si substrates, SiC substrates, etc., which have been conventionally used as base substrates for the growth of nitride semiconductors. Therefore, it is possible to form GaN having lower dislocations than before.

FIG. 4 is a diagram showing the relationship between the type of the substrate and the penetration dislocation density of the GaN growth layer. In FIG. 4, the shaded portion of the dots is the dislocation density usually reported. The white areas that are not shaded are areas where future improvements are expected as they are still being improved. It can be seen that the ScAlMgO ₄ substrate has an advantage in through dislocation density due to the small lattice mismatch over the Si substrate, the SiC substrate and the sapphire substrate.

Further, ScAlMgO ₄ can produce a crystalline ingot by the same Czochralski method (CZ method) as sapphire or Si. Therefore, there is an advantage that the substrate cost can be reduced.

FIG. 5 is a diagram showing the relationship between the cost of various substrates and the through-dislocation density of the GaN growth layer. As shown in FIG. 5, the ScAlMgO ₄ substrate (SCAMO in the figure) is a substrate that can obtain the quality closest to the homoepitaxial growth on the GaN substrate at a lower cost than any of the Si substrate, the SiC substrate and the sapphire substrate. It can be said that there is. Further, the cost of the ScAlMgO ₄ substrate can be suppressed to 1/20 or less as compared with the GaN substrate.

FIG. 6 is a diagram showing the relationship between the through-dislocation density and the withstand voltage in a GaN-based vertical field effect transistor. As shown in FIG. 6, the pressure resistance performance correlates with the through-dislocation density. Therefore, a substrate substrate capable of growing a nitride semiconductor layer having a lower penetration dislocation density is desired. However, the cost of a self-supporting GaN substrate capable of homoepitaxial growth remains high, and the current situation is that it is limited to research and development applications. Based on these things, in the present embodiment, while keeping costs to 1/20 or less by using a ScAlMgO ₄ substrate as an underlying substrate, to reduce the threading dislocation density, a high vertical breakdown voltage of the field effect transistor 100 It will be possible to realize.

The field effect transistor 100 according to the present embodiment, the ScAlMgO ₄ on the substrate, M-containing layer 102 is a Group III nitride semiconductor layer containing Mg is formed. As a result of the study by the inventors of the present application, by forming the M-containing layer 102 as an initial growth layer on the ScAlMgO ₄ substrate, the effect of further reducing the penetration dislocation density of the nitride semiconductor layer grown above the M-containing layer 102. It became clear that there is.

FIG. 7 is a diagram showing an impurity concentration profile of the nitride semiconductor layer and the underlying substrate in the field effect transistor 100 according to the present embodiment. Specifically, FIG. 7 shows an impurity profile near the interface of the ScAlMgO ₄ substrate measured by secondary ion mass spectrometry (SIMS: Secondary-Ion Mass-Spectroscopy).

As shown in FIG. 7, the Mg concentration in the M-containing layer 102 exceeds 10 ²⁰ cm ^-3 near the interface of the ScAlMgO ₄ substrate. For example, the M-containing layer 102 has a Mg concentration of 10 ²⁰ cm ^-3 or more in a region having a predetermined thickness from the interface with the substrate 101. The predetermined thickness is, for example, less than half the thickness of the M-containing layer 102.

Further, it can be seen that the Mg concentration in the M-containing layer 102 decreases from the substrate 101 side toward the n-type layer 103. For example, the Mg concentration in the M-containing layer 102 is less than 10 ¹⁸ cm ^-3 in the vicinity of the interface with the n-type layer 103.

Mg impurities in GaN become acceptor impurities mainly by being replaced with Ga. However, when the Mg concentration becomes very high, the lattice constant of GaN is modulated to increase the lattice constant.

FIG. 8A is a diagram showing the relationship between the impurity concentration in GaN and the lattice constant of GaN. Specifically, FIG. 8A shows the Mg concentration dependence (calculated value) of the a-axis lattice constant of GaN. Figure 8B is a diagram showing the relationship between lattice mismatch with respect to the impurity concentration and ScAlMgO ₄ in GaN. Specifically, FIG. 8B shows the Mg concentration dependence (calculated value) of the lattice mismatch between ScAlMgO ₄ and Mg-containing GaN.

From the graph shown in FIG. 8A, it can be seen that when Mg is contained in GaN in an amount of 10 ²⁰ cm ^-3 or more, the lattice constant increases. Further, from the graph shown in FIG. 8B, it can be seen that the lattice mismatch of 1.5% is reduced to 1.0% when the concentration becomes 3 × 10 ²¹ cm ^-3 . As described above, the M-containing layer 102 has an effect of reducing lattice mismatch. As a result, it is considered that the through-dislocation density of the GaN layer formed on ScAlMgO ₄ could be reduced.

When forming a Mg-doped GaN layer by the MOCVD method or the like, the doping amount is generally less than 10 ²⁰ cm- ³ . This is because when the concentration is 10 ²⁰ cm ^-3 or more, segregation of Mg element occurs and the crystal quality deteriorates. However, in this ^embodiment, it has a 10 20 ^{cm -3} or more high-density layer is realized by Mg diffusion from ScAlMgO ₄ substrate. For this reason, it is considered that the conventional Mg segregation does not become a problem so much, and as a result, the quality improvement due to the effect of increasing the lattice constant is exhibited.

The Mg concentration of the M-containing layer 102 can be controlled by the growth conditions of the initial growth layer. Specifically, the profile of Mg can be changed by adjusting the growth temperature, growth rate, NH ₃ partial pressure, and / or H ₂ partial pressure. As shown in FIG. 7, the Mg concentration of the M-containing layer 102 becomes higher toward the ScAlMgO ₄ substrate side. At this time, the Mg concentration is, for example, 10 ²⁰ cm ^-3 or more.

Here, the M-containing layer 102 is a p-type conductive layer or a high resistance layer. The boundary between the M-containing layer 102 and the n-type layer 103 can be defined by the magnitude of the concentration of Si, which is an n-type impurity, and the concentration of Mg. Since the activation rate of the p-type conductivity of Mg impurities is about 10% to 50%, strictly speaking, there is an ambiguous portion at the boundary between the M-containing layer 102 and the n-type layer 103. However, as a layer structure design, it is appropriate to consider the place where n-type impurities are intentionally introduced more than Mg impurities as the interface between the two layers. Therefore, for example, as shown in FIG. 7, the position where the Mg content rapidly increases and the ionic strength of Si decreases can be regarded as the boundary between the two layers.

The thickness of the M-containing layer 102 is, for example, 50 nm or more and 2000 nm or less. When the thickness of the M-containing layer 102 is 50 nm or more, it is possible to suppress a steep change in the lattice constant due to a change in Mg concentration, and it is possible to suppress a deterioration in quality. Further, since the M-containing layer 102 is 2000 nm or less, it is possible to easily remove the M-containing layer 102 when the drain electrode 112 is formed after the through hole 114 is formed in the substrate 101.

As described above, by appropriately adjusting the growth conditions and constitution of the M-containing layer 102, the through-dislocation density on the outermost surface of the nitride semiconductor layer laminated above should be 1 × 10 ⁸ cm- ² or less. Can be done. The outermost surface of the nitride semiconductor layer is the upper surface of the nitride semiconductor layer located on the uppermost layer among the plurality of nitride semiconductor layers formed by epitaxial growth on the M-containing layer 102. For example, in the field effect transistor 100 according to the present embodiment, the penetration dislocation density on the upper surface of the third base layer 107 is 1 × 10 ⁸ cm- ² or less. The third threading dislocation density in the upper surface of the regrown layer 109 is 1 × 10 ⁸ cm ^{-2 or} less which is formed by subsequent regrowth.

FIG. 9 is a TEM image of the vicinity of the interface between ScAlMgO ₄ and the Mg-containing GaN layer. The TEM image is an atomic image obtained by using a transmission electron microscope (Tarnmission Electron Microscope). As shown in FIG. 9, it can be confirmed that a high-quality interface is formed at the interface between the ScAlMgO ₄ substrate and the Mg-containing GaN layer.

In the present embodiment, ScAlMgO ₄ is used as the substrate 101, but a RAMO ₄ substrate made of a single crystal represented by the general type RAMO ₄ represented by ScAlMgO ₄ can also be used as the substrate 101. is there. In any of the above-mentioned elements, an increase in the lattice constant of GaN due to M content is exhibited. Further, ScAlMgO ₄ having a stoichiometric composition deviating from the notation to a certain extent can be used without any problem.

(Modification example)
Hereinafter, a modified example of the above embodiment will be described. In the following description, the differences from the embodiments will be mainly described, and the description of the common points will be omitted or simplified.

FIG. 10 is a schematic cross-sectional view showing the structure of the vertical field effect transistor 200 according to the modified example of the embodiment. Compared with the field effect transistor 100 according to the embodiment, the field effect transistor 200 according to the present modification has a plurality of through holes 214 provided in the substrate 101 and the drain electrode 212 instead of the drain electrode 112. It is different from the point of having.

Specifically, the plurality of through holes 214 are provided not only in the direction directly below the gate electrode 110 but also at positions other than the direction directly below. That is, in bottom view (or top view), at least one of the plurality of through holes 214 is provided at a position that does not overlap with the gate electrode 110. The shape and size of each of the plurality of through holes 214 are not particularly limited. Further, the number of through holes 214 is not particularly limited. With this configuration, the drain electrode 212 is connected not only directly under the gate electrode 110 but also at a plurality of positions with respect to the n-type layer 103 via a plurality of through holes 214.

This arrangement makes it possible to reduce the individual areas of the plurality of through holes 214, than the case of forming a single large-area through holes, it is possible to maintain the mechanical strength of ScAlMgO ₄ substrate. This improves the yield of device fabrication.

It should be noted that there is a concern that the series resistance will increase due to the smaller area of the drain electrode 212 located directly below the gate electrode 110. However, since the interface between the M-containing layer 102 and the n-type layer 103 becomes a pn junction and exhibits a 2DEG-like behavior, an increase in series resistance is hardly a problem.

(Other embodiments)
The group III nitride semiconductor device and the method for manufacturing the group III nitride semiconductor device according to one or more aspects have been described above based on the embodiments, but the present disclosure is not limited to these embodiments. As long as the gist of the present disclosure is not deviated, various modifications that can be conceived by those skilled in the art are applied to the present embodiment, and a form constructed by combining components in different embodiments is also included in the scope of the present disclosure. Is done.

For example, in the above-described embodiment and its modifications, the composition and layer thickness of each semiconductor layer are not limited to the examples shown in Table 1, and can be appropriately changed.

Further, for example, in the above-described embodiment and its modification, the GaN-based vertical field effect transistor 100 has been described as an example of the group III nitride semiconductor device, but the same applies to other vertical conduction type devices. The structure of is applicable. Group III nitride semiconductor devices can also be used, for example, in GaN-based LEDs (Light Emitting Diodes), laser diodes, pn junction diodes, Schottky barrier diodes, and the like.

Further, for example, the group III nitride semiconductor element includes an n-type layer 103, a drift layer 104, a first base layer 105, a second base layer 106, a third base layer 107, and a first regrowth layer 108. The second regrowth layer, the third regrowth layer 109, the gate electrode 110, the source electrode 111, the drain electrode 112, and the gate opening 113 need not be provided. Necessary components may be appropriately provided according to the functions required for the group III nitride semiconductor device. For example, when the group III nitride semiconductor element is a pn junction diode, two opposing electrodes may be provided instead of the gate electrode 110, the source electrode 111, and the drain electrode 112. One of the two electrodes is provided on the lower surface side of the substrate 101 and is connected to the n-type layer 103 via the through hole 114.

In addition, each of the above embodiments can be changed, replaced, added, omitted, etc. within the scope of claims or the equivalent scope thereof.

The present disclosure can be used as a group III nitride semiconductor element such as a field effect transistor having high withstand voltage performance, and can be used as a power device such as a power transistor used in a power supply circuit of a consumer device such as a television. Can be done.

100, 200 Field effect transistor 101 Substrate 102 M-containing layer 103 n-type layer 104 Drift layer 105 First base layer 106 Second base layer 107 Third base layer 108 First regrowth layer 109 Third regrowth layer 110 Gate electrode 111 Source electrode 112, 212 Drain electrode 113 Gate opening 114, 214 Through hole 115 Two-dimensional electron gas layer

Claims (10)

A RAMO ₄ substrate made of a single crystal represented by the general formula RAMO ₄ and
An M-containing Group III nitride layer located on the RAMO ₄ substrate and containing an element represented by M in the general formula,
The n-type Group III nitride layer located on the M-containing Group III nitride layer and
An electrode that penetrates the RAMO ₄ substrate is provided.
In the above general formula
R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements.
A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al.
M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd.
Group III nitride semiconductor device. The electrode penetrates the M-containing Group III nitride layer and is connected to the n-type Group III nitride layer.
The group III nitride semiconductor device according to claim 1. The R is Sc,
A is Al,
M is Mg,
The group III nitride semiconductor device according to claim 1 or 2. The M-containing Group III nitride layer contains a region in which the content concentration of the element represented by M is 10 ²⁰ cm- ³ units.
The group III nitride semiconductor device according to any one of claims 1 to 3. The thickness of the M-containing Group III nitride layer is 50 nm or more and 2000 nm or less.
The M-containing Group III nitride layer is a p-type conductive layer or a high resistance layer.
The group III nitride semiconductor device according to any one of claims 1 to 4. The n-type Group III nitride layer contains Si or O as an n-type dopant.
In the n-type Group III nitride layer, the content concentration of the n-type dopant is larger than the content concentration of the element represented by M.
The group III nitride semiconductor device according to any one of claims 1 to 5. The thickness of the RAMO ₄ substrate is 50 μm or more and 400 μm or less.
The group III nitride semiconductor device according to any one of claims 1 to 6. The through-dislocation density on the outermost surface of the nitride semiconductor layer including the n-type group III nitride layer is 1 × 10 ⁸ cm- ² or less.
The group III nitride semiconductor device according to any one of claims 1 to 7. An M-containing group III nitride layer containing an element represented by M in the general formula and an M-containing group III nitride layer on a RAMO ₄ substrate made of a single crystal represented by the general formula RAMO _4. The process of sequentially laminating the n-type III nitride layer located above and
A step of forming a through hole penetrating the RAMO ₄ substrate by etching, and
A step of removing the M-containing Group III nitride layer exposed in the through hole by etching, and
Including a step of forming an electrode connected to the n-type III nitride layer through the through hole.
In the above general formula
R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements.
A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al.
M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd.
A method for manufacturing a group III nitride semiconductor device. The step of forming the through hole by etching is a step of performing the etching by immersing the RAMO ₄ substrate in an etching solution obtained by heating a mixed solution of sulfuric acid and hydrogen peroxide solution to 50 ° C. or higher.
The method for manufacturing a group III nitride semiconductor device according to claim 9.