JP2020127023A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving a breakdown voltage of a gate insulating film at the upper edge of a trench.SOLUTION: A semiconductor layer has a quadrangular shape in a plan view. A gate pad is arranged near the center of the first side of the semiconductor layer. A gate finger includes a first portion connected to the gate pad and extending along a first side of the semiconductor layer toward a second side and a third side orthogonal to the first side, a second portion extending from a second side end of the first portion toward a fourth side facing the first side, and a third portion extending from the third side end of the first portion toward the fourth side.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having a trench gate structure.

For example, Patent Document 1 discloses an epitaxial layer in which an active cell array and a gate bus area are formed, a gate trench formed in the active cell array, a gate oxide film formed in the gate trench, and polysilicon embedded in the gate trench. A trench gate vertical structure including a gate electrode made of, a trench formed in the gate bus area and connected to the gate trench, and a gate bus made of polysilicon embedded in the trench so as to cover the surface of the epitaxial layer in the gate bus area. Type MOSFETs are disclosed.

Japanese Patent Publication No. 2006-520091

An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage of the gate insulating film at the upper edge of the trench.

One embodiment of the present invention is a semiconductor layer and a gate trench that is dug down from the surface of the semiconductor layer and has a side surface portion and a bottom surface portion, wherein the surface of the semiconductor layer and the side surface portion are interposed via a circular surface. A continuous gate trench, a gate insulating film formed so as to cover at least the side surface portion and the bottom surface portion of the gate trench, a gate electrode embedded in the gate trench, and a part of the surface of the semiconductor layer An interlayer insulating film formed so as to cover the gate electrode, a gate pad electrically connected to the gate electrode, a part formed on the interlayer insulating film and penetrating the interlayer insulating film. A gate finger electrically connected to the gate electrode, the semiconductor layer has a quadrangular shape in a plan view, and the gate pad is arranged near a central portion of a first side of the semiconductor layer. The gate finger is connected to the gate pad and extends along a first side of the semiconductor layer toward a second side and a third side orthogonal to the first side, and the first portion. A second part extending from the second side end of the part toward the fourth side facing the first side, and a second part extending from the third side end of the first part toward the fourth side. And a third portion.

In one embodiment of the present invention, the side surface portion is formed so as to be continuous with the bottom surface portion via a curved surface portion in a cross-sectional view.
In an embodiment of the present invention, the thickness of the gate insulating film on the bottom surface portion is larger than the thickness of the gate insulating film on the side surface portion.

In one embodiment of the present invention, the gate insulating film is also formed on a surface of the semiconductor layer in a predetermined region, and the thickness of the gate insulating film on the surface of the semiconductor layer is the side surface. It is larger than the thickness of the gate insulating film on the portion.

In one embodiment of the present invention, the thickness of the gate insulating film on the bottom surface portion is larger than the thickness of the gate insulating film on the surface of the semiconductor layer.
In one embodiment of the present invention, the gate electrode is made of polysilicon.
In an embodiment of the present invention, the gate finger is made of aluminum.

In one embodiment of the present invention, the gate finger includes a fourth portion protruding toward the third side from an end of the second portion on the fourth side side, and a fourth side of the third portion. A fifth portion protruding from the end toward the second side is further included.

In one embodiment of the present invention, in plan view, a portion formed of the second portion and the fourth portion and a portion formed of the third portion and the fifth portion are at the center of the first side of the semiconductor layer. It is line-symmetric with respect to an imaginary line connecting the point and the center point of the fourth side.

In one embodiment of the present invention, in plan view, the second portion and the fourth portion are arranged along outer peripheries of the second side and the fourth side of the semiconductor layer, respectively, and the third portion and The fifth portions are arranged along the outer peripheries of the third side and the fourth side of the semiconductor layer, respectively.

In one embodiment of the present invention, in a plan view, a portion where the gate finger is not formed exists in the outer peripheral portion of the semiconductor layer.

In an embodiment of the present invention, the source region of the first conductivity type formed in the surface layer portion of the semiconductor layer is in contact with the lower surface of the source layer of the first conductivity type and a part of the side surface portion. The semiconductor device further includes a second conductivity type channel layer formed in the semiconductor layer, and a source pad electrically connected to the source region and formed in a region not overlapping the gate finger.

In one embodiment of the present invention, the drain layer of the first conductivity type formed so as to reach the back surface of the semiconductor layer so as to be in contact with the channel layer of the second conductivity type, and the back surface side of the semiconductor layer, It further includes a drain electrode electrically connected to the drain layer.

In one embodiment of the present invention, the first conductivity type is n-type and the second conductivity type is p-type.
In one embodiment of the present invention, the first conductivity type is p-type and the second conductivity type is n-type.

In one embodiment of the present invention, the plurality of gate trenches are formed in a grid pattern in the active region and in a stripe pattern in the non-active region in a plan view.
In one embodiment of the present invention, the plurality of gate trenches are formed at equal intervals.

In one embodiment of the present invention, the gate insulating film integrally includes a side surface insulating film on a side surface of the gate trench and a bottom surface insulating film on a bottom surface of the gate trench, and the side surface insulating film is the gate trench. An upper edge formed at the opening end of the side trench includes an overhang portion that is selectively thicker than other portions of the side surface insulating film so as to project only inward of the gate trench.

In one embodiment of the present invention, the semiconductor layer is made of SiC.
In one embodiment of the present invention, in a plan view, the longitudinal direction of the gate finger formed along the outer periphery of the semiconductor layer is parallel to the gate electrode.

1A and 1B are schematic plan views of a semiconductor device according to an embodiment of the present invention. FIG. 1A is an overall view and FIG. 1B is an enlarged internal view. Show. 2A, 2B, and 2C are cross-sectional views of the semiconductor device. FIG. 2A is a sectional view taken along a cutting line IIa-IIa in FIG. 1B and FIG. Shows the section along the section line IIb-IIb in FIG. 1(b), and FIG. 2(c) shows the section along the section line IIc-IIc in FIG. 1(b). FIG. 3 is a sectional view showing a first embodiment of the gate finger portion of the semiconductor device. FIG. 4 is a sectional view showing a second embodiment of the gate finger portion of the semiconductor device. FIG. 5 is a sectional view showing a third embodiment of the gate finger portion of the semiconductor device. FIG. 6 is a sectional view showing a fourth embodiment of the gate finger portion of the semiconductor device. FIG. 7 is a sectional view showing a fifth embodiment of the gate finger portion of the semiconductor device. FIG. 8 is a sectional view showing a sixth embodiment of the gate finger portion of the semiconductor device. FIG. 9 is a cross-sectional view showing a seventh embodiment of the gate finger portion of the semiconductor device. FIG. 10 is a flowchart for explaining the method of manufacturing the semiconductor device. FIG. 11 is a diagram for explaining a step of forming an inclined surface on the upper edge. FIG. 12 is a diagram for explaining a step of forming a circular surface on the upper edge.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1A and 1B are schematic plan views of a semiconductor device according to an embodiment of the present invention. FIG. 1A is an overall view and FIG. 1B is an enlarged internal view. Show.
The semiconductor device 1 includes a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element (individual element) using SiC (silicon carbide). For example, the vertical length on the paper surface of FIG. 1 is about 1 mm. ..

As shown in FIG. 1A, a semiconductor device 1 is arranged in a central portion on a SiC substrate 2 as an example of a semiconductor layer and has an active region 3 functioning as a field effect transistor and an inactive region surrounding the active region 3. The outer peripheral area 4 is provided as an area. Source pad 5 made of aluminum, for example, is formed to cover almost the entire active region 3. The source pad 5 has a square shape in a plan view in this embodiment. A removal region 6 that surrounds the central region of the source pad 5 is formed along the outer peripheral region 4 at the peripheral portion of the source pad 5. A part of the removal region 6 is selectively recessed toward the central region of the source pad 5. The gate pad 7 is installed in this recess. A gate finger 8 made of aluminum, for example, extends from the gate pad 7 along the outer peripheral region 4 over the entire removal region 6. In this embodiment, the pair of gate fingers 8 are formed symmetrically with respect to the gate pad 7.

As shown in FIG. 1B, a gate trench 9 is formed in the SiC substrate 2 immediately below the source pad 5 and the like. The gate trench 9 is formed across the active region 3 and the outer peripheral region 4. The gate trenches 9 are formed in a lattice shape in the active region 3, and are formed in a stripe shape in which active trenches 91 used as the gates of the MOSFETs and the respective outer ends of the active trenches 91 are drawn out to the outer peripheral region 4. And a contact trench 92 serving as a contact to the gate electrode 15 (described later) in 91. The contact trench 92 is formed by an extension of the active trench 91. The patterns of the active trench 91 and the contact trench 92 are not limited to these shapes. For example, the active trench 91 may have a stripe shape or a honeycomb shape. Further, the contact trench 92 may have a lattice shape or a honeycomb shape.

The active region 3 is divided into a larger number of unit cells 10 by the active trench 91. A large number of unit cells 10 are regularly arranged in a matrix in the active region 3. On the upper surface of each unit cell 10, a p ⁺ type channel contact layer 11 is formed in the central region thereof, and an n ⁺ type source layer 12 is formed so as to surround the p ⁺ type channel contact layer 11. The n ⁺ type source layer 12 forms a side surface of each unit cell 10 (a side surface of the active trench 91).

In the outer peripheral region 4, the gate fingers 8 are laid along the direction crossing the striped contact trenches 92. In this embodiment, the gate finger 8 is laid in a region inside the longitudinal end portion of the contact trench 92 (the end portion on the side opposite to the active trench 91), and the end portion of the contact trench 92 is the gate finger. It protrudes outside of 8. In the region further outside the terminal end portion, the SiC substrate 2 is formed with a low step portion 13 dug down over the entire outer peripheral region 4.

Next, a basic sectional structure of the active region 3 and the outer peripheral region 4 of the semiconductor device 1 will be described.
2A, 2B, and 2C are cross-sectional views of the semiconductor device. FIG. 2A is a sectional view taken along a cutting line IIa-IIa in FIG. 1B and FIG. Shows the section along the section line IIb-IIb in FIG. 1(b), and FIG. 2(c) shows the section along the section line IIc-IIc in FIG. 1(b).

As described above, the semiconductor device 1 includes the SiC substrate 2. In this embodiment, the SiC substrate 2 is n-type as the first conductivity type and functions as the drain region (drift layer) of the field effect transistor.
A p-type channel layer 14 is formed on the front surface 21 side of the SiC substrate 2. In the p-type channel layer 14, an n ⁺ -type source layer 12 and a p ⁺ -type channel contact layer 11 surrounded by the n ⁺ -type source layer 12 and serving as an example of a second conductivity type impurity region are formed. ing. Both n ⁺ type source layer 12 and p ⁺ type channel contact layer 11 are exposed on surface 21 of SiC substrate 2.

Further, on the surface 21 side of SiC substrate 2, a gate trench 9 is formed which penetrates n ⁺ type source layer 12 and p type channel layer 14 and reaches SiC substrate 2 as a drain region. The gate trench 9 divides the p-type channel layer 14 into a large number of unit cells 10 arranged in a lattice, for example.
A gate electrode 15 made of, for example, polysilicon is embedded in the gate trench 9, and a gate insulating film 16 is interposed between the gate electrode 15 and the SiC substrate 2.

Gate electrode 15 is buried in gate trench 9 (active trench 91) up to surface 21 of SiC substrate 2 in active region 3 as shown by hatching in FIG. 1B, for example. As a result, the gate electrode 15 is also formed in a lattice shape, and the upper surface of each unit cell 10 is exposed without being covered with the gate electrode 15. On the other hand, the outer peripheral region 4 has the overlap portion 17 formed so as to cover the surface 21 of the SiC substrate 2 from the opening end of the gate trench 9 (contact trench 92). In this embodiment, the overlap portion 17 is formed so as to cross the striped contact trench 92 along the gate finger 8. Gate insulating film 16 integrally includes side surface insulating film 18 on the side surface of gate trench 9, bottom surface insulating film 19 on the bottom surface, and planar insulating film 20 on surface 21 of SiC substrate 2. In this embodiment, the planar insulating film 20 is interposed at least between the overlap portion 17 and the surface 21 of the SiC substrate 2.

In the active region 3, the gate electrode 15 extends between the n ⁺ -type source layer 12 and the SiC substrate 2 serving as the drain region, and the inversion layer (side surface of the active trench 91) on the surface of the p-type channel layer 14 (side face). Channel) formation. That is, the semiconductor device 1 has a so-called trench gate type MOSFET.
In the active region 3, the p-type pillar layer 22 is formed in the SiC substrate 2 as the drain region. The p-type pillar layer 22 is formed in a region inside the p-type channel layer 14 of each unit cell 10. More specifically, in this embodiment, the p-type pillar layer 22 has, for example, a shape similar to the p-type channel layer 14 in a substantially central region of the p-type channel layer 14 (in a plan view in the layout of FIG. 1B). It is formed in a square). P-type pillar layer 22 is formed so as to be continuous with p-type channel layer 14, and extends toward the back surface of SiC substrate 2 to a position deeper than p-type channel layer 14 in SiC substrate 2 as the drain region. There is. That is, the p-type pillar layer 22 is formed in a substantially columnar shape (in the layout of FIG. 1B, a substantially square columnar shape). As a result, on the SiC substrate 2, the p-type pillar layers 22 arranged at an appropriate pitch and the SiC substrate 2 as an n-type drain region sandwiched between the p-type pillar layers 22 adjacent to each other are formed on the surface 21. Are arranged alternately in the direction along.

An interlayer film 23 made of, for example, silicon oxide is formed on the surface 21 of the SiC substrate 2. A contact hole 24 is selectively formed in the interlayer film 23 in the central region of the p-type channel layer 14 in the active region 3. The contact hole 24 is formed in a region where the p ⁺ type channel contact layer 11 and a part of the surrounding n ⁺ type source layer 12 can be selectively exposed. Further, as shown in FIG. 1B, a contact hole 25 is selectively formed in the interlayer film 23 in the outer peripheral region 4 immediately below the gate finger 8. In this embodiment, the contact hole 25 is formed in a linear shape surrounding the active region 3 along the outer peripheral region 4 at the center of the gate finger 8 in the width direction.

The source pad 5 and the gate finger 8 (gate pad 7) are formed on the interlayer film 23. The source pad 5 collectively enters all the contact holes 24 and is connected to the n ⁺ type source layer 12 and the p ⁺ type channel contact layer 11 in each unit cell 10. Therefore, the n ⁺ type source layer 12 has the same potential as the source pad 5. Further, since the p-type channel layer 14 is connected to the source pad 5 via the p ⁺ -type channel contact layer 11, it has the same potential as the source pad 5. The gate finger 8 has entered the contact hole 25 and is connected to the overlapping portion 17 of the gate electrode 15. Therefore, the gate electrode 15 embedded in the active trench 91 is connected to the gate finger 8 via the overlap portion 17, and therefore has the same potential as the gate finger 8 (gate pad 7).

Then, in the semiconductor device 1 having such a configuration, when the ON voltage is applied to the gate finger 8, the ON voltage is also applied to the overlapping portion 17 of the gate electrode 15 by this. Therefore, the electric field generated from the overlapping portion 17 is likely to concentrate on the upper edge of the contact trench 92. As a result, there is a risk that the gate insulating film 16 will be dielectrically broken down at the upper edge of the contact trench 92. Therefore, the inventors of the present application have found the structure shown in FIGS. 3 to 9 as a structure capable of preventing such dielectric breakdown of the gate insulating film 16.

3 to 9 are sectional views showing first to seventh embodiments of the gate finger portion of the semiconductor device. 4 to 9, parts corresponding to the respective parts shown in the above-mentioned drawings are designated by the same reference numerals rather than the respective drawings.
As shown in FIG. 3, in the first embodiment, the side surface insulating film 18 is formed on the other portion of the side surface insulating film 18 so as to project inward of the contact trench 92 at the upper edge 26 of the contact trench 92. It includes an overhang portion 27 that is selectively thicker than the other. Here, upper edge 26 is a corner portion including a line of intersection formed by the side surface of contact trench 92 and surface 21 of SiC substrate 2.

With this overhang portion 27, the breakdown voltage of the gate insulating film 16 at the upper edge 26 can be improved. Therefore, even if an electric field is concentrated on the upper edge 26 when the gate is turned on, it is possible to prevent dielectric breakdown of the gate insulating film 16 at the upper edge 26. As a result, the reliability with respect to the gate-on voltage can be improved.
Regarding the relationship of the thickness of each part of the gate insulating film 16, the thickness t ₂ of the bottom surface insulating film 19 is equal to or more than the thickness t ₁ of the flat insulating film 20 (t ₂ ≧t ₁ ), and the thickness t ₁ , It is preferable that both t ₂ are larger than the thickness t ₃ of the side surface insulating film 18 (excluding the overhang portion 27). That is, the relationship of t ₂ ≧t ₁ >t ₃ is satisfied.

With this configuration, it is possible to reduce the capacitance of the capacitor formed by the gate electrode 15 and the SiC substrate 2 serving as the n-type drain region that face each other via the bottom surface insulating film 19. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. Further, since the breakdown voltage of the bottom surface insulating film 19 can be improved, it is also possible to prevent dielectric breakdown of the bottom surface insulating film 19 when the gate is off. Further, since the planar insulating film 20 is also thick, it is possible to reduce the capacitance of the capacitor formed by the gate electrode 15 (overlap portion 17) and the SiC substrate 2 as the n-type drain region which face each other with the planar insulating film 20 interposed therebetween. You can As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

The lower edge at the bottom of the contact trench 92 is a circular surface 28 that connects the side surface and the bottom surface of the contact trench 92. That is, the lower edge of the contact trench 92 is not sharp, but is rounded by the circular surface 28.
With this configuration, the electric field applied to the lower edge when the gate is off can be dispersed in the circular surface 28, so that the electric field concentration at the lower edge can be relaxed.

In the second embodiment shown in FIG. 4, in addition to the configuration of FIG. 3, the upper edge 26 of the contact trench 92 further has an inclined surface 29 connecting the surface 21 of the SiC substrate 2 and the side surface of the contact trench 92. Has become. That is, the upper edge 26 of the contact trench 92 is chamfered.
With this configuration, the electric field applied to the upper edge 26 when the gate is turned on can be dispersed in the inclined surface 29, so that the electric field concentration at the upper edge 26 can be relaxed.

In the third embodiment shown in FIG. 5, in addition to the configuration of FIG. 3, the upper edge 26 of the contact trench 92 further includes a circular surface 30 that connects the surface 21 of the SiC substrate 2 and the side surface of the contact trench 92. Has become. That is, the upper edge 26 of the contact trench 92 is not sharp and is rounded by the circular surface 30.
With this configuration, the electric field applied to the upper edge 26 when the gate is turned on can be dispersed in the circular surface 30, so that the electric field concentration at the upper edge 26 can be relaxed.

In the fourth embodiment shown in FIG. 6, in addition to the configuration of FIG. 4, the same depth as the p-type channel layer 14 (see FIG. 2A) of the active region 3 is further provided on the surface 21 side of the SiC substrate 2. A p-type layer 31 as a second conductivity type layer formed at the position is formed.
With this configuration, the p-type layer 31 in the outer peripheral region 4 can be formed in the same step as the p-type channel layer 14 in the active region 3, so that the manufacturing process of the semiconductor device 1 can be simplified. Moreover, since the contact area between the gate insulating film 16 and the SiC substrate 2 as the n-type drain region can be reduced, the leak current can be reduced and the gate capacitance can be reduced.

In the fifth embodiment shown in FIG. 7, in addition to the configuration of FIG. 6, the p-type layer 31 further has the same depth position as the n ⁺ -type source layer 12 (see FIG. 2A) of the active region 3. An n ⁺ -type layer 32 is formed as a first conductivity type layer formed on the substrate.
With this configuration, the n ⁺ -type layer 32 in the outer peripheral region 4 can be formed in the same step as the n ⁺ -type source layer 12 in the active region 3, so that the manufacturing process of the semiconductor device 1 can be simplified. ..

In the sixth embodiment shown in FIG. 8, in addition to the configuration of FIG. A bottom p-type layer 33 as a conductivity type layer is formed. The bottom p-type layer 33 is formed on the bottom surface and the side surface of the contact trench 92 so that the SiC substrate 2 as the drain region exposed in the contact trench 92 is hidden below the p-type layer 31. The bottom p-type layer 33 is continuous with the p-type layer 31 on the side surface of the contact trench 92.

With this configuration, a depletion layer generated by the junction (pn junction) between bottom p-type layer 33 and SiC substrate 2 as the n-type drain region can be generated near contact trench 92. The presence of this depletion layer can keep the equipotential surface away from the gate insulating film 16. As a result, the electric field applied to the gate insulating film 16 at the bottom of the contact trench 92 can be relaxed. Furthermore, since the bottom p-type layer 33 of the outer peripheral region 4 can be formed in the same step as the p-type pillar layer 22 of the active region 3, the manufacturing process of the semiconductor device 1 can be simplified. This bottom p-type layer 33 may be combined with the configuration of FIG. 7 as in the seventh embodiment shown in FIG.

Although not shown here, the overhang portion 27, the circular surface 28, the inclined surface 29, and the circular surface 30 shown in FIGS. 3 to 9 may be similarly formed in the active trench 91.
FIG. 10 is a flowchart for explaining the method of manufacturing the semiconductor device.
To manufacture the semiconductor device 1, for example, impurities are selectively implanted into the surface 21 of the SiC substrate 2 and an annealing treatment is performed (step S1). Thereby, impurity regions such as the p-type channel layer 14, the n ⁺ -type source layer 12, and the p ⁺ -type channel contact layer 11 are formed. Then, by etching SiC substrate 2 from surface 21 with a predetermined pattern, gate trench 9 (active trench 91 and contact trench 92) is formed in SiC substrate 2 (step S2).

The next step is the formation of the gate insulating film 16 (step S3). The gate insulating film 16 is formed under predetermined conditions (gas flow rate, gas species, gas ratio) so that the overhang portion 27 that is selectively thicker than other portions is formed at the upper edge 26 of the contact trench 92. , Gas supply time, etc.) is used to deposit an insulating material in the gate trench 9. As a result, the gate insulating film 16 having the overhang portion 27 is formed.

Here, when the inclined surface 29 is formed on the upper edge 26 as shown in FIGS. 4 and 6 to 9, the SiC substrate 2 is heated after the formation of the gate trench 9 and before the formation of the gate insulating film 16. Oxidize. Specifically, as shown in FIG. 11, the sacrificial oxide film 34 is formed by thermally oxidizing the SiC substrate 2. When forming the sacrificial oxide film 34, in the vicinity of the contact trench 92, oxidation uniformly starts from both the surface 21 of the SiC substrate 2 and the side surface of the contact trench 92. Therefore, at the upper edge 26, the oxide film that has progressed from the surface 21 of the SiC substrate 2 and the oxide film that has progressed from the side surface of the contact trench 92 are integrated earlier than other regions. As a result, the inclined surface 29 is formed below the integrated oxide film. After that, the sacrificial oxide film 34 may be removed and the gate insulating film 16 may be formed by the CVD method.

When the method of FIG. 11 is adopted, if the p-type layer 31 and the n ⁺ -type layer 32 are formed on the surface 21 side of the SiC substrate 2 as shown in FIGS. 6 to 9, a drain region is formed in that portion. Since the thermal oxidation rate is faster than that of the SiC substrate 2, the inclined surface 29 can be formed more easily.
On the other hand, when the circular surface 30 is formed on the upper edge 26 as shown in FIG. 5, the SiC substrate 2 is annealed with H ₂ after the formation of the gate trench 9 and before the formation of the gate insulating film 16. Specifically, as shown in FIG. 12, circular surface 30 is formed on upper edge 26 by applying H ₂ annealing (H ₂ etching) to SiC substrate 2 at 1400° C. or higher.

Returning to FIG. 10 again, after forming the gate insulating film 16, the gate trench 9 is backfilled and polysilicon is deposited until the entire gate trench 9 is hidden (step S4). Then, by patterning the deposited polysilicon, the polysilicon outside the active trench 91 is removed in the active region 3, and at the same time, the polysilicon is left as the overlap portion 17 in the outer peripheral region 4.

Next, the interlayer film 23 is formed on the SiC substrate 2 by the CVD method (step S5). Next, the contact hole 24 and the contact hole 25 are simultaneously formed by patterning the interlayer film 23 (step S6).
Next, a metal material such as aluminum is deposited on the interlayer film 23 by the sputtering method and the vapor deposition method (step S7). As a result, the source pad 5, the gate pad 7 and the gate finger 8 are formed. Through the above steps and the like, the semiconductor device 1 shown in FIG. 1 is obtained.

Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms.
For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

The semiconductor adopted in the semiconductor device 1 is not limited to SiC, and may be Si, GaN, diamond, or the like.
Further, the overlapping portion 17 is not limited to the outer peripheral region 4 and may be formed in the active region 3. For example, the overlapping portion 17 may be formed in the active region 3 by covering only the periphery of the open end of the active trench 91 to the extent that the upper surface of each unit cell 10 is not hidden. In this case, by forming the overhang portion 27 also in the active trench 91, the same withstand voltage improving effect as described above can be obtained. That is, the structure immediately below the gate finger 8 is merely an example showing the effect of improving the withstand voltage by the overhang portion 27 of the present invention, and is not limited to the gate finger portion as long as the same effect can be obtained. ..

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor Device 2 SiC Substrate 21 Surface 3 Active Region 4 Peripheral Region 8 Gate Finger 9 Gate Trench 91 Active Trench 92 Contact Trench 12 n ⁺ Type Source Layer 14 p Type Channel Layer 15 Gate Electrode 16 Gate Insulating Film 17 Overlap 18 Side Insulating film 19 Bottom insulating film 20 Planar insulating film 22 p-type pillar layer 23 Interlayer film 26 Upper edge 27 Overhang part 28 Circular surface 29 Inclined surface 30 Circular surface 31 p-type layer 32 n ⁺ type layer 33 Bottom p-type layer 34 Sacrifice Oxide film

Claims (20)

A semiconductor layer,
A gate trench that is dug down from the surface of the semiconductor layer and has a side surface portion and a bottom surface portion, wherein the surface of the semiconductor layer and the side surface portion are continuous through a circular surface, and
A gate insulating film formed to cover at least the side surface portion and the bottom surface portion of the gate trench;
A gate electrode embedded in the gate trench,
An interlayer insulating film formed so as to cover a part of the surface of the semiconductor layer and the gate electrode;
A gate pad electrically connected to the gate electrode,
A gate finger formed on the interlayer insulating film and partly penetrating the interlayer insulating film and electrically connected to a gate electrode;
The semiconductor layer has a rectangular shape in a plan view,
The gate pad is arranged near the center of the first side of the semiconductor layer,
The gate finger is connected to the gate pad and extends along a first side of the semiconductor layer toward a second side and a third side orthogonal to the first side, and the first portion. A second portion extending from the second side end of the first portion toward a fourth side opposite to the first side, and a third portion of the first portion extending from the third side end toward the fourth side. A semiconductor device including a third portion. The semiconductor device according to claim 1, wherein the side surface portion is formed so as to be continuous with the bottom surface portion via a curved surface portion in a cross-sectional view. The semiconductor device according to claim 1, wherein the thickness of the gate insulating film on the bottom surface portion is larger than the thickness of the gate insulating film on the side surface portion. The gate insulating film is also formed on the surface of the semiconductor layer in a predetermined region,
The semiconductor device according to claim 3, wherein the thickness of the gate insulating film on the surface of the semiconductor layer is larger than the thickness of the gate insulating film on the side surface portion. The semiconductor device according to claim 4, wherein the thickness of the gate insulating film on the bottom surface portion is larger than the thickness of the gate insulating film on the surface of the semiconductor layer. The semiconductor device according to claim 1, wherein the gate electrode is made of polysilicon. The semiconductor device according to claim 1, wherein the gate finger is made of aluminum. The gate finger is
A fourth portion projecting from the fourth side edge of the second portion toward the third side;
The semiconductor device according to claim 1, further comprising: a fifth portion protruding from the end of the third portion on the fourth side toward the second side. In a plan view, a portion formed of the second portion and the fourth portion and a portion formed of the third portion and the fifth portion are a center point of the first side and a center point of the fourth side of the semiconductor layer. 9. The semiconductor device according to claim 8, which is line-symmetric with respect to an imaginary line connecting and. In a plan view, the second portion and the fourth portion are arranged along the outer peripheries of the second side and the fourth side of the semiconductor layer, respectively.
The semiconductor device according to claim 9, wherein the third portion and the fifth portion are arranged along outer peripheries of the third side and the fourth side of the semiconductor layer, respectively. 11. The semiconductor device according to claim 10, wherein a portion where the gate finger is not formed is present in an outer peripheral portion of the semiconductor layer in a plan view. A source region of the first conductivity type formed in a surface layer portion of the semiconductor layer;
A second conductivity type channel layer formed in the semiconductor layer so as to contact the lower surface of the first conductivity type source layer and a part of the side surface portion;
The semiconductor device according to claim 1, further comprising a source pad electrically connected to the source region and formed in a region that does not overlap the gate finger. A drain layer of the first conductivity type formed so as to reach the back surface of the semiconductor layer so as to be in contact with the channel layer of the second conductivity type;
The semiconductor device according to claim 12, further comprising a drain electrode electrically connected to the drain layer on the back surface side of the semiconductor layer. 14. The semiconductor device according to claim 12, wherein the first conductivity type is n type and the second conductivity type is p type. 14. The semiconductor device according to claim 12, wherein the first conductivity type is p-type and the second conductivity type is n-type. 16. The semiconductor according to claim 1, wherein the plurality of gate trenches are formed in a grid pattern in an active region and in a stripe pattern in a non-active region in a plan view. apparatus. The semiconductor device according to claim 16, wherein the plurality of gate trenches are formed at equal intervals. The gate insulating film integrally includes a side surface insulating film on a side surface of the gate trench and a bottom surface insulating film on a bottom surface of the gate trench,
The side surface insulating film is selectively thicker than other portions of the side surface insulating film so that the side surface insulating film protrudes only inside the gate trench at the upper edge formed at the opening end of the gate trench. The semiconductor device according to claim 1, further comprising an overhang portion. The semiconductor device according to claim 1, wherein the semiconductor layer is made of SiC. 20. The semiconductor device according to claim 1, wherein a longitudinal direction of the gate finger formed along the outer periphery of the semiconductor layer is parallel to the gate electrode in a plan view.

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