JP2020124113A - Power supply switching device - Google Patents

Abstract

To provide a power supply switching device capable of preventing a cross current from being generated in power supply switching without providing synchronous switching means or means for detecting a cross current component mutually flowing between AC power sources.SOLUTION: A power supply switch consisting of a thyristor is provided in each of two power supply circuits for supplying power from first and second AC power sources to a common load. When switching power to be supplied to the load by changing over these power supply switches, a turned-on power supply switch at a change-over source power source side is turned off, and a polarity of a phase voltage of the power supply switch at the change-over source power source side is discriminated. If the discriminated polarity of the phase voltage is a positive polarity, a gate-on permission signal is given to a thyristor of the positive polarity of the turned-off-side power supply switch. If the polarity of the phase voltage is a negative polarity, a gate-on permission signal is given to a thyristor of the negative polarity of the turned-off-side power supply switch.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power supply switching device for selectively supplying power to a load from two alternating-current power supplies.

Generally, in a power supply device including two redundant AC power supplies capable of selectively supplying power to a load, when an abnormality such as a power failure or a voltage drop occurs in the power supply system during power supply, the power supply system has a normal voltage. It is switched to the standby power supply. The power source is switched by the power source switching device. However, when the changeover switches for switching the power source system are simultaneously turned on, a short circuit occurs between the two power sources and a cross current flows.

On the other hand, if the switching of the power supply system is delayed, there is a problem that a power failure or voltage fluctuation occurs with respect to the load.

As a power supply switching device for suppressing such voltage fluctuations and occurrence of cross current, devices disclosed in Patent Documents 1 and 2 have been conventionally known. However, such a conventional power supply switching device has a synchronous switching means for switching the voltage of the power supply including the inverter and the voltage of the other commercial AC power supply in synchronization with each other, and a cross current component flowing between the AC power supplies. There is a problem in that the configuration becomes complicated because it is provided with a means for detecting.

Japanese Patent Laid-Open No. 09-019065 Japanese Patent Publication No. 07-004052

In order to solve the above-mentioned problems in the conventional apparatus, the present invention can prevent the occurrence of a cross current at the time of power supply switching without providing a synchronization switching means, a means for detecting a cross current component flowing between AC power supplies. An object of the present invention is to provide a power supply switching device having a simple structure.

In order to solve the above-mentioned problems, the present invention is configured such that two thyristor elements are respectively connected in parallel in reverse polarity to two power supply circuits that supply power to a common load from each of the first and second AC power supplies. In the power supply switching device, which is provided with the power supply switch, and switches the power supply to the load by switching these power supply switches on and off,
Means for detecting the phase voltage of the power supply to which the power supply switch on the side is turned on when a switching command is given to the two power supply switches; and means for determining the polarity of the phase voltage detected by the voltage detection means. When the polarity of the phase voltage determined by the polarity determination means is positive, a gate-on permission signal is given to the positive thyristor of the power feed switch on the off side, and the polarity of the phase voltage is negative. Is provided with a switching control circuit having means for giving a gate-on permission signal to the negative polarity thyristor of the feed switch on the off side.
Further, in the present invention, the means for determining the polarity of the phase voltage of the power source detects the 90° or 270° phase of the voltage obtained by differentiating the line voltage of the power source, and the detected 90° or It can be composed of a phase estimating means for estimating the phase of the phase voltage of the power source from the 270° phase and a polarity determining means for determining whether the phase voltage is positive or negative from the phase of the phase voltage estimated in the previous period. .. Further, the means for detecting the 90° or 270° phase of the voltage obtained by differentiating the line voltage of the power supply obtains the amount of change in the voltage obtained by differentiating the line voltage of the power supply, and changes from negative to positive or positive. Is used as a means for generating a signal exhibiting a 90° phase or a 270° phase by catching the change from to negative.

In addition, a power supply switch configured by connecting two thyristor elements in parallel in opposite polarities is provided in two power supply circuits that supply power to a common load from each of the first and second AC power supplies. In the power switching device that switches the power supply to the load by switching on and off of
Corresponding to each of the power supply switches, voltage detection means for detecting at least the load-side all-phase voltage of the power supply switch, and voltage conversion means for full-wave rectifying the output of this voltage detection means to convert it to a DC voltage. The voltage determining means for determining that the output voltage of the voltage converting means is lower than a reference value, and the voltage determining means for the power supply switch that is turned on when a switching command is given to the two power supply switches. A switching control circuit having means for giving a gate-on permission signal to the thyristor of the power feed switch on the side turned off based on the determination output.
Further, in the present invention, it is possible to provide a timing element for delaying the judgment output of the voltage judgment means by a time corresponding to the delay phase angle of the load current corresponding to the inductive component of the load.

According to the present invention, when the power supply switches are switched by turning on and off the power supply switches each of which is provided in each of the two power supply circuits that supply power to the common load from the two AC power supplies, the power supply switches are turned on. The phase voltage of the power supply applied to the power supply switch on the side where the power is turned on is detected, the polarity of the detected phase voltage is determined, and if the polarity of the voltage is positive, the positive voltage thyristor of the power supply switch on the side turned off is detected. When the gate is turned on and the polarity of the voltage is negative, the gate of the negative thyristor of the feed switch on the off side is allowed to be turned on. The thyristors of the switches do not turn on at the same time, and the thyristors of the power supply switches on the off side are switched on after the thyristors of the switches on the on side turn off. Therefore, it is possible to prevent the occurrence of a cross current when the power supply circuit is switched, without providing a synchronous switching means, a means for detecting a cross current flowing between the AC power supplies, or the like.

It is a circuit block diagram which shows the 1st Example of this invention. It is an operation|movement waveform diagram of the 1st Example of this invention. It is a circuit block diagram which shows the 2nd Example of this invention. It is a circuit block diagram which shows the 3rd Example of this invention. It is an operation|movement waveform diagram of the 3rd Example of this invention.

Embodiments of the present invention will be described with reference to examples shown in the drawings.

FIG. 1 is a configuration diagram showing a first embodiment of a power supply switching device of the present invention. Since each phase of a three-phase AC circuit has the same configuration, only the U-phase circuit configuration is shown here, and others. The circuit configuration of the phase is indicated by a block.

In FIG. 1, 1 and 2 are first and second three-phase AC power supplies. Each of the two AC power supplies switches the three-phase power supply paths 11 and 21 to supply power to the common load 5. The power supply paths 11 and 21 are provided with power supply switches 3 and 4 for selectively switching the power supply paths to the voltage detectors 12 and 22 and the load 5, respectively. The switches 3U to 3W and 4U to 4W for the respective phases of the power feeding switches 3 and 4 are configured by connecting in parallel two thyristors 3P, 3N, and 4P, 4N having opposite polarities. In this case, the polarity of the thyristors 3P and 4P in which the current flow direction is directed from the power supply to the load side is positive in the feed switch of each phase and the current flow direction is directed from the load to the power supply side. The polarities of 3N and 4N are defined as negative polarity.

The feed switches 3 and 4 are provided with switching control circuits 30 and 40 for each phase. The switching control circuits 30 and 40 prevent the other power feeding switch from being turned off and the two power feeding switches 3 and 4 from being turned on at the same time when one power feeding switch is turned on by a switching command from the outside. Controls the on/off switching of the power feeding switches 3 and 4.

The switching control circuit 30 turns on (“1”) the gate signals G3P and G3N to the thyristors 3P and 3N of the power feeding switch 3 when the switching signal S3 to the power feeding switch 3 is on (“1”), and the power feeding switch 4 The gate signals G4P and G4N to the thyristors 4P and 4N are turned off ("0"). Then, when the switching signal S4 for the power feeding switch 4 is on (“1”), the switching control circuit 40 turns on (“1”) the gate signals G4P, G4N to the thyristors 4P, 4N of the power feeding switch 4 to feed power. The gate signals G3P and G3N to the thyristors 3P and 3N of the switch 3 are turned off (“0”).

Since the switching control circuits 30 and 40 have the same configuration, only the configuration of the switching control circuit 40 is shown in detail in FIG. 1, and the switching control circuit 30 is shown as a block, and the detailed configuration is omitted.

The switching control circuit 40 includes a differential operation unit 41 that obtains a differential value of the U-V phase line voltage E1 _UV of the three-phase AC power source 1 detected by the voltage detector 12. The differentiating means 41 performs the differentiating operation by sampling the line voltage E1 _UV thus detected in synchronization with a predetermined clock signal and taking in it, and obtaining a change amount between the voltage value previously taken in and the voltage value taken in this time. To do.

The output of the differential calculation means 41 is input to the 90° phase detection means 42a and the 270° phase detection means 42b in order to detect the 90° and 270° phases of the line voltage E1 _UV of the power feeding path 11. The 90° phase detection means 42a monitors the change in the polarity of the differential value E1 _UV ′ of the line voltage E1 _UV output from the differential calculation means 41, and determines the timing at which the differential value, that is, the amount of change changes from positive to negative. Then, the 90° phase detection signal S90 of the line voltage E1 _UV is generated. The 270° phase detecting means 42b monitors the change in the polarity of the differential value E1 _UV ′ of the line voltage E1 _UV output from the differential calculating means 41, and catches the timing when the differential value, that is, the change amount changes from negative to positive. And generates a 270° phase detection signal S270 of the line voltage E1 _UV .

90 ° phase detecting means 42a and 270 ° phase detection the detection signal S90 and S270 from the means 42b, phase estimation means 43a and 4 to estimate the phase of the power supply 1 U phase voltage E1 _U
3b is input.
The phase estimating means 43a and 43b are composed of counters that count the clock signal Cl. The counter which constitutes the phase estimating means 43a starts counting from the initial value 60° set in the initial value setting device 44a by the 90° phase detection signal S90, counts the clock signal Cl corresponding to 180°, and 240°. When the count value of is reached, the count value is reset. The counter constituting the phase estimating means 43b starts counting from the initial value 240° set in the initial value setting unit 44b by the 270° phase detection signal S270, counts a clock corresponding to 180°, and 420° (60°). The count value is reset when (°) is reached. From this, it is estimated from each count value how much the phase of the phase voltage has advanced from the detected 90° and 270° phase of the line voltage.

Since the phase voltage has a phase delay of 30° with respect to the line voltage, as is well known, the initial values of the counters of the phase estimating means 43a and 43b are set by the initial value setting devices 44a and 44b. By setting to 60° and 240°, which are 30° less than the detected values of 90° and 270°, respectively, the phase of the detected line voltage is converted into the phase of the phase voltage, and immediately from the count values of the phase estimating means 43a and 43b. The phase of the phase voltage can be estimated. The reset values of the counters of the phase estimating means 43a and 43b are set to 240° and 60° for the same reason.
Accordingly, the count value of the phase estimation means 43a and 43b, the phase voltage E1, would indicate an estimate of the phase of the U-phase voltage E1 _U here.

The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimation means 43a is input to the comparison inputs of the comparators 45a and 45b. The comparator 45a compares the count value indicating the phase estimated value θ _U with the set value 180° input to the negative reference input from the setter S13, and when the phase estimated value θ _U is equal to or larger than the set value 180°, “1” is set. Then, when the set value is 180° or less, the comparison output S45a which is "0" is generated. Further, the comparator 45b compares the phase estimation value θ _U input to the comparison input with the set value 180° input to the positive reference input from the setter S14, and the phase estimated value θ _U is set to 180°. The comparison output S45b is "1" in the following cases, and "0" in the case where the set value is 180° or more.
The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimation means 43b is input to the comparison inputs of the comparators 46a and 46b. The comparator 46a compares the count value indicating the phase estimated value θ _U with the set value 0° input to the positive reference input from the setter S15, and when the phase estimated value θ _U is equal to or larger than the set value 0°, “1” is set. , And when the set value is 0° or less, the comparison output S46a which is "0" is generated. Further, the comparator 46b compares the phase estimated value θ _U input to the comparison input with the set value 0° input to the positive reference input from the setter S16, and the phase estimated value θ _U is set to 0°. The comparison output S46b is "1" in the following cases, and "0" in the case of the set value or more.

The outputs S45b and S46a of the comparator 45b and the comparator 46a are input to the signal holding means 49a composed of a flip-flop circuit via the OR gate 47a and the AND gate 48a. The outputs S45a and S46b of the comparator 45a and the comparator 46b are input to the signal holding means 49b composed of a flip-flop circuit via the OR gate 47b and the AND gate 48b.

The output of the signal holding means 49a is input to the AND gate 48P as a gate-on permission signal S4P for the positive thyristor 4P of the power feeding switch 4 of the power feeding path 21. Further, the output of the signal holding means 49b is input to the AND gate 48N as a gate-on permission signal S4N for the negative polarity thyristor 4N of the power feeding switch 4 of the power feeding path 21.

The switching signal input terminal C41 of the switching control circuit 40 receives the switching signal S4 from the outside to the power feeding switch 4, while the switching signal input terminal C42 rejects the switching signal S3 to the power feeding switch 3. S3 is input. The switching signal input terminal C31 of the switching control circuit 30 receives the switching signal S3 to the power feeding switch 3, while the switching signal input terminal C32 receives the signal S4 that negates the switching signal S4 to the power feeding switch 4. Is entered.
When the switching signal S4 to the power feeding switch 4 becomes "1" to instruct the power feeding switch 4 to turn on, the switching signal S3 to the power feeding switch 3 becomes "0" to command the power feeding switch 3 to turn off. .. On the contrary, when the switching signal S3 to the power feeding switch 3 becomes "1" and the power feeding switch 3 is instructed to turn on, the switching signal S4 to the power feeding switch 4 becomes "0" and the power feeding switch 4 is instructed. Command off.
When the switching signal S4 to the power feeding switch 4 becomes "0" and the off command is issued, the signal holding means 49a and 49b receives a reset signal which becomes "1" via the knot gate 51, and holds the signals. Means 49a, 49b are reset.

Further, the switching signal S3 input from the switching control circuit 30 to the switching control circuit 40 is input to the AND gates 48a and 48b via the knot gate 52. The switching signal S4 input from the switching control circuit 40 to the switching control circuit 30 corresponds to AND gates 48a and 48b in the switching control circuit 40 via the knot gate 53. The switching control circuit 30 is not shown here. Input to the AND gate inside.
The line voltage E2 _UV detected by the voltage detector 22 of the power supply path 21 is input to the switching control circuit 30.

Next, the operation of the power supply switching device of the present invention thus constructed will be described with reference to the operation waveform diagram shown in FIG.

In the power source switching device of FIG. 1, when no measures against cross current are taken, for example, in the process of switching from the power source 1 of the switching source to the power source 2 of the switching destination, the U-phase power supply switch 3U on the power source 1 side. When the positive thyristor 3P is turned on and the current IP1 shown by the dotted line flows through the load 5 and the negative thyristor 4N of the U-phase power supply switch 4U on the power supply 2 side is turned on, the power is supplied through this. The current IN2 flows from 1 to the power source 2 as a cross current until the thyristor 3P is turned off as shown by the dotted line.
The present invention prevents such a cross current IN2 from flowing.

Here, the power supply switching device of FIG. 1 is in a state where the power supply switch 3 is turned on, the power supply switch 4 is turned off, and power is supplied from the power supply 1 to the load 5 through the power supply switch 3. The switching operation in the case where the power supply switch 3 is turned off and the power supply switch 4 is turned on from this state to switch the power supply 2 to the load 5 through the power supply switch 4 will be described. Therefore, here, the power source 1 is the switching source power source and the power source 2 is the switching destination power source.

In the state where the power supply switch 3 is turned on and the current I1 is supplied from the power supply 1 to the load 5 through the power supply path 11, the voltage generator 12 causes the U-V of the power supply 1 as shown by the solid line in FIG. The line voltage E1 _UV between the phases is detected.
The line voltage E1 _UV of the switching source power source 1 is input to the differentiation operation means 41 of the switching control circuit 40 on the switching destination power source 2 side and differentiated. From this differential calculation means 41, a differential voltage E1 _UV ' of a line voltage as shown in FIG. 2B is obtained.

'As is apparent from the waveform of the differential voltage _{E1 UV'} the differential voltage _{E1 UV} period becomes positive is voltage positive variation as shown in FIG. 2 (c) is "1", and the differential voltage _{E1 UV} ' During the period in which is negative, the negative voltage change amount is “1” as shown in FIG.

The 90° phase detecting means 42a monitors the voltage negative change amount of the line voltage E1 _UV shown in FIG. 2D, detects that it rises from 0 to 1, and generates a 90° phase detection signal S90. .. Therefore, the 90° phase detection means 42a generates the 90° phase detection signal S90 at time t6 when the line voltage E1 _UV has a 90° phase, as shown in FIG. 2(e).

The 270° phase detecting means 42b monitors the positive change amount of the line voltage E1 _UV shown in FIG. 2C, detects that it rises from 0 to 1, and generates the 270° phase detection signal S270. .. Therefore, the 270° phase detection signal S270 is generated at time t3 when the line voltage E1 _UV has a 270° phase, as shown in FIG. 2(f).

The phase estimating means 43a and 43b for counting the clock signal Cl and estimating the phase of the phase voltage E1 of the power supply 1 have the 90° phase detection signal S90 and the 90° phase detection signal S90 as shown in FIGS. 2(g) and 2(h), respectively. When the 270° phase detection signal S270 is input, counting is started from the initial values 60° and 240° set in the initial value setters 44a and 44b, respectively. The phase estimating means 43a and 43b that have started counting, start counting by the 270° phase detection signal S270 and the 90° phase detection signal S90, respectively, and then count until the count values become 240° and 60°, respectively. When it reaches 240° and 60°, the count value is reset to the initial value (60° and 240°).

Therefore, the phase estimating means 43a performs the counting operation up to the time point t3 and between the time points t6 and t10, and the phase estimating means 43b performs the counting operation between the time points t3 and t6. the value, the phase estimate of the U-phase voltage switch 3U is inserted in the U-phase E1 _U is shown.
The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimating means 43a and 43b is compared with the set value 180° set in the setters S13 and S14 by the comparators 45a and 45b, respectively. The comparator 45a generates a signal S45a which becomes "1" when the count value (phase voltage phase estimated value) is 180° or more, and the comparator 45b outputs "1" when the count value is 180° or less. Signal S45b is generated. Thus, it detects that the output of the comparator 45a, the phase voltage E1 can detect that _{the U} phase is above 180 °, and the phase of the phase voltage E1 _U from the output of the comparator 45b is 180 ° or less.

The count value indicating the phase voltage phase estimated value of the phase estimating means 43b is compared with the set value 0° set in the setters S15 and S16 by the comparators 46a and 46b, and if the count value is 0° or more, the comparator. 46a outputs the signal S46a which becomes "1", and when the count value is 0° or less, the comparator 46b outputs the signal S46b which becomes "1". Thus detect that the comparator output from the phase voltages E1 _U phase 46a is able to detect that the 0 ° or more, and the phase of the phase voltage E1 _U from the output of the comparator 46b is 0 ° or less.

Therefore, from the OR gate 47a for extracting the OR outputs of the comparators 45b and 46a, the phase of the phase voltage E1 _U is "1" as shown in FIG. 2(i) while the phase is 0° (360°) to 180°. Output is generated. This phase because the voltage shows a positive polarity E1 _U, can detect a positive polarity of the phase voltage E1 _U from the output of the OR gate 47a.

OR gate 47b for taking out an OR output of comparator 45a and 46b are 360 (0) from phase 180 ° of the phase voltage E1 _U ° between the output becomes "1" as shown in FIG. 2 (j) is generated To be done. This indicates the negative polarity of the phase voltage E1 _U, can detect a negative polarity of the phase voltage from the output E1 _U of the OR gate 47b.

The outputs of the OR gates 47a and 47b are input to one ends of the AND gates 48a and 48b, respectively. To the other ends of these AND gates 48a and 48b, the signal S3 that is the negation of the switching signal S3 of the switch 3 is input via the NOT gate 52. Therefore, the AND gate 48a, between t5~t9 time when the phase voltage E1 _U as shown in FIG. 2 (i) has a positive polarity, the switching signal S3 is such that shown in FIG. 2 (k) When it is turned off, that is, when it becomes "0", the output S48a which becomes "1" is obtained, and this is held as the gate-on permission signal S4P by the signal holding means 49a. The gate-on permission signal S4P is input to one end of an AND gate 48P that outputs a gate signal to the positive thyristor 4P of the power supply switch 4 on the power supply 2 side.

Further, the AND from the gate 48b, between the negative polarity going on t2~t5 when the phase voltage E1 _U as shown in FIG. 2 (j), or at t9 after time, switching signal S3 is FIG 2 (k ), when it is turned off, that is, when it is "0", an output S48b which is "1" is obtained, and this is held as the gate-on permission signal S4N by the signal holding means 49b. The gate-on permission signal S4N is input to one end of an AND gate 48N that outputs a gate signal to the negative polarity thyristor 4N of the power supply switch 4 on the power supply 2 side.

As described above, when the switching signal S4 for instructing the switching to the power feeding switch 4 is turned on (“1”) with the gate-on permission signal S4P or S4N being input to one end of the AND gate 48P or 48N, the AND gate 48P Alternatively, since the gate signals G4P and G4N are generated from 48N and output to the positive polarity thyristor 4P or the negative polarity thyristor 4N of the power feeding switch 4, the thyristor 4P or thyristor 4N is turned on.

In the state where the power supply switch 3 in FIG. 1 is turned on and power is being supplied from the power supply 1 to the load 5 through the power supply path 11, a power supply switching command is given at time t7 and the switching signal S3 of the power supply switch 3 is turned on (“1 )) to off (“0”) and the switching signal S4 of the power supply switch 4 switches from off (“0”) to on (“1”), the gate signal G3P to the switch 3 on the power supply 1 side is displayed. , G3N are turned off by AND gates 38P, 38N. In this case, since the still U-phase voltage E1 _U of the power supply 3 is in the positive polarity, the positive polarity thyristor 3P switch 3U gate signal to continue flowing be turned off. This voltage of the phase voltage E1 _U is negative polarity, is continued until the current I1 flowing through the thyristor 3P passes through the zero point.

In this state, when the negative thyristor 4N of the switch 4U of the power supply switch 4 on the power source 2 side, which has the same current conduction polarity as the positive thyristor 3P of the switch 3U, which is in conduction, becomes conductive, the conduction is continued. The cross current IP2 flows from the power source 1 to the power source 2 through the negative polarity thyristor 4N of the switch 4U which starts conduction with the positive polarity thyristor 3P.

However, in the present invention, it is given a power switching command at time t7, when the phase voltage E1 _U is in the positive polarity, providing a gate-on enable signal S4P, a gate signal to the positive thyristor 4P switches 4U and Since it is given only to the gate 48P and is not given to the AND gate 48N which gives the gate signal to the negative polarity thyristor 4N, the negative polarity thyristor 4N is not turned on during this period.

Further, when the gate-on permission signal S4P is given, the AND gate 48P is turned on, the gate signal G4P is input to the gate of the positive polarity thyristor 3P, and this thyristor 4P is turned on, but the flow direction of the thyristor 4P is the power source. The thyristor 4P blocks the cross flow because it is opposite to the flow direction of the cross flow flowing from the first side.
Therefore, until the positive polarity end time t9 voltage E1 _U to positive thyristor 3P is flowing through the switch 3, the switch 4 (4U) never to flow through the lateral flow, the power supply 2 from the power supply 1 side A cross current is prevented from flowing.

In t9 when the positive polarity end of the phase voltage E1 _U, because the current I1 is zero, positive thyristor 3P switch 3 (3U) are turned off, the switch 3 (3U) is closed, power source 1 is cut off It
Even if the power supply 1 is cut off, the voltage phase estimation means 43a continues from the timing (t6) when the 90° phase of the line voltage (60° of the phase voltage) is finally detected until the phase voltage becomes 240°. To continue counting regardless of the presence or absence of voltage, the timing when the phase advances by 120° from the initial count value (60°) and the polarity of the phase voltage E1 _U changes to turn off the thyristor (180° phase voltage phase It is possible to estimate that the time t9, which is That is, when the count value indicating the phase estimation value of the phase estimation means 43a becomes 180° or more, the output signal S45a of "1" output from the comparator 45a turns off the thyristor 3U at the timing (of the phase voltage). 180° phase).

The output signal S45a became "1" indicating that the phase voltage E1 _U of the comparator 45a is negative are input to the signal holding unit 49b via the OR gate 47b and an AND gate 48b,, switching signal switching destination S4 is the on ( "1"), made possible phase voltage E1 _U is held in the signal holding unit 49b when the first becomes negative. As a result, the gate holding enable signal S4N is given from the signal holding means 49b to the AND gate 48N, and the switching signal S4 of the switch 4 (4U) is supplied as the gate signal G4N through the AND gate 48N to the gate of the negative thyristor 4N of the switch 4 (4U). Given to. As a result, the negative polarity thyristor 4N of the switch 4 (4U) becomes conductive, power supply from the power supply 2 to the load 5 is started, and the switching of the power supply is completed.

When the input voltage E1 _UV of the switching circuit 40 becomes zero by turning off the thyristor 3P of the power feeding switch 3 at time t9 when the phase voltage E1 _U becomes zero, the output of the phase detecting means (42a, 42b). Since the signal becomes indefinite, the positive voltage change amount, the negative voltage change amount, and the 90° detection signal S90 and the 270° detection signal S270 are shown in FIGS. 2(c), (d), (e), and (f). As shown by the solid hatching, it becomes indefinite after time t9. As a result, the phase estimating means 43a and 43b start counting at the false rise of the positive voltage change amount and the negative voltage change amount, and the phase estimating means 43a and 43b after the time t9 in FIGS. 2(e) and (f). The count indicated by the grid-like hatching may be a false count.
However, even if the phase estimation means 43a and 43b of the switching circuit 40 are erroneously counted in this way, there is no particular problem because the power feeding switch 3 has already been switched to the power feeding switch 4. ..

As described above, according to the present invention, when the power source is switched, the polarity of the phase voltage from the switching source power source is determined, and when the polarity of the phase voltage is positive, the power supply of the switching destination power source is performed. The gate-on permission signal is given to the positive polarity thyristor of the switch, and in the case of negative polarity, the gate-on permission signal is given to the negative polarity thyristor of the power feed switch of the switching destination power source so that the switching source power source and the switching destination power source are connected. Since the occurrence of the cross current between the AC power supplies is prevented, it is not necessary to provide a synchronization switching means, a means for detecting the cross current flowing between the AC power supplies, and the configuration can be simplified.

Further, when switching from the power source 2 to the power source 1, the switching control circuit 30 on the switch 3 side performs switching without generating a cross current between the power sources at the time of switching, similarly to the switching control circuit 40 on the switch 4 side. be able to.

FIG. 3 shows a second embodiment of the present invention.
In the first embodiment described above, the switching of the power source is controlled with reference to the phase voltage of the power source. Therefore, when the load 5 does not include the inductive component, the occurrence of the cross current can be reliably prevented. However, if the load contains an inductive component and the load current is delayed with respect to the voltage, it may not be possible to prevent the occurrence of cross current.
In the second embodiment, in order to solve such a problem, it is possible to reliably prevent the occurrence of the cross current even if the load current is delayed.

In the second embodiment of FIG. 3, the phase angle α of the delay of the load current due to the inductive component of the load 5 is preset and the phase angle α of the delay is added to the comparison reference value of the comparator 4. I am trying.
Specifically, the reference value setting devices S13a and S14a of the comparators 45a and 45b are set to "180°+α" by adding the phase angle α of the delay to 180°. Further, the reference value setting devices S15a and S16a of the comparators 46a and 46b add "0°+α" by adding the phase angle α of the delay amount to 0° to correct the delay phase amount of the current.
Since the other structure is the same as that of the first embodiment shown in FIG. 1, the description is omitted.

Similarly to the first embodiment, the outputs of the comparators 45a, 45b, 46a, 46b in the second embodiment allow the signal holding means 49a, 49b to turn on through the OR gates 47a, 47b and the AND gates 48a, 48b. It is held as signals S4P and S4N. In the comparators 45a, 45b, 46a, 46b, since the reference value to be compared is a phase delayed by the phase angle α from the reference phase, the phase of the load current I delayed by the phase angle α from the phase voltage is set as the reference value. The comparison is equivalent to determining the polarity of the load current.
Therefore, after the gate-off signal (power supply switching signal) on the conversion source power supply side is output, the gate-on permission signals S4P and S4N are generated when a phase delay of the load current elapses after the phase voltage has a predetermined polarity. Will be done.

As a result, even if the load 5 includes an inductive component and the load current is delayed, the phase delay of the load current can be corrected, so that the source switch 3 and the destination switch 4 can be switched when the power source is switched. As a result, the power supply is not short-circuited, and it is possible to prevent the occurrence of cross current when the power supply is switched.

A third embodiment of the present invention is shown in FIG.
In the third embodiment, the power supply side voltages E1a and E2a or the load side voltages E1b and E2b of the power supply switches 3 and 4 provided between the power sources 1 and 2 and the load 5 are detected to detect the power supply switches. At the time of switching, the source voltage or load voltage of the switching source drops below a predetermined value, and then the switching switch of the switching destination is turned on to suppress the cross current flowing between the two power sources.

Therefore, in order to detect the voltages E1a and E2a on the power supply side of the power supply switches 3 and 4 and the voltages E1b and E2b on the load side, voltage detectors 12a and 12b are respectively provided on the power supply side and the load side of the power supply switches 3 and 4. And 22a and 22b are provided.
The outputs of the voltage detectors 12a and 12b on the power source 1 side are input to the control circuit 40 that controls switching of the power supply switch 4 on the power source 2 side, and the outputs of the voltage detectors 22a and 22b on the power source 2 side are the power source 1 side. Is input to the control circuit 30 which controls the switching of the power feeding switch 3.

Since the control circuits 30 and 40 for controlling the switching of the power feeding switches 3 and 4 have the same configuration, the control circuit 40 of the power feeding switch 4 shows the entire configuration here, and the control circuit 30 of the power feeding switch 3 is Only part of the configuration is shown and the illustration is simplified.
Each of the power supply switches 3 and 4 has a thyristor 3PU (V, W), 3NU (V, W) and a thyristor 4PU (V, W), 4NU (V, W) connected in reverse polarity in parallel. And configure.

The power supply side voltage and the load side voltage of the AC on the power supply 1 side detected by the voltage detectors 12a and 12b input to the control circuit 40 that controls the power supply switch 4 are the DC voltage E1a and the load side voltage, respectively, by the full wave rectifiers REa and REb. Converted to E1b. The DC voltages E1a and E1b are respectively compared by the comparators CPa and CPb with the reference voltage Es set in the reference voltage setters S18a and S18b to determine whether the DC voltages E1a and E1b are higher or lower than the reference voltage Es. judge. The reference voltage Es is set to a low voltage of 10% or less of the rated voltage of the power supplies 1 and 2.

Comparators CPa and CPb generate determination outputs that are "0" when DC voltages E1a and E1b are higher than reference voltage Es, and generate determination outputs that are "1" when they are lower than reference voltage Es.
The judgment outputs of the comparators CPa and CPb are input to one end of an AND gate 48 via the time elements Ta and Tb and the OR gate 47, respectively. To the other end of the AND gate 48, a switching signal S3 to the power feeding switch 3 input from the control circuit 30 that controls switching of the power feeding switch 3 on the power source 1 side is input via the not gate 52.

The time elements Ta and Tb are provided with a time delay ts for reaching the timing when the voltage on the power supply side or the load side becomes 0 V because the thyristor is turned off.

The output signal of the AND gate 48 is held as the gate-on permission signal SI4 by the signal holding means 49 composed of a flip-flop circuit or the like. The switching signal S4 applied to the switching signal input terminal C41 of the control circuit 40 to the power feeding switch 4 is input to the reset terminal R of the signal holding means 49 via the not gate 51. Therefore, when the switching signal S4 becomes "0" and the power supply switch 4 is instructed to be turned off, the signal holding means 49 adds a reset signal which becomes "1" via the knot gate 51, and holds the held gate-on permission signal. SI4 is reset to "0".

The gate-on permission signal SI4 inputted from the signal holding means 49 is passed through the AND gates 48PU, 48NU, 48PV, 48NV and 48PW, 48NW of the switch 4, and the positive polarity thyristors 4PU, 4PV of the phase switches 4U, 4V, 4W are respectively supplied. 4PW and negative polarity thyristors 4NU, 4NV, and 4NW. The switching signal S4 to the power feeding switch 4 is input to the other ends of the AND gates 48PU to 48NW.

Therefore, the AND gates 48PU to 48NW are input with the switching signal S4 which is "1" for instructing the power feeding switch 4 to turn on and the gate-on permission signal SI4 which is "1" from the signal holding means 4 to the other end. When it is turned on, the gate signal is input to the gates of the positive thyristor and the negative polarity thyristor of each phase of the power supply switch 4, and each thyristor (4PU to 4NW) is turned on, so that the power supply switch 4 is turned on and the power supply is turned on. Power is supplied from 2 to the load 5.
The thyristors (3PU to 3NW) of each phase switch of the power feeding switch 3 are also controlled by the control circuit 30 in the same manner as the thyristor of the switch 4.

FIG. 5 shows an operation waveform diagram at the time of switching the power source of the power source switching device of the third embodiment configured as described above.
Next, the power supply switching operation of the power supply switching device of the third embodiment will be described with reference to this figure.

The power supply switching device of FIG. 4 is now in a state where the power supply switch 3 is turned on, the power supply switch 4 is turned off, and power is supplied from the power supply 1 to the load 5 through the power supply switch 3. The switching operation in the case where the power supply switch 3 is turned off and the power supply switch 4 is turned on from this state to switch the power supply 2 to the load 5 through the power supply switch 4 will be described. Therefore, here, the power source 1 is the switching source power source and the power source 2 is the switching destination power source.

At time t50 in FIG. 5, the switching signal S3 for the power feed switch 3 input from the outside to the input end C31 of the control circuit 30 becomes “1”, and the power feed switch 4 input to the input end C41 of the control circuit 40 from the outside. The switching signal S4 for the signal is "0", and this state continues until time t51 when the power supply switching command is issued.
When the power supply switch 3 is turned on and power is being supplied from the power supply 1 to the load 5 through the power supply path 11, the three-phase AC on the power supply side of the power supply switch 3 is controlled by the voltage generator 12a provided on the power supply side of the power supply switch 3. A voltage is detected, which is rectified by the full-wave rectifier circuit REa in the control circuit 40 and converted into a DC power supply voltage E1a. This is shown as the power supply voltage E1a in FIG.

Similarly, the voltage detector 12b provided on the load side of the power feed switch 3 detects a three-phase AC voltage applied to the load 5 from the power supply 1 through the power feed switch 3, and this is rectified by the full-wave rectifier circuit REb to generate a direct current. It is converted into the load voltage E1b. This is shown as load voltage E1b in FIG. 5(b).

The power supply voltage E1a on the power supply side and the load voltage E1b on the load side of the power supply switch 3 of the switching source power supply 1 are the same when the power supply switch 3 is on. The voltages E1a and E1b are input to the comparators CPa and CPb, respectively, and are constantly compared with the reference value Es set in the reference value setters S18a and S18b. The voltage E1a, E1b is higher than the reference value Es until the time point t51 when the power supply switching is commanded, so the determination outputs of the comparators CPa and CPb are “0” as shown in FIGS. 5(e) and (f). Become.
For this reason, the gate-on enable signal SI4 output from the signal holding means 49 is "0" as shown in FIG. 5(j), so that the AND gates 48PU to 48NW of the power feeding switch 4 output the thyristor of each phase. The gate signal G4 input to the gate becomes "0" as shown in FIG. 5(l), and the power feeding switch 4 is off.

At time t51, in order to switch the power supply to the load 5 from the power supply 1 to the power supply 2, the switching signal S3 for the power supply switch 3 is changed from "1" to "0" as shown in FIGS. 5C and 5D. The switching signal S4 for the power feeding switch 4 is simultaneously switched from "0" to "1".
As a result, the signal holding means 39 holding the gate-on permission signal SI3 of the control circuit 30 is immediately reset, and the gate-on permission signal SI3 becomes "0" (see FIG. 5(i)). The gate signal G3 to the thyristor switches 3U to 3W of each phase is 0 (see FIG. 5(k)), and the voltage of each phase of the thyristor switches 3U to 3W of the feed switch 3 becomes zero. Are sequentially turned off, and the power feeding switch 3 is turned off.

By sequentially turning off the thyristor switches 3U to 3W of each phase of the power feeding switch 3, the load side voltage E1b of the power feeding switch 3 gradually decreases from the time point t51, as shown in FIG. 5B. If there is no abnormality in the power supply 1, the power supply side voltage E1a is maintained at a constant voltage as shown in FIG.

When the load side voltage E1b reaches the reference value Es at time t52, the comparator CPb generates a determination output that is “1” (see FIG. 5(f)). The determination output that has become “1” is delayed by the time-limiting element Tb by the time period ts corresponding to the delay phase angle of the load current, and is input to the set input of the signal holding means 49 through the AND gate 48. Since the AND gate 48 has been opened by the switching signal S3 which has already been input via the NOT gate 52 and has become "0", the signal holding means 49 sets the gate-on permission which becomes "1" at time t52. The signal SI4 is held (see FIG. 5(j)).

By inputting the gate-on permission signal SI4, which is "1", to the AND gates 48PU to 48NW of the gate circuits of the thyristor switches of the respective phases of the power feeding switch 4, "1" is already present at the other ends of these AND gates. Since the switching signal S4 of the power feeding switch 4 is input, the gate signal G4 of "1" is input to the gate of the thyristor switch of each phase of the power feeding switch 4, and these thyristor switches are turned on to supply the power feeding switch. 4 turns on.

As described above, after the switching signal S4 is applied at the time point t51, the power feeding switch 4 is further connected to the timing element Tb from the time point t52 when the voltage E1 applied from the power source 1 to the load 5 reaches the preset reference voltage Es. It is turned on at time t53, which is delayed by the time ts until the voltage on the load side becomes 0 V in advance. At this time, the voltage E1b applied from the power supply switch 3 to the load 5 is lower than the reference voltage Es and becomes a sufficiently low voltage, and the current flowing through the load 5 also decreases to almost zero, and the thyristor is turned off. A cross current does not occur even when the power supply switch 4 is turned on.

When switching the power supply to the load 5 from the power source 2 to the power source 1, the switching control is performed by the control circuit 30 similarly to the control circuit 40.
Further, the voltage detectors 12a and 22a that detect the voltage on the power supply side of the power supply switches 3 and 4 are used to switch to a sound power supply when a power failure or a voltage drop occurs in the power supply during power supply due to an accident or the like. It will be.

1, 2: AC power supply 11, 21: Power feeding path 12, 22: Voltage detector 3, 4: Power feeding switch 5: Loads 3P, 3N, 4P, 4N: Thyristor 30, 40: Switching control circuit 41: Differentiating means 42a : 90° phase detecting means 42b: 270° phase detecting means 43a, 43b: phase voltage phase estimating means (counter)
44a, 44b: Count initial value setting devices 45a, 45b, 46a, 46b: Comparators 47a, 47b: OR gates 38P, 38N, 48a, 48b, 48P, 48N: AND gates 49a, 49b: Signal holding means (flip-flop circuits)
51, 52, 53, 54: Not gates C31, C32, C41, C42: Switching signal input terminal S3: Switching signal for power feeding switch 3 S4: Switching signal for power feeding switch 4 G3P, G3N, G4P, G4N: Gate signal SI3P, SI3N, SI4P, SI4N: Gate-on permission signal

The present invention relates to a power supply switching device for selectively supplying power to a load from two alternating-current power supplies.

Generally, in a power supply device including two redundant AC power supplies capable of selectively supplying power to a load, when an abnormality such as a power failure or a voltage drop occurs in the power supply system during power supply, the power supply system has a normal voltage. It is switched to the standby power supply. The power source is switched by the power source switching device. However, when the changeover switches for switching the power source system are simultaneously turned on, a short circuit occurs between the two power sources and a cross current flows.

On the other hand, if the switching of the power supply system is delayed, there is a problem that a power failure or voltage fluctuation occurs with respect to the load.

As a power supply switching device for suppressing such voltage fluctuations and occurrence of cross current, devices disclosed in Patent Documents 1 and 2 have been conventionally known. However, such a conventional power supply switching device has a synchronous switching means for switching the voltage of the power supply including the inverter and the voltage of the other commercial AC power supply in synchronization with each other, and a cross current component flowing between the AC power supplies. There is a problem in that the configuration becomes complicated because it is provided with a means for detecting.

Japanese Patent Laid-Open No. 09-019065 Japanese Patent Publication No. 07-004052

In order to solve the above-mentioned problems in the conventional apparatus, the present invention can prevent the occurrence of a cross current at the time of power supply switching without providing a synchronization switching means, a means for detecting a cross current component flowing between AC power supplies. An object of the present invention is to provide a power supply switching device having a simple structure.

In order to solve the above-mentioned problems, the present invention is configured such that two thyristor elements are respectively connected in parallel in reverse polarity to two power supply circuits that supply power to a common load from each of the first and second AC power supplies. In the power supply switching device, which is provided with the power supply switch, and switches the power supply to the load by switching these power supply switches on and off,
Corresponding to each of the power supply switches, voltage detection means for detecting at least the load-side all-phase voltage of the power supply switch, and voltage conversion means for full-wave rectifying the output of this voltage detection means to convert it to a DC voltage. The voltage determining means for determining that the output voltage of the voltage converting means is lower than a reference value, and the voltage determining means for the power supply switch that is turned on when a switching command is given to the two power supply switches. A switching control circuit having means for giving a gate-on permission signal to the thyristor of the power feed switch on the side turned off based on the determination output.
Further, in the present invention, it is possible to provide a timing element for delaying the judgment output of the voltage judgment means by a time corresponding to the delay phase angle of the load current corresponding to the inductive component of the load.

According to the present invention, when the power supply switch is switched by turning on and off the power supply switch formed by the thyristor element, which is provided in each of the two power supply circuits for supplying power from the two AC power supplies to the common load, each power supply switch is switched. in response to detect the total phase voltage of at least the load side of the power supply switch, the detection output by the full-wave rectified into a DC voltage, determines that the output voltage has dropped below a predetermined value, when switching instruction into two feed switch is given, since the to give a gate-on enable signal to the thyristor of the feed switch on the side that is turned off based on the determination output of the power supply switch on and have that side, 2 When switching one power feeding switch, the thyristors of the two power feeding switches are not turned on at the same time, and the thyristor of the power feeding switch on the off side is turned on after the thyristor of the on side switch is turned off. .. Therefore, it is possible to prevent the occurrence of a cross current when the power supply circuit is switched, without providing a synchronous switching means, a means for detecting a cross current flowing between the AC power supplies, or the like.

It is a circuit block diagram which shows the 1st reference example of this invention. It is an operation|movement waveform diagram of the 1st reference example of this invention. It is a circuit block diagram which shows the 2nd reference example of this invention. It is a circuit block diagram which shows the Example of this invention. It is an operation|movement waveform diagram of the Example of this invention.

Embodiments of the present invention will be described with reference to examples shown in the drawings.

Reference example 1

FIG. 1 is a configuration diagram showing a first reference example of a power supply switching device of the present invention. Since each phase of a three-phase AC circuit has the same configuration, only the U-phase circuit configuration is shown here, The circuit configuration of the phase is indicated by a block.

In FIG. 1, 1 and 2 are first and second three-phase AC power supplies. Each of the two AC power supplies switches the three-phase power supply paths 11 and 21 to supply power to the common load 5. The power supply paths 11 and 21 are provided with power supply switches 3 and 4 for selectively switching the power supply paths to the voltage detectors 12 and 22 and the load 5, respectively. The switches 3U to 3W and 4U to 4W for the respective phases of the power feeding switches 3 and 4 are configured by connecting in parallel two thyristors 3P, 3N, and 4P, 4N having opposite polarities. In this case, the polarity of the thyristors 3P and 4P in which the current flow direction is directed from the power supply to the load side is positive in the feed switch of each phase and the current flow direction is directed from the load to the power supply side. The polarities of 3N and 4N are defined as negative polarity.

The feed switches 3 and 4 are provided with switching control circuits 30 and 40 for each phase. The switching control circuits 30 and 40 prevent the other power feeding switch from being turned off and the two power feeding switches 3 and 4 from being turned on at the same time when one power feeding switch is turned on by a switching command from the outside. Controls the on/off switching of the power feeding switches 3 and 4.

The switching control circuit 30 turns on (“1”) the gate signals G3P and G3N to the thyristors 3P and 3N of the power feeding switch 3 when the switching signal S3 to the power feeding switch 3 is on (“1”), and the power feeding switch 4 The gate signals G4P and G4N to the thyristors 4P and 4N are turned off ("0"). Then, when the switching signal S4 for the power feeding switch 4 is on (“1”), the switching control circuit 40 turns on (“1”) the gate signals G4P, G4N to the thyristors 4P, 4N of the power feeding switch 4 to feed power. The gate signals G3P and G3N to the thyristors 3P and 3N of the switch 3 are turned off (“0”).

Since the switching control circuits 30 and 40 have the same configuration, only the configuration of the switching control circuit 40 is shown in detail in FIG. 1, and the switching control circuit 30 is shown as a block, and the detailed configuration is omitted.

The switching control circuit 40 includes a differential operation unit 41 that obtains a differential value of the U-V phase line voltage E1 _UV of the three-phase AC power source 1 detected by the voltage detector 12. The differentiating means 41 performs the differentiating operation by sampling the line voltage E1 _UV thus detected in synchronization with a predetermined clock signal and taking in it, and obtaining a change amount between the voltage value previously taken in and the voltage value taken in this time. To do.

The output of the differential operation means 41 is input to the 90° phase detection means 42a and the 270° phase detection means 42b in order to detect the 90° and 270° phases of the line voltage E1 _UV of the power supply path 11. The 90° phase detecting means 42a monitors the change in the polarity of the differential value E1 _UV ′ of the line voltage E1 _{U V} output from the differential calculating means 41, and the timing at which the differential value, that is, the amount of change changes from positive to negative. Then, the 90° phase detection signal S90 of the line voltage E1 _UV is generated. The 270° phase detecting means 42b monitors a change in the polarity of the differential value E1 _UV ′ of the line voltage E1 _UV output from the differential calculating means 41, and catches the timing when the differential value, that is, the change amount changes from negative to positive. And generates a 270° phase detection signal S270 of the line voltage E1 _UV .

90 ° phase detecting means 42a and 270 ° detection signals S90 and S270 from the phase detection unit 42b is input to the phase estimation means 43a and 43b for estimating the phase of the power supply 1 U phase voltage E1 _U.
The phase estimating means 43a and 43b are composed of counters that count the clock signal Cl. The counter which constitutes the phase estimating means 43a starts counting from the initial value 60° set in the initial value setting device 44a by the 90° phase detection signal S90, counts the clock signal Cl corresponding to 180°, and 240°. When the count value of is reached, the count value is reset. The counter constituting the phase estimating means 43b starts counting from the initial value 240° set in the initial value setting unit 44b by the 270° phase detection signal S270, counts a clock corresponding to 180°, and 420° (60°). The count value is reset when (°) is reached. From this, it is estimated from each count value how much the phase of the phase voltage has advanced from the detected 90° and 270° phase of the line voltage.

Since the phase voltage has a phase delay of 30° with respect to the line voltage, as is well known, the initial values of the counters of the phase estimating means 43a and 43b are set by the initial value setting devices 44a and 44b. By setting to 60° and 240°, which are 30° less than the detected values of 90° and 270°, respectively, the phase of the detected line voltage is converted into the phase of the phase voltage, and immediately from the count values of the phase estimating means 43a and 43b. The phase of the phase voltage can be estimated. The reset values of the counters of the phase estimating means 43a and 43b are set to 240° and 60° for the same reason.
Accordingly, the count value of the phase estimation means 43a and 43b, the phase voltage E1, would indicate an estimate of the phase of the U-phase voltage E1 _U here.

The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimation means 43a is input to the comparison inputs of the comparators 45a and 45b. The comparator 45a compares the count value indicating the phase estimated value θ _U with the set value 180° input to the negative reference input from the setter S13, and when the phase estimated value θ _U is equal to or larger than the set value 180°, “1” is set. Then, when the set value is 180° or less, the comparison output S45a which is "0" is generated. Further, the comparator 45b compares the phase estimation value θ _U input to the comparison input with the set value 180° input to the positive reference input from the setter S14, and the phase estimated value θ _U is set to 180°. The comparison output S45b is "1" in the following cases, and "0" in the case where the set value is 180° or more.
The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimation means 43b is input to the comparison inputs of the comparators 46a and 46b. The comparator 46a compares the count value indicating the phase estimated value θ _U with the set value 0° input to the positive reference input from the setter S15, and when the phase estimated value θ _U is equal to or larger than the set value 0°, “1” is set. , And when the set value is 0° or less, the comparison output S46a which is "0" is generated. Further, the comparator 46b compares the phase estimated value θ _U input to the comparison input with the set value 0° input to the positive reference input from the setter S16, and the phase estimated value θ _U is set to 0°. The comparison output S46b is "1" in the following cases, and "0" in the case of the set value or more.

The outputs S45b and S46a of the comparator 45b and the comparator 46a are input to the signal holding means 49a composed of a flip-flop circuit via the OR gate 47a and the AND gate 48a. The outputs S45a and S46b of the comparator 45a and the comparator 46b are input to the signal holding means 49b composed of a flip-flop circuit via the OR gate 47b and the AND gate 48b.

The output of the signal holding means 49a is input to the AND gate 48P as a gate-on permission signal S4P for the positive thyristor 4P of the power feeding switch 4 of the power feeding path 21. Further, the output of the signal holding means 49b is input to the AND gate 48N as a gate-on permission signal S4N for the negative polarity thyristor 4N of the power feeding switch 4 of the power feeding path 21.

The switching signal input terminal C41 of the switching control circuit 40 receives the switching signal S4 from the outside to the power feeding switch 4, while the switching signal input terminal C42 rejects the switching signal S3 to the power feeding switch 3. S3 is input. The switching signal input terminal C31 of the switching control circuit 30 receives the switching signal S3 to the power feeding switch 3, while the switching signal input terminal C32 receives the signal S4 that negates the switching signal S4 to the power feeding switch 4. Is entered.
When the switching signal S4 to the power feeding switch 4 becomes "1" to instruct the power feeding switch 4 to turn on, the switching signal S3 to the power feeding switch 3 becomes "0" to command the power feeding switch 3 to turn off. .. On the contrary, when the switching signal S3 to the power feeding switch 3 becomes "1" and the power feeding switch 3 is instructed to turn on, the switching signal S4 to the power feeding switch 4 becomes "0" and the power feeding switch 4 is instructed. Command off.
When the switching signal S4 to the power feeding switch 4 becomes "0" and the off command is issued, the signal holding means 49a and 49b receives a reset signal which becomes "1" via the knot gate 51, and holds the signals. Means 49a, 49b are reset.

Further, the switching signal S3 input from the switching control circuit 30 to the switching control circuit 40 is input to the AND gates 48a and 48b via the knot gate 52. The switching signal S4 input from the switching control circuit 40 to the switching control circuit 30 corresponds to AND gates 48a and 48b in the switching control circuit 40 via the knot gate 53. The switching control circuit 30 is not shown here. Input to the AND gate inside.
The line voltage E2 _UV detected by the voltage detector 22 of the power supply path 21 is input to the switching control circuit 30.

Next, the operation of the power supply switching device of the present invention thus constructed will be described with reference to the operation waveform diagram shown in FIG.

In the power source switching device of FIG. 1, when no measures against cross current are taken, for example, in the process of switching from the power source 1 of the switching source to the power source 2 of the switching destination, the U-phase power supply switch 3U on the power source 1 side. When the positive thyristor 3P is turned on and the current IP1 shown by the dotted line flows through the load 5 and the negative thyristor 4N of the U-phase power supply switch 4U on the power supply 2 side is turned on, the power is supplied through this. The current IN2 flows from 1 to the power source 2 as a cross current until the thyristor 3P is turned off as shown by the dotted line.
The present invention prevents such a cross current IN2 from flowing.

Here, the power supply switching device of FIG. 1 is in a state where the power supply switch 3 is turned on, the power supply switch 4 is turned off, and power is supplied from the power supply 1 to the load 5 through the power supply switch 3. The switching operation in the case where the power supply switch 3 is turned off and the power supply switch 4 is turned on from this state to switch the power supply 2 to the load 5 through the power supply switch 4 will be described. Therefore, here, the power source 1 is the switching source power source and the power source 2 is the switching destination power source.

In the state where the power supply switch 3 is turned on and the current I1 is supplied from the power supply 1 to the load 5 through the power supply path 11, the voltage generator 12 causes the U-V of the power supply 1 as shown by the solid line in FIG. The line voltage E1 _UV between the phases is detected.
The line voltage E1 _UV of the switching source power source 1 is input to the differentiation operation means 41 of the switching control circuit 40 on the switching destination power source 2 side and differentiated. From this differential calculation means 41, a differential voltage E1 _UV ' of a line voltage as shown in FIG. 2B is obtained.

'As is apparent from the waveform of the differential voltage _{E1 UV'} the differential voltage _{E1 UV} period becomes positive is voltage positive variation as shown in FIG. 2 (c) is "1", and the differential voltage _{E1 UV} ' During the period in which is negative, the negative voltage change amount is “1” as shown in FIG.

The 90° phase detecting means 42a monitors the voltage negative change amount of the line voltage E1 _UV shown in FIG. 2D, detects that it rises from 0 to 1, and generates a 90° phase detection signal S90. .. Therefore, the 90° phase detection means 42a generates the 90° phase detection signal S90 at time t6 when the line voltage E1 _{U V} becomes 90° in phase, as shown in FIG. 2(e).

The 270° phase detecting means 42b monitors the positive change amount of the line voltage E1 _UV shown in FIG. 2C, detects that it rises from 0 to 1, and generates the 270° phase detection signal S270. .. Therefore, the 270° phase detection signal S270 is generated at time t3 when the line voltage E1 _UV has a 270° phase, as shown in FIG. 2(f).

The phase estimating means 43a and 43b for counting the clock signal Cl and estimating the phase of the phase voltage E1 of the power supply 1 have a 90° phase detection signal S90 and a 90° phase detection signal S90 as shown in FIGS. 2(g) and 2(h), respectively. When the 270° phase detection signal S270 is input, counting is started from the initial values 60° and 240° set in the initial value setters 44a and 44b, respectively. The phase estimating means 43a and 43b that have started counting, start counting by the 270° phase detection signal S270 and the 90° phase detection signal S90, respectively, and then count until the count values become 240° and 60°, respectively. When it reaches 240° and 60°, the count value is reset to the initial value (60° and 240°).

Therefore, the phase estimating means 43a performs the counting operation until the time point t3 and between the time points t6 and t10, and the phase estimating means 43b performs the counting operation between the time points t3 and t6. the value, the phase estimate of the U-phase voltage switch 3U is inserted in the U-phase E1 _U is shown.
The count value indicating the estimated phase value θ _U of the U-phase voltage E1 _U of the phase estimating means 43a and 43b is compared with the set value 180° set in the setters S13 and S14 by the comparators 45a and 45b, respectively. The comparator 45a generates a signal S45a which becomes "1" when the count value (phase voltage phase estimated value) is 180° or more, and the comparator 45b outputs "1" when the count value is 180° or less. Signal S45b is generated. Thus, it detects that the output of the comparator 45a, the phase voltage E1 can detect that _{the U} phase is above 180 °, and the phase of the phase voltage E1 _U from the output of the comparator 45b is 180 ° or less.

The count value indicating the phase voltage phase estimated value of the phase estimating means 43b is compared with the set value 0° set in the setters S15 and S16 by the comparators 46a and 46b, and if the count value is 0° or more, the comparator. 46a outputs the signal S46a which becomes "1", and when the count value is 0° or less, the comparator 46b outputs the signal S46b which becomes "1". Thus detect that the comparator output from the phase voltages E1 _U phase 46a is able to detect that the 0 ° or more, and the phase of the phase voltage E1 _U from the output of the comparator 46b is 0 ° or less.

Therefore, from the OR gate 47a for extracting the OR outputs of the comparators 45b and 46a, the phase of the phase voltage E1 _U is "1" as shown in FIG. 2(i) while the phase is 0° (360°) to 180°. Output is generated. This phase because the voltage shows a positive polarity E1 _U, can detect a positive polarity of the phase voltage E1 _U from the output of the OR gate 47a.

OR gate 47b for taking out an OR output of comparator 45a and 46b are 360 (0) from phase 180 ° of the phase voltage E1 _U ° between the output becomes "1" as shown in FIG. 2 (j) is generated To be done. This indicates the negative polarity of the phase voltage E1 _U, can detect a negative polarity of the phase voltage from the output E1 _U of the OR gate 47b.

The outputs of the OR gates 47a and 47b are input to one ends of the AND gates 48a and 48b, respectively. To the other ends of these AND gates 48a and 48b, the signal S3 that is the negation of the switching signal S3 of the switch 3 is input via the NOT gate 52. Therefore, the AND gate 48a, between t5~t9 time when the phase voltage E1 _U as shown in FIG. 2 (i) has a positive polarity, the switching signal S3 is such that shown in FIG. 2 (k) When it is turned off, that is, when it becomes "0", the output S48a which becomes "1" is obtained, and this is held as the gate-on permission signal S4P by the signal holding means 49a. The gate-on permission signal S4P is input to one end of an AND gate 48P that outputs a gate signal to the positive thyristor 4P of the power supply switch 4 on the power supply 2 side.

Further, the AND from the gate 48b, between the negative polarity going on t2~t5 when the phase voltage E1 _U as shown in FIG. 2 (j), or at t9 after time, switching signal S3 is FIG 2 (k ), when it is turned off, that is, when it is "0", an output S48b which is "1" is obtained, and this is held as the gate-on permission signal S4N by the signal holding means 49b. The gate-on permission signal S4N is input to one end of an AND gate 48N that outputs a gate signal to the negative polarity thyristor 4N of the power supply switch 4 on the power supply 2 side.

As described above, when the switching signal S4 for instructing the switching to the power feeding switch 4 is turned on (“1”) with the gate-on permission signal S4P or S4N being input to one end of the AND gate 48P or 48N, the AND gate 48P Alternatively, since the gate signals G4P and G4N are generated from 48N and output to the positive polarity thyristor 4P or the negative polarity thyristor 4N of the power feeding switch 4, the thyristor 4P or thyristor 4N is turned on.

In the state where the power supply switch 3 in FIG. 1 is turned on and power is being supplied from the power supply 1 to the load 5 through the power supply path 11, a power supply switching command is given at time t7 and the switching signal S3 of the power supply switch 3 is turned on (“1 )) to off (“0”) and the switching signal S4 of the power supply switch 4 switches from off (“0”) to on (“1”), the gate signal G3P to the switch 3 on the power supply 1 side is displayed. , G3N are turned off by AND gates 38P, 38N. In this case, since the still U-phase voltage E1 _U of the power supply 3 is in the positive polarity, the positive polarity thyristor 3P switch 3U gate signal to continue flowing be turned off. This voltage of the phase voltage E1 _U is negative polarity, is continued until the current I1 flowing through the thyristor 3P passes through the zero point.

In this state, when the negative thyristor 4N of the switch 4U of the power supply switch 4 on the power source 2 side, which has the same current conduction polarity as the positive thyristor 3P of the switch 3U, which is in conduction, becomes conductive, the conduction is continued. The cross current IP2 flows from the power source 1 to the power source 2 through the negative polarity thyristor 4N of the switch 4U which starts conduction with the positive polarity thyristor 3P.

However, in the present invention, it is given a power switching command at time t7, when the phase voltage E1 _U is in the positive polarity, providing a gate-on enable signal S4P, a gate signal to the positive thyristor 4P switches 4U and Since it is given only to the gate 48P and is not given to the AND gate 48N which gives the gate signal to the negative polarity thyristor 4N, the negative polarity thyristor 4N is not turned on during this period.

Further, when the gate-on permission signal S4P is given, the AND gate 48P is turned on, the gate signal G4P is input to the gate of the positive polarity thyristor 3P, and this thyristor 4P is turned on, but the flow direction of the thyristor 4P is the power source. The thyristor 4P blocks the cross flow because it is opposite to the flow direction of the cross flow flowing from the first side.
Therefore, until the positive polarity end time t9 voltage E1 _U to positive thyristor 3P is flowing through the switch 3, the switch 4 (4U) never to flow through the lateral flow, the power supply 2 from the power supply 1 side A cross current is prevented from flowing.

In t9 when the positive polarity end of the phase voltage E1 _U, because the current I1 is zero, positive thyristor 3P switch 3 (3U) are turned off, the switch 3 (3U) is closed, power source 1 is cut off It
Even if the power supply 1 is cut off, the voltage phase estimation means 43a continues from the timing (t6) when the 90° phase of the line voltage (60° of the phase voltage) is finally detected until the phase voltage becomes 240°. To continue counting regardless of the presence or absence of voltage, the timing when the phase advances by 120° from the initial count value (60°) and the polarity of the phase voltage E1 _U changes to turn off the thyristor (180° phase voltage phase It is possible to estimate that the time t9, which is That is, when the count value indicating the phase estimation value of the phase estimation means 43a becomes 180° or more, the output signal S45a of "1" output from the comparator 45a turns off the thyristor 3U at the timing (of the phase voltage). 180° phase).

The output signal S45a became "1" indicating that the phase voltage E1 _U of the comparator 45a is negative are input to the signal holding unit 49b via the OR gate 47b and an AND gate 48b,, switching signal switching destination S4 is the on ( "1"), made possible phase voltage E1 _U is held in the signal holding unit 49b when the first becomes negative. As a result, the gate holding enable signal S4N is given from the signal holding means 49b to the AND gate 48N, and the switching signal S4 of the switch 4 (4U) is supplied as the gate signal G4N through the AND gate 48N to the gate of the negative thyristor 4N of the switch 4 (4U). Given to. As a result, the negative polarity thyristor 4N of the switch 4 (4U) becomes conductive, power supply from the power supply 2 to the load 5 is started, and the switching of the power supply is completed.

When the input voltage E1 _UV of the switching circuit 40 becomes zero by turning off the thyristor 3P of the power feeding switch 3 at time t9 when the phase voltage E1 _U becomes zero, the output of the phase detecting means (42a, 42b). Since the signal becomes indefinite, the positive voltage change amount, the negative voltage change amount, and the 90° detection signal S90 and the 270° detection signal S270 are shown in FIGS. 2(c), (d), (e), and (f). As shown by the solid hatching, it becomes indefinite after time t9. As a result, the phase estimating means 43a and 43b start counting at the false rise of the positive voltage change amount and the negative voltage change amount, and the phase estimating means 43a and 43b after the time t9 in FIGS. 2(e) and (f). The count indicated by the grid-like hatching may be a false count.
However, even if the phase estimation means 43a and 43b of the switching circuit 40 are erroneously counted in this way, there is no particular problem because the power feeding switch 3 has already been switched to the power feeding switch 4. ..

As described above, according to the present invention, when the power source is switched, the polarity of the phase voltage from the switching source power source is determined, and when the polarity of the phase voltage is positive, the power supply of the switching destination power source is performed. The gate-on permission signal is given to the positive polarity thyristor of the switch, and in the case of negative polarity, the gate-on permission signal is given to the negative polarity thyristor of the power feed switch of the switching destination power source so that the switching source power source and the switching destination power source are connected. Since the generation of the cross current between the AC power supplies is prevented, it is not necessary to provide a synchronization switching means, a means for detecting the cross current flowing between the AC power supplies, and the configuration can be simplified.

Further, when switching from the power source 2 to the power source 1, the switching control circuit 30 on the switch 3 side performs switching without generating a cross current between the power sources at the time of switching, similarly to the switching control circuit 40 on the switch 4 side. be able to.

Reference example 2

FIG. 3 shows a second reference example of the present invention.
In the first reference example described above, since the switching of the power source is controlled with reference to the phase voltage of the power source, when the load 5 does not include an inductive component, it is possible to reliably prevent the occurrence of the cross current. However, if the load contains an inductive component and the load current is delayed with respect to the voltage, it may not be possible to prevent the occurrence of cross current.
In the second reference example , in order to solve such a problem, it is possible to reliably prevent the occurrence of a cross current even if a delay occurs in the load current.

In the second reference example of FIG. 3, the phase angle α of the delay of the load current due to the inductive component of the load 5 is preset and the phase angle α of the delay is added to the comparison reference value of the comparator 4. I am trying.
Specifically, the reference value setting devices S13a and S14a of the comparators 45a and 45b are set to "180°+α" by adding the phase angle α of the delay to 180°. Further, the reference value setting devices S15a and S16a of the comparators 46a and 46b add "0°+α" by adding the phase angle α of the delay amount to 0° to correct the delay phase amount of the current.
The other configuration is the same as that of the first reference example shown in FIG.

The outputs of the comparators 45a, 45b, 46a, 46b in the second reference example are gated on to the signal holding means 49a, 49b via the OR gates 47a, 47b and the AND gates 48a, 48b, as in the first reference example. It is held as signals S4P and S4N. In the comparators 45a, 45b, 46a, 46b, since the reference value to be compared is a phase delayed by the phase angle α from the reference phase, the phase of the load current I delayed by the phase angle α from the phase voltage is set as the reference value. The comparison is equivalent to determining the polarity of the load current.
Therefore, after the gate-off signal (power supply switching signal) on the conversion source power supply side is output, the gate-on permission signals S4P and S4N are generated when a phase delay of the load current elapses after the phase voltage has a predetermined polarity. Will be done.

As a result, even if the load 5 includes an inductive component and the load current is delayed, the phase delay of the load current can be corrected, so that the source switch 3 and the destination switch 4 can be switched when the power source is switched. As a result, the power supply is not short-circuited, and it is possible to prevent the occurrence of cross current when the power supply is switched.

Shows an embodiment of the present invention in FIG.
In this embodiment , the power supply side voltages E1a, E2a or the load side voltages E1b, E2b of the power supply switches 3 and 4 provided between the power supplies 1 and 2 and the load 5 are detected, and when the power supply switches are switched, After the power source voltage or the load voltage of the switching source drops below a predetermined value, the changeover switch of the switching destination is turned on to suppress the cross current flowing between the two power sources.

Therefore, in order to detect the voltages E1a and E2a on the power supply side of the power supply switches 3 and 4 and the voltages E1b and E2b on the load side, voltage detectors 12a and 12b are respectively provided on the power supply side and the load side of the power supply switches 3 and 4. And 22a and 22b are provided.
The outputs of the voltage detectors 12a and 12b on the power source 1 side are input to the control circuit 40 that controls switching of the power supply switch 4 on the power source 2 side, and the outputs of the voltage detectors 22a and 22b on the power source 2 side are the power source 1 side. Is input to the control circuit 30 which controls the switching of the power feeding switch 3.

Since the control circuits 30 and 40 for controlling the switching of the power feeding switches 3 and 4 have the same configuration, the control circuit 40 of the power feeding switch 4 shows the entire configuration here, and the control circuit 30 of the power feeding switch 3 is Only part of the configuration is shown and the illustration is simplified.
The power feeding switches 3 and 4 of the respective phases are two thyristors 3PU (V, W), 3NU (V, W) and thyristors 4PU (V, W) and 4NU (V, W) connected in reverse polarity in parallel, respectively. And configure.

The power supply side voltage and the load side voltage of the AC on the power supply 1 side detected by the voltage detectors 12a and 12b input to the control circuit 40 that controls the power supply switch 4 are the DC voltage E1a and the load side voltage, respectively, by the full wave rectifiers REa and REb. Converted to E1b. The DC voltages E1a and E1b are respectively compared by the comparators CPa and CPb with the reference voltage Es set in the reference voltage setters S18a and S18b to determine whether the DC voltages E1a and E1b are higher or lower than the reference voltage Es. judge. The reference voltage Es is set to a low voltage of 10% or less of the rated voltage of the power supplies 1 and 2.

Comparators CPa and CPb generate determination outputs that are "0" when DC voltages E1a and E1b are higher than reference voltage Es, and generate determination outputs that are "1" when they are lower than reference voltage Es.
The judgment outputs of the comparators CPa and CPb are input to one end of an AND gate 48 via the time elements Ta and Tb and the OR gate 47, respectively. To the other end of the AND gate 48, a switching signal S3 to the power feeding switch 3 input from the control circuit 30 that controls switching of the power feeding switch 3 on the power source 1 side is input via the not gate 52.

The time elements Ta and Tb are provided with a time delay ts for reaching the timing when the voltage on the power source side or the load side becomes 0V because the thyristor is turned off.

The output signal of the AND gate 48 is held as the gate-on permission signal SI4 by the signal holding means 49 composed of a flip-flop circuit or the like. The switching signal S4 applied to the switching signal input terminal C41 of the control circuit 40 to the power feeding switch 4 is input to the reset terminal R of the signal holding means 49 via the not gate 51. Therefore, when the switching signal S4 becomes "0" and the power supply switch 4 is instructed to be turned off, the signal holding means 49 adds a reset signal which becomes "1" via the knot gate 51, and holds the held gate-on permission signal. SI4 is reset to "0".

The gate-on permission signal SI4 input from the signal holding means 49 is passed through the AND gates 48PU, 48NU, 48PV, 48NV and 48PW, 48NW of the switch 4, and the positive polarity thyristors 4PU, 4PV of the phase switches 4U, 4V, 4W are respectively supplied. 4PW and negative polarity thyristors 4NU, 4NV, and 4NW. The switching signal S4 to the power feeding switch 4 is input to the other ends of the AND gates 48PU to 48NW.

Therefore, the AND gates 48PU to 48NW are input with the switching signal S4 which is "1" for instructing the power feeding switch 4 to turn on and the gate-on permission signal SI4 which is "1" from the signal holding means 4 to the other end. When it is turned on, the gate signal is input to the gates of the positive thyristor and the negative polarity thyristor of each phase of the power supply switch 4, and each thyristor (4PU to 4NW) is turned on, so that the power supply switch 4 is turned on and the power supply Power is supplied from 2 to the load 5.
The thyristors (3PU to 3NW) of each phase switch of the power feeding switch 3 are also controlled by the control circuit 30 in the same manner as the thyristor of the switch 4.

FIG. 5 shows an operation waveform diagram at the time of switching the power source of the power source switching device of the embodiment configured as described above.
Next, the power supply switching operation of the power supply switching device of the embodiment will be described with reference to this figure.

The power supply switching device of FIG. 4 is now in a state where the power supply switch 3 is turned on, the power supply switch 4 is turned off, and power is supplied from the power supply 1 to the load 5 through the power supply switch 3. The switching operation in the case where the power supply switch 3 is turned off and the power supply switch 4 is turned on from this state to switch the power supply 2 to the load 5 through the power supply switch 4 will be described. Therefore, here, the power source 1 is the switching source power source and the power source 2 is the switching destination power source.

At time t50 in FIG. 5, the switching signal S3 for the power feed switch 3 input from the outside to the input end C31 of the control circuit 30 becomes “1”, and the power feed switch 4 input to the input end C41 of the control circuit 40 from the outside. The switching signal S4 for the signal is "0", and this state continues until time t51 when the power supply switching command is issued.
When the power supply switch 3 is turned on and power is being supplied from the power supply 1 to the load 5 through the power supply path 11, the three-phase AC on the power supply side of the power supply switch 3 is controlled by the voltage generator 12a provided on the power supply side of the power supply switch 3. A voltage is detected, which is rectified by the full-wave rectifier circuit REa in the control circuit 40 and converted into a DC power supply voltage E1a. This is shown as the power supply voltage E1a in FIG.

Similarly, the voltage detector 12b provided on the load side of the power feed switch 3 detects a three-phase AC voltage applied to the load 5 from the power supply 1 through the power feed switch 3, and this is rectified by the full-wave rectifier circuit REb to generate a direct current. It is converted into the load voltage E1b. This is shown as load voltage E1b in FIG. 5(b).

The power supply voltage E1a on the power supply side and the load voltage E1b on the load side of the power supply switch 3 of the switching source power supply 1 are the same when the power supply switch 3 is on. The voltages E1a and E1b are input to the comparators CPa and CPb, respectively, and are constantly compared with the reference value Es set in the reference value setters S18a and S18b. The voltage E1a, E1b is higher than the reference value Es until the time point t51 when the power supply switching is commanded, so the determination outputs of the comparators CPa and CPb are “0” as shown in FIGS. 5(e) and (f). Become.
For this reason, the gate-on enable signal SI4 output from the signal holding means 49 is "0" as shown in FIG. 5(j), so that the AND gates 48PU to 48NW of the power feeding switch 4 output the thyristor of each phase. The gate signal G4 input to the gate becomes "0" as shown in FIG. 5(l), and the power feeding switch 4 is off.

At time t51, in order to switch the power supply to the load 5 from the power supply 1 to the power supply 2, the switching signal S3 for the power supply switch 3 is changed from "1" to "0" as shown in FIGS. 5C and 5D. The switching signal S4 for the power feeding switch 4 is simultaneously switched from "0" to "1".
As a result, the signal holding means 39 holding the gate-on permission signal SI3 of the control circuit 30 is immediately reset, and the gate-on permission signal SI3 becomes "0" (see FIG. 5(i)). The gate signal G3 to the thyristor switches 3U to 3W of each phase becomes “0” (see FIG. 5(k)), and the voltage of each phase of the thyristor switches 3U to 3W of the power supply switch 3 becomes zero. Are sequentially turned off, and the power feeding switch 3 is turned off.

By sequentially turning off the thyristor switches 3U to 3W of each phase of the power feeding switch 3, the load side voltage E1b of the power feeding switch 3 gradually decreases from the time point t51, as shown in FIG. 5B. If there is no abnormality in the power supply 1, the power supply side voltage E1a is maintained at a constant voltage as shown in FIG.

When the load-side voltage E1b reaches the reference value Es at time t52, the comparator CPb generates a determination output of "1" (see FIG. 5(f)). The determination output that has become “1” is delayed by the time period element Tb by the time period ts corresponding to the delay phase angle of the load current, and is input to the set input of the signal holding means 49 through the AND gate 48. Since the AND gate 48 has been opened by the switching signal S3 which has already been input via the NOT gate 52 and has become "0", the signal holding means 49 sets the gate-on permission which becomes "1" at time t52. The signal SI4 is held (see FIG. 5(j)).

By inputting the gate-on permission signal SI4, which is "1", to the AND gates 48PU to 48NW of the gate circuits of the thyristor switches of the respective phases of the power feeding switch 4, "1" is already present at the other ends of these AND gates. Since the switching signal S4 of the power feeding switch 4 is input, the gate signal G4 of "1" is input to the gate of the thyristor switch of each phase of the power feeding switch 4, and these thyristor switches are turned on to supply the power feeding switch. 4 turns on.

As described above, after the switching signal S4 is applied at the time point t51, the power feeding switch 4 is further connected to the timing element Tb from the time point t52 when the voltage E1 applied from the power source 1 to the load 5 reaches the preset reference voltage Es. It is turned on at time t53, which is delayed by the time ts until the voltage on the load side becomes 0 V in advance. At this time, the voltage E1b applied from the power supply switch 3 to the load 5 is lower than the reference voltage Es and becomes a sufficiently low voltage, and the current flowing through the load 5 also decreases to almost zero, and the thyristor is turned off. A cross current does not occur even when the power supply switch 4 is turned on.

When switching the power supply to the load 5 from the power source 2 to the power source 1, the switching control is performed by the control circuit 30 similarly to the control circuit 40.
Further, the voltage detectors 12a and 22a that detect the voltage on the power supply side of the power supply switches 3 and 4 are used to switch to a sound power supply when a power failure or a voltage drop occurs in the power supply during power supply due to an accident or the like. It will be.

1, 2: AC power supply 11, 21: Power feeding path 12, 22: Voltage detector 3, 4: Power feeding switch 5: Loads 3P, 3N, 4P, 4N: Thyristor 30, 40: Switching control circuit 41: Differentiating means 42a : 90° phase detecting means 42b: 270° phase detecting means 43a, 43b: phase voltage phase estimating means (counter)
44a, 44b: Count initial value setting devices 45a, 45b, 46a, 46b: Comparators 47a, 47b: OR gates 38P, 38N, 48a, 48b, 48P, 48N: AND gates 49a, 49b: Signal holding means (flip-flop circuit)
51, 52, 53, 54: Not gates C31, C32, C41, C42: Switching signal input terminal S3: Switching signal for power feeding switch 3 S4: Switching signal for power feeding switch 4 G3P, G3N, G4P, G4N: Gate signal SI3P, SI3N, SI4P, SI4N: Gate-on permission signal

Claims (2)

Two power supply circuits that supply power to a common load from each of the first and second AC power supplies are provided with power supply switches configured by connecting two thyristor elements in parallel in reverse polarity, and the power supply switches are turned on. , In the power supply switching device that switches the power supply to the load by switching off,
Corresponding to each of the power supply switches, voltage detection means for detecting at least the load-side all-phase voltage of the power supply switch, and voltage conversion means for full-wave rectifying the output of this voltage detection means to convert it to a DC voltage. The voltage determining means for determining that the output voltage of the voltage converting means has dropped to a predetermined value or less, and the voltage determining means for the power supply switch that is turned on when a switching command is given to the two power supply switches. And a switching control circuit having a means for giving a gate-on permission signal to the thyristor of the power supply switch on the off side based on the determination output of 1. The power supply switching device according to claim 1,
A power supply switching device comprising a time-limiting element for delaying the determination output of the voltage determination means by the time during which the thyristor is turned off.