JP2020123654A - Wiring board and mounting structure - Google Patents

Wiring board and mounting structure Download PDF

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JP2020123654A
JP2020123654A JP2019014230A JP2019014230A JP2020123654A JP 2020123654 A JP2020123654 A JP 2020123654A JP 2019014230 A JP2019014230 A JP 2019014230A JP 2019014230 A JP2019014230 A JP 2019014230A JP 2020123654 A JP2020123654 A JP 2020123654A
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insulating layer
insulating
wiring board
wiring
insulating substrate
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JP7283909B2 (en
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隆文 大吉
Takafumi Oyoshi
隆文 大吉
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

To provide a wiring board that can stably operate an electronic component.SOLUTION: A wiring board comprises: an insulating substrate 2 in a quadrangle shape that includes a plurality of laminated first insulating layers 7; a mounting area 10 that is partitioned on a top face of the insulating substrate 2 and has corner parts; wiring conductors 3 that are located between the first insulating layers 7; a plurality of connection pads 4 that are located on an under surface of the insulating substrate 2; and a via hole conductor 14 that is located in the first insulating layers 7, and electrically connects the wiring conductors 3 between layers different from each other and the connection pads 4 and the wiring conductors 3. On the undermost layer of the insulating substrate 2 corresponding to at least one of an area where the connection pads 4 at the four corners of the insulating substrate 2 are located in a transparent plan view and an area where the connection pads 4 at the corners of the mounting area 10 are located in a transparent plan view, second insulating layers 12 having a Young's modulus smaller than the Young's modulus of the first insulating layers 7 are located.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板および配線基板を含む実装構造に関するものである。 The present invention relates to a wiring board and a mounting structure including the wiring board.

近年、コンピューターやゲーム機等に代表される電子機器は、高機能化が進んでいる。このような電子機器に対応して、同時に多くの演算処理を行うことができる半導体チップを実装するための配線基板の開発が行われている(特許文献1を参照)。 2. Description of the Related Art In recent years, electronic devices typified by computers and game machines have become more sophisticated. Corresponding to such an electronic device, a wiring board for mounting a semiconductor chip capable of simultaneously performing many arithmetic processes has been developed (see Patent Document 1).

特開2008−251702号公報JP, 2008-251702, A

演算処理能力の優れた半導体チップは、作動時に多量の熱を発生する。このため、半導体チップが接続された配線基板を、例えばマザーボードのような電気基板に搭載すると、半導体チップから放出される熱によって電気基板が熱伸縮する。このとき、配線基板との接続部に応力が発生し、接続部にクラックが生じることがある。その結果、半導体チップが安定的に作動しない場合がある。 A semiconductor chip with excellent arithmetic processing capacity generates a large amount of heat during operation. Therefore, when a wiring board to which a semiconductor chip is connected is mounted on an electric board such as a mother board, the electric board thermally expands and contracts due to the heat released from the semiconductor chip. At this time, stress may be generated in the connection portion with the wiring board, and cracks may occur in the connection portion. As a result, the semiconductor chip may not operate stably.

本開示の配線基板は、積層された複数の第1絶縁層を含む四角形状の絶縁基板と、絶縁基板の上面に区画されており角部を有する実装領域と、第1絶縁層同士の層間に位置している配線導体と、絶縁基板の下面に位置している複数の接続パッドと、第1絶縁層に位置しており、互いに異なる層間の配線導体同士、および接続パッドと配線導体とを電気的に接続するビアホール導体と、平面透視で絶縁基板の四隅にある接続パッドが位置している領域、および平面透視で実装領域の角部にある接続パッドが位置している領域の少なくとも一方に対応する絶縁基板の最下層に、第1絶縁層のヤング率よりも小さいヤング率の第2絶縁層が位置していることを特徴とするものである。 The wiring substrate of the present disclosure includes a rectangular insulating substrate including a plurality of stacked first insulating layers, a mounting region that is partitioned on the upper surface of the insulating substrate and has a corner, and an interlayer between the first insulating layers. The wiring conductor located, the plurality of connection pads located on the lower surface of the insulating substrate, the wiring conductors located in the first insulating layer and different from each other, and the connection pad and the wiring conductor are electrically connected to each other. Corresponding to at least one of the via-hole conductors that are electrically connected to each other, the regions where the connection pads at the four corners of the insulating substrate are located in plan view, and the regions where the connection pads at the corners of the mounting region are located in plan view. The second insulating layer having a Young's modulus smaller than that of the first insulating layer is located at the lowermost layer of the insulating substrate.

本開示の実装構造は、上記構成の配線基板と、実装領域に位置している電子部品と、配線基板の上面において、電子部品の少なくとも一部を覆うとともに、実装領域の周囲と接続している金属リッドと、配線基板の接続パッドと導電材を介して接続している電気基板と、を有していることを特徴とするものである。 The mounting structure according to the present disclosure covers at least a part of the electronic component on the upper surface of the wiring board, the electronic component located in the mounting area, and the wiring board configured as described above, and is connected to the periphery of the mounting area. It is characterized in that it has a metal lid and an electric board connected to the connection pad of the wiring board via a conductive material.

本開示の構造によれば、電子部品を安定的に作動させることが可能な配線基板を提供することができる。 According to the structure of the present disclosure, it is possible to provide a wiring board capable of stably operating an electronic component.

本開示の構造によれば、電子部品を安定的に作動させることが可能な実装構造を提供することができる。 According to the structure of the present disclosure, it is possible to provide a mounting structure capable of stably operating an electronic component.

図1は、本開示に係る配線基板の一例を示す概略平面図である。FIG. 1 is a schematic plan view showing an example of a wiring board according to the present disclosure. 図2は、本開示に係る配線基板の一例を示す概略断面図である。FIG. 2 is a schematic cross-sectional view showing an example of a wiring board according to the present disclosure. 図3は、本開示に係る配線基板の別の一例を示す概略平面図である。FIG. 3 is a schematic plan view showing another example of the wiring board according to the present disclosure. 図4は、本開示に係る実装構造の一例を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing an example of the mounting structure according to the present disclosure.

次に、図1〜図3を基にして、本開示の一例である配線基板1について説明する。図1は、配線基板1の下面を示す平面図である。図2は、図1におけるX−X間を通る断面図である。図3は、別の一例における配線基板1の下面を示す平面図である。 Next, the wiring board 1 which is an example of the present disclosure will be described based on FIGS. 1 to 3. FIG. 1 is a plan view showing the lower surface of the wiring board 1. FIG. 2 is a sectional view taken along line XX in FIG. FIG. 3 is a plan view showing the lower surface of the wiring board 1 in another example.

配線基板1は、絶縁基板2と、配線導体3と、接続パッド4と、ソルダーレジスト5と、を備えている。 The wiring board 1 includes an insulating substrate 2, a wiring conductor 3, a connection pad 4, and a solder resist 5.

絶縁基板2は、平面視で四角形状をしており、配線基板1の剛性および機械的な強度等を確保する機能を有している。また、絶縁基板2は、配線導体3および複数の接続パッド4を互いに電気的に絶縁して配置するための基体としての機能を有している。 The insulating substrate 2 has a quadrangular shape in a plan view and has a function of ensuring the rigidity and mechanical strength of the wiring substrate 1. Further, the insulating substrate 2 has a function as a base for electrically arranging the wiring conductor 3 and the plurality of connection pads 4 with each other.

絶縁基板2は、コア基板6および積層用の第1絶縁層7を備えている。コア基板6は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等を含浸させて硬化させた絶縁材料を含んでいる。コア基板6は、複数のスルーホール8を有している。スルーホール8の直径は、例えば100〜200μmに設定されている。 The insulating substrate 2 includes a core substrate 6 and a first insulating layer 7 for lamination. The core substrate 6 includes, for example, an insulating material obtained by impregnating a glass cloth with an epoxy resin, a bismaleimide triazine resin, or the like and curing the glass cloth. The core substrate 6 has a plurality of through holes 8. The diameter of the through hole 8 is set to, for example, 100 to 200 μm.

第1絶縁層7は、例えばエポキシ樹脂やポリイミド樹脂にシリカやアルミナ等の無機絶縁粒子を分散させて硬化させた絶縁材料を含んでいる。本例では、第1絶縁層7は、コア基板6の上下面にそれぞれ2層ずつ積層されている。第1絶縁層7は、複数のビアホール9を有している。ビアホール9の直径は、例えば10〜80μmに設定されている。 The first insulating layer 7 contains, for example, an insulating material in which inorganic insulating particles such as silica and alumina are dispersed and cured in epoxy resin or polyimide resin. In this example, two first insulating layers 7 are laminated on each of the upper and lower surfaces of the core substrate 6. The first insulating layer 7 has a plurality of via holes 9. The diameter of the via hole 9 is set to, for example, 10 to 80 μm.

第1絶縁層7の厚さは、例えば5〜25μmに設定されている。第1絶縁層7のヤング率は、例えば5〜15GPaに設定されている。 The thickness of the first insulating layer 7 is set to, for example, 5 to 25 μm. The Young's modulus of the first insulating layer 7 is set to, for example, 5 to 15 GPa.

絶縁基板2の上面には、角部を有する実装領域10が区画されている。実装領域10には、例えば半導体チップ等の電子部品20を実装するための実装パッド11が、縦横の並びで位置している。言い換えれば、絶縁基板2の上面の中央部に縦横に複数の実装パッド11が配置された領域があり、この領域が実装領域10になっている。 On the upper surface of the insulating substrate 2, a mounting area 10 having a corner is defined. In the mounting area 10, mounting pads 11 for mounting an electronic component 20 such as a semiconductor chip are located in a vertical and horizontal array. In other words, there is a region in which a plurality of mounting pads 11 are arranged vertically and horizontally at the center of the upper surface of the insulating substrate 2, and this region is the mounting region 10.

実装パッド11は、電子部品20と例えば半田を介して接続される。これにより、電子部品20と配線基板1とが電気的および機械的に接続される。実装パッド11は、例えば銅めっき等の良導電性金属を含んでいる。実装パッド11の表面は、金めっき等の薄層を有していても構わない。この場合、実装パッド11と半田との接続性が向上する。 The mounting pad 11 is connected to the electronic component 20 via, for example, solder. As a result, the electronic component 20 and the wiring board 1 are electrically and mechanically connected. The mounting pad 11 contains a good conductive metal such as copper plating. The surface of the mounting pad 11 may have a thin layer such as gold plating. In this case, the connectivity between the mounting pad 11 and the solder is improved.

絶縁基板2の下面には、例えばマザーボード等の電気基板40と接続するための接続パッド4が、縦横の並びで位置している。接続パッド4は、電気基板40と例えば半田を介して接続される。これにより、電気基板40と配線基板1とが電気的および機械的に接続される。この結果、電子部品20と電気基板40とが電気的に接続される。接続パッド4は、例えば銅めっき等の良導電性金属を含んでいる。 On the lower surface of the insulating substrate 2, connection pads 4 for connecting to an electric substrate 40 such as a mother board are located in a vertical and horizontal array. The connection pad 4 is connected to the electric board 40 via, for example, solder. As a result, the electric board 40 and the wiring board 1 are electrically and mechanically connected to each other. As a result, the electronic component 20 and the electric board 40 are electrically connected. The connection pad 4 contains a good conductive metal such as copper plating.

本開示の配線基板1の一例では、絶縁基板2の最下層には、平面透視で実装領域10の角部の接続パッド4が位置している領域に、第1絶縁層7のヤング率よりも小さいヤング率の第2絶縁層12が位置している。言い換えれば、絶縁基板2の最下層において、平面透視で実装領域10の4つの角部に重なり、接続パッド4が位置している領域に第2絶縁層12が位置している。 In an example of the wiring board 1 of the present disclosure, the lowermost layer of the insulating substrate 2 has a lower Young's modulus than the Young's modulus of the first insulating layer 7 in a region where the connection pads 4 at the corners of the mounting region 10 are seen in a plan view. The second insulating layer 12 having a small Young's modulus is located. In other words, in the lowermost layer of the insulating substrate 2, the second insulating layer 12 is located in the region where the connection pad 4 is located, overlapping the four corners of the mounting region 10 in plan view.

第2絶縁層12は、例えばシリコン樹脂やポリイミド樹脂等を含んでいる。第2絶縁層12の厚みは、絶縁基板2の最下層に位置している第1絶縁層7の厚みと同じである。 The second insulating layer 12 contains, for example, silicon resin or polyimide resin. The thickness of the second insulating layer 12 is the same as the thickness of the first insulating layer 7 located in the lowermost layer of the insulating substrate 2.

第2絶縁層12のヤング率は、第1絶縁層7のヤング率よりも小さく、例えば0.5GPaに設定されている。このため、第2絶縁層12は、第1絶縁層7よりも弾性力に富んでおり、外部からの応力を分散させる機能を有している。これにより、例えば第2絶縁層12の下面に位置している接続パッド4に電気基板40の熱伸縮に伴う応力が加わった場合でも、第2絶縁層12によって応力を分散することが可能になる。つまり、電気基板40との接続部である接続パッド4に応力が集中することを回避することが可能になる。第2絶縁層12のヤング率は、例えば引張試験法等の方法で測定することができる。 The Young's modulus of the second insulating layer 12 is smaller than that of the first insulating layer 7, and is set to 0.5 GPa, for example. Therefore, the second insulating layer 12 is richer in elastic force than the first insulating layer 7 and has a function of dispersing stress from the outside. Thereby, for example, even when the stress due to the thermal expansion and contraction of the electric substrate 40 is applied to the connection pad 4 located on the lower surface of the second insulating layer 12, the stress can be dispersed by the second insulating layer 12. .. That is, it becomes possible to avoid the stress from concentrating on the connection pads 4 that are the connection portions with the electric substrate 40. The Young's modulus of the second insulating layer 12 can be measured by a method such as a tensile test method.

このように、平面透視で実装領域10の角部の接続パッド4が位置している領域に、第1絶縁層7のヤング率よりも小さいヤング率の第2絶縁層12が位置しているときには、特に、電子部品20と配線基板1との熱伸縮差が大きい場合に、接続パッド4に応力が集中することを回避することに有利である。 As described above, when the second insulating layer 12 having a Young's modulus smaller than the Young's modulus of the first insulating layer 7 is located in the region where the connection pad 4 at the corner of the mounting region 10 is located in a perspective view, Especially, it is advantageous to avoid stress concentration on the connection pad 4 when the difference in thermal expansion and contraction between the electronic component 20 and the wiring board 1 is large.

つまり、例えば熱伸縮量の小さな電子部品20が実装された実装領域10と、電子部品20が実装されず熱伸縮量が大きな領域と、の境界を含み応力が最も集中する角部において、第2絶縁層12によって応力を回避することで接続パッド4と電気基板40との間にクラックが発生することを抑制することができる。 That is, for example, in the corner portion where the stress is most concentrated, including the boundary between the mounting region 10 in which the electronic component 20 having a small thermal expansion/contraction amount is mounted and the region in which the electronic component 20 is not mounted and the thermal expansion amount is large, By avoiding stress by the insulating layer 12, it is possible to suppress the occurrence of cracks between the connection pads 4 and the electric substrate 40.

なお、図3に示すように、絶縁基板2の四隅の接続パッド4が位置している領域に第2絶縁層12が位置しているときには、特に、配線基板1と電気基板40との熱伸縮差が大きい場合に、接続パッド4に応力が集中することを回避することに有利である。 As shown in FIG. 3, when the second insulating layer 12 is located in the regions where the connection pads 4 are located at the four corners of the insulating substrate 2, the thermal expansion and contraction of the wiring substrate 1 and the electrical substrate 40 is particularly likely to occur. When the difference is large, it is advantageous to avoid concentration of stress on the connection pad 4.

つまり、例えば熱伸縮量の小さな配線基板1と、熱伸縮量が大きな電気基板40と、の接続領域において応力が最も集中する絶縁基板2の四隅について、第2絶縁層12によって応力を回避することで接続パッド4と電気基板40との間にクラックが発生することを抑制することができる。 That is, for example, the stress is avoided by the second insulating layer 12 at the four corners of the insulating substrate 2 where the stress is most concentrated in the connection region between the wiring substrate 1 having a small thermal expansion and contraction amount and the electric substrate 40 having a large thermal expansion and contraction amount. Thus, it is possible to suppress the occurrence of cracks between the connection pads 4 and the electric board 40.

なお、第2絶縁層12には、後述するビアホール導体14が不存在であり、第2絶縁層12の下面に位置している接続パッド4は、第1絶縁層7に位置しているビアホール導体14により上層の配線導体3と電気的に接続していても構わない。 The second insulating layer 12 has no via-hole conductor 14 described later, and the connection pad 4 located on the lower surface of the second insulating layer 12 has the via-hole conductor 14 located on the first insulating layer 7. It may be electrically connected to the upper wiring conductor 3 by 14.

言い換えれば、第2絶縁層12の下面に位置している接続パッド4は、絶縁基板2の最下層の第1絶縁層7に位置しているビアホール導体14によって接続パッド4よりも上層に位置している配線導体3と電気的に接続される。 In other words, the connection pad 4 located on the lower surface of the second insulating layer 12 is located above the connection pad 4 by the via hole conductor 14 located on the lowermost first insulating layer 7 of the insulating substrate 2. Is electrically connected to the wiring conductor 3.

ヤング率の小さい第2絶縁層12に位置しているビアホール導体14と、ヤング率の大きい第1絶縁層7に位置している配線導体3とが接続している場合、例えば配線基板1に熱が加わったときに、第1絶縁層7の熱変形量と第2絶縁層12の熱変形量との差が大きくなり、ビアホール導体14と配線導体3との接続部に大きな応力が生じクラックが生じるおそれがある。 When the via-hole conductor 14 located in the second insulating layer 12 having a small Young's modulus and the wiring conductor 3 located in the first insulating layer 7 having a large Young's modulus are connected, for example, the wiring board 1 is heated. Is added, the difference between the amount of thermal deformation of the first insulating layer 7 and the amount of thermal deformation of the second insulating layer 12 becomes large, and a large stress is generated in the connection portion between the via-hole conductor 14 and the wiring conductor 3 to cause cracks. May occur.

上記のように、第2絶縁層12にビアホール導体14を設けない場合には、ビアホール導体14と配線導体3との接続部に生じる応力を回避することが可能になることから、接続信頼性の向上に有利である。 As described above, when the via-hole conductor 14 is not provided in the second insulating layer 12, it is possible to avoid the stress generated at the connecting portion between the via-hole conductor 14 and the wiring conductor 3, so that the connection reliability can be improved. It is advantageous for improvement.

第2絶縁層12の大きさは、平面視で例えば1辺の長さが3〜15mm程度に設定されている。3mmよりも小さい場合には、応力の分散が不十分になり、接続パッド4と電気基板40との間のクラックを抑制する効果が小さくなるおそれがある。15mmよりも大きい場合には、ビアホール導体14を形成しない領域が大きくなり配線の自由度が小さく
なるおそれがある。ビアホール導体14の形成領域の確保に影響がなければ、第2絶縁層12の領域を上記以上に大きくしても構わない。
The size of the second insulating layer 12 is set such that the length of one side is approximately 3 to 15 mm in plan view. When it is smaller than 3 mm, the stress is insufficiently dispersed, and the effect of suppressing cracks between the connection pads 4 and the electric substrate 40 may be reduced. If it is larger than 15 mm, the area where the via-hole conductor 14 is not formed becomes large and the degree of freedom of wiring may be reduced. The area of the second insulating layer 12 may be made larger than the above, as long as the formation area of the via-hole conductor 14 is not affected.

配線導体3は、例えば銅めっきや銅箔等の良導電性金属を含んでいる。配線導体3は、コア基板6の上下面、スルーホール8の内部、第1絶縁層7の上面または下面、およびビアホール9の内部に位置している。スルーホール8内部の配線導体3は、スルーホール導体13として機能する。ビアホール9内部の配線導体3は、ビアホール導体14として機能する。 The wiring conductor 3 contains a good conductive metal such as copper plating or copper foil. The wiring conductors 3 are located on the upper and lower surfaces of the core substrate 6, the inside of the through holes 8, the upper or lower surface of the first insulating layer 7, and the inside of the via holes 9. The wiring conductor 3 inside the through hole 8 functions as a through hole conductor 13. The wiring conductor 3 inside the via hole 9 functions as the via hole conductor 14.

コア基板6の上面および下面に位置している配線導体3は、スルーホール導体13を介して導通される。第1絶縁層7の上面または下面に位置している配線導体3とコア基板6の上下面に位置している配線導体3とは、ビアホール導体14を介して導通されている。 The wiring conductors 3 located on the upper surface and the lower surface of the core substrate 6 are electrically connected via the through hole conductors 13. The wiring conductors 3 located on the upper surface or the lower surface of the first insulating layer 7 and the wiring conductors 3 located on the upper and lower surfaces of the core substrate 6 are electrically connected via the via hole conductors 14.

実装パッド11および接続パッド4は、スルーホール導体13およびビアホール導体14を含む配線導体3によって電気的に接続されている。 The mounting pad 11 and the connection pad 4 are electrically connected by the wiring conductor 3 including the through hole conductor 13 and the via hole conductor 14.

ソルダーレジスト5は、例えばアクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂を含有する電気絶縁材料を含んでいる。ソルダーレジスト5は、本開示において必須の要件ではないが、例えば配線基板1と電子部品20とを半田を介して接続する場合に、半田を溶融する時の熱から配線導体3を保護する点で有利である。 The solder resist 5 contains, for example, an electrically insulating material containing a thermosetting resin having photosensitivity such as an acrylic modified epoxy resin. Although the solder resist 5 is not an essential requirement in the present disclosure, when the wiring board 1 and the electronic component 20 are connected via solder, for example, the solder resist 5 protects the wiring conductor 3 from heat when melting the solder. It is advantageous.

ソルダーレジスト5は、実装領域10を一括して露出させる開口部5aを有している。また、絶縁基板2の下面に位置しているソルダーレジスト5は、それぞれの接続パッド4を個別に露出させる開口部5bを有している。 The solder resist 5 has an opening 5a that exposes the mounting region 10 collectively. Further, the solder resist 5 located on the lower surface of the insulating substrate 2 has openings 5b for individually exposing the respective connection pads 4.

上記のように、本開示の配線基板1の一例によれば、積層された複数の第1絶縁層7を含む絶縁基板2と、絶縁基板2の上面に区画されており角部を有する実装領域10と、第1絶縁層7同士の層間に位置している配線導体3と、絶縁基板2の下面に位置している複数の接続パッド4と、第1絶縁層7に位置しており、互いに異なる層間の配線導体3同士、および接続パッド4と配線導体3とを電気的に接続するビアホール導体14と、平面透視で絶縁基板2の四隅にある接続パッド4が位置している領域、および平面透視で実装領域10の角部にある接続パッド4が位置している領域の少なくとも一方に対応する絶縁基板2の最下層に、第1絶縁層7のヤング率よりも小さいヤング率の第2絶縁層12が位置している。 As described above, according to the example of the wiring substrate 1 of the present disclosure, the insulating substrate 2 including the plurality of stacked first insulating layers 7 and the mounting region that is partitioned into the upper surface of the insulating substrate 2 and has the corners. 10, the wiring conductor 3 located between the first insulating layers 7, the plurality of connection pads 4 located on the lower surface of the insulating substrate 2, and the first insulating layer 7, Areas in which the wiring conductors 3 between different layers, the via-hole conductors 14 that electrically connect the connection pads 4 and the wiring conductors 3, and the connection pads 4 at the four corners of the insulating substrate 2 in plan view are located, The second insulation having a Young's modulus smaller than the Young's modulus of the first insulating layer 7 is formed on the lowermost layer of the insulating substrate 2 corresponding to at least one of the regions where the connection pads 4 are located at the corners of the mounting region 10 as seen through. Layer 12 is located.

第2絶縁層12のヤング率は、第1絶縁層7のヤング率よりも小さいため、第2絶縁層12は、第1絶縁層7よりも弾性力に富んでいる。これにより、例えば第2絶縁層12の下面に位置している接続パッド4に電気基板40の熱伸縮に伴う応力が加わった場合でも、第2絶縁層12によって応力を分散することが可能になる。 Since the Young's modulus of the second insulating layer 12 is smaller than the Young's modulus of the first insulating layer 7, the second insulating layer 12 is more elastic than the first insulating layer 7. Thereby, for example, even when the stress due to the thermal expansion and contraction of the electric substrate 40 is applied to the connection pad 4 located on the lower surface of the second insulating layer 12, the stress can be dispersed by the second insulating layer 12. ..

その結果、本開示の構造によれば、接続パッド4に応力が集中することを回避して接続パッド4と電気基板40との間にクラックが発生することを抑制することができ、電子部品20を安定的に作動させることが可能な配線基板1を提供することができる。 As a result, according to the structure of the present disclosure, it is possible to prevent the stress from concentrating on the connection pad 4 and to suppress the occurrence of cracks between the connection pad 4 and the electric substrate 40. It is possible to provide the wiring board 1 capable of stably operating.

なお、このような配線基板1は、例えば次のように形成される。 In addition, such a wiring board 1 is formed as follows, for example.

まず、複数のスルーホール8を有するコア基板6を用意する。コア基板6は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂を含浸させて半硬化させたプリプレグを複数枚積層し、上下面に銅箔(不図示)を配置して平板で加熱プレスすることで形成される。スルーホール8は、例えばドリル加工、レーザー加工、あるいはブラスト
加工等により形成される。
First, a core substrate 6 having a plurality of through holes 8 is prepared. For the core substrate 6, for example, glass cloth is impregnated with an epoxy resin or a bismaleimidetriazine resin, and a plurality of semi-cured prepregs are laminated, copper foils (not shown) are arranged on the upper and lower surfaces, and a flat plate is hot-pressed. Is formed by. The through hole 8 is formed by, for example, drilling, laser processing, blasting, or the like.

次に、コア基板6の上下面およびスルーホール8内に、例えばセミアディティブ法を用いて銅めっき金属を含む配線導体3を形成する。 Next, the wiring conductor 3 containing copper-plated metal is formed in the upper and lower surfaces of the core substrate 6 and in the through holes 8 by using, for example, a semi-additive method.

次に、コア基板6の上下面に第1絶縁層7を形成する。第1絶縁層7は、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂、あるいはポリイミド樹脂等を含む熱硬化性の絶縁層用の樹脂シートを、真空下でコア基板6の上下面に被着させて熱硬化することで形成される。 Next, the first insulating layer 7 is formed on the upper and lower surfaces of the core substrate 6. For the first insulating layer 7, a thermosetting resin sheet for an insulating layer containing, for example, an epoxy resin, a bismaleimide triazine resin, a polyimide resin, or the like is adhered to the upper and lower surfaces of the core substrate 6 under vacuum and then thermoset. It is formed by doing.

次に、第1絶縁層7にビアホール9を形成する。ビアホール9は、例えばレーザー加工、あるいはブラスト加工により形成される。ビアホール9は、底部に配線導体3が露出している。 Next, the via hole 9 is formed in the first insulating layer 7. The via hole 9 is formed by, for example, laser processing or blast processing. The wiring conductor 3 is exposed at the bottom of the via hole 9.

次に、第1絶縁層7の上面または下面、およびビアホール9内に、例えばセミアディティブ法を用いて銅めっき金属を含む配線導体3を形成する。このような方法を繰り返すことで、必要な層数の第1絶縁層7および配線導体3を形成することができる。 Next, the wiring conductor 3 containing a copper-plated metal is formed on the upper surface or the lower surface of the first insulating layer 7 and the via hole 9 by using, for example, a semi-additive method. By repeating such a method, the required number of layers of the first insulating layer 7 and the wiring conductor 3 can be formed.

次に、上記第2絶縁層12を形成する領域に対応する最下層の第1絶縁層7を除去する。第1絶縁層7の除去は、例えばレーザー加工またはプラズマ加工により行う。 Next, the lowermost first insulating layer 7 corresponding to the region where the second insulating layer 12 is formed is removed. The removal of the first insulating layer 7 is performed by, for example, laser processing or plasma processing.

次に、第1絶縁層7を除去した領域に第2絶縁層用のフィルムを被着して硬化し、第1絶縁層7の下面と第2絶縁層12の下面とが同じ高さになるようにブラスト加工を行う。 Next, a film for the second insulating layer is applied to the region where the first insulating layer 7 has been removed and cured so that the lower surface of the first insulating layer 7 and the lower surface of the second insulating layer 12 have the same height. Blasting is performed.

次に、最上層の第1絶縁層7に実装パッド11、および最下層の第1絶縁層7および第2絶縁層12に接続パッド4を同時に形成する。実装パッド11および接続パッド4は、例えばセミアディティブ法を用いて形成する。 Next, the mounting pad 11 is simultaneously formed on the uppermost first insulating layer 7, and the connection pads 4 are simultaneously formed on the lowermost first insulating layer 7 and second insulating layer 12. The mounting pad 11 and the connection pad 4 are formed by using, for example, a semi-additive method.

最後に、感光性を有する熱硬化性樹脂のフィルムを絶縁基板2の上下面に貼着して、所定のパターンに露光および現像した後、紫外線硬化および熱硬化させることによりソルダーレジスト5を形成する。これにより、図1および図2に示すような配線基板1が形成される。 Finally, a film of a thermosetting resin having photosensitivity is adhered to the upper and lower surfaces of the insulating substrate 2, exposed and developed in a predetermined pattern, and then UV-cured and heat-cured to form the solder resist 5. .. As a result, the wiring board 1 as shown in FIGS. 1 and 2 is formed.

次に、図4を基にして、本開示の配線基板1を有する実装構造50の実施形態例を説明する。なお、上述の配線基板1に関しては詳細な説明を省略する。 Next, an embodiment example of the mounting structure 50 having the wiring board 1 of the present disclosure will be described based on FIG. 4. The detailed description of the wiring board 1 will be omitted.

実装構造50は、配線基板1と、電子部品20と、金属リッド30と、電気基板40とを有している。 The mounting structure 50 includes the wiring board 1, the electronic component 20, the metal lid 30, and the electric board 40.

電子部品20は、例えばASIC(Aplication Specific Integrated Circuit)等の集積回路素子が挙げられ、主に演算機能を有している。電子部品20は、例えばシリコンやゲルマニウムを含んでいる。 The electronic component 20 is, for example, an integrated circuit element such as an ASIC (Application Specific Integrated Circuit), and mainly has an arithmetic function. The electronic component 20 contains, for example, silicon or germanium.

電子部品20は、配線基板1の実装領域10に位置している実装パッド11と半田15を介して実装されている。これにより、電子部品20と配線基板1とが、電気的および機械的に接続されている。 The electronic component 20 is mounted via the mounting pad 11 located in the mounting area 10 of the wiring board 1 and the solder 15. As a result, the electronic component 20 and the wiring board 1 are electrically and mechanically connected to each other.

電子部品20と配線基板1との間は、絶縁性の封止樹脂22で充填されている。封止樹脂22は、電子部品20と配線基板1との機械的な接続を補強する機能を有している。封止樹脂22の材料としては、例えばエポキシ樹脂等が用いられる。 A space between the electronic component 20 and the wiring board 1 is filled with an insulating sealing resin 22. The sealing resin 22 has a function of reinforcing the mechanical connection between the electronic component 20 and the wiring board 1. As the material of the sealing resin 22, for example, epoxy resin or the like is used.

金属リッド30は、配線基板1の上面において、電子部品20を覆うとともに、実装領域10の周囲の領域と接着剤により接続している。電子部品20の上部と金属リッド30の被覆部とは、放熱用のグリスを介して接触している。 The metal lid 30 covers the electronic component 20 on the upper surface of the wiring board 1 and is connected to a region around the mounting region 10 with an adhesive. The upper portion of the electronic component 20 and the coating portion of the metal lid 30 are in contact with each other via grease for heat dissipation.

金属リッド30は、例えば銅またはアルミニウム等の金属を含んでいる。金属リッド30は、主に配線基板1の変形を抑制する機能を有している。 The metal lid 30 contains a metal such as copper or aluminum. The metal lid 30 mainly has a function of suppressing the deformation of the wiring board 1.

電気基板40は、例えばマザーボード等が挙げられる。電気基板40は、絶縁板41と、導体層42と、を有している。 The electric board 40 may be, for example, a motherboard. The electric board 40 includes an insulating plate 41 and a conductor layer 42.

絶縁板41は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等を含浸させて硬化させた絶縁材料を含んでいる。絶縁板41は、複数のスルーホール43を有している。 The insulating plate 41 includes an insulating material obtained by impregnating glass cloth with epoxy resin, bismaleimide triazine resin, or the like and curing the glass cloth. The insulating plate 41 has a plurality of through holes 43.

導体層42は、絶縁板41の上面、下面およびスルーホール43の内部に位置している。導体層42は、銅等の良導電性金属を含んでいる。上面および下面に位置している導体層42の一部は、スルーホール43内の導体層42によって導通している。 The conductor layer 42 is located on the upper surface and the lower surface of the insulating plate 41 and inside the through hole 43. The conductor layer 42 contains a highly conductive metal such as copper. A part of the conductor layer 42 located on the upper surface and the lower surface is electrically connected by the conductor layer 42 in the through hole 43.

絶縁板41の上面に位置している導体層42の一部は、配線基板1と接続する第1電極44として機能する。絶縁板41の下面に位置している導体層42の一部は、例えば電子機器と接続する第2電極45として機能する。 A part of the conductor layer 42 located on the upper surface of the insulating plate 41 functions as a first electrode 44 connected to the wiring board 1. A part of the conductor layer 42 located on the lower surface of the insulating plate 41 functions as, for example, a second electrode 45 connected to an electronic device.

このような実装構造50は、上記のように電気基板40の熱伸縮に伴う応力が接続パッド4に加わった場合でも、応力を分散することが可能な第2絶縁層12を有する配線基板1が実装されていることから、配線基板1と電気基板40との間の接続信頼性に優れている。 In such a mounting structure 50, the wiring board 1 having the second insulating layer 12 that can disperse the stress even when the stress accompanying the thermal expansion and contraction of the electric substrate 40 is applied to the connection pad 4 as described above. Since it is mounted, the connection reliability between the wiring board 1 and the electric board 40 is excellent.

このように、本開示の構造によれば、電子部品20を安定的に作動させることが可能な実装構造50を提供することができる。 As described above, according to the structure of the present disclosure, it is possible to provide the mounting structure 50 capable of stably operating the electronic component 20.

なお、本開示の配線基板1は上述の実施形態の一例に限定されるものではなく、本開示の要旨を逸脱しない範囲であれば種々の変更は可能である。 The wiring board 1 according to the present disclosure is not limited to the above-described example of the embodiment, and various modifications can be made without departing from the scope of the present disclosure.

図1において、平面視で第2絶縁層12の形状が四角形状である一例を示したが、平面視における第2絶縁層12の形状は、L字形状、長方形状、多角形状であっても構わない。外部からの応力が集中する接続パッド4の位置に合わせて適宜形状を設計することで、配線設計の自由度の向上が可能になる。 Although FIG. 1 shows an example in which the second insulating layer 12 has a quadrangular shape in a plan view, the second insulating layer 12 may have an L-shape, a rectangular shape, or a polygonal shape in a plan view. I do not care. The degree of freedom in wiring design can be improved by appropriately designing the shape in accordance with the position of the connection pad 4 where external stress concentrates.

さらに、上述の一例では、4つの第2絶縁層12の形状および大きさが同じである一例を示したが、第2絶縁層12の形状および大きさが、それぞれ異なる形状および大きさであっても構わない。外部からの応力が集中する接続パッド4の位置に合わせて第2絶縁層12の形状および大きさを設定することで、より応力の分散に優れた配線基板1とすることが可能になる。 Further, in the above example, the four second insulating layers 12 have the same shape and size, but the second insulating layer 12 has different shapes and sizes. I don't mind. By setting the shape and size of the second insulating layer 12 in accordance with the position of the connection pad 4 where the stress from the outside concentrates, it is possible to obtain the wiring board 1 in which the stress is more dispersed.

また、上述の実装構造50の一例においては、配線基板1上に一つの電子部品20が実装されている場合を示したが、例えば電子部品20の周囲に複数の電子部品が実装されていても構わない。このような電子部品は、例えばHBM(High Bandwidth
Memory)等の広帯域メモリ等が挙げられる。このようなHBM、および先述のASICを有する実装構造50は、多くの情報を高速で処理することが可能になる。
Further, in the example of the mounting structure 50 described above, the case where one electronic component 20 is mounted on the wiring board 1 is shown, but for example, even if a plurality of electronic components are mounted around the electronic component 20. I do not care. Such electronic components are, for example, HBM (High Bandwidth).
A wide band memory such as Memory) and the like. The mounting structure 50 including the HBM and the ASIC described above can process a large amount of information at high speed.

また、実装構造50に接続される金属リッド30は、電子部品20の上部を露出する開口部を有していても構わない。言い換えれば、上面視で、電子部品20の上部が開口部の内側に見える状態で位置している。電子部品20の上部は、金属リッド30の上部よりも高くても構わないし低くても構わない。このような場合、例えば発熱量の大きい先述のASICの上部に冷却部材を接続させることが可能になり、実装構造50が受ける熱の影響を低減することが可能になる。 The metal lid 30 connected to the mounting structure 50 may have an opening that exposes the upper part of the electronic component 20. In other words, when viewed from above, the upper portion of the electronic component 20 is positioned so as to be visible inside the opening. The upper portion of the electronic component 20 may be higher or lower than the upper portion of the metal lid 30. In such a case, for example, a cooling member can be connected to the upper part of the above-mentioned ASIC that generates a large amount of heat, and the influence of heat on the mounting structure 50 can be reduced.

1 配線基板
2 絶縁基板
3 配線導体
4 接続パッド
7 第1絶縁層
10 実装領域
12 第2絶縁層
14 ビアホール導体
20 電子部品
30 金属リッド
40 電気基板
50 実装構造
1 Wiring Board 2 Insulating Board 3 Wiring Conductor 4 Connection Pad 7 First Insulating Layer 10 Mounting Area 12 Second Insulating Layer 14 Via Hole Conductor 20 Electronic Component 30 Metal Lid 40 Electric Board 50 Mounting Structure

Claims (4)

積層された複数の第1絶縁層を含む四角形状の絶縁基板と、
該絶縁基板の上面に区画されており角部を有する実装領域と、
前記第1絶縁層同士の層間に位置している配線導体と、
前記絶縁基板の下面に位置している複数の接続パッドと、
前記第1絶縁層に位置しており、互いに異なる層間の前記配線導体同士、および前記接続パッドと前記配線導体とを電気的に接続するビアホール導体と、
平面透視で前記絶縁基板の四隅にある前記接続パッドが位置している領域、および平面透視で前記実装領域の角部にある前記接続パッドが位置している領域の少なくとも一方に対応する前記絶縁基板の最下層に、前記第1絶縁層のヤング率よりも小さいヤング率の第2絶縁層が位置していることを特徴とする配線基板。
A rectangular insulating substrate including a plurality of stacked first insulating layers;
A mounting region having a corner portion which is partitioned on the upper surface of the insulating substrate;
A wiring conductor located between the first insulating layers,
A plurality of connection pads located on the lower surface of the insulating substrate,
A via-hole conductor that is located in the first insulating layer and that electrically connects the wiring conductors between different layers and the connection pad and the wiring conductor;
The insulating substrate corresponding to at least one of a region where the connection pads are located at four corners of the insulating substrate in plan view and a region where the connection pads are located at corners of the mounting region in plan view. The second insulating layer having a Young's modulus smaller than the Young's modulus of the first insulating layer is located as the lowermost layer of the wiring board.
前記ビアホール導体は、前記第2絶縁層に不存在であるとともに、前記接続パッドは、前記第1絶縁層に位置している前記ビアホール導体により上層の前記配線導体と電気的に接続していることを特徴とする請求項1に記載の配線基板。 The via-hole conductor is absent in the second insulating layer, and the connection pad is electrically connected to the wiring conductor in the upper layer by the via-hole conductor located in the first insulating layer. The wiring board according to claim 1, wherein: 請求項1または2のいずれかに記載の配線基板と、
前記実装領域に位置している電子部品と、
前記配線基板の上面において、前記電子部品の少なくとも一部を覆うとともに、前記実装領域の周囲と接続している金属リッドと、
前記配線基板の前記接続パッドと導電材を介して接続している電気基板と、
を有していることを特徴とする実装構造。
The wiring board according to claim 1 or 2,
An electronic component located in the mounting area,
On the upper surface of the wiring board, a metal lid that covers at least a part of the electronic component and is connected to the periphery of the mounting area,
An electric board connected to the connection pad of the wiring board via a conductive material,
A mounting structure characterized by having.
前記金属リッドは、前記電子部品の上部を露出する開口部を有していることを特徴とする請求項3に記載の実装構造。 The mounting structure according to claim 3, wherein the metal lid has an opening that exposes an upper portion of the electronic component.
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Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2009009957A (en) * 2007-06-26 2009-01-15 Nec Electronics Corp Semiconductor device
JP2009260255A (en) * 2008-03-25 2009-11-05 Panasonic Corp Semiconductor device, multilayer wiring board, and manufacturing method for them
JP2012018952A (en) * 2010-07-06 2012-01-26 Furukawa Electric Co Ltd:The Printed wiring board, semiconductor device, printed wiring board manufacturing method and semiconductor device manufacturing method
JP2018120954A (en) * 2017-01-25 2018-08-02 京セラ株式会社 Wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009009957A (en) * 2007-06-26 2009-01-15 Nec Electronics Corp Semiconductor device
JP2009260255A (en) * 2008-03-25 2009-11-05 Panasonic Corp Semiconductor device, multilayer wiring board, and manufacturing method for them
JP2012018952A (en) * 2010-07-06 2012-01-26 Furukawa Electric Co Ltd:The Printed wiring board, semiconductor device, printed wiring board manufacturing method and semiconductor device manufacturing method
JP2018120954A (en) * 2017-01-25 2018-08-02 京セラ株式会社 Wiring board

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