JP2020119970A - Mounting device and mounting method - Google Patents

Mounting device and mounting method Download PDF

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JP2020119970A
JP2020119970A JP2019009086A JP2019009086A JP2020119970A JP 2020119970 A JP2020119970 A JP 2020119970A JP 2019009086 A JP2019009086 A JP 2019009086A JP 2019009086 A JP2019009086 A JP 2019009086A JP 2020119970 A JP2020119970 A JP 2020119970A
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mounting
substrate
chip
recognition
recognition mark
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JP7013400B2 (en
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泰司 田村
Taiji Tamura
泰司 田村
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Toray Engineering Co Ltd
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Toray Engineering Co Ltd
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Priority to JP2019009086A priority Critical patent/JP7013400B2/en
Priority to CN202080009673.7A priority patent/CN113302725A/en
Priority to PCT/JP2020/001153 priority patent/WO2020153203A1/en
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Priority to US17/381,823 priority patent/US20210351057A1/en
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Abstract

To provide a mounting apparatus and a mounting method that achieve stable and highly accurate mounting and inspection of 100% mounting position accuracy measurement in the mounting device without increasing costs and decreasing productivity in face-up mounting in which the electrode surface of a board and the electrode surface of a chip component face in the same direction.SOLUTION: In a mounting device, after a chip component is aligned with a board, a mounting head holding the chip component is lowered in the vertical direction with respect to the board, the chip component comes into close contact with the substrate, and then a control unit includes a function to cause a recognition mechanism to start a recognition operation of a chip recognition mark and a board recognition mark in parallel, and recognizes the chip recognition mark and the board recognition mark when the chip component is in close contact with the board through the mounting head to calculate the mounting position accuracy of the chip component and the board, and there is also provide a mounting method.SELECTED DRAWING: Figure 1

Description

本発明はチップ部品を基板に実装する実装装置および実装方法に関する。特に、基板の電極面とチップ部品の電極面が同方向を向くフェイスアップ実装を行なう実装装置および実装方法に係る。 The present invention relates to a mounting device and a mounting method for mounting a chip component on a substrate. In particular, the present invention relates to a mounting apparatus and a mounting method for performing face-up mounting in which an electrode surface of a substrate and an electrode surface of a chip component face the same direction.

配線基板等の基板に半導体チップ等のチップ部品を実装する実装形態として、基板の電極面にチップ部品の電極面を対向させて実装するフェイスダウン実装と、基板の電極面とチップ部品の電極面を同方向にして実装するフェイスアップ実装があることは良く知られている。 As a mounting form for mounting a chip component such as a semiconductor chip on a substrate such as a wiring substrate, face-down mounting in which the electrode face of the chip component is opposed to the electrode face of the substrate, and the electrode face of the substrate and the electrode face of the chip component are mounted. It is well known that there is a face-up implementation that implements in the same direction.

いずれの実装形態においても、基板の所定位置にチップ部品を実装するための高精度な位置合わせが必要であり、位置合わせのための認識マークがチップ部品および基板には付されている。ここで、チップ部品を基板の所定位置に位置合わせするのは、基板の電極とチップ部品の電極の位置関係を所定の精度で実装するためであり、フェイスダウン実装、フェイスアップ実装ともに、基板およびチップ部品において、認識マーク位置は電極位置を基準として配置され、相対位置が明確な電極面側に付されているのが一般的である。 In any of the mounting forms, it is necessary to perform highly accurate alignment for mounting the chip component at a predetermined position on the substrate, and a recognition mark for alignment is attached to the chip component and the substrate. Here, the reason why the chip component is aligned with the predetermined position of the substrate is to mount the positional relationship between the electrode of the substrate and the electrode of the chip component with predetermined accuracy. In the chip component, the recognition mark position is generally arranged on the basis of the electrode position, and is generally attached to the electrode surface side where the relative position is clear.

ここで、図20にフェイスアップ実装の例を示す。チップ部品Cには、図20(a)のように、チップ部品の認識マーク(以下チップ認識マークと記す)として、チップ認識第1マークAC1とチップ認識第2マークAC2が2つ配置されるのが一般的である。(図20の例では対角上の配置)一方、基板Sには、基板の認識マーク(以下基板認識マークと記す)として、基板認識第1マークAS1と基板認識第2マークAS2が2つ配置されるのが一般的である。(図20の例は対角上の配置)そこで、位置合わせに際しては、チップ認識第1マークAC1と基板認識第1マークAS1の位置関係およびチップ認識第1マークAC2と基板認識第2マークAS2の位置関係から、所定実装位置に対する位置ズレ量(基板面内方向の位置及び角度)を求めて、相対位置を補正してから実装している(図20(b))。 Here, FIG. 20 shows an example of face-up mounting. In the chip component C, as shown in FIG. 20A, two chip recognition first marks AC1 and two chip recognition second marks AC2 are arranged as chip component recognition marks (hereinafter referred to as chip recognition marks). Is common. (Diagonal arrangement in the example of FIG. 20) On the other hand, on the substrate S, two substrate recognition first marks AS1 and two substrate recognition second marks AS2 are arranged as substrate recognition marks (hereinafter referred to as substrate recognition marks). It is generally done. (Diagonal arrangement in the example of FIG. 20) Therefore, at the time of alignment, the positional relationship between the chip recognition first mark AC1 and the substrate recognition first mark AS1 and the chip recognition first mark AC2 and the substrate recognition second mark AS2 are arranged. A positional deviation amount (position and angle in the in-plane direction of the substrate) with respect to a predetermined mounting position is obtained from the positional relationship, and the relative position is corrected before mounting (FIG. 20B).

ところで、フェイスダウン実装、フェイスアップ実装ともに、実装ヘッドが上側から保持したチップ部品を基板に圧着して実装する。このため、基板とチップ部品の電極同士を対向させて実装するフェイスダウン実装では基板認識マークとチップ認識マークを、上下2視野カメラを用いることで同時に直接観察する方法が知られている。一方、基板とチップ部品の電極を同方向として実装するフェイスアップ実装では、チップ部品の電極面が実装ヘッドに密着しているため、チップ部品の認識マークを直接観察して位置合わせできる様に、実装ヘッドのチップ部品を保持する部分に透明部材を用いる等の工夫をして、実装ヘッド越しに各認識マークを観察できる手法が提案されている。(例えば特許文献1、特許文献2) By the way, in both the face-down mounting and the face-up mounting, the chip component held from the upper side by the mounting head is pressure-bonded to the substrate for mounting. For this reason, in face-down mounting in which the electrodes of the substrate and the chip component are opposed to each other, a method of directly observing the substrate recognition mark and the chip recognition mark at the same time by using an upper and lower two-view camera is known. On the other hand, in face-up mounting in which the electrodes of the board and the chip component are mounted in the same direction, since the electrode surface of the chip component is in close contact with the mounting head, it is possible to directly observe and align the recognition mark of the chip component. A method has been proposed in which each recognition mark can be observed through the mounting head by devising such as using a transparent member in a portion of the mounting head that holds a chip component. (For example, Patent Documents 1 and 2)

国際公開第2003/041478号公報International Publication No. 2003/041478 特開2017−208522号公報JP, 2017-208522, A

半導体部品の高密度化、多電極化、狭ピッチ化は著しく進んでおり、実装装置においては、大幅なコスト上昇や生産性低下を伴わずに、従来よりも高精度な位置合わせを行い、実装することが求められるとともに、品質管理の観点から、実装状態の実装位置精度測定検査を全数行うことが求められるようになっている。しかし、特許文献2では実装状態の実装位置精度測定検査にまで言及されていない。 As semiconductor parts are becoming denser, with more electrodes, and at narrower pitches, mounting equipment performs positioning with higher accuracy than before without significantly increasing costs or decreasing productivity. From the viewpoint of quality control, it is required to perform 100% of the mounting position accuracy measurement inspections of the mounting state. However, Patent Document 2 does not mention the mounting position accuracy measurement inspection in the mounting state.

また、実装工程の完了後に実装装置と別装置で実装位置精度測定を行うことは、コストの上昇を伴うという問題とともに、実装位置精度の不良が発生した時、気付くまでに時間を要するため修正処置の遅れを伴うという問題もある。 In addition, when the mounting position accuracy measurement is performed by a device different from the mounting device after the mounting process is completed, there is a problem that the cost is increased, and when defective mounting position accuracy occurs, it takes time to notice it. There is also the problem of being delayed.

本発明は、上記の問題を鑑みてなされたものであり、基板の電極面とチップ部品の電極面が同方向を向くフェイスアップ実装において、コストの上昇や生産性の低下を伴わずに、実装装置内で全数の実装位置精度測定検査を行い、安定した高精度な実装を実現させる実装装置および実装方法を提供するものである。 The present invention has been made in view of the above problems, and in face-up mounting in which the electrode surface of the substrate and the electrode surface of the chip component face in the same direction, without increasing cost or decreasing productivity, mounting The present invention provides a mounting apparatus and a mounting method for realizing stable and highly accurate mounting by performing all the mounting position accuracy measurement inspections in the apparatus.

上記の課題を解決するために、請求項1に記載の発明は、
位置合わせ用のチップ認識マークを有するチップ部品と、位置合わせ用の基板認識マークを有する基板とを、前記チップ認識マークと前記基板認識マークが上面を向く姿勢でフェイスアップ実装する実装装置であって、
前記基板を保持する基板ステージと、
チップを保持する実装ヘッドと、
前記基板に対して垂直方向に前記実装ヘッドを昇降させる昇降手段と、
前記実装ヘッドの上側から前記実装ヘッド越しに、前記チップ認識マークと前記基板認識マークを認識し、前記基板面内方向に移動可能な認識機構と、
前記認識機構と接続し、前記認識機構から得た、前記チップ部品認識マークおよび前記基板認識マークの位置情報から、前記チップ部品と前記基板の位置ズレ量を計算する機能と、前記位置ズレ量に応じて前記実装ヘッド部または/および前記基板ステージを駆動して位置合わせを行う機能とを有する制御部とを備え、
前記チップ部品と前記基板の位置合わせを前記認識機構で行った後に、前記チップ部品を保持した前記実装ヘッドを前記基板に対して垂直方向に下降させ、前記チップ部品が前記基板に密着してから、
前記制御部が、前記認識機構に前記チップ認識マークおよび前記基板認識マークの認識動作を並行して開始させ、前記チップ部品が前記基板に密着した実装状態における前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに認識し、前記チップ部品と前記基板の実装位置精度を算出する機能を有する実装装置を提供する。
In order to solve the above problems, the invention according to claim 1 is
A mounting device for mounting a chip component having a chip recognition mark for position alignment and a substrate having a substrate recognition mark for position alignment face-up with the chip recognition mark and the substrate recognition mark facing upward. ,
A substrate stage for holding the substrate,
A mounting head that holds the chip,
An elevating means for elevating the mounting head in a direction perpendicular to the substrate,
A recognition mechanism that recognizes the chip recognition mark and the substrate recognition mark from the upper side of the mounting head over the mounting head, and is movable in the in-plane direction of the substrate,
The function of calculating the positional deviation amount of the chip component and the board from the positional information of the chip component recognition mark and the board recognition mark, which is connected to the recognition mechanism and obtained from the recognition mechanism, and the positional deviation amount. And a control unit having a function of driving the mounting head unit and/or the substrate stage in accordance with the position adjustment,
After performing the alignment between the chip component and the substrate by the recognition mechanism, the mounting head holding the chip component is lowered in the vertical direction with respect to the substrate, and after the chip component comes into close contact with the substrate. ,
The control unit causes the recognition mechanism to start the recognition operation of the chip recognition mark and the board recognition mark in parallel, and displays the chip recognition mark and the board recognition mark in a mounted state in which the chip component is in close contact with the board. Provided is a mounting apparatus having a function of recognizing through the mounting head and calculating mounting position accuracy of the chip component and the substrate.

請求項2に記載の発明は、請求項1に記載の実装装置であって、
前記チップ部品が前記基板に密着してから、並行して開始される実装位置精度を算出するための、前記実装ヘッド越しに行われる前記チップ認識マークと前記基板認識マークの認識動作において、
前記認識機構の光軸中心が、前記チップ認識マークと前記基板認識マークの中点近傍位置で前記チップ認識マークと前記基板認識マークとを同時に認識する機能を有する実装装置を提供する。
The invention described in claim 2 is the mounting apparatus according to claim 1,
In the recognition operation of the chip recognition mark and the board recognition mark performed over the mounting head, in order to calculate the mounting position accuracy that is started in parallel after the chip components are in close contact with the board,
Provided is a mounting device having a function of recognizing the chip recognition mark and the substrate recognition mark at the same time when the optical axis center of the recognition mechanism is near the midpoint of the chip recognition mark and the substrate recognition mark.

請求項3に記載の発明は、請求項2に記載の実装装置であって、
算出した実装位置精度の結果を、実装位置にフィードバックし、自動で実装位置を校正調整する機能を有する実装装置を提供する。
The invention described in claim 3 is the mounting apparatus according to claim 2,
A mounting device having a function of feeding back the calculated mounting position accuracy to the mounting position and automatically calibrating and adjusting the mounting position.

請求項4に記載の発明は、
位置合わせ用のチップ認識マークを有するチップ部品を、位置合わせ用の基板認識マークを有する基板に実装する実装方法であって、前記チップ部品を前記基板と隙間を設けて配置した状態で、前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに同一方向から認識して、前記チップ部品と前記基板の相対位置関係を合わせる位置合わせ工程と、前記チップ部品を前記基板に密着させ加圧して実装する実装工程と、前記チップ部品が前記基板に密着した実装状態にあるときに、前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに同一方向から認識して、前記チップ部品と前記基板の相対位置関係を算出する実装精度測定検査工程とを備え、
前記チップ部品が前記基板に密着してから、前記実装工程と前記実装精度測定検査工程を並行して実施する実装方法を提供する。
The invention according to claim 4 is
A mounting method for mounting a chip component having a chip recognition mark for alignment on a substrate having a substrate recognition mark for alignment, wherein the chip component is arranged with a gap provided between the chip component and the chip A positioning step of recognizing the recognition mark and the board recognition mark from the same direction over the mounting head to match the relative positional relationship between the chip component and the board, and mounting the chip part by closely contacting and pressing the board. And a mounting step in which the chip component is in close contact with the substrate, the chip recognition mark and the substrate recognition mark are recognized from the same direction over the mounting head, and the chip component and the substrate are recognized. Equipped with a mounting accuracy measurement and inspection process that calculates the relative positional relationship,
A mounting method is provided in which the mounting step and the mounting accuracy measurement/inspection step are performed in parallel after the chip component is in close contact with the substrate.

請求項5に記載の発明は、請求項4に記載の実装方法であって、
前記実装精度測定検査工程において、前記認識機構の光軸中心が前記チップ認識マークと前記基板認識マークの中点近傍位置で、前記チップ認識マークと前記基板認識マークを同時に認識する実装方法を提供する。
The invention described in claim 5 is the mounting method according to claim 4,
In the mounting accuracy measurement/inspection step, there is provided a mounting method in which the optical axis center of the recognition mechanism is near the midpoint of the chip recognition mark and the board recognition mark, and the chip recognition mark and the board recognition mark are recognized at the same time. ..

請求項6に記載の発明は、請求項5に記載の実装方法であって、
前記実装精度測定検査工程で算出した実装位置精度の結果を、実装位置にフィードバックし、自動で実装位置を校正調整する実装方法を提供する。
The invention according to claim 6 is the mounting method according to claim 5,
A mounting method for feeding back the result of the mounting position accuracy calculated in the mounting accuracy measurement/inspection step to the mounting position and automatically calibrating and adjusting the mounting position.

本発明により、基板の電極面とチップ部品の電極面が同方向を向くフェイスアップ実装において、コストの上昇や生産性の低下を伴わずに、実装装置内で実装位置精度検査を全数行い、安定して高精度に実装できる実装装置および実装方法の実現が可能となる。 According to the present invention, in face-up mounting in which the electrode surface of the substrate and the electrode surface of the chip component face in the same direction, all the mounting position accuracy inspections are performed in the mounting device and stable without increasing cost or lowering productivity. Thus, it is possible to realize a mounting apparatus and a mounting method that can be mounted with high accuracy.

本発明の実施形態に係る(a)実装装置の外観を示す図である(b)同実装装置を別の角度から見た外観と構成要素を示す図である。It is a figure which shows the external appearance of the mounting apparatus which concerns on embodiment of this invention. (b) It is a figure which shows the external appearance and the component which looked at the same mounting apparatus from another angle. 本発明の実施形態に係る実装装置で、チップ部品と基板の位置合わせを行う時の位置関係を説明する図である。It is a figure explaining the positional relationship at the time of aligning a chip component and a board|substrate with the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、チップ部品と基板の位置合わせを行う時に基板第1認識マークの位置情報を取得している状態を説明する図である。It is a figure explaining the state which acquires the positional information on the board|substrate 1st recognition mark, when aligning a chip component and a board|substrate with the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、チップ部品と基板の位置合わせを行う時にチップ第1認識マークの位置情報を取得している状態を説明する図である。It is a figure explaining the state which acquires the positional information on the chip 1st recognition mark, when performing the position alignment of a chip component and a board|substrate by the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、チップ部品と基板の位置合わせを行う時にチップ第2認識マークの位置情報を取得している状態を説明する図である。It is a figure explaining the state which acquires the positional information on the chip 2nd recognition mark, when performing the position alignment of a chip component and a board|substrate by the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、チップ部品と基板の位置合わせを行う時に基板第2認識マークの位置情報を取得している状態を説明する図である。It is a figure explaining the state which is acquiring the position information on the board 2nd recognition mark at the time of aligning a chip part and a board with a mounting device concerning an embodiment of the present invention. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程が完了した後の実装精度測定について説明する図である。It is a figure explaining the mounting accuracy measurement after the mounting process of mounting a chip component on a board|substrate is completed in the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態を説明する図である。FIG. 9 is a diagram illustrating a state in which the mounting head is lowered and the chip component is in close contact with the substrate in the mounting step of mounting the chip component on the substrate in the mounting apparatus according to the embodiment of the present invention. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第1認識マークの位置情報を取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered and a mounting accuracy measurement is performed in a state where the chip component is in close contact with the substrate. It is a figure which shows the state which has acquired the positional information on a recognition mark. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、チップ第1認識マークの位置情報を取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered and a mounting accuracy measurement is performed when the chip component is in close contact with the substrate. It is a figure which shows the state which has acquired the positional information on a recognition mark. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、チップ第2認識マークの位置情報を取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered and a mounting accuracy measurement in a state where the chip component is in close contact with the substrate is described. It is a figure which shows the state which has acquired the positional information on a recognition mark. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第2認識マークの位置情報を取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered, and mounting accuracy measurement in a state where the chip component is in close contact with the substrate will be described. It is a figure which shows the state which has acquired the positional information on a recognition mark. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程段階の実装精度測定について説明するもので、実装精度測定を行なう際に、基板第1認識マークとチップ第1認識マークの位置情報を同時に同一視野内で取得した撮像手段の画像例を示す図である。In the mounting apparatus according to the embodiment of the present invention, the mounting accuracy measurement at the mounting process step of mounting a chip component on a substrate will be described. When the mounting accuracy is measured, the board first recognition mark and the chip first recognition mark It is a figure which shows the example of an image of the image pick-up means which acquired the position information of the above simultaneously in the same visual field. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第1認識マークとチップ第1認識マークの位置情報を同時に取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered and a mounting accuracy measurement is performed in a state where the chip component is in close contact with the substrate. It is a figure which shows the state which has acquired the positional information on a recognition mark and a chip 1st recognition mark simultaneously. 本発明の実施形態に係る実装装置で、基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第2認識マークとチップ第2認識マークの位置情報を同時に取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on a substrate, a mounting head is lowered, and mounting accuracy measurement in a state where the chip component is in close contact with the substrate will be described. It is a figure which shows the state which has acquired the positional information on a recognition mark and a chip 2nd recognition mark simultaneously. 埋め込み基板へのフェイスアップ実装について説明するもので、(a)チップ部品が基板から離れた状態を示す図(b)チップ部品を基板に位置合わせして実装した状態を示す図である。FIG. 6 is a view for explaining face-up mounting on an embedded substrate, and (a) is a diagram showing a state in which the chip component is separated from the substrate, and (b) is a diagram showing a state in which the chip component is aligned and mounted on the substrate. 本発明の実施形態に係る実装装置で、埋め込み基板とチップ部品の位置合わせを行う時の状態を示す図である。It is a figure which shows the state at the time of aligning an embedded substrate and a chip component in the mounting apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る実装装置で、埋め込み基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第1認識マークとチップ第1認識マークの位置情報を同時に取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on an embedded substrate, a mounting head is lowered and a mounting accuracy measurement is performed in a state where the chip component is in close contact with the substrate. It is a figure which shows the state which has simultaneously acquired the positional information on the 1st recognition mark and the chip 1st recognition mark. 本発明の実施形態に係る実装装置で、埋め込み基板にチップ部品を実装する実装工程において、実装ヘッドが下降し、チップ部品が基板に密着した状態での実装精度測定について説明するもので、基板第2認識マークとチップ第2認識マークの位置情報を同時に取得している状態を示す図である。In a mounting apparatus according to an embodiment of the present invention, in a mounting step of mounting a chip component on an embedded substrate, a mounting head is lowered and a mounting accuracy measurement is performed in a state where the chip component is in close contact with the substrate. It is a figure which shows the state which has simultaneously acquired the positional information on the 2nd recognition mark and the chip 2nd recognition mark. フェイスアップ実装について説明するもので、(a)チップ部品が基板から離れた状態を示す図(b)チップ部品を基板に位置合わせして実装した状態を示す図である。Face-up mounting is described, and (a) is a diagram showing a state in which the chip component is separated from the substrate, and (b) is a diagram showing a state in which the chip component is aligned and mounted on the substrate.

本発明の実施形態について図を用いて説明する。図1(a)は本発明の実施形態における実装装置1の外観を示すもので、図1(b)は図1(a)と別の角度から見た外観図であり制御系も含めた構成要素も記している。 An embodiment of the present invention will be described with reference to the drawings. FIG. 1A shows an appearance of a mounting apparatus 1 according to an embodiment of the present invention, and FIG. 1B is an appearance view seen from a different angle from FIG. 1A, and a configuration including a control system. The elements are also noted.

実装装置1は基板Sにチップ部品Cを位置合わせしてフェイスアップ実装する装置であり、位置合わせにはチップ部品Cに記されたチップ認識第1マークAC1、チップ認識第2マークAC2と、基板Sに記された基板認識第1マークAS1、基板認識第2マークAS2を用いる。具体的には、チップ認識第1マークAC1と基板認識第1マークAS1との位置関係、およびチップ認識第2マークAC2と基板認識第2マークAS2の位置関係を許容範囲内に補正した後にチップ部品Cを基板Sに実装するものである。 The mounting device 1 is a device for aligning the chip component C on the substrate S by face-up mounting. For alignment, the chip recognition first mark AC1, the chip recognition second mark AC2, and the substrate The board recognition first mark AS1 and the board recognition second mark AS2 marked S are used. Specifically, after the positional relationship between the chip recognition first mark AC1 and the substrate recognition first mark AS1 and the positional relationship between the chip recognition second mark AC2 and the substrate recognition second mark AS2 are corrected within the allowable range, the chip component is corrected. C is mounted on the substrate S.

なお、チップ部品Cの基板Sへの実装は、一般的に、熱硬化性接着剤を介して行なう。熱硬化性接着剤は、通常、チップ部品Cの電極面(チップ認識マークのある面)とは反対側に設けておくが、基板S側に設けておいてもよい。 The chip component C is generally mounted on the substrate S via a thermosetting adhesive. The thermosetting adhesive is usually provided on the side opposite to the electrode surface of the chip component C (the surface having the chip recognition mark), but it may be provided on the substrate S side.

実装装置1は、基板ステージ2、昇降加圧ユニット3、実装ヘッド4、認識機構5、および制御部10を構成要素としている。 The mounting apparatus 1 includes a substrate stage 2, a lifting/pressurizing unit 3, a mounting head 4, a recognition mechanism 5, and a controller 10.

基板ステージ2は基板Sを保持するとともに、基板Sを面内方向(XY方向)に移動させる機能を有している。ここで、基板Sの保持に際しては真空吸着方式が適しているが、これに限定されるものではなく静電吸着方式を採用してもよい。 The substrate stage 2 has a function of holding the substrate S and moving the substrate S in an in-plane direction (XY directions). Here, the vacuum suction method is suitable for holding the substrate S, but the invention is not limited to this and an electrostatic suction method may be adopted.

昇降加圧ユニット3は、実装ヘッド4を基板Sの垂直方向(Z方向)に移動させる機能と、実装ヘッド4を介したチップ部品Cへの加圧力を調整する機能を有しており、実装ヘッド4をZ方向を軸とした回転方向に角度調整する機能を有していることが望ましい。 The lifting/pressurizing unit 3 has a function of moving the mounting head 4 in the vertical direction (Z direction) of the substrate S and a function of adjusting the pressure applied to the chip component C via the mounting head 4. It is desirable to have a function of adjusting the angle of the head 4 in the rotational direction about the Z direction.

実装ヘッド4はチップ部品Cを保持して基板Sに圧着するものである。実装ヘッド4は、ヘッド本体40、ヒーター部41、アタッチメントツール42を構成要素としている。ヘッド本体40は昇降加圧ユニット3と連結しており、下側にヒーター部41を保持配置している。ヒーター部41は発熱機能を有し、アタッチメントツール42を介してチップ部品Cを加熱するものである。また、ヒーター部41は図示していない減圧流路を用いてアタッチメントツール42を吸着保持する機能を有している。アタッチメントツール42はチップ部品Cを吸着保持するものであり、チップ部品Cの形状に合わせたものが選定され、ヒーター部41に吸着保持される。 The mounting head 4 holds the chip component C and press-bonds it to the substrate S. The mounting head 4 includes a head body 40, a heater unit 41, and an attachment tool 42 as constituent elements. The head main body 40 is connected to the lifting/pressurizing unit 3, and the heater unit 41 is held and arranged on the lower side. The heater section 41 has a heat generating function, and heats the chip component C via the attachment tool 42. Further, the heater unit 41 has a function of sucking and holding the attachment tool 42 by using a depressurized flow path (not shown). The attachment tool 42 sucks and holds the chip component C. A tool suitable for the shape of the chip component C is selected and sucked and held by the heater unit 41.

本発明において、基板認識マークおよびチップ認識マークは実装ヘッド4越しに観察するものである。このため、本実施形態においては、アタッチメントツール42は透明部材で形成されているが、基板認識マークおよびチップ認識マークの位置にあわせた貫通孔を設けてもよい。ヒーター部41は基板認識マークおよびチップ認識マークが観察できるように透明部材で形成するか、開口部を設ける必要があり、本実施形態においては貫通孔41Hを設けている。ここで、貫通孔41Hは、個々の基板認識マークおよびチップ認識マークの位置に合わせて設けてもよいが、チップ部品Cの形状による交換を不要とするため、寸法仕様範囲が全て対応できる孔形状とすることが望ましい。また、実装ヘッド4には基板認識マークおよびチップ認識マークを観察する画像取込部50が進入できる空間が必要であり、本実施形態においては、図1に示すようにヘッド空間40Vを設けている。すなわち、図1の実装装置1においてヘッド本体40は、ヒーター部41上に設けた、側板、天板によって構成される構造となっている。 In the present invention, the board recognition mark and the chip recognition mark are observed through the mounting head 4. For this reason, in this embodiment, the attachment tool 42 is formed of a transparent member, but a through hole may be provided at the positions of the substrate recognition mark and the chip recognition mark. The heater portion 41 needs to be formed of a transparent member or have an opening so that the substrate recognition mark and the chip recognition mark can be observed. In this embodiment, the through hole 41H is provided. Here, the through hole 41H may be provided in accordance with the positions of the individual board recognition mark and the chip recognition mark, but since it is not necessary to replace the through hole 41H depending on the shape of the chip component C, the hole shape that can cover all dimensional specification ranges. Is desirable. Further, the mounting head 4 needs a space into which the image capturing section 50 for observing the board recognition mark and the chip recognition mark can enter, and in this embodiment, a head space 40V is provided as shown in FIG. .. That is, in the mounting apparatus 1 of FIG. 1, the head main body 40 has a structure including the side plate and the top plate provided on the heater unit 41.

認識機構5は、アタッチメントツール42、ヒーター部41を経た、実装ヘッド4越しに、基板認識マークおよびチップ認識マークの位置を認識して位置情報を取得するために用いられるものである。本実施形態において、認識機構5は、画像取込部50、光学系52、ならびに光学系52に連結する撮像手段53を構成要素としている。 The recognition mechanism 5 is used for recognizing the positions of the board recognition mark and the chip recognition mark through the attachment tool 42 and the heater unit 41 and over the mounting head 4 to acquire position information. In the present embodiment, the recognition mechanism 5 includes the image capturing unit 50, the optical system 52, and the image pickup unit 53 connected to the optical system 52 as constituent elements.

画像取込部50は、撮像手段53が取得する認識対象の上部に配置され、認識対象を視野内に納めるものである。画像取込部50は、反射手段510により、光路の方向を変更する機能を有しており、光学系52は光学レンズを有し、高解像度を得るために画像を拡大する機能を有している。 The image capturing unit 50 is arranged above the recognition target acquired by the imaging unit 53, and stores the recognition target within the visual field. The image capturing section 50 has a function of changing the direction of the optical path by the reflection means 510, and the optical system 52 has an optical lens and a function of enlarging an image to obtain high resolution. There is.

また、認識機構5は図示していない駆動機構により、ヘッド空間40V内で、基板S(およびチップ部品C)の面内方向に移動することが可能な構成となっている。更に、各々の認識マークに対して焦点位置が調整できるように、基板Sの垂直方向(Z方向)の移動も可能な構成となっている。 The recognition mechanism 5 is configured to be movable in the in-plane direction of the substrate S (and the chip component C) within the head space 40V by a drive mechanism (not shown). Further, the substrate S can be moved in the vertical direction (Z direction) so that the focus position can be adjusted for each recognition mark.

実装ヘッド4は独立して基板Sと垂直方向に移動させることが可能な構成となっており、実装ヘッド4が垂直方向に移動しても、ヘッド空間40Vに進入した認識機構5が干渉しない寸法でヘッド空間40Vは設計されている。 The mounting head 4 is configured to be independently movable in the vertical direction with respect to the substrate S, and the recognition mechanism 5 that has entered the head space 40V does not interfere even if the mounting head 4 moves in the vertical direction. Therefore, the head space 40V is designed.

制御部10は、実装装置1の動作を制御するものであり、実装ステージ2、昇降加圧ユニット3、実装ヘッド4、認識機構5と接続している。 The control unit 10 controls the operation of the mounting apparatus 1, and is connected to the mounting stage 2, the lifting/pressurizing unit 3, the mounting head 4, and the recognition mechanism 5.

制御部10は、実体的にはCPUと記憶装置を主要な構成要素とし、必要に応じてインターフェイスを介して各装置と接続されており、プログラムを内蔵することにより、取得データを用いて演算を行ない、演算結果に応じた出力を行なうことも出来る。 The control unit 10 is essentially composed of a CPU and a storage device as main constituent elements, and is connected to each device through an interface as necessary, and by incorporating a program, the acquired data is used to perform an operation. It is also possible to carry out and output according to the calculation result.

制御部10は、基板ステージ2と接続し、基板ステージ2による基板Sの保持および解除の制御や、基板Sの面内方向への移動を制御する機能を有している。 The controller 10 is connected to the substrate stage 2 and has a function of controlling the holding and releasing of the substrate S by the substrate stage 2 and controlling the movement of the substrate S in the in-plane direction.

制御部10は、昇降加圧ユニット3と接続し、実装ヘッド4の基板Sと垂直方向(Z方向)の駆動およびZ方向を軸とした回転方向の駆動、ならびに加圧力を制御する機能を有している。 The control unit 10 is connected to the lifting/pressurizing unit 3 and has a function of driving the mounting head 4 in a direction perpendicular to the substrate S (Z direction) and in a rotational direction about the Z direction, and controlling a pressing force. doing.

制御部10は、実装ヘッド4と接続し、アタッチメントツール42によるチップ部品Cの吸着保持及び解除や、ヒーター部41の加熱温度を制御する機能を有している。 The control unit 10 is connected to the mounting head 4 and has a function of suction-holding and releasing the chip component C by the attachment tool 42 and controlling a heating temperature of the heater unit 41.

制御部10は、認識機構5と接続し、基板S(およびチップ部品C)の面内方向への駆動および基板Sと垂直方向(Z方向)の駆動を制御するとともに、撮像手段53を制御して画像データを取得する機能を有している。更に、制御部10は画像処理機能を有しており、撮像手段53が取得した画像内における認識対象の位置を求める機能を有している。 The control unit 10 is connected to the recognition mechanism 5 and controls the drive of the substrate S (and the chip component C) in the in-plane direction and the drive in the direction perpendicular to the substrate S (Z direction), and also controls the imaging unit 53. It has a function of acquiring image data. Further, the control unit 10 has an image processing function, and has a function of obtaining the position of the recognition target in the image acquired by the imaging unit 53.

以下、図1に示した実装装置1による、基板Sとチップ部品Cの位置合わせ工程から実装精度測定検査工程について説明する。 Hereinafter, the process of aligning the substrate S and the chip component C to the process of measuring and inspecting the mounting accuracy by the mounting apparatus 1 shown in FIG. 1 will be described.

まず、位置合わせの前工程において、制御部10は、基板ステージ2に基板Sを保持させるとともに、実装ヘッド4にチップ部品Cを保持させている。その際、基板Sは基板ステージ2の所定範囲内に配置され、チップ部品Cはアタッチメントツール42の所定範囲内に保持されている。すなわち、チップ部品C、基板Sは大まかに位置合わせされている。このため、ヒーター41の貫通孔41Hおよびアタッチメントツール42を通して、基板認識第1マークAS1、基板認識第2マークAS2、チップ認識第1マークAC1、およびチップ認識第2マークAC2の何れもが、実装ヘッド4越に観察可能な状態になっている。 First, in the pre-process of alignment, the control unit 10 causes the substrate stage 2 to hold the substrate S and the mounting head 4 to hold the chip component C. At that time, the substrate S is arranged within a predetermined range of the substrate stage 2, and the chip component C is held within a predetermined range of the attachment tool 42. That is, the chip component C and the substrate S are roughly aligned. Therefore, through the through hole 41H of the heater 41 and the attachment tool 42, all of the board recognition first mark AS1, the board recognition second mark AS2, the chip recognition first mark AC1, and the chip recognition second mark AC2 are mounted. It is observable over 4 years.

図3から図6は、位置合わせ工程について説明するもので、基板認識マークおよびチップ認識マークの位置情報を得る過程を示す図である。 3 to 6 are diagrams for explaining the alignment step, and are diagrams showing a process of obtaining the position information of the substrate recognition mark and the chip recognition mark.

まず図3は、基板Sの基板認識第1マークAS1の位置情報を取得する過程を示すものである。ここで、図3(a)は実装装置1をY方向から見た図であり、図3(b)は実装装置1をX方向から見た(一部透視)図である。なお、図3(a)と図3(b)に示した関係は、図4から図6についても同様である(更に、図7から図12、および図14から図15、図17から図19についても同様である)。 First, FIG. 3 shows a process of acquiring the position information of the substrate recognition first mark AS1 of the substrate S. Here, FIG. 3A is a view of the mounting apparatus 1 viewed from the Y direction, and FIG. 3B is a view of the mounting apparatus 1 viewed from the X direction (partially see through). Note that the relationships shown in FIGS. 3A and 3B are the same for FIGS. 4 to 6 (in addition, FIGS. 7 to 12, 14 to 15, and 17 to 19). Is the same).

図3では、制御部10により、実装ヘッド4を降下して基板Sにチップ部品Cを近接させた状態としている。この状態では、図2に示すように、基板Sとチップ部品Cには、両者が干渉することなく面内方向に相対移動ができるだけの隙間Dが確保されている。 In FIG. 3, the control unit 10 lowers the mounting head 4 to bring the chip component C close to the substrate S. In this state, as shown in FIG. 2, the substrate S and the chip component C are provided with a gap D that allows relative movement in the in-plane direction without interference between the two.

図3では、制御部10は、認識機構5に対して、画像取込部50の光軸中心近傍に基板認識第1マークAS1が位置するように、駆動手段を制御している。この状態において、画像取込部50のXY位置情報は制御部10に記憶される。また、制御部10は、撮像手段53を制御して、基板認識第1マークAS1を焦点を合わせた状態で撮像し、画像処理機能により、視野内における基板認識第1マークAS1のXY位置情報を求め記憶する。 In FIG. 3, the control unit 10 controls the recognition mechanism 5 so that the substrate recognition first mark AS1 is located near the center of the optical axis of the image capturing unit 50. In this state, the XY position information of the image capturing section 50 is stored in the control section 10. In addition, the control unit 10 controls the image pickup unit 53 to image the substrate recognition first mark AS1 in a focused state, and uses the image processing function to obtain the XY position information of the substrate recognition first mark AS1 in the visual field. Ask and remember.

次に、制御部10は認識機構5の駆動手段を制御して、図4のように、画像取込部50の視野中心近傍にチップ認識第1マークAC1が位置されるように、認識機構5をXY面内で移動させる。その際、画像取込部50からチップ認識第1マークAC1までの距離は、基板認識第1マークAS1までの距離と異なるため、撮像手段53が取得する画像の焦点が合わなくなる。そこで、本実施形態では、基板認識第1マークAS1とチップ認識第1マークAC1の高さの差分だけ、認識機構5を基板Sと垂直方向(Z方向)に移動させている。 Next, the control unit 10 controls the driving means of the recognition mechanism 5 so that the chip recognition first mark AC1 is located near the center of the visual field of the image capturing unit 50 as shown in FIG. Are moved in the XY plane. At that time, since the distance from the image capturing unit 50 to the chip recognition first mark AC1 is different from the distance to the substrate recognition first mark AS1, the image acquired by the imaging unit 53 is out of focus. Therefore, in the present embodiment, the recognition mechanism 5 is moved in the vertical direction (Z direction) with respect to the substrate S by the difference in height between the substrate recognition first mark AS1 and the chip recognition first mark AC1.

図4の状態において、画像取込部50のXY位置情報は制御部10に記憶される。また、制御部10は、撮像手段53を制御してチップ認識第1マークAC1を焦点を合わせた状態で撮像し、画像処理機能により、視野内におけるチップ認識第1マークAC1のXY位置情報を求め記憶する。 In the state of FIG. 4, the XY position information of the image capturing unit 50 is stored in the control unit 10. Further, the control unit 10 controls the imaging unit 53 to image the chip recognition first mark AC1 in a focused state, and obtains the XY position information of the chip recognition first mark AC1 in the visual field by the image processing function. Remember.

次に、制御部10は認識機構5の駆動手段を制御して、図5のように、画像取込部50の視野中心近傍にチップ認識第2マークAC2が位置されるように、認識機構5をXY面内で移動させる。その際、画像取込部50からチップ認識第2マークAC2までの距離は、チップ認識第1マークAC1までの距離と変わらないので、焦点調整のために認識機構5を基板Sと垂直方向(Z方向)に移動させる必要はない。 Next, the control unit 10 controls the driving unit of the recognition mechanism 5 so that the chip recognition second mark AC2 is positioned near the center of the visual field of the image capturing unit 50 as shown in FIG. Are moved in the XY plane. At that time, since the distance from the image capturing unit 50 to the chip recognition second mark AC2 is the same as the distance to the chip recognition first mark AC1, the recognition mechanism 5 is moved in the vertical direction (Z Direction) need not be moved.

図5の状態において、画像取込部50のXY位置情報は制御部10に記憶される。また、制御部10は、撮像手段53を制御してチップ認識第2マークAC2を焦点を合わせた状態で撮像し、画像処理機能により、視野内におけるチップ認識第2マークAC2のXY位置情報を求め記憶する。 In the state of FIG. 5, the XY position information of the image capturing unit 50 is stored in the control unit 10. Further, the control unit 10 controls the image pickup means 53 to image the chip recognition second mark AC2 in a focused state, and obtains the XY position information of the chip recognition second mark AC2 in the visual field by the image processing function. Remember.

この後、制御部10は認識機構5の駆動手段を制御して、図6のように、画像取込部50の視野中心近傍に基板認識第2マークAS2が位置されるように、認識機構5をXY面内で移動させる。その際、焦点を合わせるためにチップ認識第2マークAC2と基板認識第2マークAS2との高さの差分だけ、認識機構5を基板Sと垂直方向(Z方向)に移動させている。 After that, the control unit 10 controls the driving unit of the recognition mechanism 5 so that the board recognition second mark AS2 is positioned near the center of the visual field of the image capturing unit 50 as shown in FIG. Are moved in the XY plane. At that time, in order to adjust the focus, the recognition mechanism 5 is moved in the vertical direction (Z direction) with respect to the substrate S by the difference in height between the chip recognition second mark AC2 and the substrate recognition second mark AS2.

図6の状態において、画像取込部50のXY位置情報は制御部10に記憶される。また、制御部10は、撮像手段53を制御して基板認識第2マークAS2を焦点を合わせた状態で撮像し、画像処理機能により、視野内における基板認識第2マークAS2のXY位置情報を求め記憶する。 In the state of FIG. 6, the XY position information of the image capturing unit 50 is stored in the control unit 10. Further, the control unit 10 controls the image pickup means 53 to image the substrate recognition second mark AS2 in a focused state, and obtains the XY position information of the substrate recognition second mark AS2 in the visual field by the image processing function. Remember.

このように、本実施形態では、認識機構5のXY位置情報と撮像手段53が取得する画像の視野内における認識マークのXY位置情報により、基板認識マークとチップ認識マークの相対位置関係を得ることが出来る。また、個々の基板認識マークおよびチップ認識マークに焦点を合わせた状態で撮像認識して位置情報を得ているため、精度の高い位置情報を得ることができる。 As described above, in the present embodiment, the relative positional relationship between the substrate recognition mark and the chip recognition mark is obtained based on the XY position information of the recognition mechanism 5 and the XY position information of the recognition mark within the field of view of the image acquired by the imaging unit 53. Can be done. Further, since the position information is obtained by recognizing the image while focusing on the individual board recognition mark and the chip recognition mark, it is possible to obtain highly accurate position information.

前記で得られた相対位置情報から、制御部10は基板Sとチップ部品Cとの位置ズレ量を演算して求める。 From the relative position information obtained above, the control unit 10 calculates and obtains the amount of positional deviation between the board S and the chip component C.

その後、制御部10は、この位置ズレを修正するために基板面内における基板Sとチップ部品Cの補正移動量を算出し、基板ステージ2および/または実装ヘッド4を基板面内方向に駆動して、基板Sとチップ部品Cの位置ズレ量が許容範囲となるように位置合わせを行う。 After that, the control unit 10 calculates the correction movement amount of the substrate S and the chip component C within the substrate surface in order to correct this positional deviation, and drives the substrate stage 2 and/or the mounting head 4 in the in-plane direction. Then, the substrate S and the chip component C are aligned so that the amount of positional deviation is within an allowable range.

基板Sとチップ部品Cの位置合わせが完了した後、実装工程が開始される。実装工程において、制御部10は、実装ヘッド4を下降させて、基板Sにチップ部品Cを密着させ、所定の加圧力にて実装を行う。その際、基板Sとチップ部品Cの間に熱硬化性接着剤を、実装ヘッド4のヒーター部41で加熱することで、基板Sにチップ部品Cが固定される。所定時間の加圧加熱を行った後、実装ヘッド4はチップ部品Cの吸着保持を解除して上昇し、実装工程は完了する。 After the alignment of the board S and the chip component C is completed, the mounting process is started. In the mounting process, the control unit 10 lowers the mounting head 4 to bring the chip component C into close contact with the substrate S, and mounts the chip component C with a predetermined pressure. At that time, the chip component C is fixed to the substrate S by heating the thermosetting adhesive between the substrate S and the chip component C by the heater portion 41 of the mounting head 4. After pressurizing and heating for a predetermined time, the mounting head 4 releases the suction holding of the chip component C and ascends, and the mounting process is completed.

ところで、品質管理の観点から、実装工程完了後には、全数実装位置精度測定検査を行うことが求められるようになってきている。しかし、実装工程完了後に別装置で実装位置精度測定を行うことは、コストの上昇を伴う。また、実装位置精度の不良が発生した時に、気付くまでに時間を要するため修正処置の遅れを伴う。そこで、図7に示すように、実装装置1の認識機構5を使用して、実装工程完了後に位置合わせ工程と同様、基板認識第1マークAS1とチップ認識第1マークAC1の位置情報と、基板認識第2マークAS2とチップ認識第2マークAC2の位置情報を得て、チップ部品Cを基板Sに実装した状態の実装位置精度を求める機能を追加している。この方法であれば、実装装置と別の装置は不要であり、コストの上昇は伴わない。 By the way, from the viewpoint of quality control, it is required to perform 100% mounting position accuracy measurement inspection after the mounting process is completed. However, if the mounting position accuracy measurement is performed by another device after the mounting process is completed, the cost is increased. Further, when a defect in mounting position accuracy occurs, it takes time to notice it, which causes a delay in corrective action. Therefore, as shown in FIG. 7, by using the recognition mechanism 5 of the mounting apparatus 1, the positional information of the board recognition first mark AS1 and the chip recognition first mark AC1 and the board after the mounting step is completed as in the alignment step. A function is added to obtain the position information of the recognition second mark AS2 and the chip recognition second mark AC2 and obtain the mounting position accuracy in the state where the chip component C is mounted on the substrate S. With this method, a device different from the mounting device is unnecessary, and the cost does not increase.

しかし、実装工程完了後に実装装置1の認識機構5を使用して実装位置精度を測定検査することは、実装位置精度測定の動作の時間が増加するため、特に全数の実装位置精度測定検査する場合には生産性の著しい低下を伴う。 However, when the mounting position accuracy is measured and inspected by using the recognition mechanism 5 of the mounting apparatus 1 after the mounting process is completed, the operation time of the mounting position accuracy measurement is increased. Is accompanied by a marked decrease in productivity.

そこで、本発明では、実装ヘッド4越しにチップ認識マークおよび基板認識マークが認識できる構成であることと、基板Sとチップ部品Cとの位置関係は、チップ部品Cが基板Sに密着した段階で決定されることに着目し、実装工程中の段階で、各々の基板認識マークおよびチップ認識マークの位置情報を得て、実装位置精度の測定検査を行うことを実現させている。すなわち、基板ステージ2に保持された基板Sに、実装ヘッド4に保持され加圧されたチップ部品Cは、密着した段階で固定され、その状態は接着剤硬化により維持されることを根拠とし、実装工程中の段階で実装位置精度の測定検査を開始させ、両工程を並行させることでにより、コストの上昇や生産能力の低下を伴うことなく、全数の実装精度測定検査を行うことを実現させるものである。 Therefore, according to the present invention, the chip recognition mark and the board recognition mark can be recognized through the mounting head 4 and the positional relationship between the substrate S and the chip component C is determined when the chip component C is in close contact with the substrate S. Focusing on the determination, the position information of each board recognition mark and chip recognition mark is obtained at the stage of the mounting process, and the measurement and inspection of the mounting position accuracy is realized. That is, the chip component C held and pressed by the mounting head 4 is fixed to the substrate S held by the substrate stage 2 at the stage of close contact, and the state is maintained by the adhesive curing, By starting the measurement and inspection of the mounting position accuracy at the stage during the mounting process, and by performing both processes in parallel, it is possible to perform all the mounting accuracy measurement and inspection without increasing costs and lowering production capacity. It is a thing.

以後、実装装置1を用い、実装工程と並行して実装位置精度測定を行なう実施形態について説明する。図8は、実装装置1が、実装工程において実装ヘッド4を下降させて、チップ部品Cを基板Sに密着させた状態を示すものである。本実施形態における実装精度測定検査工程は、実装ヘッド4が下降し、チップ部品Cが基板Sに密着した直後から開始することができる。ここで、チップ部品Cが基板Sに密着したか否かは、図示していない圧力センサーまたは変位センサー等により判断できるようにしている。 Hereinafter, an embodiment in which the mounting apparatus 1 is used to measure the mounting position accuracy in parallel with the mounting process will be described. FIG. 8 shows a state in which the mounting apparatus 1 lowers the mounting head 4 in the mounting process to bring the chip component C into close contact with the substrate S. The mounting accuracy measurement/inspection step in the present embodiment can be started immediately after the mounting head 4 is lowered and the chip component C is brought into close contact with the substrate S. Here, whether or not the chip component C is in close contact with the substrate S can be determined by a pressure sensor, a displacement sensor, or the like (not shown).

図9は、実装装置1がチップ部品Cが基板Sに密着させた実装工程において、基板Sの基板認識第1マークAS1の位置情報を取得する過程を示すものであり、認識機構5の動作は図3に示した位置合わせ工程と同様である。 FIG. 9 shows a process in which the mounting apparatus 1 acquires the position information of the substrate recognition first mark AS1 of the substrate S in the mounting process in which the chip component C is brought into close contact with the substrate S. The operation of the recognition mechanism 5 is as follows. This is the same as the alignment step shown in FIG.

以降の実装精度測定検査工程の動作は、図10から図12に示すように、位置合わせ工程と同様であり、図9から図12の状態で得られた基板認識第1マークAS1とチップ認識第1マークAC1の相対位置関係と、基板認識第2マークAS2とチップ認識第2マークAC2の相対位置関係から実装位置精度を求める。すなわち、制御部10は、基板認識第1マークAS1とチップ認識第1マークAC1の相対位置関係および基板認識第2マークAS2とチップ認識第2マークAC2の位置関係について、基板Sの所定位置にチップ部品Cが正確に実装されている場合と、認識機構5を用いた認識で実際に得られた位置情報とを比較して、基板Sに対するチップ部品Cの実装位置精度を演算して求める。 The subsequent mounting accuracy measurement/inspection process is similar to the alignment process as shown in FIGS. 10 to 12, and the substrate recognition first mark AS1 and the chip recognition first mark AS1 obtained in the states of FIGS. The mounting position accuracy is obtained from the relative positional relationship between the 1 mark AC1 and the relative positional relationship between the substrate recognition second mark AS2 and the chip recognition second mark AC2. That is, the controller 10 determines the relative positional relationship between the substrate recognition first mark AS1 and the chip recognition first mark AC1 and the positional relationship between the substrate recognition second mark AS2 and the chip recognition second mark AC2 at a predetermined position on the substrate S. The mounting position accuracy of the chip component C on the substrate S is calculated and calculated by comparing the case where the component C is accurately mounted and the position information actually obtained by the recognition using the recognition mechanism 5.

ところで、図3から図6の位置合わせ工程では、認識機構5は基板認識第2マークAS2を認識する状態で終わっているので、実装位置精度測定検査工程を基板認識第2マークAS2から始めるのが最も効率的である。また、認識機構5は実装ヘッド4と独立しているため、位置合わせ工程と実装工程の間で実装ヘッド4が降下しても、画像取込部50と基板認識第2マークAS2の位置関係に何ら変化はないので、焦点調整は不要である。 By the way, in the alignment process of FIGS. 3 to 6, since the recognition mechanism 5 finishes in the state of recognizing the board recognition second mark AS2, it is preferable to start the mounting position accuracy measurement/inspection process from the board recognition second mark AS2. Most efficient. Further, since the recognition mechanism 5 is independent of the mounting head 4, even if the mounting head 4 is lowered between the alignment process and the mounting process, the positional relationship between the image capturing unit 50 and the board recognition second mark AS2 is maintained. Since there is no change, focus adjustment is unnecessary.

なお、実装工程に要する時間よりも、実装精度測定検査工程に要する時間が長い場合、実装精度測定工程中に実装ヘッド4が上昇することになるが、認識機構5は実装ヘッド4と独立しているため、画像取込部50と各認識対象までの距離に何ら変化はないので、認識機構5の動作は実装ヘッド4の位置に関する影響を受けない。
すなわち、実装工程の時間(実装ヘッド4が下降し、チップ部品Cが基板Sに密着した直後から実装ヘッド4の上昇が完了するまでの時間)≧実装位置精度測定検査工程の時間が成立する場合、生産性の低下を伴わずに全数の実装位置測定検査が可能となる。
If the time required for the mounting accuracy measurement/inspection process is longer than the time required for the mounting process, the mounting head 4 rises during the mounting accuracy measurement process, but the recognition mechanism 5 is independent of the mounting head 4. Since there is no change in the distance between the image capturing unit 50 and each recognition target, the operation of the recognition mechanism 5 is not affected by the position of the mounting head 4.
That is, the time of the mounting process (the time from immediately after the mounting head 4 is lowered and the chip component C is brought into close contact with the substrate S until the mounting head 4 is completely lifted)≧the time of the mounting position accuracy measurement/inspection process Therefore, it is possible to measure and inspect all the mounting positions without lowering the productivity.

ところで、チップ部品Cが基板Sに密着した状態は、図2における隙間Dがゼロになり、基板認識マークとチップ認識マークの上下方向高低差は「チップ部品Cの厚みTC」となる。すなわち、チップ厚みTCが小さくなれば、基板認識マークとチップ認識マークの垂直方向の高低差も小さくなる。ここで、基板認識マークとチップ認識マークの垂直方向の高低差が撮像手段53の被写界深度以内であれば、図13に示すように基板認識第1マークAS1とチップ認識第1マークAC1の両方を明瞭かつ同時に撮像できることを意味するものである。 By the way, when the chip component C is in close contact with the substrate S, the gap D in FIG. 2 is zero, and the vertical difference in height between the substrate recognition mark and the chip recognition mark is “the thickness TC of the chip component C”. That is, as the chip thickness TC becomes smaller, the vertical difference between the substrate recognition mark and the chip recognition mark also becomes smaller. Here, if the vertical difference between the board recognition mark and the chip recognition mark is within the depth of field of the image pickup means 53, as shown in FIG. 13, the board recognition first mark AS1 and the chip recognition first mark AC1 are displayed. This means that both can be clearly and simultaneously imaged.

すなわち、チップ厚みTCが小さく、実装状態の基板認識マークとチップ認識マークの垂直方向の高低差が撮像手段53の被写界深度以内の場合には、図14に示すように、画像取込部50を基板認識第1マークAS1とチップ認識第1マークAC1の中点近傍位置とし、撮像手段53が両方の認識マークを焦点深度内かつ同一視野内で同時に撮像して認識することが可能となる。更に、図15のように、基板認識第2マークA2とチップ認識第2マークAC2も同様に同時に撮像して認識すれば、撮像回数を半減することが出来るため、実装位置精度測定検査工程に要する時間を大幅に短縮することが出来る。したがって、このような機能を追加しておくことで、実装工程の時間(実装ヘッド4が下降し、チップ部品Cが基板Sに密着した直後から実装ヘッド4の上昇が完了するまでの時間)≧実装位置精度測定検査工程の時間を成立させ、生産性の低下を伴わずに全数の実装位置精度測定検査できる可能性が極めて高くなる。 That is, when the chip thickness TC is small and the vertical difference between the mounted board recognition mark and the chip recognition mark is within the depth of field of the image pickup means 53, as shown in FIG. 50 is the position near the midpoint of the substrate recognition first mark AS1 and the chip recognition first mark AC1, and the image pickup means 53 can simultaneously image and recognize both recognition marks within the depth of focus and within the same field of view. .. Further, as shown in FIG. 15, if the board recognition second mark A2 and the chip recognition second mark AC2 are similarly imaged and recognized at the same time, the number of times of imaging can be reduced by half, which is required in the mounting position accuracy measurement/inspection step. The time can be greatly reduced. Therefore, by adding such a function in advance, the time of the mounting process (the time from immediately after the mounting head 4 is lowered and the chip component C is brought into close contact with the substrate S until the mounting head 4 is completely lifted)≧ There is an extremely high possibility that the mounting position accuracy measurement/inspection process can be completed and that all the mounting position accuracy measurement/inspections can be performed without lowering productivity.

ところで、撮像手段53を用いて実装工程中に実装位置精度を求めることが可能となれば、環境変化に伴う撮像手段53の光軸位置の変化や光軸傾斜の変化、または昇降加圧ユニット3の傾斜の変化などに起因する実装位置のシフトに対して、校正演算させることが可能である。すなわち、撮像手段53が基板認識マークとチップ認識マークを撮像して位置合わせを行う位置合わせ工程において、演算結果の位置ズレ量が許容範囲であっても、撮像手段53を用いて基板認識マークとチップ認識マークを撮像する実装位置精度測定結果で位置ズレがある場合、撮像手段53の光軸位置の変化や光軸傾斜の変化、または昇降加圧ユニット3の傾斜の変化が生じていることが容易に判り、常時自動で校正演算することにより、チップ部品Cの基板Sに対する実装位置をシフトさせることなく、常に安定して所定位置の許容範囲内に実装することが可能となる。 By the way, if it is possible to obtain the mounting position accuracy during the mounting process using the image pickup means 53, the change of the optical axis position or the change of the optical axis inclination of the image pickup means 53 due to the environmental change, or the lifting/pressurizing unit 3 can be performed. It is possible to perform a calibration calculation for a shift of the mounting position due to a change in the inclination of the. That is, in the alignment process in which the image pickup unit 53 images the substrate recognition mark and the chip recognition mark to perform the alignment, even if the positional deviation amount of the calculation result is within the allowable range, the image pickup unit 53 is used to identify the substrate recognition mark. If there is a displacement in the mounting position accuracy measurement result of imaging the chip recognition mark, it is possible that the optical axis position of the imaging means 53 has changed, the optical axis inclination has changed, or the inclination of the lifting/pressurizing unit 3 has changed. It is easy to understand, and by always performing the calibration calculation automatically, it is possible to always stably mount the chip component C within the permissible range of the predetermined position without shifting the mounting position on the substrate S.

このように、実装工程中の段階で実装位置精度を演算して求め、実装位置にフィードバックして、常時自動で実装位置を校正調整することにより、コストの上昇や生産能力の低下を伴うことなく、非常に安定した高い精度での実装が可能となる。 In this way, by calculating the mounting position accuracy at the stage during the mounting process, feeding it back to the mounting position, and constantly automatically adjusting and adjusting the mounting position, there is no increase in cost or reduction in production capacity. , Very stable and highly accurate implementation is possible.

なお、部品埋めこみ基板(エンベデッド基板)へのチップ部品Cの実装においては、基板認識マークとチップ認識マークを焦点深度内かつ同一視野内で同時に撮像する機能は極めて有効である。すなわち、図16(a)および図17に示すような凹部SCを有する基板Sの凹部SCにチップ部品Cを実装する場合、基板Sの上面とチップ部品Cの上面とは、図16(b)のようにほぼ同一高さとなる。このため、図18に示すように、認識機構の画像取込部50から、基板認識第1マークAS1までと、チップ認識第1マークAC1までは、ほぼ同一垂直距離となり、同一視野内で両方の認識マークに焦点が合った状態で同時に撮像することが容易となる。これは、図19に示す基板認識第2マークA2とチップ認識第2マークAC2を撮像する場合においても同様である。 In mounting the chip component C on the component-embedded substrate (embedded substrate), the function of simultaneously imaging the substrate recognition mark and the chip recognition mark within the depth of focus and within the same field of view is extremely effective. That is, when the chip component C is mounted in the recess SC of the substrate S having the recess SC as shown in FIGS. 16A and 17, the upper surface of the substrate S and the upper surface of the chip component C are as shown in FIG. It becomes almost the same height like. Therefore, as shown in FIG. 18, from the image capturing unit 50 of the recognition mechanism to the substrate recognition first mark AS1 and the chip recognition first mark AC1 are substantially the same vertical distance, and both of them are in the same visual field. It becomes easy to take images simultaneously with the recognition mark in focus. This is the same in the case of imaging the board recognition second mark A2 and the chip recognition second mark AC2 shown in FIG.

また、基板Sの上面とチップ部品Cの上面が同一高さになるような条件であれば、基板認識マークとチップ認識マークの上下方向高低差はゼロとなり、より明瞭な画像を取得できるため、撮像手段53の光軸位置の変化や光軸傾斜の変化、または昇降加圧ユニット3の傾斜の変化などを把握し、実装位置を常時自動で校正調整する機能にも最適であり、更に安定性、信頼性の高い、高精度な実装装置を実現することが可能である。 Also, under the condition that the upper surface of the substrate S and the upper surface of the chip component C are at the same height, the vertical height difference between the board recognition mark and the chip recognition mark is zero, and a clearer image can be obtained. It is also most suitable for the function of constantly calibrating and adjusting the mounting position automatically by grasping the change of the optical axis position of the image pickup means 53, the change of the optical axis tilt, the change of the tilt of the lifting/pressurizing unit 3, and the like. It is possible to realize a highly reliable and highly accurate mounting device.

1 実装装置
2 基板ステージ
3 昇降加圧ユニット
4 実装ヘッド
5 認識機構
10 制御部
40 ヘッド本体
40V ヘッド空間
41 ヒーター部
41H 貫通孔
42 アタッチメントツール
50 画像取込部
52 光学系
53 撮像手段
510 反射手段
C チップ部品
S 基板
AC1、AC2 チップ認識マーク
AS1、AS2 基板認識マーク
D 位置合わせ時の、チップ部品と基板の隙間
TC チップ部品の厚み
TS 基板の厚み
SC 基板の凹部
DESCRIPTION OF SYMBOLS 1 Mounting device 2 Substrate stage 3 Lifting/pressurizing unit 4 Mounting head 5 Recognition mechanism 10 Control part 40 Head body 40V Head space 41 Heater part 41H Through hole 42 Attachment tool 50 Image capturing part 52 Optical system 53 Imaging means 510 Reflecting means C Chip component S Substrate AC1, AC2 Chip identification mark AS1, AS2 Substrate identification mark D Gap between chip component and substrate during alignment TC Thickness of chip component TS Thickness of substrate SC Recess of substrate

Claims (6)

位置合わせ用のチップ認識マークを有するチップ部品と、位置合わせ用の基板認識マークを有する基板とを、前記チップ認識マークと前記基板認識マークが上面を向く姿勢でフェイスアップ実装する実装装置であって、
前記基板を保持する基板ステージと、
チップを保持する実装ヘッドと、
前記基板に対して垂直方向に前記実装ヘッドを昇降させる昇降手段と、
前記実装ヘッドの上側から前記実装ヘッド越しに、前記チップ認識マークと前記基板認識マークを認識し、前記基板面内方向に移動可能な認識機構と、
前記認識機構と接続し、前記認識機構から得た、前記チップ部品認識マークおよび前記基板認識マークの位置情報から、前記チップ部品と前記基板の位置ズレ量を計算する機能と、前記位置ズレ量に応じて前記実装ヘッド部または/および前記基板ステージを駆動して位置合わせを行う機能とを有する制御部とを備え、
前記チップ部品と前記基板の位置合わせを前記認識機構で行った後に、前記チップ部品を保持した前記実装ヘッドを前記基板に対して垂直方向に下降させ、前記チップ部品が前記基板に密着してから、
前記制御部が、前記認識機構に前記チップ認識マークおよび前記基板認識マークの認識動作を並行して開始させ、前記チップ部品が前記基板に密着した実装状態における前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに認識し、前記チップ部品と前記基板の実装位置精度を算出する機能を有する実装装置。
A mounting device for mounting a chip component having a chip recognition mark for position alignment and a substrate having a substrate recognition mark for position alignment face-up with the chip recognition mark and the substrate recognition mark facing upward. ,
A substrate stage for holding the substrate,
A mounting head that holds the chip,
An elevating means for elevating and lowering the mounting head in a direction perpendicular to the substrate,
A recognition mechanism that recognizes the chip recognition mark and the substrate recognition mark from the upper side of the mounting head over the mounting head, and is movable in the in-plane direction of the substrate,
The function of calculating the positional deviation amount of the chip component and the substrate from the positional information of the chip component recognition mark and the substrate recognition mark, which is connected to the recognition mechanism and obtained from the recognition mechanism, and the positional deviation amount. And a control unit having a function of driving the mounting head unit and/or the substrate stage to perform position adjustment.
After performing the alignment of the chip component and the substrate by the recognition mechanism, the mounting head holding the chip component is lowered in the vertical direction with respect to the substrate, and after the chip component comes into close contact with the substrate. ,
The control unit causes the recognition mechanism to start the recognition operation of the chip recognition mark and the board recognition mark in parallel, and displays the chip recognition mark and the board recognition mark in a mounted state in which the chip component is in close contact with the board. A mounting apparatus having a function of recognizing through the mounting head and calculating mounting position accuracy of the chip component and the substrate.
請求項1に記載の実装装置であって、
前記チップ部品が前記基板に密着してから、並行して開始される実装位置精度を算出するための、前記ヘッド越しに行われる前記チップ認識マークと前記基板認識マークの認識動作において、
前記認識機構の光軸中心が、前記チップ認識マークと前記基板認識マークの中点近傍位置で前記チップ認識マークと前記基板認識マークとを同時に認識する機能を有する実装装置。
The mounting apparatus according to claim 1, wherein
In the recognition operation of the chip recognition mark and the board recognition mark performed over the head, in order to calculate the mounting position accuracy that is started in parallel after the chip components are in close contact with the board,
A mounting device having a function of simultaneously recognizing the chip recognition mark and the board recognition mark at a position near the midpoint of the chip recognition mark and the board recognition mark, with the optical axis center of the recognition mechanism.
請求項2に記載の実装装置であって、
算出した実装位置精度の結果を、実装位置にフィードバックし、自動で実装位置を校正調整する機能を有する実装装置。
The mounting apparatus according to claim 2, wherein
A mounting device having a function of feeding back the calculated mounting position accuracy to the mounting position and automatically calibrating and adjusting the mounting position.
位置合わせ用のチップ認識マークを有するチップ部品を、位置合わせ用の基板認識マークを有する基板に実装する実装方法であって、前記チップ部品を前記基板と隙間を設けて配置した状態で、前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに同一方向から認識して、前記チップ部品と前記基板の相対位置関係を合わせる位置合わせ工程と、前記チップ部品を前記基板に密着させ加圧して実装する実装工程と、前記チップ部品が前記基板に密着した実装状態にあるときに、前記チップ認識マークと前記基板認識マークを前記実装ヘッド越しに同一方向から認識して、前記チップ部品と前記基板の相対位置関係を算出する実装精度測定検査工程とを備え、
前記チップ部品が前記基板に密着してから、前記実装工程と前記実装精度測定検査工程を並行して実施する実装方法。
A mounting method for mounting a chip component having a chip recognition mark for alignment on a substrate having a substrate recognition mark for alignment, wherein the chip component is arranged with a gap provided between the chip component and the chip A positioning step of recognizing the recognition mark and the board recognition mark from the same direction over the mounting head to match the relative positional relationship between the chip component and the board, and mounting the chip part by closely contacting and pressing the board. And a mounting step in which the chip component is in close contact with the substrate, the chip recognition mark and the substrate recognition mark are recognized from the same direction over the mounting head, and the chip component and the substrate are recognized. Equipped with a mounting accuracy measurement and inspection process that calculates the relative positional relationship,
A mounting method in which the mounting step and the mounting accuracy measurement/inspection step are performed in parallel after the chip component comes into close contact with the substrate.
請求項4に記載の実装方法であって、
前記実装精度測定検査工程において、前記認識機構の光軸中心が前記チップ認識マークと前記基板認識マークの中点近傍位置で、前記チップ認識マークと前記基板認識マークを同時に認識する実装方法。
The mounting method according to claim 4, wherein
The mounting method for recognizing the chip recognition mark and the board recognition mark at the same time in the mounting accuracy measurement/inspection step, where the center of the optical axis of the recognition mechanism is near the midpoint of the chip recognition mark and the board recognition mark.
請求項5に記載の実装方法であって、
前記実装精度測定検査工程で算出した実装位置精度の結果を、実装位置にフィードバックし、自動で実装位置を校正調整する実装方法。
The mounting method according to claim 5, wherein
A mounting method in which the result of the mounting position accuracy calculated in the mounting accuracy measurement/inspection step is fed back to the mounting position to automatically calibrate and adjust the mounting position.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10145094A (en) * 1996-11-14 1998-05-29 Nec Corp Parts mounting device
JPH11330109A (en) * 1998-05-20 1999-11-30 Nec Corp Device and method for packaging element
JP2017208522A (en) * 2016-05-11 2017-11-24 パナソニックIpマネジメント株式会社 Component mounting device
JP2018056481A (en) * 2016-09-30 2018-04-05 ボンドテック株式会社 Alignment device and alignment method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10145094A (en) * 1996-11-14 1998-05-29 Nec Corp Parts mounting device
JPH11330109A (en) * 1998-05-20 1999-11-30 Nec Corp Device and method for packaging element
JP2017208522A (en) * 2016-05-11 2017-11-24 パナソニックIpマネジメント株式会社 Component mounting device
JP2018056481A (en) * 2016-09-30 2018-04-05 ボンドテック株式会社 Alignment device and alignment method

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