JP2020119624A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device that realizes a mechanism that solves RowHammer problem without significantly increasing a DRAM chip area.SOLUTION: A semiconductor storage device includes: a memory portion having a plurality of memory cells; an address latch portion that receives an active command and its address, and latches and holds the address each time the active command is received; a refresh control portion that instructs a normal refresh operation to a memory access control portion when receiving a refresh command, and instructs an interrupt refresh operation to the memory access control portion for an address near the address latched by the address latch portion; and the memory access control portion that executes the normal refresh operation and the interrupt refresh operation to the memory portion based on the instruction from the refresh control portion.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device having improved resistance to failures caused by the Row Hammer problem.

The progress of miniaturization of DRAM (Dynamic Random Access Memory) manufacturing process is remarkable. As a result, interference between memory cells is likely to occur. Further, due to the miniaturization of the manufacturing process, the variation becomes large, and it becomes easy to fabricate a memory cell that is susceptible to interference. As a result, the data destruction of the memory cell has become remarkable.

In particular, in recent years, attention has been paid to the problem that when a row (row) having a specific address is repeatedly accessed, data in a row near the row is destroyed. Such a problem is called the RowHammer problem. Various solution methods have been proposed for this RowHammer problem.

Patent Document 1
Patent Document 1 below discloses a method of counting the number of accesses to a row of a DRAM and refreshing a row near the row when the count reaches a predetermined threshold value.

In the method described in Patent Document 1, in addition to the normal (normal) refresh operation in the DRAM, the address of a row in the vicinity of the row in which the access number reaches the threshold value is interrupt refreshed, so that the number of refresh times is increased compared to the conventional case. Resulting in. Therefore, it is considered that the access performance of the DRAM is lowered due to the increase in the number of refresh times. Further, it is necessary to provide a count circuit for counting the number of accesses to all the rows of the DRAM, which causes a problem of increasing the DRAM area. Therefore, in a DRAM having the same capacity, the chip area will increase.

Patent Document 2
The following Patent Document 2 discloses a method in which interrupt refresh is executed according to a principle substantially similar to the method described in Patent Document 1 above. However, Patent Document 2 proposes a method of resetting the count of the number of accesses to a row (address) that is the target of a refresh operation by normal refresh. By such an operation, it is considered that the execution of the interrupt refresh for the row is suppressed as compared with Patent Document 1.

According to the method of Patent Document 2, since the number of interrupt refreshes is suppressed, it is considered that the deterioration of the performance of the DRAM is less than that of the method of Patent Document 1.
However, the method of Patent Document 2 also requires a count circuit for counting the access to each row (address), as in the method of Patent Document 1. Since this count circuit is generally composed of an SRAM that stores the number of accesses, the problem that the chip area of the DRAM increases due to the mounting of the SRAM is the same as in Patent Document 1, It is considered that it also exists in Reference 2.

JP, 2013-239228, A JP, 2005-162253, A

The present invention has been made in view of such circumstances, and an object thereof is to realize a mechanism for solving the RowHammer problem without significantly increasing the chip area of a DRAM.

(1) In order to solve the above problems, the present invention receives a memory unit having a plurality of memory cells, an address, and an active command applied to the memory cell designated by the address, An address latch unit that keeps latching the address at the time of receiving the active command each time the active command is received, and a normal refresh operation based on the refresh command to the memory unit when a refresh command is received. The memory access control unit is instructed to execute the refresh operation based on the address latched by the address latch unit, and the memory access is performed to execute an interrupt refresh operation for an address near the address. A semiconductor memory device including: a refresh control unit for instructing a control unit; and the memory access control unit for executing the normal refresh operation and the interrupt refresh operation on the memory unit based on an instruction from the refresh control unit. Is.

(2) Further, in order to solve the above problems, the present invention receives a memory unit having a plurality of memory cells, an address, and an active command applied to the memory cell designated by the address. Then, the address when the active command is received is latched each time the active command is received, and an address latch unit that holds n latched addresses and a refresh command are received when a refresh command is received. The memory access control unit is instructed to execute a normal refresh operation on the memory unit, and the refresh operation is based on the one or more addresses latched by the address latch unit, and addresses near the address. A refresh control unit for instructing the memory access control unit to execute an interrupt refresh operation with respect to the memory unit, and the normal refresh operation and the interrupt refresh operation for the memory unit based on an instruction from the refresh control unit. And a memory access control unit that executes the address refresh, wherein the address latch unit is reset when the memory access control unit executes the interrupt refresh operation, and can latch an address when an active command is received next time. The semiconductor memory device is brought into a state. Here, the n is a natural number.

(3) The present invention provides the semiconductor memory device according to (2), wherein the address latch unit is a basis of the interrupt refresh operation when the memory access control unit executes the interrupt refresh operation. This is a semiconductor memory device in which only the address is reset and the address can be latched when the next active command is received.

(4) Further, in the semiconductor memory device according to (2), the refresh control unit is a refresh operation based on any one of the addresses latched by the address latch unit. , The memory access control unit is instructed to execute an interrupt refresh operation only for an address near the one address, and the address latch unit causes the refresh control unit to execute the interrupt refresh operation. In the semiconductor memory device, only the one address that is the basis of the interrupt refresh operation is reset, and the address when the next active command is received can be latched.

(5) Further, the present invention provides the semiconductor memory device according to any one of (2) to (4), wherein after the refresh command is received, the active command is received m times and then the address latch is received. And a monitor start unit for starting a latch operation of the unit. Here, the m is a natural number.

(6) In the semiconductor memory device according to (5), the monitor start unit receives the refresh command, and then the address latch unit receives random k active commands. It is a semiconductor memory device for starting the latch operation of. Here, k is a random natural number.

(7) Further, in the semiconductor memory device according to any one of (2) to (6), the present invention provides an address and an active command applied to the memory cell specified by the address. An access count address latch unit that receives and monitors the address when the active command is received, and counts the number of accesses to the same address, and the number of accesses to the same address counted by the access count address latch unit, It is a semiconductor memory device including an upper limit determination unit that causes the address latch unit to latch the same address when the value exceeds a predetermined value.

(8) Further, according to the present invention, in the semiconductor memory device according to any one of (1) to (7), the address when the active command is received and the address latch unit have already latched. The semiconductor memory device includes: an address comparison unit that compares the address and an address comparison unit that causes the address latch unit to perform a latch operation when the addresses are different as a result of the comparison.

(9) Further, according to the present invention, in the semiconductor memory device according to any one of (2) to (7), the number of addresses less than n already latched by the address latch unit and the active command are An address comparison unit that compares the address when it is received, and causes the address latch unit to execute the latch operation of the address when the active command is newly received, only when the comparison result shows that the addresses are different. It is a semiconductor memory device including.

(10) The present invention provides the semiconductor memory device according to (8) or (9), in which the address comparison section is refreshed when the refresh control section instructs the memory access control section to perform a normal refresh operation. The semiconductor memory device resets the address latched by the address latch unit when the address is near the address latched by the address latch unit.

(11) Further, according to the present invention, in the semiconductor memory device according to any one of (1) to (10), the active command to be received is monitored, the active command is transmitted after the refresh command is received. The semiconductor memory device further includes a monitor unit that inhibits the refresh control unit from instructing the memory access control unit to perform the interrupt refresh operation when not receiving.

(12) Further, according to the present invention, in the semiconductor memory device according to any one of (1) to (11), the active command is received in the vicinity of an address when the active command is received. The semiconductor memory device is either an address obtained by adding +1 to the address obtained when the data is added or an address obtained by adding -1.

(13) The present invention provides the semiconductor memory device according to any one of (1) to (12), wherein the active command is a command for activating a word line of the memory section, and at least: A semiconductor memory device including a read command, a write command, and a refresh command.

As described above, according to the present invention, the interrupt refresh executed to deal with the RowHammer problem is executed for the row (address) which is estimated to be effective. Therefore, it is not necessary to provide a circuit for counting the access to each row for each row. As a result, the area of the circuit for dealing with the RowHammer problem can be made smaller than before, and the increase in the chip area of the DRAM can be prevented.

3 is a circuit block diagram of a countermeasure circuit against a RowHammer problem in the DRAM device according to the first embodiment. FIG. 6 is a time chart illustrating the operation of the countermeasure circuit for the RowHammer problem according to the first embodiment. FIG. 9 is a circuit block diagram of a countermeasure circuit against a RowHammer problem of the DRAM device according to the second embodiment. 9 is a time chart illustrating the operation of the countermeasure circuit for the RowHammer problem according to the second embodiment. FIG. 11 is a circuit block diagram of a countermeasure circuit against a RowHammer problem of the DRAM device according to the third embodiment. 9 is a time chart for explaining the operation of the countermeasure circuit for the RowHammer problem according to the third embodiment. FIG. 10 is a circuit block diagram of a countermeasure circuit against a RowHammer problem in the DRAM device according to the fourth embodiment. 9 is a time chart for explaining the operation of the countermeasure circuit for the RowHammer problem according to the fourth embodiment.

Hereinafter, a stacked semiconductor device according to a preferred embodiment of the present invention will be described in detail with reference to the drawings. The embodiment described below is an example as a means for realizing the present invention, and should be appropriately modified or changed according to the configuration of the device to which the present invention is applied and various conditions. However, the present invention is not limited to the embodiment.

First. Embodiment 1
Configuration FIG. 1 is a circuit block diagram showing a RowHammer countermeasure circuit 10 of a DRAM device according to the first embodiment. The RowHammer countermeasure circuit 10 shown in FIG. 1 is a part of the configuration of the DRAM device. In FIG. 1, the part other than the memory 18 is the RowHammer countermeasure circuit 10. That is, the Row Hammer countermeasure circuit 10 includes an Active monitor circuit 12, a refresh control circuit 14, a memory access control circuit 16, address latch circuits 20a and 20b, and an address comparison circuit 22. Also in each of the embodiments described later, the portion excluding the memory is the RowHammer countermeasure circuit.

In FIG. 1, an external input command and an external input address are both input to the DRAM device. The DRAM device executes the operation designated by the external input command with respect to the memory cell designated by the external input address. Thus, the external input address and the external input command designating the process for the memory cell designated by the external input address are simultaneously input to the DRAM device.
The external input command is input to the memory access control circuit 16. The memory access control circuit 16 is a circuit for controlling the operation of the DRAM device, and executes a predetermined operation for the memory 18 based on the input external input command.
The memory 18 corresponds to a suitable example of the memory unit in the claims. Further, the memories 38, 58, 78 in the embodiments described later also correspond to a suitable example of the memory section in the claims.

In the first embodiment, the external input command is input to the active monitor circuit 12, the refresh control circuit 14, the address latch circuits 20a and 20b, and the address comparison circuit 22 in addition to the memory access control circuit 16. ing.
The external input address is input to the memory access control circuit 16. The memory access control circuit 16 is a circuit for controlling the operation of the DRAM device, and executes a predetermined operation designated by the external input command on the memory cell designated by the input external input address.

In the first embodiment, the external input address is input to the address latch circuits 20a and 20b and the address comparison circuit 22 in addition to the memory access control circuit 16.
The refresh control circuit 14 is a circuit that controls refresh of the DRAM device. First, when a refresh command is input as an external input command, the refresh control circuit 14 controls the memory access control circuit 16 to perform a normal (normal) refresh operation. To execute. This operation is literally a conventional refresh operation itself.
The memory access control circuit 16 corresponds to a preferred example of the memory access control unit in the claims. Similarly, the memory access control circuits 36, 56, and 76 of Embodiments 2 to 4 described later also correspond to suitable examples of the memory access control unit in the claims.

The characteristic feature of the refresh control circuit 14 in the first embodiment is that when a regular refresh operation is executed, if there is an active command input before the refresh command is input, the regular refresh operation is performed. In addition to executing the interrupt refresh operation.

In the first embodiment, the active command is an external input command for activating (activating) the word line in the memory 18 of the DRAM device, and a read command, a write command, a refresh command, etc. are typical active commands. Is.
When such active commands are intensively input to a specific address, the RowHammer problem occurs as described above. Therefore, in the first embodiment, an active command that may cause a RowHammer problem is monitored.
The refresh control circuit 14 corresponds to a suitable example of the refresh control unit in the claims. Further, the refresh control circuits 34, 54, 74 in the embodiments described later also correspond to a suitable example of the refresh control section in the claims.

The Active monitor circuit 12 determines whether or not there is an active command. The Active monitor circuit 12 is a circuit that monitors an external input command and monitors whether or not a predetermined active command is input from the input of the refresh command to the input of the next refresh command. ..

The active monitor circuit 12 monitors an external input command, and when a refresh command is input again without any active command being input after the refresh command is input to the DRAM device, a refresh control circuit 14 to be described later. Control to prevent interrupt refresh (suppress interrupt refresh operation). In this case, the refresh control circuit 14 instructs the memory access control circuit 16 to perform only the normal refresh operation, to execute only the normal refresh operation, and not to execute the interrupt refresh operation.
However, even when the refresh control circuit 14 suppresses the interrupt refresh operation, the memory access control circuit 16 executes the interrupt refresh based on the address when the address latch circuit 20 latches the address.
The Active monitor circuit 12 corresponds to a suitable example of the monitor unit in the claims. Further, the Active monitor circuits 32, 52, 72 and the control circuit, which will be described later, also correspond to a preferable example of the monitor unit in the claims.

On the other hand, when the Active monitor circuit 12 does not suppress the interrupt refresh operation (when there is an active command), the refresh control circuit 14 executes the interrupt refresh operation to the memory access control circuit 16 when executing the normal refresh operation. Let

The address latch circuits 20a and 20b are latch circuits that hold an address when an interrupt refresh operation is executed, and the refresh control circuit 14 relates to the address held in the address latch circuit 20 to perform an interrupt refresh in a memory. Instruct the access control circuit 16.
The address latch circuit 20 monitors an external input command and, when an active command other than the refresh command is input, latches the external input address when the external input command (other than the refresh command) is input. ..

In the first embodiment, two address latch circuits 20a and 20b are provided, and two addresses can be latched. The number "2" of the latches corresponds to a preferable example of n in the claims.
The address comparison circuit 22 is a circuit that controls the address latch circuit 20 so as not to latch the same address. The address latch circuit 20 latches an external input address every time an active command is input. The address to be latched and the address already latched by the address latch circuit 20 are compared with each other by the address comparison circuit 22. Have been compared by. As a result of this comparison, when the already latched address and the address to be latched are the same, the address comparison circuit 22 controls the address latch circuit 20 to stop the latch operation. This operation prevents the same address from being latched.
The address comparison circuit 22 corresponds to a preferred example of the address comparison unit in the claims. Further, the address comparison circuits 42, 62, 82 in the embodiments described later also correspond to a preferable example of the address comparison unit in the claims.

In the first embodiment, the address latched by the address latch circuit 20 is the address that is the basis of interrupt refresh. Therefore, since it is meaningless to latch the same address, the address comparison circuit 22 is provided to allow the address latch circuit 20a and the address latch circuit 20b to latch different addresses.

The address latch circuits 20a and 20b according to the first embodiment monitor the external input command, and when the external input command is a refresh command, the address latch circuits 20a and 20b are reset at a predetermined timing and a new address can be latched. .. Then, every time an active command other than the refresh command is input, the external input address input at that time is latched. The address latch circuit 20 executes this latch operation twice, latches two addresses, and then stops the latch operation.

By such an operation, the address latch circuit 20 latches a maximum of two external input addresses at the time of an active command input between refresh commands.
That is, in principle, the address latch circuit 20 latches the (different) addresses of the first two active commands after the refresh command is input. Based on the address thus latched, interrupt refresh is executed when a refresh command is input.
The address latch circuit 20 corresponds to a preferred example of the address latch unit in the claims. The address latch circuits 40, 60, 80 in the embodiments described later also correspond to a suitable example of the address latch unit in the claims.

A feature of the first embodiment is that when the refresh control circuit 14 performs the normal refresh operation based on the refresh command, when the active command is input between the previous normal refresh and the interrupt refresh operation of this time. That is, the address of is latched (held). Then, the interrupt refresh is executed based on the latched address. This makes it possible to execute an interrupt refresh operation based on an address when an active command that causes a RowHammer problem is input, and to perform an interrupt refresh operation on an address at which a RowHammer problem is likely to occur.

Operation Hereinafter, the operation of the RowHammer countermeasure circuit 10 of the first embodiment described with reference to FIG. 1 will be described based on the time chart of FIG.

In the time chart of FIG. 2, CMD represents the external input command in FIG. ACT represents an active command other than the refresh command, and is a read command or the like. PRE represents the precharge for the DRAM device. REF represents a refresh command.
WL_Enable in FIG. 2 is a signal output from the memory access control circuit 16 to the memory 18, and is a signal that activates a word (row) line.
The external input address of FIG. 2 represents the external input address of FIG.
Address latch 1set in FIG. 2 represents the address latch circuit 20a in FIG. 1, and address latch 2set represents the address latch circuit 20b in FIG.

In the time chart of FIG. 2, when the active command ACT is input, the memory access control circuit 16 outputs one pulse of WL_Enable accordingly. The precharge PRE is issued at a predetermined timing within the one pulse.

In the time chart of FIG. 2, two active commands ACT are continuously input, and the external input addresses at that time are #000 and #100 in order. The first address #000 is latched by the address latch 1set (address latch circuit 20a). The next address #100 is latched by the address latch 2set (address latch circuit 20b).

When the refresh command REF is input subsequently to the two active commands ACT, the refresh control circuit 14 instructs the memory access control circuit 16 to perform the refresh operation based on the refresh command REF.

The refresh control circuit 14 first executes a regular (normal) refresh operation based on the refresh command REF and an instruction from the refresh control circuit 14. In the example shown in FIG. 2, three predetermined refresh counter values are used and three refresh operations are executed. In FIG. 2, the counter value is a value of a predetermined (not shown) refresh counter, and is all represented as a “counter value” in FIG. 2, but is a value that is incremented by +2 for each refresh operation. .. In the first embodiment, the refresh operation for two word lines is performed at one time by one refresh operation, and the counter value increases by +2.

A feature of this embodiment is that the interrupt refresh operation is executed subsequent to the regular refresh operation performed three times. The refresh control circuit 14 also instructs the memory access control circuit 16 to perform this interrupt refresh operation. However, as described above, when the Active monitor circuit 12 does not detect the active command, the refresh control circuit 14 does not instruct the memory access control circuit 16 to perform the interrupt refresh operation, and the interrupt in FIG. No refresh operation is performed.

In the first embodiment, the interrupt refresh operation is performed once. The address at that time is determined by alternately using the addresses latched in the address latch 1set and the address latch 2set as a basis. In the example of FIG. 2, the address #000 latched by the address latch 1set is used as a basis. The address that is actually the target of the interrupt refresh operation is the “nearby” address of address #000. In the first embodiment, for example, a value obtained by inverting the lower 1 bit of the address latched by the address latch circuit 20 is used. That is, an address obtained by adding +1 or -1 to the address latched in the address latch 1set or 2set is an address to be refreshed. In the example of FIG. 2, the address #001, which is the address #000 latched by the address latch 1set, is incremented by 1, which is the address to be refreshed.

The DRAM device according to the first embodiment will be described by taking, as an example, a DRAM device in which every two word lines are controlled as a pair. In such a DRAM device, the word lines forming the pair are arranged close to each other, and it is known in advance that the word line causing the RowHammer problem is the opposite word line of the pair. Therefore, when the active command is applied to the address latched in the address latch circuit 20, the RowHammer problem occurs when the least significant 1 bit of the latched address is inverted, that is, The address becomes +1 or -1.

The memory access control circuit 16 inverts the least significant 1 bit of the address latched by the address latch circuit 20 and calculates the address for executing the interrupt refresh operation.
In the first embodiment, the address latch circuit 20 latches two addresses. Therefore, in the interrupt refresh operation, the address related to the refresh operation is calculated based on one of the addresses. Then, the address that is the basis of the calculation is reset after the refresh operation, and a state where a new address can be latched is entered. In the example of FIG. 2, since #000 of the address latch 1set is used to execute the interrupt refresh operation for #001, the address latch 1set is reset and a new address can be latched. As a result, in FIG. 2, the address latch 1set latches the external input address #111 when the active command ACT immediately after the refresh operation is input.

On the other hand, the address #100 latched by the address latch 2set is not used as a basis in the interrupt refresh operation, so the latched address is held. Then, it is used as a basis in the interrupt refresh operation in the next refresh operation. That is, in the refresh operation performed after the refresh operation shown in FIG. 2, the interrupt refresh operation is executed on #101 obtained by incrementing #100 which is the address latched in the address latch 2set.

As described above, in the first embodiment, the address latch circuit 20 can latch two addresses, and the addresses are alternately used as the basis of the interrupt refresh operation. Then, the address latch (1set or 2set) that is the basis of the calculation of the address that is the target of the interrupt refresh operation is reset, and a new address can be latched.

When another active command is not input between the refresh commands, the Active monitor circuit 32 controls the refresh control circuit 14 to execute the interrupt refresh operation, as described above. Only the normal refresh operation is executed.

Approach to the RowHammer problem In order to deal with the RowHammer problem, the inventors of the present invention considered as follows.

(1) First, the maximum number of RowHammers is examined.
Consider that the total number of words per bank of the DRAM device according to the first embodiment is, for example, 32 k (WL). Here, WL is WordLine, which is the number of word lines.

In the first embodiment, the number of words refreshed by one normal refresh (AREF (AutoRefresh)) is 6 WL (WordLine) per bank as described above. As described with reference to FIG. 2, since two word lines are accessed three times, the total number is six.
The cycle tREF of the refresh operation is 7.8 μs. That is, in principle, the refresh command is input to the DRAM device every 7.8 μsec.
Further, the interval tRC(min) for inputting the active command is 50 ns. This tRC is the minimum value.

(2) Under the above premise, the regular refresh number required to refresh all the word lines of one bank is calculated as follows.
32kWL/6WL about 5333 times The refresh cycle tREF is 7.8 μs, so the time required for completely refreshing one bank is
(32kWL/6WL)*7.8μs About 41600μs
Is. The number of times an active command is issued during this time is
((32kWL/6WL)*7.8μs/50ns)
=832k
Is. Therefore, the active command may be applied up to 832k times during the refresh interval. This is described as RH(max)=832k.

(3) Number of target word lines that need to be processed to solve the RH problem Also, in the semiconductor process for forming the DRAM device, the number of RHs guaranteed by the process, that is, the number of active commands that does not cause the RowHammer problem is determined. It is 100k. That is, if the refresh operation is performed before the active command is applied 100 k times, the RowHammer problem does not occur.

Therefore, the number of word lines that must be dealt with for the RowHammer problem is about 8.32.
8.32(WL)=832k/100k
Thus, the target word that needs to be processed for the RowHammer problem is called the RH target word. Here, the number of RH target words is about 8.32.

(4) Also, at the time of normal refresh (AREF), the probability of hitting the RH target word (refreshing that word is executed) is examined.
First, the probability of activating the RH target word immediately before the refresh command is input is calculated as 0.1202 (=100/832). Then, the probability of never hitting the RH target word during the refresh operation N times is obtained as follows.
N=1 0.8837
N=2 0.7810
N=X 100*(100/832) to the power of X N=5.3K/64 0.000028 AREF command (refresh command) Execute interrupt refresh once every 64 times.
N=5.3K/8 3.8E-35 AREF command (refresh command) Execute interrupt refresh once every eight times.
N=5.3K 4.2E-290 AREF command (refresh command) Executes interrupt refresh once at a time. This corresponds to the first embodiment.

As described above, according to the interrupt refresh method adopted in the first embodiment, if the interrupt refresh operation is performed for each regular refresh operation on the basis of the external input address when the active command is input, the probability is high. It can be controlled so that the RowHammer problem does not occur.
As described above, according to the first embodiment, it is possible to realize the DRAM device capable of coping with the RowHammer problem without providing a counter for each word line. Therefore, it is possible to provide a DRAM device which can utilize the area of the semiconductor chip more effectively and is excellent in area efficiency.

Modification of First Embodiment (1) In the first embodiment, interrupt refresh is performed on the basis of a normal (normal) refresh operation and an external input address at the time of an active command input during the refresh operation. ing. In particular, the example has been described in which the address when the "first" two active commands are input after the refresh operation is latched and used for the interrupt refresh operation. That is, in the first embodiment, the address latch circuit 20 latches the first two addresses and then stops.

However, the address latch circuit 20 may continue latching without stopping. With this configuration, the addresses of the two active commands immediately before the refresh operation is latched. Therefore, rather than the "first" two addresses, the address during the "last" active command during the period between its refresh operations may be latched and used as the basis for the address during an interrupt refresh.
That is, the address may be latched at any timing. It may be appropriately adjusted depending on the application of the DRAM device, the application of the computer in which the DRAM device is used, and the like.

(2) In the first embodiment, the address latch circuit 20 is configured to be able to latch two addresses (corresponding to a preferable example of n in the claims). However, the number of latches may be one. That is, n may be 1. Further, more addresses may be latchable. That is, it may be a natural number of n≧3. Similarly, in Embodiments 2 to 4 described later, an example in the case of n=2 is shown, but n=1 or n≧3 may be satisfied.
(3) In the first embodiment, the interrupt refresh operation is performed on one address for each regular refresh operation. However, the interrupt refresh operation is performed for two or more addresses for each regular refresh operation. The operation may be executed.
(4) Further, in the first embodiment, the address adjacent to the address when the active command is input is set as the target of the interrupt refresh operation as the address that may cause the RowHammer problem. However, the address may be a neighboring address instead of the adjacent address, and the interrupt refresh operation may be executed for the word lines of a plurality of neighboring addresses.

Second. Embodiment 2
In the first embodiment, the first two external input addresses are latched after the refresh command is input (issued). However, the address at any place (timing) may be latched. In the second embodiment, a DRAM device including a RowHammer countermeasure circuit capable of arbitrarily setting the timing of starting address latch will be described.

Configuration FIG. 3 is a circuit block diagram showing the RowHammer countermeasure circuit 30 of the DRAM device according to the second embodiment. The RowHammer countermeasure circuit 30 shown in FIG. 3 is a part of the configuration of the DRAM device. In FIG. 3, the part other than the memory 38 is the RowHammer countermeasure circuit 30. That is, the RowHammer countermeasure circuit 30 includes an Active monitor Start control circuit 31, an Active monitor circuit 32, a refresh control circuit 34, a memory access control circuit 36, address latch circuits 40 a and 40 b, and an address comparison circuit 42. Composed.
In FIG. 3, the configuration different from that of FIG. 1 described above is the Active monitor Start control circuit 31, and the other configuration is basically the same as that of FIG. 1 of the first embodiment, and basically performs the same operation. To do.

The Active monitor Start control circuit 31 according to the second embodiment monitors the external input command, and after the refresh command is input, for example, the third active command is detected, and then the Active monitor Enable signal is enabled (“1 )) to start the operation of the Active monitor circuit 32 and the address latch circuits 40a and 40b.
The Active monitor Start control circuit 31 corresponds to a preferred example of the monitor start unit in the claims. Further, the Active monitor Start control circuits 51 and 71 in the embodiments described later also correspond to a preferable example of the monitor start unit in the claims.
The Active monitor circuit 32 performs almost the same operation as the Active monitor circuit 12 of FIG. 1 of the first embodiment. Unlike the Active monitor circuit 12 of FIG. 1, the Active monitor circuit 32 of FIG. 3 monitors the external input command only when the Active monitor Enable signal is “1”, and detects whether or not the active command is input. ing.

Therefore, for example, when only one active command is input between the refresh commands REF and the refresh commands REF, the active monitor circuit 32 determines that the active command has not been input. This point is different from the first embodiment.

The address latch circuits 40a and 40b perform almost the same operations as the address latch circuits 20a and 20b of FIG. 1 of the first embodiment. Unlike the address latch circuits 20a and 20b of FIG. 1, the address latch circuits 40a and 40b of FIG. 3 latch the external input address only when the Active monitor Enable signal is "1".

Therefore, in the second embodiment, the address latch circuits 40a and 40b start latching between the refresh command REF and the refresh command REF from the external input address at the time of the third input active command. This point is different from the first embodiment. The other operations are the same as those of the address latch circuits 20a and 20b of the first embodiment, and the point that the number of addresses to be latched is two is the same as the address latch circuits 20a and 20b.

As described above, the characteristic of the second embodiment is that the position of the address for starting the latch can be arbitrarily designated.
The Active monitor Start control circuit 31 outputs the Active monitor Enable signal to the Active monitor circuit 32, and as described above, controls the timing at which the Active monitor circuit 32 monitors the external input command. Further, the Active monitor Start control circuit 31 outputs the same Active monitor Enable signal to the address latch circuits 40a and 40b, and controls the timing at which the address latch circuits 40a and 40b latch the external input address, as described above. There is.

In the above example, the timing from the third active command after the refresh command REF is input is set as the timing to be set by the Active monitor Start control circuit 31. However, other than the third, it may be the fourth or the fifth and can be arbitrarily set. The setting may be determined from the design stage of the DRAM device, or may be determined (programmed) at the test stage in the manufacturing process of the DRAM device, and may be controlled from the outside after the DRAM device is manufactured. The timing may be arbitrarily set by a signal.

It should be noted that such an operation can be generally expressed as starting the address latch after receiving m active commands. Here, m is a natural number.
Operation Hereinafter, the operation of the RowHammer countermeasure circuit 30 of the second embodiment described with reference to FIG. 3 will be described based on the time chart of FIG.
In the time chart of FIG. 4, a signal different from the time chart of FIG. 2 is an Active monitor Enable signal, and other signals are basically the same as those of the time chart of FIG. In FIG. 4, unlike FIG. 2, the address latch 1set is the address latch circuit 40a and the address latch 2set is the address latch circuit 40b.

In the time chart of FIG. 4, when the active command ACT is input, the memory access control circuit 16 outputs one pulse of the WL_Enable signal accordingly. Note that the precharge PRE is issued at a predetermined timing in the one pulse, as in FIG.

The time chart of FIG. 4 shows an example in which five active commands ACT are continuously input. External input addresses at that time are #000, #100, #200, #300, and #400 in order.
A feature of the second embodiment is that the Active monitor Enable signal is set to “0” until the first two active commands are input. This signal is a signal generated by the Active monitor Start control circuit 31 as described above and supplied to the Active monitor circuit 32 and the address latch circuits 40a and 40b. After detecting two active commands, the Active monitor Start control circuit 31 sets the Active monitor Enable signal to “1”, enables the monitoring function of the Active monitor circuit 32, and latches the address latch circuits 40a and 40b. To start.

As a result, the active monitor circuit 32 detects the active command from the third active command, and controls the refresh control circuit 34 to execute the interrupt refresh operation at the next regular refresh operation.
Further, the address latch circuits 40a and 40b latch #200 which is the external input address at the time of the third active command. Subsequently, the external input address #300 at the time of the fourth active command is latched.

As a result, as shown in FIG. 4, the address latch 1set (address latch circuit 40a) latches the address #200, and the address latch 2set (address latch circuit 40b) latches the address #300.
When the refresh command REF is input subsequently to the five active commands ACT, the refresh control circuit 34 instructs the memory access control circuit 36 to perform the refresh operation based on the refresh command REF.

Based on the refresh command REF and the instruction from the refresh control circuit 34, the memory access control circuit 36 executes the regular (normal) refresh operation three times, as in FIG.
Also in the second embodiment, the interrupt refresh operation is executed subsequent to the regular refresh operation performed three times. The interrupt refresh operation itself is the same as in the first embodiment. Also, the interrupt refresh operation is performed once. The address at that time is similar to that of the first embodiment in that the address latched in the address latch 1set and the address latch 2set are alternately used as a basis.

In the example of FIG. 4, the address #200 latched by the address latch 1set is used as a basis. The address that is actually the target of the interrupt refresh operation is the “nearby” address of address #200. In the second embodiment, for example, the value #201 obtained by inverting the least significant 1 bit of the address latched by the address latch circuit 20 is used as the neighboring address.

Other operations are the same as those in the first embodiment, and in the second embodiment as well, adjacent addresses (addresses with the least significant 1 bit inverted) are used as neighboring addresses.
In the time chart shown in FIG. 4, the Active monitor Start control circuit 31 controls the Active monitor Enable signal so that the external input command is monitored from the second active command after the normal refresh operation and the interrupt refresh operation are executed. Is set to "1" from the second active command. As a result, the address latch circuits 40a and 40b also start latching the external input address when the active command is input from the second active command. For example, the example shown in FIG. 4 shows an operation in which #222, which is the external input address at the time of the second active command after the refresh operation, is latched in the address latch 1set.

As described above, according to the second embodiment, the timing for starting command monitoring and the timing for latching addresses can be freely set, and thus the present invention can be applied to DRAM devices of various semiconductor processes, and the RowHammer problem It becomes easy to prevent the occurrence of.

Modification of First Embodiment (1) Various variations described in the modification of the first embodiment can be applied to the second embodiment. For example, the address latch circuits 40a and 40b may continuously perform the latch operation, and the number of addresses to be latched may be three or more. The interrupt refresh operation may be performed twice or more, and neighboring addresses may be spread to a plurality of word lines in which the RowHammer problem may occur.

(2) In the second embodiment, after the power is turned on, the Active monitor Start control circuit starts monitoring the external input command from the third active command, and starts the external input address from the third active command. Is starting to latch. Then, after the normal refresh operation is executed, monitoring of the external input command is started from the second active command, and latching of the external input address is started from the second active command.
As described above, it may be appropriate for the operation of the semiconductor to make the timing different immediately after the power is turned on and after the normal refresh operation is executed. Moreover, each timing can also be set arbitrarily. For example, the monitoring may be performed from the fourth active command immediately after the power is turned on, and the monitoring may be performed from the sixth active command after the regular refresh operation is executed.
However, the same timing may be applied immediately after the power is turned on and after the normal refresh operation is executed, depending on the semiconductor process and the circuit configuration. For example, it is also preferable to set such that the monitoring is started from the fourth active command.

(3) Furthermore, it is also preferable to set the above-mentioned timing to random timing. For example, processing such as latching the third address this time and latching the fifth address next time may be performed. Such random timing may be generated by a random number, or random timing may be generated using various time information such as the generation timing of the active command. Such an operation can also be expressed as starting the address latch after receiving the random number kth address. Alternatively, a random number may be generated based on the external input address, and the timing may be generated based on the random number. These timings may be generated by the Active monitor Start control circuit 31. Here, the random number k is a natural number.

Third. Embodiment 3
In the second embodiment, the address at an arbitrary location (timing) is latched. For example, after the two addresses are latched, the address is not newly latched. This is basically the same in the first embodiment.
However, it is known that in computer applications, accesses to the memory at the same address are often intensively executed. For example, the same variable is continuously rewritten.
When such continuous access to the same address is performed, it is considered that there is a high possibility that the RowHammer problem will occur. Therefore, unlike the second embodiment, if there are addresses that are continuously accessed even after the two addresses are once latched, the addresses that have been latched so far are continuously accessed. It is preferable to latch the address.

In this way, the third embodiment is provided with the RowHammer countermeasure circuit that can latch the address when there is an address that is continuously accessed and execute the interrupt refresh based on the address. A DRAM device will be described.

Configuration FIG. 5 is a circuit block diagram showing a RowHammer countermeasure circuit 50 of the DRAM device according to the third embodiment. The RowHammer countermeasure circuit 50 shown in FIG. 5 is a part of the configuration of the DRAM device. In FIG. 5, the part other than the memory 58 is the RowHammer countermeasure circuit 50. That is, the RowHammer countermeasure circuit 50 includes an Active monitor Start control circuit 51, an Active monitor circuit 52, a refresh control circuit 54, a memory access control circuit 56, address latch circuits 60a and 60b, an address comparison circuit 62, and a continuous circuit. It is composed of an access count circuit 64 and a continuous access upper limit determination circuit 66.
5, the configuration different from that of FIG. 3 of the second embodiment is mainly a continuous access count circuit 64 and a continuous access upper limit determination circuit 66. Other configurations are basically the same as those in FIG. 3 of the second embodiment, and basically perform the same operations as those in FIG. 3 and the like, except for the operation particularly described in the third embodiment.

The continuous access count circuit 64 in the third embodiment monitors the external input command and the external input address, and the external input address when the active command is input is the external input address when the previous active command is input. If it is the same as the input address, the number of times the same address is input is counted and the count value is supplied to the continuous access upper limit determination circuit 66.

Further, the continuous access upper limit determination circuit 66 in the third embodiment compares the count value of the continuous access count circuit 64 with a predetermined upper limit value u to check whether the continuous access exceeds the upper limit value u. If it exceeds, the continuous address access signal is set to "1" and output. Here, the upper limit value u is a natural number of 2 or more. This continuous address access signal is supplied to the address comparison circuit 62.
The continuous access upper limit determination circuit 66 corresponds to a preferred example of the upper limit determination unit in the claims. The continuous access upper limit determination circuit 86 in Embodiment 4 described later also corresponds to a preferable example of the upper limit determination unit in the claims.
The address comparison circuit 62 basically performs the same operation as the address comparison circuit 22 (or 42) in FIG. 1 (or FIG. 3). However, the address comparison circuit 62 of the third embodiment forcibly instructs the address latch circuits 60a and 60b to latch the external input address when the continuous address access signal becomes "1".

The address latch circuits 60a and 60b basically perform the same operation as the address latch circuits 20a and 20b (or 40a and 40b) in FIG. 1 (or FIG. 3), provided that the address latch circuit 60a of the third embodiment is the same. , 60b are forcibly instructed by the address comparison circuit 62 to latch the external input address, even if two addresses have already been latched, one of the addresses is discarded and a new external input is made. Latch the address.
As a result, the interrupt refresh operation can be executed for the addresses near the addresses that are continuously accessed, and it can be expected that the occurrence of the RowHammer problem can be prevented more effectively.

The Active monitor Start control circuit 51 shown in FIG. 5 is the same circuit as the Active monitor Start control circuit 31 shown in FIG. In the following, an example will be described in which the Active monitor Start control circuit 51 operates so as to be executed from the second active command.

Operation Hereinafter, the operation of the RowHammer countermeasure circuit 50 of the third embodiment described with reference to FIG. 5 will be described based on the time chart of FIG.
In the time chart of FIG. 6, signals different from the time chart of FIG. 4 are continuous address access signals, and other signals are basically the same as those of the time chart of FIG. In FIG. 6, unlike FIG. 4, the address latch 1set is the address latch circuit 60a and the address latch 2set is the address latch circuit 60b.

Further, the upper limit value u in the continuous access upper limit determination circuit 66 is 4, and the continuous address access signal is set to “1” when an active command relating to the same address is input four times consecutively.
First, in the time chart of FIG. 6, when the active command ACT is input, the memory access control circuit 16 outputs one pulse of the WL_Enable signal accordingly. Note that the precharge PRE is issued at a predetermined timing in the one pulse, as in FIG. In addition, in the time chart of FIG. 6, a total of eight active commands are input.

In addition, as described above, in the third embodiment, the Active monitor Start control circuit 51 sets the monitoring timing of the external input command from the second monitoring timing. Therefore, as shown in FIG. 6, the Active monitor Enable signal is set to a value of "1" from the second active command.

Therefore, the active command ACT is monitored by the Active monitor circuit 52 from the second active command ACT. Similarly, the latching of the external input address by the address latch circuits 60a and 60b is executed from the second active command ACT.

As a result, in the time chart of FIG. 6, the external input address #100 when the second active command ACT is input is latched in the address latch 1set (address latch circuit 60a). Similarly, #200, which is the external input address when the third active command ACT is input, is latched in the address latch 2set (address latch circuit 60b).

After that, five active commands ACT are input, and the external input address when the active commands ACT are input are all #300.
As described above, in the continuous access upper limit determination circuit 66 according to the third embodiment, when the number of active commands accompanied by the same address reaches the upper limit value u, the continuous access upper limit determination circuit 66 in the uth active command. Sets the continuous address access signal to "1" for one pulse.
As a result of the continuous address access signal being set to "1" for one pulse, the address comparison circuit 62 causes the address latch circuits 60a and 60b to latch the external input address based on this signal. As a result, in the third embodiment, the external latched address #300 continuously input to the address latch 1set is latched.

A feature of the third embodiment is that even after both the address latch 1set and the address latch 2set latch the external input address, four active commands ACT with the same external input address are consecutive (=u). When input, the same external input address is configured to be latched by the address latch 1set (or 2set). As a result, when the same address is continuously accessed, the interrupt refresh operation can be executed for the address (or the word line) based on that address, which effectively causes the occurrence of the RowHammer problem. Can be prevented.

In the time chart of FIG. 6, the refresh command REF is input after the active command ACT with the five #300 addresses is input. When this refresh command REF is input, the refresh control circuit 54 instructs the memory access control circuit 56 to perform a refresh operation based on this refresh command REF.

The memory access control circuit 56 executes the regular (normal) refresh operation three times based on the refresh command REF and the instruction from the refresh control circuit 54, as in FIG. 2 (or FIG. 4). Further, similarly to FIG. 2 (FIG. 4), the interrupt refresh operation is subsequently executed. The interrupt refresh operation itself is the same as in the first and second embodiments.

The characteristic feature of the third embodiment is that the target address in the interrupt refresh operation is #301 in which the least significant 1 bit of the address is inverted based on #300 latched in the address latch 1set. It is.
As in the first and second embodiments, the addresses latched in the address latches 2set and 1set are alternately used as a basis, so that in some cases, the address latch 2set is based on #200 which is latched. The interrupt refresh operation for the address #201 to be performed may be executed, and the interrupt refresh operation for #301 described above may be executed when the next regular fresh command REF is input. The operation other than the operation described above is the same as that of the second embodiment.

As described above, according to the third embodiment, when the external input addresses when the active command ACT is input are the same u consecutively, the interrupt based on the external input address is interrupted. A refresh operation is being performed. Therefore, the RowHammer countermeasure circuit 50 can more effectively prevent the occurrence of the RowHammer problem. Similarly, the DRAM device including the RowHammer countermeasure circuit 50 can more effectively prevent the occurrence of the RowHammer problem. Further, of course, as in the first embodiment and the like, it is not necessary to provide a counter for each word line, so that the area of the semiconductor chip can be used more efficiently, and compared with the DRAM device according to the conventional technique. Thus, the chip area of the DRAM device having the same capacity can be reduced.

Modification of Embodiment 3 (1) The various variations described in the modifications of Embodiments 1 and 2 can also be applied to Embodiment 2. For example, the address latch circuits 40a and 40b may continuously perform the latch operation, and the number of addresses to be latched may be three or more. The interrupt refresh operation may be performed twice or more, and neighboring addresses may be spread to a plurality of word lines in which the RowHammer problem may occur.
Further, similarly to the example shown in the second embodiment, the timing to start monitoring the external input command and the timing to latch the external input address can be set arbitrarily. Further, this timing can be made different immediately after the power is turned on and after the regular refresh operation is executed. Furthermore, it is possible to set these timings at random.

(2) In the third embodiment, the upper limit value u is a natural number of 2 or more. However, an appropriate number should be set as u according to the semiconductor process for manufacturing the DRAM device, the circuit configuration of the DRAM device, and the like. Is preferred. It is also preferable that the DRAM device is completed and u can be set from the outside.

Fourth. Embodiment 4
In the first to third embodiments, the interrupt refresh operation is performed on the address (adjacent address) in the vicinity based on the external input address when the active command ACT is input, and the occurrence of the RowHammer problem is efficiently performed. Can be prevented.

However, this interrupt refresh operation is performed independently of the normal refresh operation, and both refresh operations may be executed for the same address, but the same address is duplicated. Executing the refresh operation is useless, and may cause unnecessarily hindering the operation as a regular storage device.
That is, if the address at the time of executing the normal refresh operation is an address near the address latched in the address latch circuit, it is not necessary to perform the interrupt refresh operation.

In the fourth embodiment, when the address at the time of executing the normal refresh operation is in the vicinity of the address latched in the address latch circuit, the interrupt refresh operation is suppressed (stopped). A DRAM device that performs various operations will be described.

Configuration FIG. 7 is a circuit block diagram showing a RowHammer countermeasure circuit 70 of the DRAM device according to the fourth embodiment. The RowHammer countermeasure circuit 70 shown in FIG. 7 is a part of the configuration of the DRAM device. In FIG. 7, the part other than the memory 78 is the RowHammer countermeasure circuit 70. That is, the RowHammer countermeasure circuit 70 includes an Active monitor Start control circuit 71, an Active monitor circuit 72, a refresh control circuit 74, a memory access control circuit 76, address latch circuits 80a and 80b, an address comparison circuit 82, and a continuous circuit. The access count circuit 84 and the continuous access upper limit determination circuit 86 are included.
In FIG. 7, an operation different from that of FIG. 5 of the third embodiment is executed, and one of the characteristic configurations in the third embodiment is an address comparison circuit 82. The address comparison circuit 82 basically performs the same operation as the address comparison circuit 62 in the third embodiment, but the fourth embodiment is that the address comparison circuit 82 performs the comparison with the address when the normal refresh operation is performed. Is a characteristic point in.

Also in the fourth embodiment, the memory access control circuit 76 executes the normal refresh operation based on the external input command and the control signal from the refresh control circuit 74. This operation is the same as in the first to third embodiments. However, in the fourth embodiment, the memory access control circuit 76 outputs the address for executing the normal refresh operation to the outside as the normal refresh address. Then, the address comparison circuit 82 compares whether this normal refresh address is in the vicinity of the address latched by the address latch circuits 80a and 80b. If it is determined that the normal refresh address is near the address latched by the address latch circuits 80a and 80b as a result of this comparison, the contents of the address latch circuits 80a and 80b are skipped because the interrupt refresh operation is not executed. To reset. In this case, what is reset is the address where the normal refresh address is determined to be in the vicinity, and either one or both of the address latch circuits 80a and 80b.

If the normal refresh address is near both the addresses latched by the address latch circuits 80a and 80b, both the addresses latched by the address latch circuits 80a and 80b are reset, and as a result, the interrupt refresh operation is performed. Not executed

If the normal refresh address is in the vicinity of one of the addresses latched by the address latch circuits 80a and 80b, the address on the side of the address latch circuits 80a and 80b in the vicinity thereof is reset and As a result, the interrupt refresh operation is executed for the addresses in the vicinity based on the address that has not been reset.

As a result, it is possible to prevent the normal refresh operation and the interrupt refresh operation from being performed overlappingly on a nearby nearby address, thereby preventing unnecessary refresh operations from being performed. , RowHammer problem can be prevented more efficiently. As a result, it is possible to provide a DRAM device in which the performance of the DRAM device is not degraded more than necessary.

Operation Hereinafter, the operation of the RowHammer countermeasure circuit 70 of the fourth embodiment described with reference to FIG. 7 will be described based on the time chart of FIG.
In the operation in the time chart of FIG. 8, the address #100 is latched in the address latch 1set and the address #200 is latched in the address latch 2set, as in the time chart of FIG. 6 in the third embodiment. Since four active commands ACT based on the same address are continuously input, the address #300 is latched in the address latch 1set as in the third embodiment.
The address latch 1set is the address latch circuit 80a, and the address latch 2set is the address latch circuit 80b.

The time chart of FIG. 8 differs from the time chart of FIG. 6 in that the first address targeted for the normal refresh operation is #301.
Therefore, in the first cycle in which the normal refresh operation is executed in the time chart of FIG. 8, the address comparison circuit 82 causes the normal refresh address (that is, #301) to be near the address #300 latched in the address latch 1set. Judge that there is. Therefore, the address comparison circuit 82 resets the address latch 1set which is the basis of the determination that it is in the vicinity.

Also in the fourth embodiment, the interrupt refresh operation is executed subsequent to the normal refresh operation. At this time, the address that is the target of the interrupt refresh operation is obtained based on the address latch 1set (or 2set), as in the first to third embodiments. In the example of FIG. 8, since the address latch 1set is reset, the address related to the interrupt refresh operation is obtained based on the address latched in the address latch 2set. In the fourth embodiment as well, as before, #201 obtained by inverting the least significant 1 bit of the address #200 latched in the address latch 2set is obtained as the address to be the target of the interrupt refresh operation. As a result, as shown in FIG. 8, the interrupt refresh operation is executed for the address #201.

As described above, according to the fourth embodiment, it is determined whether or not the regular refresh address is near the address (latched) that is the basis of the interrupt refresh operation. The interrupt refresh operation for the address based on that address (neighboring address) is suppressed. As a result, it is possible to prevent the refresh operation from being performed on an address in the vicinity, so that it is possible to more efficiently prevent the occurrence of the RowHammer problem and to provide a DRAM device that does not unnecessarily reduce the performance. You can

Modification of Embodiment 4 (1) The various variations described in the modifications of Embodiments 1 to 3 can be applied to Embodiment 4.

(2) In the fourth embodiment, the address comparison circuit 82 determines whether the normal refresh address is near the address latched by the address latch circuit 80. The judgment of whether or not there is a neighborhood is a little different from the simple comparison of addresses. Therefore, the address comparison circuit 82 of the fourth embodiment may be provided as a configuration different from the address comparison circuits 22, 42 and 62 of the first to third embodiments described above.
The “neighborhood” address is an address that represents a word line affected by the occurrence of the RowHammer problem, and may be one or more. Particularly, in this embodiment, the address of the word line adjacent to the word line accessed by the active command is described as a preferable example. Further, as an example of an address of an adjacent word, an address obtained by adding +1 or -1 to a base address is a preferable example. For example, it is also preferable to use an address obtained by inverting the least significant bit of the base address.

(3) In the fourth embodiment, the memory access control circuit 76 outputs the regular refresh address. This is because the memory access control circuit 76 holds a refresh address counter. However, the normal refresh address may be output by another circuit and supplied to the memory access control circuit 76.
For example, the refresh control circuit 74 may include a refresh counter or the like in order to manage the regular refresh address. In this case, the refresh control circuit 74 supplies a normal refresh address to the address comparison circuit 82.

4. Summary Although the embodiments of the present invention have been described in detail above, the above-described embodiments merely show specific examples for carrying out the present invention. The technical scope of the present invention is not limited to the above embodiment. The present invention can be variously modified without departing from the spirit thereof, and these are also included in the technical scope of the present invention.

10, 30, 50, 70 Row Hammer countermeasure circuit 12, 32, 52, 72 Active monitor circuit 14, 34, 54, 74 Refresh control circuit 16, 36, 56, 76 Memory access control circuit 18, 38, 58, 78 Memory 20a , 20b, 40a, 40b, 60a, 60b, 80a, 80b Address latch circuit 22, 42, 62, 82 Address comparison circuit 31, 51, 71 Active monitor Start control circuit 64, 84 Continuous access count circuit 66, 86 Continuous access upper limit Judgment circuit

Claims (13)

A memory unit having a plurality of memory cells,
An address latch unit that receives an address and an active command applied to the memory cell specified by the address, and continues to latch the address when the active command is received each time the active command is received. ,
When the refresh command is received, the memory access control unit is instructed to execute the normal refresh operation based on the refresh command to the memory unit, and the refresh operation based on the address latched by the address latch unit is performed. A refresh control unit for instructing the memory access control unit to perform an interrupt refresh operation on an address near the address;
A memory access control unit that executes the regular refresh operation and the interrupt refresh operation to the memory unit based on an instruction from the refresh control unit;
Including a semiconductor memory device. A memory unit having a plurality of memory cells,
An address and an active command applied to the memory cell specified by the address are received, the address at the time of receiving the active command is latched every time the active command is received, and the latched address is An address latch unit that holds n pieces,
When the refresh command is received, the memory access control unit is instructed to execute the normal refresh operation based on the refresh command to the memory unit, and the address latch unit latches the one or more addresses. A refresh control unit for instructing the memory access control unit to perform an interrupt refresh operation on an address in the vicinity of the address,
A memory access control unit that executes the regular refresh operation and the interrupt refresh operation to the memory unit based on an instruction from the refresh control unit;
Including
A semiconductor memory device in which the address latch unit is reset when the memory access control unit executes the interrupt refresh operation and is set to a state in which an address can be latched when an active command is received next time. Here, the n is a natural number. The semiconductor memory device according to claim 2,
When the memory access control unit executes the interrupt refresh operation, the address latch unit resets only the address that is the basis of the interrupt refresh operation, and can latch the address when the next active command is received. Storage device that is brought into a stable state. The semiconductor memory device according to claim 2,
The refresh control unit performs a refresh operation based on any one of the addresses latched by the address latch unit, and performs an interrupt refresh operation only on an address near the one address. To the memory access control unit,
When the refresh control unit executes the interrupt refresh operation, the address latch unit resets only the one address that is the basis of the interrupt refresh operation and then receives the active command. A semiconductor memory device in which a latch is enabled. The semiconductor memory device according to any one of claims 2 to 4,
A monitor start unit that starts the latch operation of the address latch unit after receiving the m active commands after receiving the refresh command,
Including a semiconductor memory device. Here, the m is a natural number. The semiconductor memory device according to claim 5,
The monitor start unit is
A semiconductor memory device which, after receiving the refresh command, receives k random number of the active commands, and then starts the latch operation of the address latch unit. Here, k is a random natural number. The semiconductor memory device according to claim 2, wherein
An access count address latch that receives an address and an active command applied to the memory cell specified by the address, monitors the address when the active command is received, and counts the number of accesses to the same address. Department,
An upper limit determination unit that causes the address latch unit to latch the same address when the number of accesses to the same address counted by the access count address latch unit exceeds a predetermined value,
Including a semiconductor memory device. The semiconductor memory device according to claim 1, wherein
The address at the time of receiving the active command is compared with the address already latched by the address latch unit, and if the result of the comparison is that the addresses are different, the address that causes the address latch unit to perform the latch operation. Comparison section,
Including a semiconductor memory device. The semiconductor memory device according to claim 2, wherein:
The address latch unit compares less than n addresses already latched with the address at the time of receiving the active command, and only when the addresses are different as a result of comparison, a new address is added to the address latch unit. An address comparison unit that executes an address latch operation when the active command is received,
Including a semiconductor memory device. The semiconductor memory device according to claim 8 or 9,
The address comparison unit latches the address when the refresh control unit instructs the memory access control unit to perform a normal refresh operation when a refresh address is near the address latched by the address latch unit. A semiconductor memory device that resets the address latched by a unit. The semiconductor memory device according to claim 1, wherein
A monitor unit that monitors the active command to be received and suppresses the refresh control unit from instructing the memory access control unit to perform the interrupt refresh operation when the active command is not received after receiving the refresh command. ,
A semiconductor memory device further comprising: The semiconductor memory device according to claim 1, wherein
The address near the address when the active command is received is a semiconductor memory device that is either an address obtained by adding +1 or an address obtained by adding -1 to the address when the active command is received. The semiconductor memory device according to any one of claims 1 to 12,
The semiconductor memory device, wherein the active command is a command for activating a word line of the memory unit and includes at least a read command, a write command, and a refresh command.

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