JP2001093278A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which power consumption by refresh can be reduced. SOLUTION: In a semiconductor memory provided with a means receiving information specifying a region to be refreshed from the outside, power consumption by refreshment can be reduced comparing power consumption with case when refreshment is performed in all regions by performing refreshment only for a specified specific address or region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device with low power consumption, and more particularly to a semiconductor memory device that refreshes only a specified specific area.

[0002]

2. Description of the Related Art In recent years, mobile information devices have rapidly spread. It is important for these mobile information devices to reduce power consumption. Especially for mobile phones, etc., not only during operation,
It is necessary to reduce power consumption during standby.

[0003] In these portable information devices, a DRAM (Dynamic Random Access Memory) which is inexpensive and has a large capacity is used in many information processing apparatuses. In a DRAM, it is necessary to periodically perform a refresh operation in order to hold stored data.

FIG. 7 shows a configuration diagram of a conventional DRAM. Generally, refresh includes auto refresh and self refresh. First, the auto refresh will be described. In the auto-refresh, it is necessary to externally determine the timing at which the refresh is to be performed, and to instruct the refresh from the outside at regular intervals. This refresh instruction is performed by transmitting a combination of control signals to the command decoder 103. When an auto-refresh is instructed, an address of the cell array 109 indicated by the refresh counter 101 is generated, a signal for a refresh operation is output from the control signal generator 107, and is held in the address buffer 105. On the other hand, when the refresh operation is completed, the refresh counter 101 is incremented. The normal data input / output operation is performed by the data control circuit 111.
Done by

The same operation is performed in the case of self refresh. In the self-refresh, if a self-refresh instruction is first issued, the internal refresh is automatically performed periodically. Also in this case, the refresh is performed on the refresh area indicated by the refresh counter 101 at the same time as the auto refresh, and the refresh counter 101 is incremented after completion.

FIG. 8 is a state transition diagram of such a conventional DRAM control signal generator. The control signal generator generates a predetermined timing in accordance with a given read or write request. When a refresh instruction is issued, a refresh operation is performed (specifically, a word is read and written again). At this time, the value of the refresh counter is used as the word address. When the refresh is completed, a refresh counter update instruction is issued, and the process returns to the initial state.

[0007]

In both the auto refresh and the self refresh, as the refresh counter 101 is updated, the refresh is performed on the entire DRAM area. Even when the portable information device is on standby, refreshing is required to retain data on the DRAM, which increases power consumption. However, for example, when a program and data are stored in a DRAM and only the program is to be held during standby, all data is lost in the conventional DRAM unless the entire DRAM is refreshed.
The entire RAM was refreshed. As a result, power consumption during standby has increased.

An object of the present invention is to provide means for allowing a user to specify an area to be refreshed in a DRAM, and to enable refreshing only a necessary area.

That is, in order to achieve the above object, a semiconductor memory device according to the present invention has means for externally receiving information for specifying an area to be refreshed, and refreshes only the refresh area. And

According to another aspect of the semiconductor memory device of the present invention, a means for externally inputting a timing for refreshing, a means for externally inputting a region to be refreshed, and a region for refreshing are sequentially shown. A refresh counter, means for comparing the value of the refresh counter with the external refresh area and a value of the refresh counter, and determining whether or not to perform refreshing; and means for controlling refreshing in accordance with the determining means for determining whether or not to perform refreshing. And characterized in that:

In a preferred embodiment, a plurality of areas can be designated as areas to be refreshed.

Further, according to another aspect of the semiconductor memory device of the present invention, there is provided means for externally designating an area which does not need to be refreshed, and means for excluding the area which does not need to be refreshed externally specified. Is refreshed.

Further, according to another aspect of the semiconductor memory device of the present invention, a means for externally inputting a timing for refreshing, a means for externally inputting a region which does not need to be refreshed, and a method for sequentially setting a region to be refreshed. Means for comparing a refresh counter, which is to be shown, with the area of the external counter that does not need to be refreshed, and the value of the refresh counter to determine whether or not to perform refreshing; and determining whether or not to perform refreshing. Means for controlling refresh according to the means.

In a preferred embodiment, the semiconductor device according to the fifth aspect is characterized in that a plurality of areas can be designated as areas which do not need to be refreshed.

Further, according to another aspect of the semiconductor memory device of the present invention, a cell array composed of a plurality of blocks for retaining data, a refresh execution unit for refreshing the cell array, and an address of the block for refreshing are stored. Means for inputting data to the cell array; means for holding information for dividing the block of the cell array into areas to be refreshed and areas not to be refreshed; and referring to the information held in the holding means, Means for controlling the refresh execution means so as to refresh the block in an area to be refreshed and not to refresh the block in an area not to be refreshed.

In a preferred embodiment, the apparatus further comprises a refresh counter for sequentially updating an address of the block of the cell array, and the control means controls the refresh when the address of the refresh counter indicates an area to be refreshed. The refreshing is performed by controlling the execution means.

Further, in a preferred embodiment, the semiconductor memory device is a DRAM.

Therefore, according to the present invention, the DRAM is refreshed only for a specified specific address or area. Power consumption by refresh can be reduced as compared with the case where refresh is performed on all areas. This is effective when the program and data are stored on the DRAM, and when only the program area is refreshed in the sleep mode. Particularly, in image processing and the like, a frame buffer is secured on the DRAM, but data in this area may be lost during sleep. However, it is effective in such a case because you want to secure the program.

[0018]

FIG. 1 is a state transition diagram of a control signal generator of a DRAM according to the present invention. The control signal generator generates a predetermined timing in accordance with a given read or write request. However, here, the refresh operation is performed only when the given read or write request is included in the predetermined refresh range. When the refresh is completed, a refresh counter update instruction is issued, and the process returns to the initial state. When the given read or write request is not included in the predetermined refresh range, only the refresh counter is immediately updated without performing the refresh operation.

FIG. 2 shows a first embodiment of the present invention. The semiconductor memory device of the present invention has a DR
AM. The DRAM 1 receives a control signal including a command signal CKEi = 1 (i = 0 to n) from the outside, and receives a command decoder 3 for interpreting the command, a control signal generator 5 for generating a control signal, and an address buffer for holding an address. 7, a data control circuit 9 for controlling data input / output, a cell array 11 including a plurality of blocks for holding data, a refresh counter 13 for holding a cell block number to be refreshed, and a refresh range determination circuit for determining whether or not to refresh. 15 is comprised. An access operation to the DRAM 1 other than the refresh operation is performed by a normal DRAM.
The operation is the same as in the first operation. That is, chip select, R
An address is externally transferred together with control signals such as AS, CAS, and WE, and data is read / written from / to a predetermined cell. Data is transferred via the data control circuit 9.

Next, the refresh operation will be described. Refreshing is performed by dividing the cell array 11 into several blocks and sequentially performing each block. For example, each row is one block. Generally, refresh includes auto refresh and self refresh. First, the auto refresh will be described.

In the auto-refresh, it is necessary to externally determine the timing at which the refresh is performed, and to instruct the refresh from the outside at regular intervals. This refresh instruction is given by a combination of control signals. For example,
CKEn-1 = 1, CKEn = 1, CS = 0, RAS =
It is assumed that the auto refresh mode is set when 0, CAS = 0, and WE = 1. When the auto refresh is instructed, an address of the cell array 11 block indicated by the refresh counter 13 is generated, and a signal for the refresh operation is generated from the control signal generator 5.

At this time, the address of the refresh range specified from the outside is compared with the value of the refresh counter 13. If the refresh area indicated by the refresh counter 13 is within the refresh range specified from the outside, the refresh operation is performed. Will be If not, no refresh is performed. When a series of operations is completed regardless of whether refresh is performed or not, the refresh counter 13 is incremented.

The address of the refresh range is given from outside via a normal data terminal. That is, when the refresh range start address is given to the data terminal, a combination of the command signals CKEi indicating the start address is given to the command decoder 3. Similarly, when the refresh range end address is given to the data terminal, the combination of the control signal CKEi indicating the end is given by
It is provided to the command decoder 3. Then, those addresses are held in registers in the refresh range determination circuit 15.

FIG. 3 shows a refresh range judging circuit 15.
3 is a diagram showing an internal configuration of FIG. The refresh range determination circuit 15 includes two comparators 21 and 23, and AND
The circuit 25 includes a register 27 for latching a refresh range start address and a register 29 for latching a refresh range end address. Comparator 21
One input receives the refresh range start address, and the other input receives the value of the refresh counter 13, that is, the refresh address. When the refresh address is larger than the refresh range start address, "1" is output; otherwise, "0" is output. On the other hand, the comparator 23 receives a refresh range end address at one input and a refresh address at the other input. When the refresh address is smaller than the refresh range end address,
1 is output, otherwise it outputs 0. Therefore, if the logical sum of the outputs of these two comparators 21 and 23 is calculated by the AND circuit 25, it is determined whether the refresh address is within the refresh range. Can be determined.

The same operation is performed in the case of self refresh. In self-refresh, if a self-refresh instruction is issued first (for example, CKEn-1 =
1, CKEn = 0, CS = 0, RAS = 0, CAS =
0, WE = 1), and refresh is automatically performed internally periodically. In this case as well, like auto refresh,
The refresh area indicated by the refresh counter 13 is
If it is within the refresh range specified from the outside,
A refresh is performed, otherwise no refresh is performed. Thereafter, the refresh counter 13 is incremented.

FIG. 4 shows a second embodiment of the present invention. The difference from the first embodiment is that a plurality of areas can be designated as a refresh range designated from the outside.

Also, the address of the refresh range is
Provided from outside via a normal data terminal. That is,
When the refresh range A start address is given to the data terminal, a combination of the control signals CKEi indicating the start address is given to the command decoder 3, and when the refresh range A end address is given to the data terminal. , And a control signal CKEi indicating the combination is supplied to the command decoder 3. Similarly, when the refresh range B head address is given to the external data terminal, a combination of control signals CKEi indicating the same is given to the command decoder 3, and the refresh range B end address is given to the data terminal. In this case, a combination of control signals CKEi indicating the combination is supplied to the command decoder 3.

At this time, the refresh range determination circuit 15b
Compares the address of the two refresh ranges specified from the outside with the value of the refresh counter 13. If the refresh area indicated by the refresh counter 13 falls within any of the refresh ranges specified from the outside, the refresh is performed. Is performed. If not, refresh is not performed. When a series of operations is completed regardless of whether refresh is performed or not, the refresh counter 13 is incremented.

FIG. 5 shows a third embodiment of the present invention.
The difference from the first embodiment is that a range that is not refreshed from outside is specified. When the value of the refresh counter 13 is within the range that is not refreshed specified from the outside, the refresh range determination circuit 15c outputs a control signal to the control signal generator 5 so as not to perform refresh.

The range that is not refreshed from the outside is given as a non-refresh range start address and a non-refresh range end address through an external data terminal in the same manner as in the above embodiment.

FIG. 6 shows a fourth embodiment of the present invention.
The difference from the second embodiment is that a range that is not refreshed from outside is specified. If the value of the refresh counter 13 falls within the two ranges that are not refreshed externally, the refresh range determination circuit 15d outputs a control signal to the control signal generator 5 so as not to perform refresh.

The refresh range determination circuit 15d compares the addresses of the two refresh ranges specified from the outside with the value of the refresh counter 13, and determines whether the refresh area indicated by the refresh counter 13 is any of the refresh ranges specified from the outside. If not,
Refresh is performed. If it is, no refresh is performed. When a series of operations is completed regardless of whether refresh is performed or not, the refresh counter 13 is incremented.

Although the present invention has been described in detail with reference to the embodiments, it is obvious to those skilled in the art that the present invention is not limited to the embodiments described in the present application. The device of the present invention can be embodied as modifications and alterations without departing from the spirit and scope of the present invention defined by the claims. Therefore, the description of the present application is intended for illustrative purposes, and has no restrictive meaning to the present invention.

For example, in the above example, the address that determines the refresh range is given from outside through a normal data terminal, but is not limited to this. For example, another terminal may be used, or a dedicated terminal may be provided. Depending on the application, it is also effective to fix the address information for determining the refresh range fixedly as hardware in the DRAM.

[0035]

As described above, the refresh operation is performed only on the minimum necessary area and the refresh operation is not performed on the unnecessary area, so that the power consumption by the refresh can be reduced.

[Brief description of the drawings]

FIG. 1 is a state transition diagram of a control signal generator of a DRAM of the present invention.

FIG. 2 is a configuration diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an internal configuration of a refresh range determination circuit.

FIG. 4 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional semiconductor memory device.

FIG. 8 is a state transition diagram of a control signal generator of a conventional DRAM.

[Explanation of symbols]

Reference Signs List 1 DRAM 3 Command decoder 5 Control signal generator 7 Address buffer 9 Data control circuit 11 Cell array 13 Refresh counter 15, 15b, 15c, 15d Refresh range determination circuit 21, 23 Comparator 25 AND circuit 27, 29 Register

Claims (9)

[Claims] 1. A semiconductor memory device requiring refresh, comprising means for externally receiving information for specifying an area to be refreshed, and refreshing only the refresh area. 2. A semiconductor memory device requiring refresh, a means for externally inputting a timing for refreshing, a means for externally inputting a region to be refreshed, a refresh counter for sequentially indicating a region to be refreshed, Means for comparing a refresh area from the outside with a value of a refresh counter to determine whether or not to perform refreshing; and means for controlling refreshing according to the determining means for performing or not performing the refreshing. A semiconductor memory device characterized by the above-mentioned. 3. The semiconductor memory device according to claim 2, wherein a plurality of areas can be designated as the area to be refreshed. 4. A semiconductor memory device requiring refreshing, comprising means for externally specifying an area that does not need to be refreshed, and refreshing an area other than the area that does not need to be externally specified and not refreshing. A semiconductor memory device characterized by the following. 5. A semiconductor memory device requiring refresh, a means for externally inputting a timing for refreshing, a means for externally inputting a region which does not need to be refreshed, and a refresh counter for sequentially indicating a region to be refreshed. Means for comparing the area which does not need to be refreshed from the outside with the value of a refresh counter to determine whether or not to perform refreshing; A semiconductor memory device comprising: 6. The semiconductor memory device according to claim 5, wherein a plurality of areas can be designated as areas that do not need to be refreshed. 7. A cell array including a plurality of blocks for holding data, a refresh execution unit for refreshing the cell array, a unit for inputting an address of the block to be refreshed to the cell array, and the block of the cell array. Means for holding information for classifying an area to be refreshed and an area not to be refreshed; and referring to the information held in the holding means, refreshing the block in the area to be refreshed, Means for controlling the refresh execution means so as not to refresh the block in an area not to be refreshed. 8. The semiconductor memory device according to claim 7, further comprising a refresh counter for sequentially updating an address of said block of said cell array, wherein said control means indicates an area where the address of said refresh counter is to be refreshed. A semiconductor memory device that controls the refresh execution means to perform a refresh when the device is in operation. 9. The semiconductor memory device according to claim 7, wherein said semiconductor memory device is a DRAM.