JP2020113759A - Processing method and plasma processing device - Google Patents

Abstract

To remove a deposit on an outer peripheral member while suppressing the wear of the outer peripheral member.SOLUTION: A processing method for processing a workpiece by a plasma processing device having a work-holder table to put the workpiece on in a chamber, an outer peripheral member disposed around the work-holder table, and a first power source for applying a voltage to the outer peripheral member is provided. The processing method comprises the steps of: exposing a workpiece to plasma including a depositable precursor while applying a voltage to the outer peripheral member by the first power source; and observing the state of a deposit film including carbon deposited on the outer peripheral member during the process of exposure to the plasma, and controlling the voltage to be applied to the outer peripheral member on the state of the deposit film.SELECTED DRAWING: Figure 6

Description

The present disclosure relates to a processing method and a plasma processing apparatus.

There is a step of depositing a by-product generated by plasma processing on a wafer to form a deposited film. For example, in Patent Document 1, a step of etching a region made of silicon oxide and forming a deposit containing fluorocarbon on the region, and a step of etching the region with radicals of fluorocarbon contained in the deposit We propose a technology that repeats and. The deposit (hereinafter, also referred to as “by-product”) is deposited on the wafer and also on the outer peripheral member (hereinafter, also referred to as “edge ring”) provided around the wafer.

JP, 2015-173240, A

The present disclosure provides a technique capable of removing deposits on an outer peripheral member while suppressing wear of the outer peripheral member.

According to one aspect of the present disclosure, a mounting table on which the object to be processed is mounted in the chamber, an outer peripheral member arranged around the mounting table, and a first power source for applying a voltage to the outer peripheral member. And a plasma treatment apparatus for treating an object to be treated, wherein the object is treated with a plasma having a deposition precursor while applying a voltage from the first power source to the outer peripheral member. During the exposing step and the plasma exposing step, the state of the deposited film containing carbon deposited on the outer peripheral member is observed, and the voltage applied to the outer peripheral member is controlled based on the observed state of the deposited film. And a treatment method comprising:

According to one aspect, it is possible to remove the deposit on the outer peripheral member while suppressing the consumption of the outer peripheral member.

FIG. 3 is a schematic sectional view showing an example of a plasma processing apparatus according to one embodiment. FIG. 6 is a diagram for explaining a deposition process and a sputtering process. The figure which shows an example of the monitoring method of the accumulation state of an edge ring. The figure which shows an example of the correlation of the monitor value and the accumulation state of an edge ring which concern on one Embodiment. 6 is a flowchart showing an example of voltage application control processing according to an embodiment. FIG. 6 is a diagram showing an example of an effect of voltage application control according to an embodiment. The figure which shows an example of the etching rate when a voltage is applied to an edge ring. The figure which shows an example of the etching rate when a voltage is applied to an edge ring. The figure which shows an example of the process result of the processing method which concerns on one Embodiment. The flowchart which shows an example of the processing method which concerns on one Embodiment. 6 is a flowchart showing an example of a correction process according to an embodiment.

Hereinafter, modes for carrying out the present disclosure will be described with reference to the drawings. In each drawing, the same components may be denoted by the same reference numerals and redundant description may be omitted.

[Plasma processing equipment]
A plasma processing apparatus 1 according to an embodiment will be described with reference to FIG. FIG. 1 is a schematic sectional view showing an example of a plasma processing apparatus 1 according to an embodiment. A plasma processing apparatus 1 according to an embodiment is a capacitively coupled parallel plate processing apparatus and has a chamber 10. The chamber 10 is, for example, a cylindrical container made of aluminum whose surface is anodized, and is grounded.

At the bottom of the chamber 10, a columnar support 14 is arranged via an insulating plate 12 made of ceramics or the like, and a mounting table 16, for example, is provided on the support 14. The mounting table 16 has an electrostatic chuck 20 and a base 16 a, and mounts the wafer W on the upper surface of the electrostatic chuck 20. An annular edge ring 24 made of, for example, silicon is arranged around the wafer W. The edge ring 24 is also called a focus ring. The edge ring 24 is an example of an outer peripheral member arranged around the mounting table 16. An annular insulator ring 26 made of, for example, quartz is provided around the base 16a and the support 14. Inside the center side of the electrostatic chuck 20, the first electrode 20a made of a conductive film is sandwiched between the insulating layers 20b. The first electrode 20a is connected to the power supply 22. An electrostatic force is generated by the DC voltage applied from the power source 22 to the first electrode 20a, and the wafer W is attracted to the wafer mounting surface of the electrostatic chuck 20. The electrostatic chuck 20 may have a heater to control the temperature.

Inside the support base 14, for example, a ring-shaped or spiral refrigerant chamber 28 is formed. A coolant having a predetermined temperature, for example, cooling water supplied from a chiller unit (not shown) is returned to the chiller unit through the pipe 30a, the coolant chamber 28, and the pipe 30b. By circulating the coolant in such a path, the temperature of the wafer W can be controlled by the temperature of the coolant. Further, the heat transfer gas supplied from the heat transfer gas supply mechanism, for example, He gas, is supplied through the gas supply line 32 to the gap between the front surface of the electrostatic chuck 20 and the back surface of the wafer W. The heat transfer gas lowers the heat transfer coefficient between the front surface of the electrostatic chuck 20 and the back surface of the wafer W, and the temperature of the wafer W is more effectively controlled by the temperature of the coolant. When the electrostatic chuck 20 has a heater, the temperature of the wafer W can be controlled with high responsiveness and high accuracy by heating with the heater and cooling with the coolant.

The upper electrode 34 is provided on the ceiling of the chamber 10 so as to face the mounting table 16. A plasma processing space is formed between the upper electrode 34 and the mounting table 16. The upper electrode 34 closes the opening of the ceiling of the chamber 10 via the insulating shield member 42. The upper electrode 34 has an electrode plate 36 and an electrode support 38. The electrode plate 36 has a large number of gas discharge holes 37 formed on the surface facing the mounting table 16, and is made of a silicon-containing material such as silicon or SiC. The electrode support 38 detachably supports the electrode plate 36, and is made of a conductive material, for example, aluminum whose surface is anodized. Inside the electrode support 38, a large number of gas flow holes 41a and 41b extend downward from the gas diffusion chambers 40a and 40b and communicate with the gas discharge hole 37.

The gas inlet 62 is connected to a processing gas supply source 66 via a gas supply pipe 64. The gas supply pipe 64 is provided with a mass flow controller (MFC) 68 and an opening/closing valve 70 in order from the upstream side where the processing gas supply source 66 is arranged. The processing gas is supplied from the processing gas supply source 66, the flow rate and opening/closing of which are controlled by the mass flow controller 68 and the opening/closing valve 70. It is discharged like a shower from the through gas discharge hole 37.

The plasma processing apparatus 1 has a first high frequency power supply 90 and a second high frequency power supply 48. The first high frequency power source 90 is a power source that generates a first high frequency power (hereinafter, also referred to as “HF power”). The first high frequency power has a frequency suitable for plasma generation. The frequency of the first high frequency power is, for example, a frequency within the range of 27 MHz to 100 MHz. The first high frequency power supply 90 is connected to the base 16a via a matching unit 88 and a power supply line 89. The matching device 88 has a circuit for matching the output impedance of the first high-frequency power supply 90 and the load-side (base 16a side) impedance. The first high frequency power supply 90 may be connected to the upper electrode 34 via the matching unit 88.

The second high frequency power supply 48 is a power supply that generates a second high frequency power (hereinafter, also referred to as “LF power”). The second high frequency power has a frequency lower than the frequency of the first high frequency power. When the second high frequency power is used together with the first high frequency power, the second high frequency power is used as the bias high frequency power for attracting ions to the wafer W. The frequency of the second high frequency power is, for example, a frequency within the range of 400 kHz to 13.56 MHz. The second high frequency power supply 48 is connected to the base 16a via a matching unit 46 and a power supply line 47. The matching unit 46 has a circuit for matching the output impedance of the second high-frequency power supply 48 and the load side (base 16a side) impedance.

The plasma may be generated using the second high frequency power, that is, using only the single high frequency power, without using the first high frequency power. In this case, the frequency of the second high frequency power may be a frequency higher than 13.56 MHz, for example 40 MHz. The plasma processing apparatus 1 may not include the first high frequency power supply 90 and the matching device 88. With this configuration, the mounting table 16 also functions as a lower electrode. The upper electrode 34 also functions as a shower head that supplies gas.

The second variable power source 50 is connected to the upper electrode 34 and applies a DC voltage to the upper electrode 34. The first variable power supply 55 is connected to the edge ring 24 and applies a DC voltage to the edge ring 24. The first variable power source 55 is an example of a first power source that applies a voltage to the outer peripheral member. The second variable power source 50 is an example of a second power source that applies a voltage to the upper electrode 34.

The exhaust device 84 is connected to the exhaust pipe 82. The exhaust device 84 has a vacuum pump such as a turbo molecular pump, and exhausts air from an exhaust port 80 formed at the bottom of the chamber 10 through an exhaust pipe 82 to reduce the pressure in the chamber 10 to a desired degree of vacuum. Further, the exhaust device 84 controls the pressure inside the chamber 10 to be constant while using the value of a pressure gauge that measures the pressure inside the chamber 10 (not shown). The carry-in/out port 85 is provided on the side wall of the chamber 10. The wafer W is loaded and unloaded through the loading/unloading port 85 by opening/closing the gate valve 86.

The baffle plate 83 is provided annularly between the insulator ring 26 and the side wall of the chamber 10. The baffle plate 83 has a plurality of through holes, is made of aluminum, and its surface is covered with ceramics such as Y ₂ O ₃ .

When performing a predetermined plasma processing such as plasma etching processing in the plasma processing apparatus 1 having such a configuration, the gate valve 86 is opened, the wafer W is loaded into the chamber 10 through the loading/unloading port 85, and the wafer W is placed on the mounting table 16. Then, the gate valve 86 is closed. The processing gas is supplied to the inside of the chamber 10, and the inside of the chamber 10 is exhausted by the exhaust device 84.

The first high frequency power and the second high frequency power are applied to the mounting table 16. A DC voltage is applied from the power supply 22 to the first electrode 20a, and the wafer W is attracted to the mounting table 16. The DC voltage may be applied to the upper electrode 34 from the second variable power source 50.

Plasma processing such as etching is performed on the surface to be processed of the wafer W by radicals and ions in the plasma generated in the plasma processing space.

The plasma processing apparatus 1 is provided with a control unit 200 that controls the operation of the entire apparatus. The CPU provided in the control unit 200 executes a desired plasma processing such as etching according to a recipe stored in a memory such as a ROM and a RAM. In the recipe, process time, pressure (gas exhaust), first high-frequency power and second high-frequency power and voltage, and various gas flow rates, which are device control information for process conditions, may be set. Further, the temperature in the chamber (upper electrode temperature, chamber side wall temperature, wafer W temperature, electrostatic chuck temperature, etc.), the temperature of the coolant output from the chiller, etc. may be set in the recipe. The programs and the recipes indicating the processing conditions may be stored in the hard disk or the semiconductor memory. Alternatively, the recipe may be set at a predetermined position and read while being stored in a portable computer-readable storage medium such as a CD-ROM or a DVD.

[Deposition process and sputtering process]
In recent years, for example, in the ALE (Atomic Layer Etching) technique in which deposition etching and non-deposition etching are repeated a predetermined number of times, the control of the deposition amount has become important. In particular, in cryogenic etching in which the temperature of the mounting table 16 is controlled to, for example, about −several tens of degrees Celsius to −hundreds of several tens of degrees Celsius, the amount of by-products deposited by etching increases. Therefore, in the cryogenic etching, it is more important to control the amount of by-products deposited on the wafer.

Hereinafter, a step of depositing a by-product by an etching process and a step of sputtering while depositing the by-product will be described with reference to FIG. FIG. 2 is a diagram for explaining the deposition process and the sputtering process.

For example, there is a deposition step of etching a region formed of silicon oxide on the wafer W and forming a deposit containing carbon on the region. In this deposition step, the processing gas supply source 66 supplies a processing gas such as a fluorocarbon gas containing carbon such as C ₄ F ₈ or a hydrocarbon gas such as CH ₄ . The processing gas may be a hydrofluorocarbon gas such as CH ₂ F ₂ . The processing gas may include an inert gas. In the following, it is assumed that argon gas is contained as the inert gas.

The processing gas becomes plasma by the first high frequency power and the second high frequency power. As shown in FIG. 2, the plasma contains radicals 102 such as CHx radicals (CHx ^* ) and CyFz radicals (CyFz ^* ), and argon ions (Ar ⁺ ) 101, for example.

Here, FIG. 2A shows a case where no DC voltage is applied to the edge ring 24, and FIG. 2B shows a case where a DC voltage is applied to the edge ring 24. The argon ion 101 has anisotropy, and in FIG. 2A, the argon ion 101 moves toward the mounting table 16 to which the second high-frequency power is applied, as shown by an arrow A1, to remove the silicon oxide on the wafer W. Contributes to etching. The radicals 102 act isotropically on the wafer W. As a result, a by-product containing carbon generated during the etching process is deposited on the wafer W. During the process, the edge ring 24 is exposed to the plasma. As a result, the by-product containing carbon is deposited not only on the wafer W but also on the edge ring 24 (d in FIG. 2A).

When a by-product containing carbon is deposited on the edge ring 24, for example, when the deposition etching and the non-deposition etching are sequentially or alternately performed, the deposition on the edge ring 24 affects the plasma. May occur and etching may not be performed properly. Therefore, a DC voltage is applied from the first variable power source 55 to the edge ring 24, and the argon ions 101 in the plasma are drawn into the edge ring 24 as shown by an arrow A2 in FIG. Sputter. As a result, the by-product containing carbon deposited on the edge ring 24 is sputtered and removed.

However, when a DC voltage is always applied to the edge ring 24, the edge ring 24 is worn faster than when the DC voltage is not applied. When the edge ring 24 is new, the upper surface of the edge ring 24 and the upper surface of the wafer W have the same height. On the other hand, when the edge ring 24 is consumed, the thickness of the edge ring 24 becomes thin, and the upper surface of the edge ring 24 becomes lower than the upper surface of the wafer W. As a result, a step is formed between the sheath on the edge ring 24 and the sheath on the wafer W.

Due to this step, the irradiation angle of the ions becomes oblique at the edge portion of the wafer W, and tilting occurs in which the shape of the concave portion formed on the wafer W becomes oblique. Therefore, it is desirable to suppress the wear of the edge ring 24 so that the tilting does not occur and to remove the deposit on the edge ring 24. Therefore, the plasma processing apparatus 1 according to the present embodiment provides a processing method for removing deposits on the edge ring 24 while suppressing the wear of the edge ring 24. Therefore, in the present embodiment, the deposition state of deposits generated during the etching process on the edge ring 24 is monitored, and whether or not a DC voltage is applied to the edge ring 24 is controlled according to the deposition state. The deposit state of the deposit is not limited to the amount of deposit, but may be the thickness of the deposited film or the coverage of the deposited film.

[Deposition status monitor]
Next, a method for monitoring the thickness of the deposit on the edge ring 24 will be described with reference to FIG. FIG. 3 is a diagram showing an example of a method of monitoring the deposition state of the edge ring. In the present monitoring method, the ammeter 100 is connected to the power supply line that connects the first variable power supply 55 and the edge ring 24. Then, when a predetermined DC voltage Vdc is applied to the first variable power source 55, a potential difference Vdc is generated in the plasma sheath between the edge ring 24 and the plasma, which causes a potential difference Vdc depending on the amount of ions drawn into the edge ring 24. The current value i flowing through the ammeter 100 is measured.

As shown in FIG. 3A, when there is no deposit on the edge ring 24, the current value i ₁ flowing through the ammeter 100 when the DC voltage is applied from the first variable power source 55 to the edge ring 24 is , When the resistance component of the plasma sheath is Rs, i ₁ =Vdc/Rs (1) is calculated.

On the other hand, as shown in FIG. 3B, when the deposit d is present on the edge ring 24, the resistance component becomes a total resistance component (Rs′+Rd) by adding the resistance component Rd due to the deposit d. Therefore, the current value i ₂ flowing through the ammeter 100 when the DC voltage Vdc is applied to the edge ring 24 is calculated as i ₂ =Vdc/(Rs′+Rd) (2).

Since the resistance component Rd of the deposit d is sufficiently larger than the resistance components Rs and Rs′ of the edge ring 24, if Rd>>Rs, then i ₂ <<i from equations (1) and (2) _It becomes _{1 and} it is predicted that the current value i decreases due to the accumulation of deposits on the edge ring 24. Therefore, by collecting the data of the correlation between the amount of the deposit on the edge ring and the current value i in advance and storing it in the memory, the current value i on the edge ring 24 can be monitored by monitoring the current value i during the plasma processing. The presence or absence of deposits can be determined.

For example, the correlation value with the coverage of the deposited film on the edge ring 24 is calculated by monitoring the current value i, and as shown in the graph of FIG. 4, an example is shown. Data of the correlation with i may be prepared in advance. This makes it possible to determine the voltage application timing of the edge ring 24 from the current value i.

The threshold I ₁ and the threshold I ₂ shown in FIG. 4 are set in advance as the timing of sputtering on the edge ring 24. The threshold I ₁ is set to a value larger than the threshold I ₂ . However, only the threshold I ₁ or the threshold I ₂ may be set in advance. For example, when the current value i becomes equal to or lower than the threshold value I ₁ , it may be determined that the coverage of the deposited film on the edge ring 24 becomes equal to or higher than a predetermined value, and the application of the DC voltage to the edge ring may be started. In this case, when the current value i becomes larger than the threshold value I ₁ , it is determined that the coverage of the deposited film on the edge ring 24 is less than the predetermined value, and the application of the DC voltage to the edge ring 24 is stopped. Good.

The application of the DC voltage to the edge ring is not limited to the binary value of on/off. For example, the application of the DC voltage to the edge ring may be controlled to be low (Low) and high (High). For example, the application of the DC voltage to the edge ring may be controlled to be low when the current value i becomes equal to or less than the threshold value I ₁ . Then, when the current value i becomes equal to or less than the threshold value I ₂ , the application of the DC voltage to the edge ring may be controlled to be high. Further, the application of the DC voltage to the edge ring may be stopped when the current value i becomes larger than the threshold value I ₁ .

The method of monitoring the deposit on the edge ring 24 is not limited to the method shown in FIG. For example, the thickness of the deposit on the edge ring 24 can be determined by irradiating the edge ring 24 with light and monitoring the reflected light. In addition, the state of the deposit may be monitored using other known techniques.

[Voltage application control process]
Next, the voltage application control process of the edge ring according to the embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing an example of the voltage application control process. This processing is controlled by the control unit 200. A program that causes the control unit 200 to execute the edge ring voltage application control processing method is stored in the memory of the control unit 200, and is read from the memory by the CPU and executed.

The voltage application control process is executed while the plasma of the processing gas containing carbon is generated in the plasma processing apparatus 1 and the wafer W and the edge ring 24 are exposed to the plasma of the processing gas.

When this process is started, the control unit 200 acquires the current value i by the ammeter 100 connected to the first variable power source 55 (step S11). Next, the control unit 200 determines whether the current value i is less than or equal to a predetermined threshold value I ₁ (step S12).

When the current value i is less than or equal to the predetermined threshold value I ₁ , the control unit 200 applies the DC voltage to the edge ring 24 (step S13). On the other hand, when the current value i is larger than the predetermined threshold value I ₁ , the control unit 200 does not apply the DC voltage to the edge ring 24 (step S14).

Next, the control unit 200 determines whether to end the process (step S15). The control unit 200 returns to step S11 and performs the processing of step S11 and subsequent steps until it determines in step S15 that the present processing is to end.

FIG. 6 is a diagram showing an example of the effect of the voltage application control described above. The horizontal axis of FIG. 6A shows the application time of the DC voltage to the edge ring 24, and the vertical axis shows the amount of wear of the edge ring 24.

Line A in FIG. 6A shows an example of the amount of wear of the edge ring 24 when the DC voltage is continuously applied to the edge ring 24. In this case, the edge ring 24 is consumed in accordance with the application time of the DC voltage to the edge ring 24.

On the other hand, the line B in FIG. 6A shows wear of the edge ring 24 when a DC voltage is intermittently applied to the edge ring 24 as shown in FIG. 6B by the voltage application control according to the present embodiment. An example of the amount is shown. In this case, since the DC voltage is applied discontinuously to the edge ring 24, the amount of wear of the edge ring 24 can be reduced as compared with the line A to which the DC voltage is continuously applied. As a result, the amount of wear of the edge ring 24 can be minimized.

[Variation of etching rate]
From the above, it was found that the wear amount of the edge ring 24 can be reduced by intermittently applying the DC voltage to the edge ring 24. However, applying a DC voltage to the edge ring 24 affects the process characteristics of the wafer W.

FIG. 7 shows an example of an experimental result when a DC voltage is applied to the edge ring 24 and the wafer W is subjected to the plasma etching process. The process conditions in this experiment are shown below.

<Process conditions>
Gas CF ₄ gas, C ₄ F ₈ gas, N ₂ gas HF power constant value LF power constant value In FIG. 7, the horizontal axis represents the DC voltage applied to the edge ring (edge ring DC voltage), and the vertical axis represents the wafer. The etching rate (E/R) at the center of W is shown. According to this, it is found that by applying a DC voltage to the edge ring 24, the etching rate of the central portion of the wafer W increases, and the higher the DC voltage applied to the edge ring 24, the higher the etching rate. ..

Further, in FIG. 8, the plasma etching process was performed by changing the HF power and the LF power in three stages. The process conditions other than the HF power and the LF power are the same as the process conditions of FIG. 7.

A line B shown in FIG. 8 is a result of the etching rate when the HF power and the LF power are set to “medium” as the reference power for convenience of description. Line A shows the result of the etching rate when the HF power and the LF power are set higher than the reference power. Line C is the result of the etching rate when the HF power and the LF power are set lower than the reference power.

According to this result, the tendency of the etching rate to increase was the same in all cases where the HF power and the LF power were changed in the above three stages. That is, it was found that when a DC voltage was applied to the edge ring 24, the etching rate at the central portion of the wafer W increased and the controllability of the etching rate deteriorated.

[Correction of HF power and LF power]
Therefore, from the relationship between the DC voltage applied to the edge ring 24, the etching rate, and the HF power and the LF power, the center of the wafer W when the DC voltage is applied to the edge ring 24 is compared with the case where the DC voltage is not applied. The shift amount of the etching rate in the part was predicted. Then, with respect to the obtained shift amount of the etching rate, an approximate expression for not shifting the etching rate was calculated, and the HF power correction value and the LF power correction value were obtained from the approximate expression.

According to this, when a DC voltage is applied to the edge ring 24, the HF power and the LF power applied during the plasma processing are corrected by the correction value of the HF power and the correction value of the LF power, so that the center of the wafer W is corrected. It is possible to suppress the shift of the etching rate of the part. Thereby, the in-plane uniformity or controllability of the etching rate can be improved, and the deterioration of the process characteristics for the wafer W when a voltage is applied to the edge ring 24 can be prevented.

The horizontal axis of FIG. 9A is the number of wafers, and the vertical axis is the etching rate of the central portion of the wafer W. The “actual measurement value” in FIG. 9A is the result of measuring the etching rate of the central portion of the wafer W by changing the process parameter for each wafer using the experimental design method.

The “evaluation value (calculated value)” in FIG. 9A is obtained from “measured value” by using multivariate analysis to obtain an approximate expression indicating the relationship between the process parameter and the etching rate of the central portion of the wafer W. This is the result of calculating the etching rate of the central portion of the wafer W by changing the process parameter for each wafer similarly to the “actually measured value”. According to this, since the “evaluation value” is almost the same as the “measured value”, it can be said that the accuracy of the approximate expression is high.

FIG. 9B shows the voltage applied to the edge ring 24 and the correction values of the HF power and the LF power when the etching rate of the central portion of the wafer W is the same, from the approximate expression obtained from the “measured value”. It is the correlation information which calculated the correlation of.

As a result, even when a DC voltage is applied to the edge ring 24 by the correction of the HF power and the LF power according to the present embodiment, the etching rate in the central portion of the wafer W does not shift, and the controllability of the etching rate is improved. Can be secured.

Note that FIG. 9B shows the correlation between the applied voltage of the edge ring and the HF power and the LF power when the HF power and the LF power are changed at the same ratio. The HF power and the LF power are It is not limited to changing at the same ratio.

[Correction of process parameters]
The approximation formula used may be an approximation formula using a linear function as long as it is a formula approximating an actual measurement value, or an approximation formula using another function (quadratic function or the like). Good. By correcting the HF power and the LF power using such an approximate expression, it is possible to secure the in-plane uniformity of the process characteristics of the wafer W without changing the etching rate of the central portion of the wafer W. it can.

How much the HF power and the LF power should be corrected with respect to the fluctuation value (difference) of the DC voltage applied to the edge ring 24 can be obtained by an approximate expression. Therefore, the correlation information is stored in the memory of the control unit 200 in advance.

For example, in the graph shown in FIG. 9B, the ratio of the DC voltage applied to the edge ring 24 to the maximum output value (expressed as the edge ring DC voltage) of the first variable power supply 55 on the horizontal axis is plotted against the vertical axis. (Left) shows the correction rate from the set value of the HF power when not applied to the edge ring 24, and the vertical axis (right) shows the correction rate from the set value of the LF power when not applied to the edge ring 24. Show.

In this example, when the DC voltage applied to the edge ring 24 is increased by "30%", the HF power is subtracted from the set value by "12.5%" and the LF power is subtracted from the set value by "12.5%". Then, the corrected HF power and the corrected LF power are applied.

In this way, the HF power and the LF power are corrected according to the DC voltage applied to the edge ring 24 or the variation thereof, so that even if the DC voltage is applied to the edge ring 24, the center of the wafer W is It is possible to suppress an increase in the etching rate of the part. As a result, the controllability of the etching rate can be improved while suppressing the occurrence of tilting of the edge portion of the wafer W by the DC voltage applied to the edge ring 24.

In the present embodiment, the HF power and the LF power are corrected according to the DC voltage applied to the edge ring 24 or its variation, but the process parameter corrected according to the DC voltage applied to the edge ring 24 is HF. It is not limited to power and LF power. The process parameter to be corrected may be any parameter as long as it is a process condition in which the generated plasma density varies. The process parameter to be corrected may be a process condition in which the etching rate changes, for example.

For example, the process parameter to be corrected may be only the LF power or the HF power. The process parameter to be corrected may be the DC voltage applied from the second variable power source 50 to the upper electrode 34, or the type and/or the flow rate of the gas supplied from the processing gas supply source 66. However, the pressure in the chamber 10 may be used.

That is, the process parameters are the high frequency power of the first frequency applied from the first high frequency power supply 90, the high frequency power of the second frequency lower than the first frequency applied from the second high frequency power supply 48, the chamber. It may be at least one of a gas supplied into the chamber 10, a pressure in the chamber 10, and a voltage applied from the second variable power source 50 to the upper electrode 34.

[Processing method and correction processing]
Finally, a processing method and a correction process performed by the control unit 200 according to the embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a flowchart showing an example of the processing method according to the embodiment. FIG. 11 is a flowchart showing an example of the correction process according to the embodiment. A program that causes the control unit 200 to execute the processing method and the correction processing method is stored in the memory of the control unit 200, and is read from the memory by the CPU and executed.

When the process shown in FIG. 10 is started, the edge ring voltage application control process is executed (step S10). In this voltage application control process, as shown in FIG. 5, it is determined whether a DC voltage is applied to the edge ring 24 based on the current value i (that is, the state of the deposit on the edge ring 24), and the DC voltage is applied. Control timing. At this time, in determining whether to end the process of step S15 in FIG. 5, the control unit 200 determines to end the process in FIG. 5 when determining that the DC voltage is applied to the edge ring 24.

When the voltage application control process of the edge ring in FIG. 5 is completed, the process returns to FIG. 10 and the correction process is executed (step S20). An example of the correction process will be described with reference to FIG. When this correction process is started, the control unit 200 acquires the value of the DC voltage (DC voltage) applied to the edge ring 24 (step S21). Next, the control unit 200 calculates the difference between the current DC voltage value and the previous DC voltage value among the DC voltage values applied to the edge ring 24 (step S22). In addition, the acquisition interval of the current DC voltage value and the previous DC voltage value may be set in any manner. Further, the difference between the current DC voltage value and the previous DC voltage value is not limited, and may be the difference between the current DC voltage value and the previous or previous DC voltage value. For example, the difference between the DC voltage value of this time and the average value of the DC voltage values of the previous time and the time before last may be used.

Next, the control unit 200 refers to the memory that stores the correlation information between the difference between the DC voltage applied to the edge ring 24 and the correction value of the HF power and the LF power shown in FIG. The correction values of the HF power and the LF power with respect to the difference of are calculated (step S23). Note that the example of the correlation information in FIG. 9B is an example of information indicating the correlation between the DC voltage applied to the edge ring 24 and the correction value of the process parameter, and is not limited to this. The correlation information may be information indicating the correlation between the variation (difference) between the current DC voltage value and the previous DC voltage value and the process parameter correction value, or the current DC voltage value and the process parameter correction value. It may be information indicating a correlation with. In the latter case, step S22 is skipped, the correlation information stored in the memory is referred to in step S3, and the HF power correction value and the LF power correction value for the current DC voltage value acquired in step S21 are set. Should be calculated.

Next, the control unit 200 subtracts the correction value of the HF power calculated in step S23 from the set value of the HF power set in the recipe to obtain the corrected HF power (step S24). Further, the LF power correction value calculated in step S23 is subtracted from the LF power setting value set in the recipe to obtain the corrected LF power (step S24).

Next, the control unit 200 applies the corrected HF power and the corrected LF power. The control unit 200 controls the other process conditions to the set values set in the recipe, executes the plasma process (step S25), ends the correction process, returns to FIG. 10, and ends the entire process.

As described above, according to the correction process of the present embodiment, it is possible to suppress the wear of the edge ring 24 by intermittently controlling the timing of applying the DC voltage to the edge ring 24. Further, when a DC voltage is applied to the edge ring 24, a process parameter (for example, HF power) is corrected according to the applied DC voltage, so that an increase in the etching rate at the central portion of the wafer W can be suppressed. Accordingly, while suppressing the wear of the edge ring 24, suppressing the occurrence of tilting of the edge portion of the wafer W by the DC voltage applied to the edge ring 24, and suppressing the increase of the etching rate in the central portion of the wafer W. The deposit on the edge ring 24 can be removed.

Particularly, in the cryogenic etching in which the temperature of the mounting table 16 is controlled to, for example, about −several tens of degrees Celsius to −hundreds of several tens of degrees Celsius, the amount of by-products deposited by the etching increases. Therefore, the processing method according to the present embodiment can be used as a more effective technique in cryogenic etching. However, of course, the processing method according to the present embodiment is not limited to the cryogenic etching.

It should be considered that the processing method and the plasma processing apparatus according to the embodiment disclosed this time are exemplifications in all points and not restrictive. The above-described embodiments can be modified and improved in various forms without departing from the scope and spirit of the appended claims. The matters described in the above plurality of embodiments can have other configurations as long as they do not contradict each other, and can be combined in a range that does not contradict.

The voltage applied to the edge ring 24 is not limited to the DC voltage and may be the AC voltage. When an AC voltage is applied to the edge ring 24, an AC power supply is connected via a matching device and a blocking capacitor instead of the first variable power supply 55. This AC power supply outputs an AC having a frequency f that ions in the plasma can follow, that is, an AC having a low frequency or a high frequency lower than the ion plasma frequency so that its power, voltage peak value or effective value can be varied. Has become. When the AC voltage from the AC power supply is applied to the edge ring 24 through the blocking capacitor during the etching process, a self-bias voltage is generated in the edge ring 24. That is, the negative DC voltage component is applied to the edge ring 24.

Although the embodiments of the present disclosure describe the etching process, the present invention is not limited thereto. In the example, the step of forming the deposited film on the processed substrate in the etching process was described. However, the deposited film is formed on the processed substrate by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD). The same effect can be obtained in the step of performing.

Further, the deposition process of the present disclosure has been described using the processing gas containing carbon, but the present invention is not limited to this. Similarly, when a plasma of a processing gas capable of generating a depositing precursor (precursor) such as TEOS gas used in CVD is used, it is also deposited on the edge ring. In PVD, the precursor generated from the target by plasma sputtering is deposited on the processed substrate, but it is also deposited on the edge ring. That is, as if a precursor having a depositing property exists in the plasma space, it deposits on the edge ring as well. Even in these processes, by applying a voltage to the edge ring, it is possible to prevent the deposition on the edge ring, and by observing the state of the deposited film and adjusting the applied voltage, the edge ring is consumed. It can be minimized.

The plasma processing apparatus of the present disclosure, Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial Line Slot Antenna (RLSA), Electron Cyclotron Resonance Plasma (ECR), any type of plasma processing of Helicon Wave Plasma (HWP) It is also applicable to devices.

In this specification, the wafer W is described as an example of the object to be processed. However, the object to be processed is not limited to this, and may be various substrates used for FPD (Flat Panel Display), a printed circuit board, or the like.

1 plasma processing apparatus 10 chamber 16 mounting table 16a base 20a first electrode 24 edge ring 34 upper electrode 48 second high frequency power supply 50 second variable power supply 55 first variable power supply 66 processing gas supply source 90 first High frequency power supply W wafer

Claims (10)

A plasma processing apparatus having a mounting table on which a target object is mounted in a chamber, an outer peripheral member arranged around the mounting table, and a first power source for applying a voltage to the outer peripheral member is used. A processing method for processing a processing body,
Exposing the object to be processed to plasma having a depositable precursor while applying a voltage from the first power source to the outer peripheral member;
During the step of exposing to the plasma, observing the state of the deposited film containing carbon deposited on the outer peripheral member, and controlling the voltage applied to the outer peripheral member based on the observed state of the deposited film,
And a processing method. A step of correcting the process parameter based on the voltage applied to the outer peripheral member with reference to a storage unit that stores the correlation information between the voltage applied to the outer peripheral member and the correction value of the process parameter;
Performing plasma treatment according to process conditions including the corrected process parameters.
The processing method according to claim 1. The process parameter is a process condition in which the generated plasma density varies.
The processing method according to claim 2. The process parameter is a process condition in which the etching rate changes.
The processing method according to claim 2. The process parameter is a high frequency power of a first frequency applied from a first high frequency power source, a high frequency power of a second frequency lower than the first frequency applied from a second high frequency power source, At least one of a gas to be supplied and a voltage applied from the second power source to the upper electrode facing the mounting table.
The processing method according to claim 2. The step of controlling the voltage applied to the outer peripheral member applies a voltage to the outer peripheral member when the observed state of the deposited film is a predetermined threshold value or more,
The processing method according to claim 1. In the step of controlling the voltage applied to the outer peripheral member, when the observed state of the deposited film is smaller than a predetermined threshold value, no voltage is applied to the outer peripheral member,
The processing method according to claim 1. The plasma with the depositable precursor is generated by a process gas capable of generating the depositable precursor,
The processing method according to claim 1. The processing gas contains carbon,
The processing method according to claim 8. A plasma processing apparatus including: a mounting table for mounting an object to be processed in a chamber; an outer peripheral member arranged around the mounting table; a first power supply for applying a voltage to the outer peripheral member; and a control unit. And
The control unit is
Exposing the object to be processed to a plasma of a processing gas containing carbon while applying a voltage from the first power source to the outer peripheral member;
During the step of exposing to the plasma of the processing gas, the state of the deposited film containing carbon deposited on the outer peripheral member is observed, and the voltage applied to the outer peripheral member is controlled based on the observed state of the deposited film. Process,
Executing a step of correcting the process parameter based on the voltage applied to the outer peripheral member with reference to the storage unit that stores the correlation information between the voltage applied to the outer peripheral member and the correction value of the process parameter.
Plasma processing equipment.

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