TW202101578A - Processing method and plasma processing apparatus - Google Patents

Abstract

A method of processing an object using a plasma processing apparatus is provided. The plasma processing apparatus includes a stage on which the object is placed in a chamber, an outer peripheral member disposed around the stage, and a first power supply configured to apply voltage to the outer peripheral member. The method includes a step of exposing the object to a plasma containing a precursor having a deposition property, while applying voltage from the first power supply to the outer peripheral member. In applying voltage to the outer peripheral member, a status of a deposition film containing carbon that is deposited on the outer peripheral member is monitored, and the voltage applied to the outer peripheral member is controlled based on the monitored status of the deposition film.

Description

Processing method and plasma processing device

The invention relates to a processing method and a plasma processing device.

There is a process of depositing by-products produced by plasma processing on a wafer to form a deposited film. For example, Patent Document 1 proposes a technique that alternately repeats the following steps: etching a region containing silicon oxide and forming a deposit containing fluorocarbon on the region; and using the fluorocarbon contained in the deposit Free radicals etch the above areas. The by-products are deposited on the wafer, and are also deposited on peripheral components (hereinafter, also referred to as "edge ring") disposed around the wafer. [Prior Technical Literature] [Patent Literature]

[Patent Document 2] Japanese Patent Laid-Open No. 2015-173240

[The problem to be solved by the invention]

The present invention provides a technology capable of suppressing the consumption of peripheral members and removing deposits on the peripheral members. [Technical means to solve the problem]

According to one aspect of the present invention, there is provided a processing method that uses a plasma processing device to treat an object to be processed. The plasma processing device includes: a mounting table for placing the object to be processed in a chamber; and a peripheral member , Which is arranged around the mounting table; and a first power source, which applies a voltage to the outer peripheral member; and the processing method includes the following steps: while applying voltage from the first power source to the outer peripheral member, while exposing the processed body During the process of exposing to the plasma of the above-mentioned plasma and during the process of being exposed to the plasma of the process gas, observe the inclusions deposited on the peripheral member The state of the deposited film of carbon, and the voltage applied to the peripheral member is controlled based on the observed state of the deposited film. [Effects of Invention]

According to one aspect, it is possible to suppress the consumption of the outer peripheral member and remove the deposits on the outer peripheral member.

Hereinafter, a mode for implementing the present invention will be described with reference to the drawings. In each of the drawings, the same components may be labeled with the same symbols and repeated descriptions may be omitted.

[Plasma processing device] A plasma processing apparatus 1 according to an embodiment will be described with reference to FIG. 1. Fig. 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus 1 according to an embodiment. The plasma processing apparatus 1 of one embodiment is a capacitive coupling type parallel plate processing apparatus, and has a chamber 10. The chamber 10 is, for example, a cylindrical container including aluminum whose surface is anodized, and is grounded.

At the bottom of the chamber 10, a cylindrical support table 14 is disposed between an insulating plate 12 containing ceramics, etc., and a mounting table 16 is provided on the support table 14, for example. The mounting table 16 has an electrostatic chuck 20 and a base 16 a, and the wafer W is mounted on the upper surface of the electrostatic chuck 20. A ring-shaped edge ring 24 including silicon, for example, is disposed around the wafer W. The edge ring 24 is also called a focus ring. The edge ring 24 is an example of an outer peripheral member arranged around the mounting table 16. A ring-shaped insulator ring 26 made of quartz, for example, is provided around the base 16a and the support 14. Inside the center side of the electrostatic chuck 20, a first electrode 20a including a conductive film is sandwiched between insulating layers 20b. The first electrode 20 a is connected to the power source 22. The electrostatic force is generated by the DC voltage applied from the power supply 22 to the first electrode 20 a, and the wafer W is attracted to the wafer mounting surface of the electrostatic chuck 20. Furthermore, the electrostatic chuck 20 may also have a heater to control the temperature.

Inside the support table 14, a refrigerant chamber 28 having a ring shape or a spiral shape is formed, for example. The refrigerant of a specific temperature supplied from the cooler unit (not shown), for example, cooling water, returns to the cooler unit through the pipe 30a, the refrigerant chamber 28, and the pipe 30b. By circulating the refrigerant in the above path, the temperature of the wafer W can be controlled by the temperature of the refrigerant. Furthermore, the heat transfer gas supplied from the heat transfer gas supply mechanism, such as He gas, is supplied to the gap between the front surface of the electrostatic chuck 20 and the back surface of the wafer W through the gas supply line 32. With the heat transfer gas, the heat transfer coefficient between the front surface of the electrostatic chuck 20 and the back surface of the wafer W is reduced, and the temperature control of the wafer W using the temperature of the refrigerant becomes more effective. Furthermore, when the electrostatic chuck 20 has a heater, the temperature of the wafer W can be controlled with high responsiveness and accuracy by heating by the heater and cooling by the refrigerant.

The upper electrode 34 is opposite to the mounting table 16 and is provided on the top wall of the chamber 10. The space between the upper electrode 34 and the mounting table 16 becomes a plasma processing space. The upper electrode 34 closes the opening of the top wall of the chamber 10 through an insulating shielding member 42. The upper electrode 34 has an electrode plate 36 and an electrode support 38. The electrode plate 36 has a plurality of gas ejection holes 37 formed on a surface opposite to the mounting table 16, and is formed of silicon or SiC or other silicon-containing materials. The electrode support 38 detachably supports the electrode plate 36, and is formed of a conductive material, for example, aluminum whose surface is anodized. Inside the electrode support 38, a plurality of gas passage holes 41a, 41b extend downward from the gas diffusion chambers 40a, 40b, and communicate with the gas ejection hole 37.

The gas introduction port 62 is connected to a processing gas supply source 66 via a gas supply pipe 64. The gas supply pipe 64 is provided with a mass flow controller (MFC) 68 and an on-off valve 70 in this order from the upstream side where the processing gas supply source 66 is arranged. The processing gas is supplied from the processing gas supply source 66, and the mass flow controller 68 and the on-off valve 70 are used to control the flow and opening and closing, and are ejected from the gas through the gas supply pipe 64 through the gas diffusion chambers 40a, 40b, and the gas passage holes 41a, 41b The holes 37 are ejected in a cluster shape.

The plasma processing apparatus 1 has a first high-frequency power source 90 and a second high-frequency power source 48. The first high-frequency power source 90 is a power source that generates first high-frequency power (hereinafter, also referred to as "HF (High Frequency) power"). The first high-frequency power has a frequency suitable for generating plasma. The frequency of the first high-frequency power is, for example, a frequency in the range of 27 MHz to 100 MHz. The first high-frequency power source 90 is connected to the base 16 a via a matching device 88 and a feeder line 89. The matcher 88 has a circuit for matching the output impedance of the first high-frequency power source 90 with the impedance on the load side (base 16a side). Furthermore, the first high-frequency power source 90 may be connected to the upper electrode 34 via a matching device 88.

The second high-frequency power source 48 is a power source that generates second high-frequency power (hereinafter, also referred to as "LF (Low frequency) power"). The second high-frequency power has a frequency lower than that of the first high-frequency power. In the case of using the first high-frequency power and the second high-frequency power, the second high-frequency power is used as the high-frequency power for bias voltage for introducing ions into the wafer W. The frequency of the second high frequency power is, for example, a frequency in the range of 400 kHz to 13.56 MHz. The second high-frequency power source 48 is connected to the base 16 a via a matching device 46 and a feed line 47. The matcher 46 has a circuit for matching the output impedance of the second high-frequency power source 48 with the impedance on the load side (base 16a side).

Furthermore, instead of using the first high frequency power, the second high frequency power may be used, that is, only a single high frequency power may be used to generate plasma. In this case, the frequency of the second high-frequency power can also be a frequency greater than 13.56 MHz, for example, 40 MHz. The plasma processing device 1 may not include the first high-frequency power source 90 and the matching device 88. With the above configuration, the mounting table 16 also functions as a lower electrode. In addition, the upper electrode 34 also functions as a shower head for supplying gas.

The second variable power source 50 is connected to the upper electrode 34 and applies a DC voltage to the upper electrode 34. The first variable power supply 55 is connected to the edge ring 24 and applies a DC voltage to the edge ring 24. In addition, the first variable power source 55 is an example of a first power source that applies voltage to outer peripheral members. The second variable power source 50 is an example of a second power source that applies a voltage to the upper electrode 34.

The exhaust device 84 is connected to the exhaust pipe 82. The exhaust device 84 has a vacuum pump such as a turbo-molecular pump, and exhausts from an exhaust port 80 formed at the bottom of the chamber 10 through an exhaust pipe 82 to reduce the pressure in the chamber 10 to a desired degree of vacuum. In addition, the exhaust device 84 uses a pressure gauge that measures the pressure in the chamber 10 (not shown), and controls the pressure in the chamber 10 to be constant. The carry-in and carry-out port 85 is provided on the side wall of the chamber 10. The wafer W is carried in and out from the carry-in and carry-out port 85 by opening and closing the gate valve 86.

The partition 83 is annularly arranged between the insulator ring 26 and the side wall of the chamber 10. The separator 83 has a plurality of through holes, is formed of aluminum, and its surface is coated with ceramics such as Y ₂ O ₃ .

When performing specific plasma processing such as plasma etching processing in the plasma processing apparatus 1 having the above configuration, the gate valve 86 is opened, and the wafer W is loaded into the chamber 10 through the loading/unloading port 85 and placed on the mounting table 16 , Close the gate valve 86. The processing gas is supplied to the inside of the chamber 10, and the inside of the chamber 10 is exhausted by the exhaust device 84.

The first high-frequency power and the second high-frequency power are applied to the mounting table 16. A DC voltage is applied from the power supply 22 to the first electrode 20 a, and the wafer W is attracted to the mounting table 16. Furthermore, a DC voltage may be applied to the upper electrode 34 from the second variable power source 50.

The plasma processing such as etching is performed on the processed surface of the wafer W by radicals or ions in the plasma generated in the plasma processing space.

The plasma processing device 1 is provided with a control unit 200 that controls the entire operation of the device. The CPU (Central Processing Unit) installed in the control unit 200 executes the recipe according to the recipes stored in ROM (Read Only Memory) and RAM (Random Access Memory). Plasma treatment required for etching etc. The control information of the device relative to the process conditions can also be set in the recipe, namely process time, pressure (gas exhaust), first high-frequency power and second high-frequency power or voltage, and various gas flows. In addition, the temperature in the chamber (the temperature of the upper electrode, the temperature of the side wall of the chamber, the temperature of the wafer W, the temperature of the electrostatic chuck, etc.), the temperature of the refrigerant output from the cooler, etc. can also be set in the recipe. Furthermore, these programs or formulas representing processing conditions can also be stored in hard disk or semiconductor memory. In addition, the formula can also be stored in CD-ROM (Compact Disc Read-Only Memory), DVD (Digital Video Disc) and other portable memory media that can be read by a computer. Specific location and read out.

[Deposition process and sputtering process] In recent years, for example, the control of the deposition amount has become important in ALE (Atomic Layer Etching) technology in which depositional etching and non-depositional etching are repeated in a specific number of times. Particularly in the very low temperature etching in which the temperature of the mounting table 16 is controlled to, for example, tens of degrees below zero to about one hundred tens of degrees below zero, the deposition amount of by-products generated by the etching increases. Therefore, in ultra-low temperature etching, it becomes more important to control the amount of by-products deposited on the wafer.

Hereinafter, using FIG. 2, the process of depositing by-products by etching treatment and the process of sputtering while depositing by-products will be described. Fig. 2 is a diagram for explaining the deposition process and the sputtering process.

For example, there is a deposition process of etching a silicon oxide-containing area on the wafer W to form a carbon-containing deposit on the area. In this deposition step, a carbon-containing C ₄ F ₈ or other fluorocarbon gas or CH ₄ or other hydrocarbon gas is supplied from the processing gas supply source 66. The processing gas may also be a hydrofluorocarbon gas such as CH ₂ F ₂ . The processing gas may also contain inert gas. Hereinafter, it is assumed that argon is included as an inert gas.

The processing gas becomes plasma by the first high-frequency power and the second high-frequency power. In the plasma, as shown in FIG. 2, for example, radicals 102 such as CHx radicals (CHx*) and CyFz radicals (CyFz*) and argon ions (Ar ⁺ ) 101 are included.

Here, FIG. 2(a) is a case where no DC voltage is applied to the edge ring 24, and FIG. 2(b) is a case where a DC voltage is applied to the edge ring 24. The argon ions 101 have anisotropy. In FIG. 2(a), as shown by arrow A1, they move toward the mounting table 16 to which the second high-frequency power is applied, and contribute to the etching of silicon oxide on the wafer W. The radical 102 acts isotropically on the wafer W. Thereby, carbon-containing by-products generated during the etching process are deposited on the wafer W. During the manufacturing process, the edge ring 24 is exposed to plasma. Thereby, the by-product containing carbon is not only deposited on the wafer W, but also deposited on the edge ring 24 (Figure 2(a), d).

If carbon-containing by-products are deposited on the edge ring 24, for example, from depositional etching to non-depositional etching sequentially or alternately, there are situations in which the deposition on the edge ring 24 Plasma is biased due to the influence of objects, and etching cannot be performed properly. Therefore, a DC voltage is applied to the edge ring 24 from the first variable power supply 55, as shown by arrow A2 in FIG. 2(b), the argon ions 101 in the plasma are introduced into the edge ring 24, and the edge ring 24 is sputtered. plating. Thereby, the by-products containing carbon deposited on the edge ring 24 are sputtered and removed.

However, if the DC voltage is always applied to the edge ring 24, the consumption of the edge ring 24 is earlier than when the DC voltage is not applied. When the edge ring 24 is a new product, the upper surface of the edge ring 24 and the upper surface of the wafer W are at the same height. In contrast, if the edge ring 24 is consumed, the thickness of the edge ring 24 becomes thinner, and the upper surface of the edge ring 24 is lower than the upper surface of the wafer W. As a result, a step difference is generated between the sheath layer on the edge ring 24 and the sheath layer on the wafer W.

Due to the level difference, a tilt occurs, that is, the irradiation angle of the ions at the edge of the wafer W is tilted so that the shape of the recess formed on the wafer W is tilted. Therefore, it is desirable to suppress the consumption of the edge ring 24 and remove the deposits on the edge ring 24 so that no tilt is generated. Therefore, in the plasma processing apparatus 1 of the present embodiment, a processing method for removing the deposits on the edge ring 24 while suppressing the consumption of the edge ring 24 is provided. For this reason, in this embodiment, the deposition state of the by-products (hereinafter, also referred to as "deposits") generated during the etching process on the edge ring 24 is monitored, and whether a DC voltage is applied to the edge ring 24 is controlled according to the deposition state . Furthermore, the deposition state of the deposit is not limited to the deposition amount, for example, it may also be the thickness of the deposited film or the coverage rate of the deposited film.

[Monitoring of deposition status] Next, the method of monitoring the thickness of the deposit on the edge ring 24 will be described with reference to FIG. 3. Fig. 3 is a diagram showing an example of a method of monitoring the deposition state of the edge ring. In this monitoring method, the ammeter 100 is connected to the feeder connecting the first variable power supply 55 and the edge ring 24. Furthermore, when a specific DC voltage Vdc is applied to the first variable power supply 55, a potential difference Vdc is generated in the plasma sheath between the edge ring 24 and the plasma, whereby the flow to the plasma is measured based on the amount of ions introduced into the edge ring 24 The current value i of the ammeter 100.

As shown in Figure 3(a), when there is no deposit on the edge ring 24, the current value i1 flowing to the ammeter 100 when the first variable power source 55 applies a DC voltage to the edge ring 24 is related to the current When the resistance component of the plasma sheath is set to Rs, it is calculated as i1=Vdc/Rs...(1).

On the other hand, as shown in FIG. 3(b), when there is a deposit d on the edge ring 24, the resistance component plus the resistance component Rd of the deposit d becomes the total resistance component (Rs'+Rd). Therefore, the current value i2 flowing to the ammeter 100 when the DC voltage Vdc is applied to the edge ring 24 is calculated as i2=Vdc/(Rs'+Rd)...(2).

The resistance component Rd of the sediment d is sufficiently greater than the resistance component Rs' of the edge ring 24. Therefore, if it is set as Rd>>Rs, then i2<<i1 can be obtained according to equations (1) and (2), which is predicted to be due to sediment Deposited on the edge ring 24 and the current value i decreases. Therefore, by pre-collecting the data of the correlation between the amount of deposits in the edge ring and the current value i and storing it in the memory, the presence or absence of deposits on the edge ring 24 can be determined by monitoring the current value i during plasma processing.

For example, it is also possible to calculate information related to the coverage rate of the deposited film on the edge ring 24 by monitoring the current value i. As shown in the graph of FIG. 4, the coverage rate and current of the deposited film on the edge ring are prepared in advance. Information about the correlation of the value i. Thereby, the voltage application timing of the edge ring 24 can be determined according to the current value i.

The threshold I ₁ and the threshold I ₂ shown in FIG. 4 are preset as the sequence of sputtering on the edge ring 24. However, only the threshold I ₁ or the threshold I ₂ may be set in advance. For example, when the current value i becomes less than or equal to the threshold value I ₁ , it is determined that the coverage rate of the deposited film on the edge ring 24 is greater than or equal to a certain value, and the application of a DC voltage to the edge ring is started. In this case, when the current value i is greater than the threshold I ₁ , it is determined that the coverage rate of the deposited film on the edge ring 24 has not reached a certain level, and the application of the DC voltage to the edge ring 24 is stopped.

The application of DC voltage to the edge ring is not limited to the two values of on and off. For example, it is also possible to control the application of the DC voltage to the edge ring to Low and High. For example, when the current value i becomes the threshold value I ₁ or less, the application of the DC voltage to the edge loop may be controlled to be low. Furthermore, when the current value i becomes the threshold value I ₂ or less, the application of the DC voltage to the edge ring may be controlled to be high. Moreover, when the current value i is greater than the threshold value I ₁ , the application of the DC voltage to the edge loop may be stopped.

Furthermore, the method of monitoring the deposits on the edge ring 24 is not limited to the method shown in FIG. 3. For example, the thickness of the deposit on the edge ring 24 can be determined by irradiating light on the edge ring 24 and monitoring the reflected light. In addition, other well-known techniques can also be used to monitor the state of the deposits.

[Voltage Application Control Processing] Next, referring to FIG. 5, the voltage application control process of the edge ring of an embodiment will be described. Fig. 5 is a flowchart showing an example of voltage application control processing. This process is controlled by the control unit 200. Furthermore, a program for the control unit 200 to execute the voltage application control processing method of the edge loop is stored in the memory of the control unit 200 in advance, and is read and executed by the CPU from the memory.

Furthermore, the voltage application control process is performed during the period in which the plasma processing apparatus 1 generates the plasma of the processing gas containing carbon and the wafer W and the edge ring 24 are exposed to the plasma of the processing gas.

When this process is started, the control unit 200 obtains the current value i from the ammeter 100 connected to the first variable power supply 55 (step S11). Next, the control unit 200 determines whether the current value i is less than or equal to a predetermined threshold I ₁ (step S12).

When the current value i is less than or equal to the predetermined threshold I ₁ , the control unit 200 applies a DC voltage to the edge ring 24 (step S13). On the other hand, when the current value i is greater than the predetermined threshold value I ₁ , the control unit 200 does not apply a DC voltage to the edge ring 24 (step S14).

Then, the control unit 200 determines whether to end the processing (step S15). The control unit 200 returns to step S11 and performs the processing after step S11 before it is determined to end this processing in step S15.

Fig. 6 is a diagram showing an example of the effect of the voltage application control described above. The horizontal axis of FIG. 6(a) represents the application time of the DC voltage to the edge ring 24, and the vertical axis represents the consumption of the edge ring 24.

The line A in FIG. 6(a) represents an example of the consumption of the edge ring 24 when the DC voltage is continuously applied to the edge ring 24. In this case, the edge ring 24 consumes corresponding to the application time of the DC voltage to the edge ring 24.

On the other hand, line B in FIG. 6(a) represents the consumption of the edge ring 24 when a DC voltage is intermittently applied to the edge ring 24 as shown in FIG. 6(b) by the voltage application control of this embodiment. An example of quantity. In this case, the DC voltage is applied to the edge ring 24 discontinuously. Therefore, the consumption of the edge ring 24 can be reduced compared with the line A where the DC voltage is continuously applied. Thereby, the consumption of the edge ring 24 can be minimized.

[Changes in etching rate] According to the above, the consumption of the edge ring 24 can be reduced by applying the DC voltage to the edge ring 24 intermittently. However, if a DC voltage is applied to the edge ring 24, the process characteristics of the wafer W will be affected.

FIG. 7 shows an example of experimental results when a DC voltage is applied to the edge ring 24 and the wafer W is subjected to plasma etching treatment. The following shows the process conditions in this experiment.

<Process conditions> Gases CF ₄ gas, C ₄ F ₈ gas, N ₂ gas HF power fixed value LF power fixed value Figure 7 horizontal axis represents the DC voltage applied to the edge ring (edge ring DC voltage), the vertical axis represents the crystal The etching rate (E/R) of the center (center) of the circle W. It can be seen from this that by applying a DC voltage to the edge ring 24, the etching rate of the center portion of the wafer W increases, and the greater the DC voltage applied to the edge ring 24, the higher the etching rate.

Furthermore, in FIG. 8, the HF power and the LF power were changed in three stages to perform the plasma etching process. The process conditions other than HF power and LF power are the same as the process conditions in FIG. 7.

The line B shown in FIG. 8 is the result of the etching rate when the HF power and the LF power are set as the "medium" of the reference power for convenience of description. Line A is the result of the etching rate when the HF power and LF power are set higher than the reference power. Line C is the result of the etching rate when the HF power and LF power are set lower than the reference power.

According to this result, when the HF power and the LF power are changed in any of the above three stages, the tendency of the etching rate to rise is the same. That is, it can be seen that when a DC voltage is applied to the edge ring 24, the etching rate of the center portion of the wafer W increases, and the controllability of the etching rate deteriorates.

[Revision of HF power and LF power] Therefore, according to the relationship between the DC voltage applied to the edge ring 24, the etching rate, and the HF power and LF power, the etching rate of the central part of the wafer W when the DC voltage is not applied to the edge ring 24 is predicted The offset. Then, for the obtained offset of the etching rate, an approximate formula for keeping the etching rate not offset is calculated, and the correction value of the HF power and the correction value of the LF power are obtained according to the approximate expression.

Thereby, when a DC voltage is applied to the edge ring 24, the correction value of HF power and the correction value of LF power are used to correct the HF power and LF power applied in the plasma processing, thereby suppressing the center portion of the wafer W The offset of the etching rate. Thereby, the in-plane uniformity or controllability of the etching rate can be improved, and the process characteristics of the wafer W can be prevented from being reduced when a voltage is applied to the edge ring 24.

The horizontal axis of FIG. 9(a) is the number of wafers, and the vertical axis is the etching rate of the center of the wafer W. The "measured value" in FIG. 9(a) is the result of measuring the etching rate of the central part of the wafer W by using the experimental planning method to change the process parameters for each wafer.

The "evaluation value (calculated value)" in Figure 9(a) is based on the "measured value" using multivariate analysis to obtain an approximate formula representing the relationship between the etching rate at the center of the wafer W and the process parameters. Value" is the result obtained by calculating the etching rate of the central part of the wafer W by changing the process parameters for each wafer. In this way, the "evaluation value" and the "measured value" are approximately the same, and therefore, the accuracy of the approximate formula can be considered to be high.

Figure 9(b) is based on the approximate formula obtained from the "measured value" to calculate the correlation between the voltage applied to the edge ring 24 and the correction value of the HF power and the LF power when the etching rate of the central part of the wafer W is the same Related information.

As a result, with the correction of the HF power and LF power of this embodiment, even when a DC voltage is applied to the edge ring 24, the etching rate at the center of the wafer W does not deviate, and the etching rate can be controlled. Sex.

Furthermore, Figure 9(b) shows the correlation between the applied voltage of the edge ring and the HF power and LF power when the HF power and LF power are changed at the same ratio, but the HF power and LF power are not limited to change at the same ratio .

[Revision of process parameters] Furthermore, as long as the approximate expression used is an expression that approximates the actual measured value, it may be an approximate expression using a linear function, or an approximate expression using other functions (quadratic functions, etc.). By correcting the HF power and the LF power using the above approximation formula, the etching rate of the center portion of the wafer W can be kept unchanged and the in-plane uniformity of the process characteristics of the wafer W can be ensured.

How much the HF power and LF power should be corrected for the variation value (differential) of the DC voltage applied to the edge ring 24 is calculated according to the approximate formula. Therefore, the related information is stored in the memory of the control unit 200 in advance.

For example, in the graph shown in FIG. 9(b), the ratio of the DC voltage applied to the edge ring 24 to the maximum output value of the first variable power supply 55 (expressed as edge ring DC voltage) relative to the horizontal axis , The vertical axis (left) represents the rate of correction of the set value of HF power when not applied to the edge ring 24, and the vertical axis (right) represents the rate of correction of the set value of LF power when not applied to the edge ring 24.

In this example, if the DC voltage applied to the edge ring 24 is increased by "30%", the HF power is subtracted from the set value by "12.5%", and the LF power is subtracted from the set value by "12.5%". Then, apply the corrected HF power and the corrected LF power.

In this way, the HF power and LF power are corrected in accordance with the DC voltage applied to the edge ring 24 or the amount of variation, thereby suppressing the center portion of the wafer W even when the DC voltage is applied to the edge ring 24 The increase in etching rate. Thereby, it is possible to prevent the edge portion of the wafer W from tilting due to the DC voltage applied to the edge ring 24, and to improve the controllability of the etching rate.

Furthermore, in this embodiment, the HF power and LF power are corrected based on the DC voltage applied to the edge ring 24 or its variation, but the process parameters corrected based on the DC voltage applied to the edge ring 24 are not limited to the HF power and LF power. The modified process parameter can be any parameter as long as it is the process condition of the generated plasma density variation. The modified process parameter can also be, for example, the process condition for changing the etching rate.

For example, the modified process parameter can only be LF power or only HF power. The modified process parameter can be the DC voltage applied from the second variable power supply 50 to the upper electrode 34, the type of gas and/or the gas flow rate supplied from the processing gas supply source 66, and can also be the chamber 10 The pressure.

That is, the process parameters can be high-frequency power at the first frequency applied from the first high-frequency power supply 90, high-frequency power at the second frequency lower than the first frequency applied from the second high-frequency power supply 48, and supplied to the chamber At least any one of the gas in 10, the pressure in the chamber 10, and the voltage applied from the second variable power source 50 to the upper electrode 34.

[Processing method and correction processing] Finally, the processing method and correction processing performed by the control unit 200 of an embodiment will be described with reference to FIGS. 10 and 11. Fig. 10 is a flowchart showing an example of a processing method of an embodiment. Fig. 11 is a flowchart showing an example of correction processing in an embodiment. Furthermore, the program for the control unit 200 to execute the processing method and the correction processing method is stored in the memory of the control unit 200, and is read and executed by the CPU from the memory.

When the processing shown in FIG. 10 is started, the voltage application control processing of the edge loop is executed (step S10). The voltage application control process determines whether to apply a DC voltage to the edge ring 24 according to the current value i (that is, the state of the deposit on the edge ring 24) as shown in FIG. 5, and controls the timing of applying the DC voltage. At this time, when the control unit 200 determines that the DC voltage has been applied to the edge ring 24 in the determination of whether to end the processing in step S15 of FIG. 5, it determines that the processing of FIG. 5 is ended.

When the voltage application control process of the edge loop of FIG. 5 ends, it returns to FIG. 10 and executes the correction process (step S20). An example of correction processing will be described with reference to FIG. 11. When this correction process is started, the control unit 200 acquires the value of the direct current voltage (DC voltage) applied to the edge ring 24 (step S21). Next, the control unit 200 calculates the difference between the current DC voltage value and the previous DC voltage value among the DC voltage values applied to the edge ring 24 (step S22). Furthermore, the acquisition interval between the current DC voltage value and the previous DC voltage value can be set arbitrarily. In addition, it is not limited to the difference between the current DC voltage value and the previous DC voltage value, but may also be the difference between the current DC voltage value and the previous DC voltage value or before. For example, it is also possible to use the difference between the current DC voltage value and the average value of the previous and last DC voltage values.

Next, the control unit 200 refers to the memory which stores the relevant information of the difference of the DC voltage applied to the edge ring 24 and the correction value of the HF power and the LF power as shown in FIG. 9(b), and calculates the difference relative to the value of the DC voltage The correction value of the HF power and LF power (step S23). Furthermore, the example of the relevant information in FIG. 9(b) is an example of information showing the correlation between the DC voltage applied to the edge ring 24 and the correction value of the process parameter, and is not limited to this. The above-mentioned related information can be the information that represents the correlation between the current DC voltage value and the variation (difference) of the previous DC voltage value and the correction value of the process parameter, or the information that represents the current DC voltage value and the process parameter Information related to the correction value. In the latter case, skip step S22. In step S3, refer to the relevant information stored in the memory to calculate the correction value of HF power and the correction of LF power for the current DC voltage value obtained in step S21. Value.

Then, the control unit 200 subtracts the corrected value of the HF power calculated in step S23 from the set value of the HF power set in the recipe, and sets it as the corrected HF power (step S24). Also, subtract the correction value of the LF power calculated in step S23 from the setting value of the LF power set in the recipe, and set it as the corrected LF power (step S24).

Then, the control unit 200 applies the corrected HF power and the corrected LF power. The control unit 200 controls other process conditions to the set values set in the recipe, executes plasma processing (step S25), ends this correction processing, returns to FIG. 10 and ends the overall processing.

As described above, according to the correction processing of the present embodiment, by intermittently controlling the timing of applying the DC voltage to the edge ring 24, the consumption of the edge ring 24 can be suppressed. In addition, when a DC voltage is applied to the edge ring 24, the increase in the etching rate of the center portion of the wafer W can be suppressed by modifying the process parameters (such as HF power, etc.) according to the applied DC voltage. Thereby, it is possible to suppress the edge ring 24 from being consumed while suppressing the inclination of the edge of the wafer W due to the DC voltage applied to the edge ring 24, and to suppress the increase in the etching rate at the center of the wafer W. The deposits on the edge ring 24 are removed.

In particular, in the very low temperature etching in which the temperature of the mounting table 16 is controlled to, for example, tens of degrees below zero to about one hundred tens of degrees below zero, the deposition amount of by-products generated by etching increases. Therefore, the processing method of this embodiment can be used as a more effective technique in the ultra-low temperature etching. However, of course, the processing method of this embodiment is not limited to ultra-low temperature etching.

It should be considered that the processing method and the plasma processing apparatus of one of the embodiments disclosed this time are illustrative in all aspects and not restrictive. The above-mentioned embodiment can be changed and improved in various forms without departing from the scope of the attached patent application and the spirit thereof. The matters described in the plural embodiments described above may also adopt other configurations within the scope of non-contradictory, and can be combined within the scope of non-contradictory.

The voltage applied to the edge ring 24 is not limited to a DC voltage, and may be an AC voltage. When an AC voltage is applied to the edge ring 24, an AC power source is connected via a matching device and a DC blocking capacitor instead of the variable DC power source 55. The output of the AC power supply has the ions in the plasma can follow the AC of the frequency f, that is, the low-frequency or high-frequency AC AC that is lower than the ion plasma frequency, which can make its power, voltage peak or effective value variable. When the AC voltage from the AC power source is applied to the edge ring 24 through the DC blocking capacitor during the etching process, a self-bias voltage is generated in the edge ring 24. That is, a negative DC voltage component is applied to the edge ring 24.

In the embodiment of the present invention, the etching process is described, but it is not limited to this. The embodiment relates to the process of forming a deposited film on the processed substrate in the etching process, and the process of forming a deposited film on the processed substrate such as chemical vapor deposition (CVD, Chemical Vapor Deposition) or physical vapor deposition (PVD, Physical Vapor Deposition) The same effect can be obtained in the middle.

In addition, the deposition process of the present invention has been described by using a carbon-containing processing gas, but it is not limited to this. For example, when using a plasma that can generate a process gas of a deposition precursor (precursor) like TEOS (tetraethoxysilane) gas used in CVD, it is also deposited on the edge ring in the same way. In addition, in PVD, the precursor produced from the target by plasma sputtering is deposited on the processing substrate, and similarly deposited on the edge ring. That is, similar to the presence of a depositable precursor in the plasma space, it is also deposited on the edge ring. In these processes, it is also possible to prevent deposition on the edge ring by applying a voltage to the edge ring, and to minimize the consumption of the edge ring by observing the state of the deposited film and adjusting the applied voltage.

The plasma processing device of the present invention can be applied to capacitively coupled plasma (CCP, Inductively Coupled Plasma), inductively coupled plasma (ICP, Inductively Coupled Plasma), radial line slot antenna (RLSA, Radial Line Slot Antenna), electronic Electron Cyclotron Resonance Plasma (ECR), Helicon Wave Plasma (HWP), any type of plasma processing device.

In this specification, the wafer W has been cited as an example of the object to be processed. However, the object to be processed is not limited to this, and may be various substrates and printed substrates used in FPD (Flat Panel Display).

1: Plasma processing device 10: Chamber 12: Insulating plate 14: Support table 16: Mounting table 16a: Base 20: Electrostatic chuck 20a: First electrode 20b: Insulating layer 22: Power supply 24: Edge ring 26: Insulator ring 28: Refrigerant chamber 30a: Piping 30b: Piping 32: Gas supply line 34: Upper electrode 36: Electrode plate 37: Gas ejection hole 38: Electrode support 40a: Gas diffusion chamber 40b: Gas diffusion chamber 41a: Gas passage hole 41b : Gas orifice 42: Shielding member 46: Matching device 47: Feeder 48: Second high frequency power supply 50: Second variable power supply 55: First variable power supply 62: Gas inlet 64: Gas supply pipe 66: Process gas supply source 68: Mass flow controller 70: On-off valve 80: Exhaust port 82: Exhaust pipe 83: Partition 84: Exhaust device 85: Loading and unloading outlet 86: Gate valve 88: Matching device 89: Feeder 90 : First high-frequency power supply 100: Ammeter 101: Argon ion 102: Radical 200: Control part A: Line A1: Arrow A2: Arrow B: Line C: Line d: Deposit i1: Current value I ₁ : Threshold value I ₂ : Threshold i2: Current value S10: Step S11: Step S12: Step S13: Step S14: Step S15: Step S20: Step S21: Step S22: Step S23: Step S24: Step S25: Step Rd: Resistance component Rs: Resistance Component Rs': resistance component Vdc: DC voltage/potential difference W: wafer

Fig. 1 is a schematic sectional view showing an example of a plasma processing apparatus according to an embodiment. Figure 2 (a) and (b) are diagrams for explaining the deposition process and the sputtering process. Figure 3 (a) and (b) are diagrams showing an example of a monitoring method for the deposition state of the edge ring. Fig. 4 is a diagram showing an example of the correlation between the monitoring value of an embodiment and the deposition state of the edge ring. Fig. 5 is a flowchart showing an example of voltage application control processing in an embodiment. 6(a) and (b) are diagrams showing an example of the effect of voltage application control in an embodiment. Fig. 7 is a diagram showing an example of the etching rate when a voltage is applied to the edge ring. Fig. 8 is a diagram showing an example of the etching rate when a voltage is applied to the edge ring. Figures 9(a) and (b) are diagrams showing an example of the processing result of the processing method of an embodiment. Fig. 10 is a flowchart showing an example of a processing method of an embodiment. Fig. 11 is a flowchart showing an example of correction processing in an embodiment.

A: Line

B: line

Claims (10)

A processing method that uses a plasma processing device to treat an object to be processed, the plasma processing device comprising: a placing table for placing the object to be processed in a chamber; and a peripheral member that is arranged around the placing table ; And the first power supply, which applies a voltage to the peripheral member; and the processing method includes the following steps: While applying a voltage from the first power source to the outer peripheral member, exposing the processed body to the plasma with depositing precursors; and During the process of exposure to the plasma, the state of the deposited film containing carbon deposited on the outer peripheral member is observed, and the voltage applied to the outer peripheral member is controlled based on the observed state of the deposited film. For example, the processing method of claim 1, which includes the following processes: Refer to the memory part that stores the relevant information of the voltage applied to the peripheral component and the correction value of the process parameter, and modify the process parameter based on the voltage applied to the peripheral component; and Plasma processing is performed in accordance with the process conditions including the modified process parameters described above. Such as the processing method of claim 2, where The above-mentioned process parameters are the process conditions for the variation of the plasma density generated. Such as the processing method of claim 2 or 3, where The above-mentioned process parameters are process conditions that change the etching rate. Such as the processing method of any one of claims 2 to 4, where The above process parameters are the high frequency power of the first frequency applied from the first high frequency power supply, the high frequency power of the second frequency lower than the first frequency applied from the second high frequency power supply, the gas supplied to the chamber, And at least any one of the voltages applied from the second power source to the upper electrode opposite to the mounting table. Such as the processing method of any one of claims 1 to 5, where The step of controlling the voltage applied to the outer peripheral member is to apply a voltage to the outer peripheral member when the observed state of the deposited film is above a specific threshold value. Such as the processing method of any one of claims 1 to 6, where The step of controlling the voltage applied to the outer peripheral member is to not apply the voltage to the outer peripheral member when the observed state of the deposited film is less than a specific threshold value. Such as the processing method of any one of claims 1 to 7, where The plasma with the above-mentioned depositional precursor is produced by a processing gas capable of generating the depositional precursor. Such as the processing method of claim 8, where The above process gas contains carbon. A plasma processing device, comprising: a mounting table for mounting a body to be processed in a chamber; a peripheral member arranged around the mounting table; a first power supply that applies a voltage to the peripheral member; and a control unit; And The aforementioned control unit performs the following processes: While applying a voltage from the first power source to the outer peripheral member, exposing the object to be processed to the plasma containing carbon processing gas; During the process of exposing to the plasma of the process gas, observe the state of the deposited film containing carbon deposited on the peripheral member, and control the application of the deposited film to the peripheral member based on the observed state of the deposited film Voltage; and By referring to the memory part that stores the relevant information of the voltage applied to the peripheral member and the correction value of the process parameter, the process parameter is corrected based on the voltage applied to the peripheral member.

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