JP2020112988A - Image processing device, image processing device malfunction detecting method and program - Google Patents

Abstract

To detect a malfunction of an image processing device including multiple processing units during an operation.SOLUTION: An image processing device according to an aspect of the disclosed technique is an image processing device that executes image processing, and includes: an image processing unit that includes multiple processing units which execute the image processing; a dual-lock-step unit that includes a smaller number of dual-lock-step processing units than the multiple processing units, the dual-lock-step processing units executing the image processing same as that of the multiple processing units in parallel; a malfunction detecting unit that detects a malfunction of the image processing device on the basis of the processing result by a predetermined processing unit among the multiple processing units, and of the processing result by the dual-lock-step processing unit; and a changing unit that changes the predetermined processing unit for each predetermined time period.SELECTED DRAWING: Figure 3

Description

The present application relates to an image processing device, a failure detection method for an image processing device, and a program.

2. Description of the Related Art Conventionally, an image processing apparatus used in an in-vehicle field or the like requires a function of detecting a failure in order to ensure functional safety.

As an image processing device having a failure detection function, there is disclosed an image processing device that determines whether or not an expected value image held in a memory and an image after processing match and detects a failure of the image processing device (for example, See Patent Document 1).

Further, there is disclosed one in which there are a plurality of cores to be monitored, and an error is detected by a number of lockstep cores smaller than the number of cores, and a failure of each core is monitored (for example, refer to Patent Document 2).

However, since the apparatus of Patent Document 1 can only compare with the expected value image of the predetermined image pattern, the image processing apparatus in which the image pattern is randomly changed from the image sensor and the image is input is different from the image processing apparatus. It was sometimes difficult to detect a failure during operation.

Further, since the device of Patent Document 2 can operate only one lockstep core, it may be difficult to detect a failure of a plurality of cores (processing units) included in the image processing device during operation. It was

The present invention has been made in view of the above points, and an object thereof is to detect a failure of an image processing apparatus including a plurality of processing units during operation.

An image processing apparatus according to an aspect of the disclosed technology is an image processing apparatus that executes image processing, and is the same as the image processing section that includes a plurality of processing sections that execute the image processing. A dual lockstep unit that executes the image processing in parallel and includes a smaller number of dual lockstep processing units than the plurality of processing units; a processing result by a predetermined processing unit of the plurality of processing units; A failure detection unit that detects a failure of the image processing device based on the processing result by the lockstep processing unit, and a switching unit that switches the predetermined processing unit for each predetermined period.

According to the embodiment of the present invention, it is possible to detect a failure of an image processing apparatus including a plurality of processing units during operation.

4A and 4B are diagrams illustrating a dual lockstep system, FIG. 7A is a diagram illustrating image input/output to and from an image processing circuit, and FIG. 7B is a diagram illustrating image input/output to and from an image processing circuit and a dual lockstep circuit. is there. It is a block diagram which shows an example of the hardware constitutions of the control system which concerns on embodiment. It is a block diagram showing an example of functional composition of an image processing device concerning a 1st embodiment. Is a diagram illustrating an example of an operation of the image processing apparatus according to the first embodiment, (a) is a diagram showing a case to be compared with the processing result of the dual lockstep circuit processing result of the arithmetic circuit 21 _1, (b ) is a diagram showing a case to be compared with the processing result of the dual lockstep circuit processing result of the arithmetic circuit 21 _2. It is a figure explaining the frame period in the image processing apparatus which concerns on 1st Embodiment. 6 is a flowchart illustrating an example of operation of the image processing apparatus according to the first exemplary embodiment. It is a figure explaining operation of an image processing device concerning a comparative example. It is a block diagram which shows an example of a functional structure of the image processing apparatus which concerns on 2nd Embodiment. 9 is a flowchart illustrating an example of operation of the image processing apparatus according to the second exemplary embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and duplicate description may be omitted.

The image processing apparatus according to the embodiment is an apparatus that performs various image processing by an image processing unit on an image input from an image sensor or the like, and compares processing results by the image processing unit and the dual lockstep unit. By doing so, the apparatus has a function of detecting a failure of the image processing apparatus.

<Dual Lockstep function>
A dual lockstep method is known as a method for detecting a failure of an image processing apparatus or the like. Dual lockstep is one of safety mechanisms that monitor the operation of a processor such as a CPU (Central Processing Unit). In dual lockstep, the same processing is executed by each processor while synchronizing the clocks of the plurality of processors. Then, the processing result of each processor is compared by the comparison circuit, and the failure is detected.

FIG. 1 is a diagram for explaining such a dual lockstep system. (A) is a figure explaining the input/output of the image with respect to an image processing circuit, (b) is a figure explaining the input/output of the image with respect to an image processing circuit and a dual lockstep circuit.

As shown in FIG. 1A, the image input to the image processing circuit 1 is subjected to predetermined image processing by the image processing circuit 1 and output. On the other hand, in FIG. 1B, the same image is input to the image processing circuit 1 and the dual lockstep circuit 2.

The image processing circuit 1 and the dual lockstep circuit 2 execute the same image processing while synchronizing the clocks, and output the respective processing results to the comparison circuit 3. The comparison circuit 3 compares the processing results of the image processing circuit 1 and the dual lockstep circuit 2 and can detect the presence/absence of a failure depending on whether or not they match. Further, it is possible to detect a failure of the image processing circuit 1 in operation.

In this way, by using the dual lockstep circuit 2, it is possible to detect a failure of the image processing circuit 1 and ensure the reliability of image processing by the image processing circuit 1.

<Control system configuration>
Next, the configuration of the control system including the image processing apparatus according to the embodiment will be described. The control system is a system that is mounted on a vehicle such as an automobile and performs vehicle control such as brake control according to the processing result by the image processing device.

FIG. 2 is a block diagram showing an example of the hardware configuration of the control system. As shown in FIG. 2, the control system 100 includes an image sensor 10, an image processing device 20, a CPU 30, and a memory 40.

The image sensor 10 is an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor Device) that captures an image, and outputs the captured image to the image processing device 20.

The image processing device 20 is configured by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) and an FPGA (Field-Programmable Gate Array) capable of executing image processing. The image processing device 20 includes an arithmetic circuit group 21 and a dual lockstep circuit group 22.

The arithmetic circuit group 21 is composed of a plurality of electric circuits that realize an image processing function necessary for the CPU 30 to control the vehicle with respect to the image input from the image pickup device 10. The arithmetic circuits included in the arithmetic circuit group 21 are the same circuit, and the respective arithmetic circuits execute the same processing in parallel, so that the specifications such as the processing speed can be satisfied.

The dual lockstep circuit group 22 is composed of a plurality of electric circuits, and each dual lockstep circuit included in the dual lockstep circuit group 22 performs the same processing in parallel as each arithmetic circuit included in the arithmetic circuit group 21. It is feasible.

The processing result by the dual lockstep circuit group 22 is compared with the processing result by each arithmetic circuit included in the arithmetic circuit group 21, and is used for ensuring reliability of the arithmetic circuit group 21 and detecting a failure. Here, in the present embodiment, the number of dual lockstep circuits included in the dual lockstep circuit group 22 is smaller than the number of arithmetic circuits included in the arithmetic circuit group 21. The details will be described later.

The image processed by the arithmetic circuit group 21 is output to the CPU 30 and an external device.

Examples of the external device include a post-process image processing device, a CPU, and a display device. The external device can execute post-process image processing, control processing, and the like according to the processing result input from the image processing apparatus 20, and can display the processed image.

The CPU 30 is an arithmetic device that controls the overall operation of the control system 100. The CPU 30 controls the vehicle based on the information included in the image input from the image processing device 20. Further, the CPU 30 can centrally control the input/output of data and signals such as holding the processed image in the memory 40.

The memory 40 is a storage device such as a semiconductor memory that holds data such as image data. It should be noted that the configuration of the control system 100 shown in FIG. 1 is an example and may have another configuration.

Very high reliability is required for vehicle brake control and the like by the control system 100, and processing by the image processing device 20 that is the basis of control by the control system 100 is also required to have very high reliability. Therefore, the image processing apparatus 20 has a failure detection function based on the dual lockstep method.

[First Embodiment]
<Functional configuration of the image processing apparatus according to the first embodiment>
The functional configuration of the image processing apparatus according to the first embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating an example of the functional configuration of the image processing apparatus according to this embodiment. All or some of the functional blocks shown in FIG. 3 may be functionally or physically dispersed/coupled in arbitrary units.

As shown in FIG. 3, the image processing device 20 includes an image input unit 23, an image processing unit 24, a dual lockstep unit 25, a failure detection unit 26, a switching unit 27, and a processing result output unit 28. Have. The image captured by the image sensor 10 is input to the image processing unit 24 and the dual lockstep unit 25 via the image input unit 23.

The image processing unit 24 is composed of the arithmetic circuit group 21 and the like, and has a plurality of processing units. The plurality of processing units included in the image processing unit 24 execute the same image processing necessary for the CPU 30 to control the vehicle in parallel on the image input from the image sensor 10. Then, the processing result is output to the processing result output unit 28.

Further, of the plurality of processing units included in the image processing unit 24, the processing result by the processing unit that is the target of the failure detection is output to the failure detection unit 26. Here, the processing unit targeted for failure detection is an example of a “predetermined processing unit”.

The dual lockstep section 25 is composed of the dual lockstep circuit group 22 and the like, and has a plurality of dual lockstep processing sections. The plurality of dual lockstep processing units respectively execute the same processing as the plurality of processing units included in the image processing unit 24 in parallel, and output the processing result to the failure detection unit 26.

The failure detection unit 26 is configured by an electric circuit that compares the processing result input from the image processing unit 24 with the processing result input from the dual lockstep unit 25 and determines whether or not they are the same. More specifically, the processing result input by the failure detection unit 26 from the image processing unit 24 is a processing result by a processing unit that is a failure detection target among a plurality of processing units included in the image processing unit 24. Further, the processing result input from the dual lockstep unit 25 by the failure detection unit 26 is a process in which a plurality of dual lockstep processing units included in the dual lockstep unit 25 are targets of failure detection in the image processing unit 24. This is the result of executing the same process as the copy.

When the processing result input from the image processing unit 24 and the processing result input from the dual lockstep unit 25 are the same, the failure detection unit 26 outputs a signal indicating that there is no failure in the processing unit targeted for failure detection. It is output to the processing result output unit 28. If they are not the same, a signal indicating that a failure has occurred in the processing unit targeted for failure detection is output to the processing result output unit 28. That is, the failure detection unit 26 detects the failure of the image processing unit 24 by comparing the processing result of the image processing unit 24 and the processing result of the dual lockstep unit 25, and detects the failure detection result. A signal can be output.

As described above, the number of dual lockstep circuits (an example of a dual lockstep processing unit) is smaller than the number of arithmetic circuits (an example of a processing unit), so that an arithmetic circuit in which the processing result cannot be compared with the dual lockstep circuit occurs. However, the processing result by such an arithmetic circuit is directly output to the processing result output unit 28 without being compared by the failure detection unit 26.

The switching unit 27 is configured by an electric circuit such as a switching circuit, and includes a frame period detection unit 271. The frame period detection unit 271 determines that the time corresponding to the frame period has elapsed when the time measured by counting the clock of the image processing device 20 matches the frame period (frame cycle) of the input image. Detect.

Here, the frame period refers to a period in which pixel data for one frame is input in an image input to the image processing device 20, and is determined according to the specifications of the image sensor 10 or the image processing device 20. .. The frame period detection unit 271 is an example of a “period detection unit”.

The switching unit 27 can access the failure detection unit 26 for each detected frame period and switch the processing unit to be the failure detection target among the plurality of processing units included in the image processing unit 24. In other words, the switching unit 27 can switch the processing unit that compares the processing result with the dual lockstep unit 25 among the plurality of processing units included in the image processing unit 24.

The processing result (output image) by the image processing unit 24 and the failure detection signal are output to the CPU 30 and an external device via the processing result output unit 28.

Next, FIG. 4 is a diagram illustrating an example of operation of the image processing apparatus according to the first embodiment, (a) is compared with the processing result of the dual lockstep circuit processing result of the arithmetic circuit 21 ₁ it is a diagram showing a case is a diagram showing a case to be compared with (b) the processing result of the dual lockstep circuit processing result of the arithmetic circuit 21 _2.

As shown in FIG. 4, the image processing apparatus 20 includes an arithmetic circuit group 21 including arithmetic circuits 21 ₁ , 21 ₂ ,..., 21 _n−1 , 21 _n , which are the same parallel electric circuit, and an arithmetic circuit. and a dual lockstep circuit 22 ₁ is the same electric circuit and arithmetic circuit included in the circuit group 21. Pixel data is input to each of the arithmetic circuits 21 ₁ , 21 ₂ ,..., 21 _n−1 , 21 _n , and the dual lockstep circuit 22 ₁ , and the same image processing is executed in parallel, and after processing, The processing result of the image and the like is output from the image processing apparatus 20. For example, when the arithmetic circuit group 21 performs a filter calculation of 3×3 pixels, the arithmetic circuit group 21 is composed of nine arithmetic circuits 21 ₁ , 21 ₂ ,..., 21 ₈ and 21 _9. .. Then, 3 × 3 pixels (nine pixels) of pixel data calculating circuit _{21 1,} 21 2, _..., are input to each of the 21 8, 21 _9, the image processing is executed in parallel.

In FIG. 4A, it is determined whether the processing result of the arithmetic circuit 21 _{1 and} the processing result of the dual lockstep circuit 22 ₁ match. On the other hand, in FIG. 4 (b), the calculation circuit to be compared to a dual lockstep circuit 22 ₁ is switched to the arithmetic circuit 21 _2, arithmetic circuit 21 _{and second} processing result and dual lockstep circuit 22 ₁ by the processing result matches It is determined whether or not to do it. Switching of the arithmetic circuits to be compared by the dual lockstep circuit 22 ₁ is performed for each frame period.

Since the arithmetic circuits to be compared are switched for each frame period, it is not possible to detect all failures of the arithmetic circuits 21 ₁ , 21 ₂ ,..., 21 _n−1 , 21 _n within one frame period. For example, as shown in FIG. 4, when the number of arithmetic circuits is n and the number of dual lockstep circuits is one, it is possible to detect the failure of all arithmetic circuits every n frames. It is preferable to determine the number of dual lockstep circuits according to the required period for detecting the failure of all the arithmetic circuits.

Next, FIG. 5 is a diagram illustrating a frame period in the image processing apparatus according to the present embodiment. In FIG. 5, the horizontal axis represents time. The invalid period (blanking period) and the valid image period are included in the frame period T of one image.

In the present embodiment, the frame period T is detected by the frame period detection unit 271 and the switching unit 27 switches the arithmetic circuit to be compared with the dual lockstep circuit once every frame period T.

FIG. 6 is a flowchart showing an example of the operation of the image processing apparatus according to this embodiment.

First, in step S61, the image input unit 23 outputs the image input from the image sensor 10 to the image processing unit 24 and the dual lockstep unit 25.

Subsequently, in step S62, the image processing unit 24 executes predetermined image processing and outputs the processing result to the processing result output unit 28. Further, the image processing unit 24 outputs, to the failure detection unit 26, a processing result of a processing unit that is a target of failure detection among the plurality of processing units (arithmetic circuit group 21) included in the image processing unit 24.

Further, in parallel with the image processing by the image processing unit 24, the dual lockstep unit 25 executes the same image processing as the image processing unit 24, and outputs the processing result to the failure detection unit 26.

Subsequently, in step S63, the failure detection unit 26 compares the processing result input from the image processing unit 24 with the processing result input from the dual lockstep unit 25, and a plurality of processing units included in the image processing unit 24. Among them, the failure of the processing unit that is the target of the failure detection is detected. Then, a signal indicating the failure detection result is output to the processing result output unit 28.

Subsequently, in step S64, the processing result output unit 28 outputs the input image-processed image and the failure detection result to the CPU 30 and the external device.

Subsequently, in step S65, the frame period detection unit 271 determines whether or not the frame period has elapsed. When it is determined in step S65 that the frame period has not elapsed (step S65, No), the process of step S65 is repeated. On the other hand, when it is determined in step S65 that the frame period has elapsed (step S65, Yes), the process proceeds to step S66.

Subsequently, in step S66, the switching unit 27 accesses the failure detection unit 26 and switches the processing unit that is the target of the failure detection among the plurality of processing units included in the image processing unit 24.

Subsequently, in step S67, the image processing device 20 determines whether or not to end the process. Alternatively, the image processing apparatus 20 inputs a signal for determining whether or not to end the processing from the CPU 30.

If it is determined in step S67 that the processing is to be ended (step S67, Yes), the image processing apparatus 20 ends the image processing. On the other hand, when it is determined that the process is not to be ended (step S67, No), the process returns to step S61, and the processes after step S61 are continued.

In this way, the image processing apparatus 20 can execute the image processing and also the failure detection processing of the image processing apparatus 20.

<Effect>
In the present embodiment, the image processing device 20 executes the same image processing as the image processing unit 24 including a plurality of processing units (arithmetic circuit group 21) that execute the image processing in parallel and the plurality of processing units. , A dual lockstep processing unit 25 having a smaller number of dual lockstep processing units (dual lockstep circuit group 22) than the plurality of processing units, processing results by a predetermined processing unit of the plurality of processing units, and dual lockstep processing A failure detection unit 26 that detects a failure of the image processing device based on a processing result by the unit, and a switching unit 27 that switches a predetermined processing unit for each frame period of an input image.

Since the failure of the image processing apparatus 20 is detected based on the result of parallel execution of the same image processing by the plurality of processing sections and the dual lockstep processing section, the failure of the image processing apparatus 20 in operation can be detected. ..

Further, while switching the predetermined processing unit of the plurality of processing units by the switching unit 27, the failure is detected by comparing the processing result by the predetermined processing unit and the processing result by the dual lockstep processing unit. Therefore, all failures of the plurality of processing units included in the image processing apparatus 20 can be detected during operation.

Here, an image processing apparatus according to a comparative example will be described with reference to FIG. 7.

FIG. 7 is a diagram for explaining the operation of the image processing apparatus according to the comparative example. As shown in FIG. 7, the image processing apparatus 50 includes an arithmetic circuit group 51 including arithmetic circuits 51 ₁ , 51 ₂ ,..., 51 _n−1 , 51 _n , which are the same parallel electric circuit, and an arithmetic circuit. And a dual lockstep circuit group 52 composed of dual lockstep circuits 52 ₁ , 52 ₂ ,..., 52 _n-1 , 52 _n , which are the same electric circuits as the arithmetic circuits included in the circuit group 51. ing. Here, the number of arithmetic circuits included in the arithmetic circuit group 51 is equal to the number of dual lockstep circuits included in the dual lockstep circuit group 52.

Arithmetic circuits _{51 1, 51 2, ···,} 51 n-1, 51 n, and dual lockstep circuit _{52 1,} 52 2, _{..., 52} to the _n-1, 52 _n, respectively the pixel data is input Then, the same image processing is performed in parallel, and the processing result of the processed image or the like is output from the image processing device 50. Arithmetic circuits _{51 1, 51 2, ···,} 51 n-1, 51 n by the processed image is output from the image processing apparatus 50.

Further, it is determined whether or not the processing result by the arithmetic circuit 51 ₁ and the processing result by the dual lockstep circuit 52 ₁ match, and the processing result by the arithmetic circuit 51 ₂ matches the processing result by the dual lockstep circuit 52 _2. It is determined whether or not to do it. Further, it is determined whether or not the processing result by the arithmetic circuit 51 _n-1 matches the processing result by the dual lockstep circuit 52 _n-1 , and the processing result by the arithmetic circuit 51 _n and the processing by the dual lockstep circuit 52 _n are determined. It is determined whether or not the result matches. Based on the determination result, the failure of the arithmetic circuits 51 ₁ , 51 ₂ ,..., 51 _n−1 , 51 _n is detected.

With such a configuration of the image processing device 50, it is possible to detect failures in all the arithmetic circuits included in the arithmetic circuit group 51. However, since the same number of dual lockstep circuits as the arithmetic circuits included in the arithmetic circuit group 51 are provided, the circuit scale becomes large.

In the present embodiment, a predetermined processing unit that is a target of failure detection is switched for each frame period of an input image. Therefore, even if the same number of dual lockstep processing units as a plurality of processing units are not provided, It is possible to detect failures in all the processing units (arithmetic circuits 21 ₁ , 21 ₂ ,..., 21 _n−1 , 21 _n ) included in the processing units (arithmetic circuit group 21 ). Therefore, it is possible to detect a failure of the image processing device 20 including a plurality of processing units during operation without increasing the circuit scale.

[Second Embodiment]
Next, an image processing apparatus according to the second embodiment will be described. Note that the description of the same components as those of the above-described embodiment will be omitted.

FIG. 8 is a block diagram showing an example of the functional configuration of the image processing apparatus according to this embodiment. The image processing device 20a has a switching unit 27a.

The switching unit 27a is configured by an electric circuit such as a switching circuit, and includes a horizontal blanking period detection unit 272. The horizontal blanking interval detection unit 272 has passed the time corresponding to the horizontal blanking interval when the time measured by counting the clock of the image processing device 20a matches the horizontal blanking interval of the input image. Detect that.

Here, the horizontal blanking period refers to a period in which pixel data for one line in the horizontal direction is input in the image input to the image processing device 20a, and depends on the specifications of the image sensor 10 or the image processing device 20a. Has been decided. The horizontal blanking period detection unit 272 is an example of a “period detection unit”.

The switching unit 27a can access the failure detection unit 26 for each detected horizontal blanking period and switch the processing unit that is the target of failure detection among the plurality of processing units included in the image processing unit 24. In other words, the switching unit 27a can switch the processing unit that compares the processing result with the dual lockstep processing unit among the plurality of processing units included in the image processing unit 24.

FIG. 9 is a flowchart showing an example of the operation of the image processing apparatus according to this embodiment. The processes of steps S91 to S94 of FIG. 9 are the same as the processes of steps S61 to S64 of FIG. 6, so description thereof will be omitted.

In step S95, the horizontal blanking period detection unit 272 determines whether the horizontal blanking period has elapsed. When it is determined in step S95 that the horizontal blanking period has not elapsed (step S95, No), the process of step S95 is repeated. On the other hand, when it is determined in step S95 that the horizontal blanking period has elapsed (step S95, Yes), the process proceeds to step S96.

Subsequently, in step S96, the switching unit 27a accesses the failure detection unit 26 and switches the processing unit that is the target of the failure detection among the plurality of processing units included in the image processing unit 24.

Subsequently, in step S97, the image processing device 20a determines whether or not to end the process. Alternatively, the image processing apparatus 20a inputs from the CPU 30 a signal for determining whether or not to end the processing.

When it is determined in step S97 that the processing is to be ended (step S97, Yes), the image processing apparatus 20a ends the image processing. On the other hand, when it is determined that the process is not to be ended (step S97, No), the process returns to step S91, and the processes after step S91 are continued.

In this way, the image processing apparatus 20a can execute the image processing and also the processing of detecting the failure of the image processing apparatus 20a.

In the present embodiment, a predetermined processing unit that is a target of failure detection is switched for each horizontal blanking period of an input image. As a result, it is possible to switch the predetermined processing unit that is the target of failure detection in a shorter period than the frame period, and it is possible to perform failure detection of all arithmetic circuits in a shorter period.

The other effects are similar to those described in the above embodiment.

The present invention is not limited to the above specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The embodiment also includes a failure detection method for the image processing apparatus. For example, a failure detection method for an image processing apparatus is a failure detection method for an image processing apparatus that executes image processing, and includes an image processing step including a plurality of processing steps for executing the image processing in parallel, and the plurality of processing steps. The same image processing as the process is executed in parallel, a dual lockstep process including a smaller number of dual lockstep process steps than the plurality of process steps, and a processing result by a predetermined process step of the plurality of process steps And a failure detection step of detecting a failure of the image processing apparatus based on the processing result of the dual lockstep processing step, and a switching step of switching the predetermined processing step for each predetermined period.

With such a failure detection method for an image processing apparatus, it is possible to obtain the same effect as the above-described image processing apparatus.

Further, the embodiment also includes a program. For example, the program is a program that is executed by an image processing device that executes image processing, and is the same as the image processing unit that includes a plurality of processing units that execute the image processing in parallel, and the plurality of processing units. A dual lockstep unit that executes the image processing in parallel in parallel with a number of dual lockstep processing units that is smaller in number than the plurality of processing units; a processing result by a predetermined processing unit of the plurality of processing units; It functions as a failure detection unit that detects a failure of the image processing device based on the processing result by the lockstep processing unit, and a switching unit that switches the predetermined processing unit for each predetermined period.

With such a program, it is possible to obtain the same effects as those of the image processing apparatus described above.

DESCRIPTION OF SYMBOLS 1 image processing circuit 2 dual lockstep circuit 3 comparison circuit 10 image pickup device 20, 20a image processing device 21 arithmetic circuit group 22 dual lockstep circuit group 23 image input unit 24 image processing unit 25 dual lockstep unit 26 failure detection unit 27, 27a Switching unit 271 Frame period detection unit 272 Horizontal blanking period detection unit 28 Processing result output unit 100 Control system T frame period

JP 2012-058123 A JP, 2016-157247, A

Claims (6)

An image processing device that executes image processing,
An image processing unit including a plurality of processing units for executing the image processing,
A dual lockstep unit that executes the same image processing as the plurality of processing units in parallel, and includes a dual lockstep processing unit that is smaller in number than the plurality of processing units,
A failure detection unit that detects a failure of the image processing device based on a processing result by a predetermined processing unit of the plurality of processing units and a processing result by the dual lockstep processing unit,
An image processing apparatus comprising: a switching unit that switches the predetermined processing unit for each predetermined period. The image processing apparatus according to claim 1, further comprising a period detection unit that detects a lapse of time corresponding to the predetermined period. The image processing device according to claim 2, wherein the period detection unit detects a frame period of an image input to the image processing device. The image processing device according to claim 2, wherein the period detection unit detects a horizontal blanking period of an image input to the image processing device. A method for detecting a failure of an image processing apparatus that executes image processing, comprising:
An image processing step including a plurality of processing steps for executing the image processing;
A dual lockstep process comprising a plurality of dual lockstep process steps, the number of which is smaller than that of the plurality of process steps, for executing the same image processing in parallel as the plurality of process steps;
A failure detection step of detecting a failure of the image processing device based on a processing result of a predetermined processing step of the plurality of processing steps and a processing result of the dual lockstep processing step,
A failure detection method for an image processing apparatus, comprising: a switching step of switching the predetermined processing steps for each predetermined period. A program executed by an image processing device that executes image processing,
Computer,
An image processing unit including a plurality of processing units that execute the image processing,
A dual lockstep unit that includes the same number of dual lockstep processing units as the plurality of processing units in parallel and that performs the same image processing in parallel,
A failure detection unit that detects a failure of the image processing device based on a processing result by a predetermined processing unit of the plurality of processing units and a processing result by the dual lockstep processing unit,
A switching unit that switches the predetermined processing unit for each predetermined period,
Program to function as.

Images