JP2020098847A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving reliability of a product.SOLUTION: A semiconductor device includes: a plurality of insulating layers formed on a semiconductor substrate; a plurality of wiring layers provided on each of the plurality of insulating layers; and an electrode pad formed on an uppermost wiring layer among the plurality of wiring layers to which bonding wires are connected. A crack detection unit arranged so as to detect conduction and non-conduction between different wiring layers is provided in the insulating layer having high crack occurrence probability under the electrode pad. The crack detection unit is arranged at a position overlapping with an area where the electrode pad and bonding wires are connected in a plan view.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device and a method for detecting cracks in its insulating layer.

In recent years, as semiconductor elements have become finer and faster, new materials for insulating layers have been developed. For example, an insulating layer made of a Low-k material such as a porous material has a lower mechanical strength than an insulating layer made of SiO ₂ or a High-k material having a relative dielectric constant higher than that of SiO _{2, and} thus has an insulating property. Cracks are easily generated in the layer.

Under such a situation, when a physical analysis was performed on a defect in the reliability evaluation of the semiconductor device including the semiconductor chip, a crack was generated in the insulating layer below the electrode pad arranged on the semiconductor chip.

For example, Patent Document 1 discloses a semiconductor device that detects a defect that occurs under an electrode pad of a semiconductor chip. By arranging a wiring for detection under the electrode pad, the crack detection circuit can detect a disconnection of the wiring or a short circuit with the electrode pad.

JP, 2017-157719, A

Patent Document 1 does not disclose in which region the cracks occurring in the insulating layer under the electrode pad are frequently generated. In the crack detection using the wiring, a crack that crosses the wiring layer can be detected, but a crack in the insulating layer extending in the direction along the main surface of the insulating layer may not be detected. That is, the semiconductor device described in Patent Document 1 has room for improvement in terms of reliability.

Semiconductor devices are required to have high reliability, but there is a problem in that high reliability cannot be ensured. Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

The semiconductor device according to the first embodiment includes a plurality of insulating layers formed on a semiconductor substrate, a plurality of wiring layers respectively provided on the plurality of insulating layers, and an uppermost wiring of the plurality of wiring layers. A via formed in a layer and including an electrode pad to which a bonding wire is connected, and a via arranged to detect impedance between different wiring layers in a region of an insulating layer below the electrode pad where cracks frequently occur. The via is arranged at a position overlapping with a region where the electrode pad and the bonding wire are connected in a plan view.

In the semiconductor device according to the second embodiment, as the region of the insulating layer below the electrode pad in which the vias are arranged, the first via density region and the second via density lower than the first via density region are used. The via having the area of the via density and being arranged to detect the impedance between different wiring layers is arranged at a position overlapping with the second via density area in a plan view.

The semiconductor device according to the third embodiment includes a semiconductor chip, a package substrate on which the semiconductor chip is mounted, and a resin formed on the package substrate so as to cover the semiconductor chip, and the semiconductor chip has a plurality of electrode pads. , A via for detecting conduction and non-conduction between different wiring layers, the via is arranged at a position overlapping with a region where the electrode pad and the bonding wire are connected in a plan view, and the electrode pad is a semiconductor chip. Are arranged in at least one corner area of the.

The semiconductor device according to the fourth embodiment includes an electrode pad to which a bonding wire is connected, a detection circuit capable of detecting impedance, a first electrode electrically connected to the detection circuit, and a wiring different from the first electrode. A second electrode formed in a layer and connected to a ground potential, the second electrode is formed to face the first electrode, and the first electrode and the second electrode are an electrode pad and a bonding wire in a plan view. Is arranged at a position overlapping with the area to which is connected.

The reliability of the semiconductor device can be improved.

FIG. 1 is a block diagram showing an example of a crack detecting device according to the first embodiment. FIG. 2 is a plan view showing an example of the arrangement of the crack detectors according to the first embodiment. FIG. 3 is a cross-sectional view taken along the line A-A′ of FIG. FIG. 4 is a cross-sectional view showing an example of the connection between the crack detection circuit and the crack detection via. FIG. 5 is a diagram showing an example of a crack that can occur in the cross-sectional view of FIG. FIG. 6 is a circuit diagram showing an example of a circuit configuration of the register shown in FIG. FIG. 7 is a plan view showing an example of regions having different via densities according to the second embodiment. FIG. 8 is a sectional view taken along line B-B′ of FIG. 7. FIG. 9 is a diagram showing an example of cracks that can occur in the cross-sectional view of FIG. FIG. 10 is a cross-sectional view showing an example of the arrangement of the crack detection unit according to the embodiment, which is arranged in a region where cracks frequently occur. FIG. 11 is a diagram showing a change in outer shape due to the temperature of the resin in the semiconductor device according to the third embodiment. FIG. 12 is a plan view showing an example of the arrangement of crack detectors in the semiconductor chip according to the third embodiment. FIG. 13 is a plan view showing an example of the arrangement of crack detection units in two semiconductor chips according to the modification of the third embodiment. FIG. 14 is a sectional view showing an example of the arrangement of the crack detection electrodes and the connection between the crack detection electrodes and the crack detection circuit according to the fourth embodiment. FIG. 15 is a circuit diagram showing an example of the crack detection circuit of FIG. 16A to 16C are diagrams showing a flow of wire bonding when the bonding region between the bonding wire and the electrode pad is normally formed. 17A to 17C are diagrams showing a flow of wire bonding when the bonding region between the bonding wire and the electrode pad is not normally formed. FIG. 18 is a plan view showing a joint region between a normally formed electrode pad and a bonding wire. FIG. 19 is a plan view showing a bonding area between an electrode pad and a bonding wire that is not normally formed. FIG. 20 is a diagram showing a force applied from the resin to the bonding wire when the resin changes from a high temperature to a low temperature. FIG. 21 is a diagram showing a force generated in a region below the electrode pad by a force applied to the bonding wire when the bonding region between the bonding wire and the electrode pad is normally formed. FIG. 22 is a diagram showing a force generated in a region below the electrode pad by a force applied to the bonding wire when the bonding region between the bonding wire and the electrode pad is not normally formed.

Hereinafter, semiconductor devices according to the embodiments will be described in detail with reference to the drawings. For clarity of explanation, the following description and drawings are appropriately omitted and simplified. In addition, in the specification and the drawings, the same or corresponding components are designated by the same reference numerals, and duplicated description will be omitted. Further, at least a part of the embodiment and each modification may be arbitrarily combined with each other.

(Preliminary examination by the inventor)
Before describing the details of the semiconductor device according to the first embodiment, the background of arriving at the later-described embodiment will be described.

Up to now, the mechanism of crack formation under the electrode pad has been that in wire bonding, when the ball formed at the tip of the bonding wire is pressed onto the electrode pad, a force is applied to the ball from above to apply it. As a result, it was thought that the insulating layer provided below the electrode pad was crushed and a crack was generated.

This time, the inventor examined cracks under the electrode pad and found that cracks were generated based on a new mechanism. The mechanism of the occurrence of cracks under the electrode pad, which the present inventor newly clarified, will be described.

Note that a crack is a crack or a crack in an interlayer insulating film used for an insulating layer, and a state where a crack is generated means that the interlayer insulating film used for the insulating layer is not in a uniform state and It seems that there is a gap.

(Results of mechanism analysis of crack generation at the concept stage)
16A to 16C are diagrams showing a flow of wire bonding when the bonding region between the bonding wire BW and the electrode pad EP is normally formed. These drawings are an example of ball bonding, which is one of the wire bonding methods, and show a state until the electrode pad EP and the bonding wire BW are connected.

First, as shown in FIG. 16A, a ball is formed at the tip of the bonding wire BW by discharging the tip of the bonding wire BW which is passed through and supported by a capillary (not shown) to melt the tip of the bonding wire BW. Next, in FIG. 16B, a load is applied from the capillary to the formed ball so that the formed ball is pressure-bonded to the electrode pad EP, so that the contact surface between the formed ball and the electrode pad EP becomes uniform. Part is alloyed. Next, in FIG. 16C, ultrasonic vibration is applied to the bonding wire BW through the capillary, whereby alloying of the ball formed on the electrode pad EP and the bonding region JRA is formed.

17A to 17C are diagrams showing a flow of wire bonding when the bonding region between the bonding wire and the electrode pad EP is not normally formed.

In FIG. 17A, similarly to FIG. 16A, a ball is formed at the tip of the bonding wire BW by discharging the tip of the bonding wire BW that is passed through and supported by a capillary (not shown) to melt the tip of the bonding wire BW. In FIG. 17B, similarly to FIG. 16B, a load is applied from the capillary to the formed ball so that the formed ball is pressed onto the electrode pad EP, so that the formed ball and the electrode pad EP come into contact with each other. The surface is partially alloyed. However, unlike FIG. 16B, in FIG. 17B, when the formed ball is pressure-bonded to the electrode pad EP, the bonding surface between the electrode pad EP and the bonding wire BW has a concave shape. Next, in FIG. 17C, ultrasonic vibration is applied to the bonding wire BW through the capillary, and the ultrasonic vibration vibrates the electrode pad EP and alloys the balls formed to form the bonding region JRB. To be done.

The joint region JRB is narrower and smaller in plan view than the joint region JRA which is normally alloyed by wire bonding.

The cause of the concave shape of the electrode pad EP is that the hardness of the ball formed at the tip of the bonding wire BW is high, and that the bonding wire BW is attached to the bonding wire BW when the bonding wire BW is pressure-bonded to the electrode pad EP. It is considered that the applied load is large.

FIG. 18 is a plan view showing a joint region JRA between the electrode pad EP and the bonding wire BW which are normally formed. FIG. 17C is a plan view of the junction area JRA of FIG. 16C.

As shown in FIG. 18, when the wire bonding is normally performed, the bonding area JRA in which the electrode pad EP and the bonding wire BW are alloyed has a substantially circular shape in a plan view.

FIG. 19 is a plan view showing a bonding region JRB between the electrode pad EP and the bonding wire which are not normally formed. FIG. 17D is a plan view of the junction area JRB of FIG. 17C.

As shown in FIG. 19, when wire bonding is not normally performed, the alloyed joint region JRB has a substantially elliptical shape in plan view.

The length of the substantially elliptical long axis of the joining region JRB of FIG. 19 is approximately equal to the diameter of the substantially circular joining region JRA of FIG. 18, but the length of the substantially elliptical minor axis of the joining region JRB of FIG. The length is shorter than the diameter of the substantially circular shape of the joining area JRA in FIG. Here, the direction of the major axis of the elliptical shape is the direction along the vibration direction of the ultrasonic wave applied to the bonding wire BW in the step of FIG. 17C.

In the manufacture of a semiconductor device, after this wire bonding flow, the resin 100 is formed at a high temperature so as to cover the semiconductor chip SC mounted on the package substrate PS and the bonding wire BW, and the temperature of the resin 100 is lowered to room temperature. To cure the resin 100.

FIG. 20 is a diagram showing a force FB1 applied from the resin 100 to the bonding wire when the resin 100 changes from high temperature to low temperature. The semiconductor chip SC is mounted on the package substrate PS, and the resin 100 is formed so as to cover the semiconductor chip SC and the bonding wires BW. When the temperature of the resin 100 changes from a high temperature to a low temperature, the resin 100 contracts when the temperature decreases, so that a force is generated in the direction of the arrow shown in the figure and applied to the bonding wire BW. This force is applied to the bonding area JRA and the bonding area JRB shown in FIGS. 18 and 19 via the bonding wire BW.

FIG. 21 is a diagram showing a force generated in a region below the electrode pad EP by a force applied to the bonding wire BW when the bonding region between the bonding wire BW and the electrode pad EP is normally formed. The force FB1 applied to the bonding wire BW generates a tensile stress FB21 in the direction of separating the electrode pad EP and the bonding wire BW by the principle of leverage with the point Q as a fulcrum. The tensile stress FB21 schematically represents the force in the direction of peeling off the electrode pad EP and the bonding wire BW. This tensile stress FB21 is applied to the insulating layer arranged in the region below the electrode pad EP in a direction along the direction perpendicular to the main surface of the insulating layer via the bonding region JRA.

FIG. 22 is a diagram showing a force generated in a region below the electrode pad EP by a force applied to the bonding wire BW when the bonding region between the bonding wire BW and the electrode pad EP is not normally formed. The force FB1 applied to the bonding wire BW generates a tensile stress FB22 in the direction of peeling the electrode pad EP and the bonding wire BW by the principle of leverage using the point Q as a fulcrum. The tensile stress FB22 schematically represents the force in the direction of peeling off the electrode pad EP and the bonding wire BW. The tensile stress FB22 is applied to the insulating layer arranged in the region below the electrode pad EP in a direction along the direction perpendicular to the main surface of the insulating layer via the joint region JRB.

As described above, the force generated as the resin 100 shrinks is applied to the insulating layer as a force in the direction in which the upper main surface of the insulating layer is pulled with respect to the lower main surface. At that time, the force per unit area applied to the insulating layer is larger when the bonding area between the bonding wire BW and the electrode pad EP is not formed normally because the bonding area is smaller.

That is, when the bonding area between the bonding wire BW and the electrode pad EP is not normally formed, a large force is intensively applied to the insulating layer in the area below the bonding area JRB. The insulating layer in the region below the junction region JRB has a high frequency of occurrence of cracks. Further, since cracks generated in the insulating layer are generated by a force acting in a direction in which the upper main surface of the insulating layer is pulled with respect to the lower main surface, the cross section of the crack is along a direction perpendicular to the main surface of the insulating layer. The direction along the main surface of the insulating layer becomes longer than such a direction.

The force generated in the mechanism of crack generation estimated by the inventor is related to the temperature change of the resin 100 and is applied over a relatively long time. On the other hand, the force generated by the load applied during wire bonding is temporarily applied during a short time during wire bonding. In other words, the force generated by the crack generation mechanism that the inventor has clarified is applied over time rather than the force generated by the load during wire bonding.

In addition, in the mechanism of crack generation that the inventor has clarified, since the force generated inside the resin 100 is related to the temperature change of the resin 100, the circuit operation after the semiconductor device is shipped as a product is also affected. To receive. Since the temperature of the resin 100 repeatedly fluctuates according to the circuit operation, repetitive force is continuously applied even after shipping. That is, the force applied to the insulating layer does not work only when the temperature is lowered for hardening from the high temperature when the resin 100 is formed. This point is also different from the force generated by the load temporarily applied during wire bonding.

Further, with respect to the force acting in the direction in which the upper main surface of the insulating layer is pulled with respect to the lower main surface, the mechanical strength of the insulating layer is increased by arranging the via in the insulating layer. It was also confirmed by the inventor's preliminary study that the frequency of cracks is higher in the region where the number of vias arranged in the insulating layer is smaller.

The crack generation mechanism estimated by the inventor has been described with reference to the example of ball bonding. However, even in wedge bonding different from ball bonding, the same mechanism causes cracks. When the bonding area between the bonding wire BW and the electrode pad EP is not normally formed in the flow for performing wedge bonding, the contact surface between the electrode pad EP and the bonding wire BW is recessed, and ultrasonic vibration is applied to the bonding wire BW. The alloying of the bonding wire BW and the electrode pad EP progresses. The joint region JRB formed as a result has a smaller area in plan view than the joint region JRA formed normally. The force generated by the temperature change of the resin 100 is intensively applied to the reduced joint region JRB from the bonding wire BW, and the force is applied to the insulating layer through the joint region JRB. The frequency of occurrence of cracks increases.

Therefore, the inventor has thought that there may be an appropriate crack detection method based on the mechanism of crack generation clarified by the above-mentioned inventor's preliminary examination, and has arrived at the following embodiments.

Hereinafter, an embodiment to which means for solving the above problems is applied will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1 is a block diagram showing an example of a crack detection device CDD included in the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing an example of the arrangement of the crack detection unit CDU in the semiconductor chip SC included in the semiconductor device according to the first embodiment.

1 and 2, the crack detection device CDD includes a crack detection circuit CDCA, a crack detection unit CDU, and a signal determination circuit SDC. The crack detection unit CDU connects the crack detection vias CDV arranged in the insulating layer because the wirings of different wiring layers are connected to each other and the crack detection vias CDV different from each other, and the crack detection wiring CDW formed in the wiring layer. including.

The impedance of the crack detection unit CDU is measured by the crack detection circuit CDCA, and based on the result, the presence or absence of a crack in the insulating layer is detected by the signal determination circuit SDC.

In FIG. 2, an elliptical joint region JRB indicated by a broken line is a region where cracks frequently occur, and when the joint region between the bonding wire BW and the electrode pad EP is not normally formed during wire bonding. It is formed. The major axis direction of the elliptical bonding region JRB is the direction along the vibration direction of the ultrasonic wave applied to the bonding wire BW during wire bonding, and is a plan view with the extending direction of the bonding wire BW (not shown). Is the first direction along the vertical direction. Although not shown, a bonding wire BW is connected on the electrode pad EP of FIG. 2 as shown in FIG. 16C or 17C, and the bonding wire BW extends in a direction orthogonal to the first direction from the bonding region JRB. Has been extended to.

According to the mechanism of generation of cracks clarified by the inventor, a force generated by a change in the temperature of the resin 100 is applied from the bonding wire BW to the joint region JRB. The force applied from the bonding wire BW is applied to the insulating layer via the joint region JRB, which causes cracks in the insulating layer. Therefore, the crack detection unit CDU including the crack detection via CDV is arranged at a position overlapping the area of the broken line in FIG. 2 in plan view.

That is, the crack detection via CDV is arranged at a position overlapping with a region where the electrode pad EP and the bonding wire BW are connected in a plan view.

In FIG. 2, the crack detection vias CDV are arranged at two places in the joint region JRB in a plan view, but the crack detection vias CDV are arranged at one place or three or more places in the joint region JRB in a plan view. May be done.

When the crack detection vias CDV are arranged at a plurality of places in the joint region JRB in a plan view, the crack detection vias CDV are arranged in a straight line in a plan view, and the arrangement direction is the extending direction of the bonding wire BW. And the first direction along the direction perpendicular to the plan view. It should be noted that all the crack detection vias CDV may be arranged at a position overlapping the joint region JRB in a plan view, or some crack detecting vias CDV may be arranged at a position overlapping the joint region JRB in a plan view. In order to reduce the area occupied by the crack detection vias CDV, it is preferable that all the crack detection vias CDV are arranged at positions overlapping the junction area JRB in plan view.

In the wire bonding specification, the bonding strength between the bonding wire BW and the electrode pad EP is a wire pull test for measuring the bonding strength between the bonding wire BW and the electrode pad EP by applying an upward force to the bonding wire BW. Is specified to withstand. That is, even if the area of the bonding region between the bonding wire BW and the electrode pad EP becomes slightly smaller, the bonding region is determined by the wire bonding specifications so that a constant bonding strength is maintained.

When the length of the minor axis of the joining region JRB is, for example, about ½ of the length of the diameter DIS of the ball bonding portion, a certain joining strength is maintained. In this state, a force is applied from the bonding wire BW to the junction region JRB based on the mechanism of crack generation which the inventor has clarified. Therefore, the force per unit area applied to the insulating layer is large. Here, the diameter DIS of the ball bonding portion is the DIS in FIGS. 16C and 17C, and is substantially equal to the length of the major axis of the joining region JRB and the diameter of the joining region JRA.

On the other hand, when the length of the minor axis of the joining region JRB is, for example, about 1/4 of the length of the diameter DIS of the ball bonding portion, the joining strength is lowered, but cracks revealed by the inventor occur. Based on the mechanism (1), a force is applied to the junction region JRB from the bonding wire BW, so that the force per unit area applied to the insulating layer is large.

Therefore, when the length of the minor axis of the joint region JRB is in the range of about 1/4 to about 1/2 of the length of the diameter DIS of the ball bonding portion, the force per unit area applied to the insulating layer is large, The frequency of cracks is high.

From the above, according to the mechanism of crack generation that the inventor has clarified, the crack detection unit CDU is provided in a range in which the length of the minor axis of the joining region JRB is approximately ¼ to approximately ½ of the diameter DIS of the ball bonding portion. It is preferably provided. By disposing the crack detection unit CDU in this range, the probability of detecting the occurrence of cracks can be increased.

In the above description, it is preferable to provide the crack detecting unit CDU in a region where the length of the minor axis of the joining region JRB is in the range of about ¼ to ½ of the diameter DIS of the ball bonding portion. , But is not necessarily limited to this area.

For example, when the bonding strength between the bonding wire BW and the electrode pad EP is stronger than the general wire bonding specifications, the length of the minor axis of the bonding region JRB is approximately 1/4 of the diameter DIS of the ball bonding portion. Even in a shorter state, cracks may occur according to the mechanism of crack generation elucidated by the inventor. Therefore, in this case, the length of the minor axis of the joining region JRB is in a range from a value shorter than approximately 1/4 of the diameter DIS of the ball bonding portion to approximately 1/2 of the diameter DIS of the ball bonding portion. The crack detection unit CDU may be provided.

FIG. 3 is a diagram showing a cross section taken along line A-A′ in FIG. 2. Six insulating layers of a first insulating layer 10, a second insulating layer 11, a third insulating layer 12, a fourth insulating layer 13, a fifth insulating layer 14 and a sixth insulating layer 15 are provided on the semiconductor substrate SS, On each insulating layer except the sixth insulating layer 15, five wiring layers of a first wiring layer 20, a second wiring layer 21, a third wiring layer 22, a fourth wiring layer 23 and a fifth wiring layer 24 are provided. Has been.

The first insulating layer 10, the second insulating layer 11, the third insulating layer 12, the fourth insulating 12 and the fifth insulating layer 14 have low mechanical strength, but have a relative dielectric constant higher than that of SiO _{2 in} order to reduce wiring capacitance. An insulating film material having a low rate, that is, a so-called Low-k material is used, and is, for example, a porous material. A material having high mechanical strength is used for the sixth insulating layer 15 because the force due to the load during wire bonding is large, and is, for example, an insulating film material having a relative dielectric constant higher than that of SiO ₂ , a so-called High-k material.

Here, the frequency of cracks generated in the insulating layer is higher in the insulating layer having low mechanical strength than in the insulating layer having high mechanical strength. Therefore, the crack detection via CDV is selectively provided not on the uppermost insulating layer using the High-k material but on the lower insulating layer using the Low-k material disposed below the uppermost insulating layer. ing. As a result, it becomes possible to efficiently detect cracks with a few crack detection vias CDV.

The crack detection via CDV is arranged in an insulating layer formed of a material having low mechanical strength. The crack detection via CDV has, for example, a length of about 0.03 μm or more to about 0.1 μm or less and a diameter of about 0.05 μm or more to about 0.1 μm or less. The material of the crack detection via CDV is, for example, Cu.

The crack detection via CDV includes first to eighth crack detection vias, and the crack detection wiring CDW includes first to ninth crack detection wirings.

Then, as shown in FIG. 3, the crack detection unit CDU is
A first crack detection wiring 30 formed on the first wiring layer 20;
A first crack detection via 40 formed in the second insulating layer 11,
A second crack detection wiring 31 formed on the second wiring layer 21;
A second crack detection via 41 formed in the third insulating layer 12;
A third crack detection wiring 32 formed on the third wiring layer 22,
A third crack detection via 42 formed in the fourth insulating layer 13,
A fourth crack detection wiring 33 formed on the fourth wiring layer 23,
A fourth crack detection via 43 formed in the fifth insulating layer 14,
A fifth crack detection wiring 34 formed on the fifth wiring layer 24;
A fifth crack detection via 44 formed in the fifth insulating layer 14,
A sixth crack detection wiring 35 formed in the fourth wiring layer 23,
A sixth crack detection via 45 formed in the fourth insulating layer 13,
A seventh crack detection wiring 36 formed on the third wiring layer 22,
A seventh crack detection via 46 formed in the third insulating layer 12,
An eighth crack detection wiring 37 formed on the second wiring layer 21,
An eighth crack detection via 47 formed in the second insulating layer 11,
A ninth crack detection wiring 38 formed in the first wiring layer 20,
Are sequentially connected in series, and the first crack detection wiring 30 formed in the first wiring layer 20 and the ninth crack detection wiring 38 formed in the first wiring layer 20 are It is connected to a crack detection circuit CDCA (not shown).

FIG. 4 is a cross-sectional view showing an example of the connection between the crack detection circuit CDCA and the crack detection via CDV. This is an example in which a register is used as the crack detection circuit CDCA, and the connection between the register and the crack detection unit CDU is shown. The crack detection circuit CDCA includes a first register 50 shown as REG1 in the figure and a second register 51 shown as REG2 in the figure, and the first register 50 is connected to the first crack detection wiring 30. The second register 51 is connected to the ninth crack detection wiring 38. The data signal DS transmitted from the first register 50 is received by the second register 51 as the detection signal DETS changed according to the impedance of the crack detection unit CDU.

Here, if a crack occurs in a region where the crack detection via CDV is arranged, the crack detection via CDV is partially damaged or broken, and the impedance of the crack detection unit CDU increases.

For example, when the crack detection via CDV is disconnected due to a crack, the impedance of the crack detection unit CDU changes from low impedance to high impedance. The crack detection circuit CDCA detects this change in impedance. The crack detection circuit CDCA is connected to the signal determination circuit SDC shown in FIG. 1, and the signal determination circuit SDC detects the occurrence of cracks in the insulating layer based on the change in impedance detected by the crack detection circuit CDCA. ..

FIG. 5 is a diagram showing an example of a crack that may occur in the insulating layer in the cross-sectional view of FIG. 4. In the case where a crack that crosses the second crack detection via 41 in the third insulating layer 12 is generated, Shows.

The crack has a shape that spreads in the direction along the main surface of the insulating layer, as described in the preliminary study by the inventor.

When no crack has occurred, the data signal DS transmitted from the first register 50 is received by the second register 51 as the detection signal DETS via the crack detection unit CDU. That is, the state of the detection signal DETS also changes in accordance with the state change of the data signal DS. On the other hand, when a crack is generated, the crack detection via CDV or the crack detection wiring CDW is broken. When the crack detection via CDV or the crack detection wiring CDW is disconnected, the detection signal DETS received by the second register 51 becomes low level or high level even if the state of the data signal DS transmitted from the first register 50 transits. It is fixed. The signal determination circuit SDC detects the occurrence of cracks in the insulating layer by detecting the state in which the detection signal DETS is fixed.

FIG. 6 is a circuit diagram showing an example of the circuit configuration of the register shown in FIGS. A register circuit 52 that is an example of a circuit of the first register 50 and the second register 51, and an example of a register reference clock circuit 53 that outputs a register reference clock signal that defines the operation timing of the register circuit 52 are shown. The first register 50 and the second register 51 have the same circuit configuration as the register circuit 52, respectively.

As shown in FIG. 6, the first register 50 and the second register 51 include an inverter 54 and a transfer gate 55, which are configured by MOSFETs, for example. Then, the states of the first register 50 and the second register 51 are transited by the two reference clock signals for registers which are output from the reference clock circuit 53 for register and have a mutually complementary relationship.

The operation of the first register 50 and the second register 51 will be described with reference to FIG. The first register 50 takes in the data signal DS output from a signal generator (not shown) from DIN at the rising of the register reference clock signal and outputs it from DOUT. The data signal DS output from DOUT is input to the first crack detection wiring 30 of the crack detection unit CDU, and as the detection signal DETS changed according to the impedance of the crack detection unit CDU, the ninth signal of the crack detection unit CDU. It is input to the second register 51 from the crack detection wiring 38. The input detection signal DETS is held in the second register 51, and is output from the second register 51 to the signal determination circuit SDC (not shown) at the next rising of the register reference clock signal.

Here, the two register reference clock signals output from the register reference clock circuit 53 and having a complementary relationship with each other are input to the gates of the PMOS transistor and the NMOS transistor that form the transfer gate 55.

The crack detection circuit CDCA can detect an impedance change such as disconnection of the crack detection unit CDU by a logic circuit having a small circuit scale using MOS transistors.

The data signal DS is a binary digital signal of a high-level and a low-level, and for example, the high level and the low level are transited in a predetermined cycle.

In order to reduce the power consumption of the crack detection device CDD, it is preferable to lengthen the cycle of the register reference clock signal generated by the register reference clock circuit 53.

Further, in order to operate the crack detection device CDD with further lower power consumption, the register reference clock circuit 53 is configured such that the other circuits of the semiconductor chip SC provided with the crack detection device CDD are operating, It is not necessary to keep it running. It is preferable to control the register reference clock circuit 53 to operate only when the temperature of the resin 100 formed on the package substrate PS of the semiconductor device so as to cover the semiconductor chip SC fluctuates by a predetermined range or more. ..

By controlling the register reference clock circuit 53 so as to operate as described above, the power consumption of the semiconductor chip SC mounted with the crack detection circuit CDCA can be suppressed for a long period after being shipped as a product. It will be possible.

Instead of the second register 51, another functional circuit capable of detecting various amplitude levels of the detection signal DETS may be used.

Even if the crack detection via CDV or the crack detection wiring CDW is partially broken without breaking, the impedance between the first crack detection wiring 30 and the ninth crack detection wiring 38 changes. The detection of the amplitude level of the detection signal DETS according to the change of the impedance can be applied to not only the presence/absence of a crack, but also the state of the crack detection via CDV or the crack detection wiring CDW. is there.

Further, the crack detection circuit CDCA continues to detect the change in the amplitude level of the detection signal DETS, accumulates the detection result as information in a storage element such as a memory, and stores the accumulated detection result in the MPU mounted on the semiconductor chip SC. It can also be analyzed by the processing device. This makes it possible to predict when the crack will affect the operation of the circuit mounted on the semiconductor device.

If the crack detection circuit CDCA can detect a change in the amplitude level of the detection signal DETS, an alarm is issued from a processing device such as an MPU mounted on the semiconductor chip SC before the crack detection unit CDU is completely disconnected. It is also possible to utilize it for sending.

Further, the method by which the signal determination circuit SDC detects the occurrence of cracks from the data signal DS and the detection signal DETS is not particularly limited to the above contents.

The data signal DS is captured and held in the first register 50 when the register reference clock signal rises. For example, the held data signal DS may be compared with the detection signal DETS captured in the second register 51 at the next rise of the register reference clock signal.

Here, the comparison between the data signal DS and the detection signal DETS can be performed by, for example, a comparator including a differential amplifier circuit.

The electrode pad EP on which the crack detection unit CDU is disposed is at least one of the plurality of electrode pads EP disposed on the semiconductor chip SC, and the crack detection unit is disposed below each of the plurality of electrode pads EP. A CDU may be placed. By disposing the crack detection unit CDU below the plurality of electrode pads EP, it is possible to monitor the occurrence of cracks in the insulating layer at a plurality of positions, and it is possible to improve the reliability of the semiconductor device having the crack detection device CDD. Becomes

Further, the electrode pad EP on which the crack detection unit CDU is arranged below may be an electrode pad EP arranged on the core region inside the edge of the semiconductor chip SC. The core region is provided with all or part of a logic circuit such as a memory circuit or MPU, or all or part of a functional circuit such as a BGR circuit, an ADC circuit, or a PLL circuit. Therefore, the crack generated in the insulating layer in the core region easily affects the electrical characteristics of the circuit mounted on the semiconductor chip SC. Providing the crack detection unit CDU in the core region makes it possible to effectively detect a crack that easily affects the electrical characteristics of the circuit.

When a plurality of crack detection units CDU are arranged on the semiconductor chip SC, the crack detection circuits CDCA are connected to the respective crack detection units CDU, and the plurality of crack detection units CDU are combined into one crack detection circuit. It may be configured to be connected in series to the CDCA. The configuration in which a plurality of crack detection units CDU are collectively connected to one crack detection circuit CDCA in series is effective for downsizing the crack detection device CDD. Even if the plurality of crack detection units CDU are collectively connected to one crack detection circuit CDCA in series, any one of the plurality of crack detection units CDU is broken. If so, the crack detection circuit CDCA can detect the occurrence of a crack, and there is no problem in the crack detection function.

A plurality of crack detection units CDU may be provided in the insulating layer and the wiring layer below the joining region JRB where the electrode pad EP and the bonding wire BW are connected.

Another via different from the crack detection via CDV may be arranged in the insulating layer below the electrode pad EP where the crack detection via CDV is arranged.

By increasing the number of vias arranged in the insulating layer, the mechanical strength of the insulating layer can be increased.

In the wiring layer below the electrode pad EP on which the crack detection wiring CDW is arranged, wiring such as another circuit different from the crack detection wiring CDW may be arranged.

The crack detection circuit CDCA may be arranged in the core region or the edge of the semiconductor chip SC. The constituent elements of the crack detection circuit CDCA may also serve as the constituent elements of other circuits arranged in the core region, or may be newly provided for the crack detection circuit CDCA.

The semiconductor device according to the present embodiment is based on the mechanism of crack generation in the insulating layer elucidated by the inventor as described above, in the insulating layer region below the electrode pad EP in which the frequency of crack generation is high, The crack detection via CDV and the crack detection wiring CDW provided in the crack detection unit CDU are selectively arranged. The crack detection unit CDU is connected to the crack detection circuit CDCA and detects a change in impedance of the crack detection unit CDU due to disconnection or the like. As a result, in the insulating layer and the wiring layer below the position overlapping with the region of the electrode pad EP in plan view, the crack detection rate equivalent to that when the crack detection via CDV and the crack detection wiring CDW are provided in a wide range is maintained, It is possible to realize a compact crack detection unit CDU.

Furthermore, according to the present embodiment, since the crack detection via CDV is arranged in the region of the insulating layer where cracks frequently occur, the crack that spreads in the insulating layer in the direction along the main surface of the insulating layer has high accuracy. Can be detected in.

Furthermore, according to the present embodiment, it is possible to utilize the information for the failure prediction by accumulating the information on the temporal change of the detection signal DETS and analyzing the accumulated information on the temporal change.

Furthermore, according to the present embodiment, the crack detection unit CDU can be arranged in a specific narrow region where the crack occurrence frequency is high in the lower layer of the electrode pad EP. Therefore, the crack detection unit CDU can be arranged in a region below the electrode pad EP arranged in the core region. Since the cracks generated in the core region have a strong influence on the electrical characteristics of the circuit mounted on the semiconductor chip SC, it is important to effectively detect the cracks generated in the insulating layer in the core region. Is effective in improving.

[Second Embodiment]
In the semiconductor chip SC, the via can be arranged in the entire region of the insulating layer below the electrode pad EP, but the electrical characteristics of the circuit to which the via is connected, the layout rule in semiconductor manufacturing, and the like are taken into consideration. Are arranged. Therefore, in the actual layout of the semiconductor chip SC, there are regions with different via densities.

FIG. 7 is a plan view showing an example of regions having different via densities with respect to the vias arranged in the insulating layer below the electrode pad EP.

An example in which a region having a high via density and a region having a low via density are provided below the electrode pad EP is shown. It can be seen that the high-density via region HVD, which is a region with high via density, and the low-density via region LVD, which is a region with lower via density than the high-density via region HVD, are mixed.

FIG. 8 is a sectional view taken along the line BB′ of FIG. 7. Similar to FIG. 3 of the first embodiment, a cross-sectional view of a semiconductor chip SC provided with first to sixth six insulating layers and first to fifth five wiring layers on a semiconductor substrate SS. Is. The sixth insulating layer 15, which is the uppermost layer immediately below the electrode pad EP, is made of a High-k material having high mechanical strength and a relative dielectric constant higher than that of SiO ₂ , and is a first layer provided below the uppermost insulating layer. Therefore, the fifth insulating layer 14 is made of a low-k porous material having low mechanical strength.

It can be seen that among the plurality of insulating layers, the third insulating layer 12 third from the bottom has a region in which the number of vias is small. This region is the low-density via region LVD having low via density in FIG. 7. On the other hand, it can be seen that the same third insulating layer 12 has a high-density via region HVD with a high via density.

Here, in the insulating layer, the low density via region LVD having a low density of vias has a low mechanical strength against an applied force, and thus a crack is generated in the third insulating layer 12 having a low density of the third via from the lower layer. It occurs frequently.

Further, according to the mechanism of crack generation that has been clarified by the inventor, the central portion of the electrode pad EP, which is a region overlapping with the region where the electrode pad EP and the bonding wire BW are connected in plan view, has a high frequency of crack generation. .. Therefore, in the case of FIGS. 7 and 8, the frequency of occurrence of cracks is high in the central portion of the electrode pad EP in the third insulating layer 12.

FIG. 9 is a cross-sectional view showing an example of a crack that may occur in the insulating layer when there are regions having different via densities in the insulating layer as shown in FIGS. 7 and 8. Here, among the plurality of insulating layers, the insulating layer having a low mechanical strength of the interlayer insulating film used for the insulating layer and a portion having a low density of vias has a high frequency of crack generation.

In FIG. 9, the crack spreads in the third insulating layer 12 along the main surface of the insulating layer at a position that includes, in a plan view, the junction region JRB to which the electrode pad EP and the bonding wire BW are connected. ing.

It should be noted that FIG. 9 shows an example in which the crack becomes large due to the temperature of the resin 100 of the semiconductor device being repeatedly changed after the crack is generated in the insulating layer. The cracks gradually increase as the temperature change of the resin 100 is repeated. Therefore, it is important to detect early before the electrical characteristics of the circuit mounted on the semiconductor chip SC provided in the semiconductor device deteriorate.

FIG. 10 is a sectional view showing an example of the arrangement of the crack detection unit CDU according to this embodiment. The plurality of insulating layers have at least one via in a region overlapping with the electrode pad EP in a plan view. The crack detection unit CDU including the crack detection via CDV is arranged in a region where cracks frequently occur. That is, the crack detection via CDV provided in the crack detection unit CDU is arranged at a position that overlaps with the bonding region JRB where the electrode pad EP and the bonding wire BW are connected in a plan view, as in the first embodiment. Further, the crack detection via CDV is arranged in an insulating layer having a small number of vias arranged in a region overlapping the electrode pad EP in a plan view among the plurality of insulating layers.

In other words, the number of vias provided in a region in the insulating layer in which the crack detection via CDV is arranged overlaps with the electrode pad EP in a plan view is the same as that in each of the plurality of insulating layers different from the insulating layer in which the crack detection via CDV is arranged. It is smaller than the number of vias provided in a region overlapping with the electrode pad EP in plan view. In FIG. 10, among the plurality of insulating layers, the crack detection via CDV is arranged in the third insulating layer 12 which is third from the bottom.

In the second embodiment, as compared with the first embodiment, as the insulating layer in which the crack detection vias CDV are arranged, the third insulating layer 12 in which the number of arranged vias is small and the density of vias is low is selectively cracked. The detection via CDV is arranged. The crack detection via CDV does not need to be arranged as a vertically stacked stack structure as in FIG. 3 of the first embodiment, for example. Therefore, even if a large number of crack detection vias CDV are not arranged vertically, it is possible to effectively detect cracks in the insulating layer.

As described above, the crack detection unit CDU including the crack detection via CDV and the crack detection wiring CDW is arranged at a position overlapping with a region where the electrode pad EP and the bonding wire BW are connected in a plan view. , The vias are selectively arranged in an insulating layer having a low density.

The semiconductor device according to this embodiment can achieve the same effects as the semiconductor device according to the first embodiment.

Further, in the semiconductor device according to the present embodiment, the crack detection unit CDU is arranged so that the crack can be effectively detected. The crack detection via CDV and the crack detection wiring CDW can be arranged in a small area in plan view and sectional view. That is, since the crack detection vias CDV are selectively arranged in the insulating layer where cracks frequently occur, the crack detection rate by the crack detection device CDD does not decrease, and a small crack detection device CDD can be realized. Become. As a result, the degree of freedom in layout at the time of layout design is increased, and a remarkable effect such as improvement in design efficiency is brought about.

[Third Embodiment]
FIG. 11 is a diagram showing a change in the outer shape of the resin 100 formed on the package substrate PS so as to cover the semiconductor chip SC and the bonding wires BW depending on the temperature after the wire bonding flow. FIG. 6 is a plan view showing a resin outline 60 at a high temperature of the resin 100 when the resin 100 is formed and a resin outline 61 at a room temperature of the resin 100 when the temperature of the resin 100 is lowered to the room temperature and cured. The xy coordinates are as shown.

In the figure, a dotted line having a large outer shape is the resin outer shape 60 at high temperature, and a dotted line having an outer shape smaller than the resin outer shape 60 at high temperature is the resin outer shape 61 at room temperature.

When the temperature of the resin 100 is lowered, each part of the resin 100 shrinks toward the center of the region where the resin 100 is formed, and thus the resin 100 shown by the resin outer shape 61 at room temperature as shown in FIG. The outer shape is smaller than the outer shape of the resin 100 indicated by the resin outer shape 60 at high temperature.

The point P1 on the resin 100 is a point at the center of the lower edge of the semiconductor chip SC in the figure, and when the temperature of the resin 100 falls from high temperature to room temperature, the point P1 on the resin 100 is in the Y-axis direction. Move to ΔP1y.

The point P2 on the resin 100 is a point at the lower left apex edge portion of the semiconductor chip SC in the figure, and when the temperature of the resin 100 falls and reaches room temperature, the point P2 on the resin 100 moves ΔP2x in the X-axis direction. , P2y moves in the Y-axis direction.

As the temperature of the resin 100 decreases, each part of the resin 100 shrinks toward the center of the region where the resin 100 is formed, so that the distance from the center of the region where the resin 100 is formed is reduced. The portion of the resin 100 located at a longer position has a longer distance to move in accordance with the change in temperature. In other words, the portion of the resin 100 located at a position where the distance from the center of the region where the resin 100 is formed is longer, the greater the amount of displacement of the position.

That is, in the resin 100 formed in the region overlapping with the region of the semiconductor chip SC in plan view, the amount of displacement of the position of each portion of the resin 100 due to the temperature change of the resin 100 is determined by the corner region of the semiconductor chip SC. The portion of the resin 100 located in is large.

The larger the amount of displacement (movement distance) of the position of the resin 100, the larger the bonding wire BW in the region, the larger the force applied from the resin 100. Therefore, among the plurality of bonding wires BW connected to the electrode pads EP of the semiconductor chip SC, the bonding wires BW connected to the electrode pads EP in the corner regions of the semiconductor chip SC are subjected to a large force. The frequency of occurrence of cracks is high in the region of the insulating layer below the electrode pad EP that is connected to the bonding wire BW to which this large force is applied.

The corner area of the semiconductor chip SC includes a corner portion of the semiconductor chip SC that is an empty area in a normal integrated circuit, and is a corner of the semiconductor chip SC rather than a line connecting midpoints of adjacent sides of the semiconductor chip SC. This is a corner area on the part side. That is, the electrode pads EP arranged in the corner regions of the semiconductor chip SC are the electrode pads EP arranged in the outer peripheral portion of the semiconductor chip SC except the electrode pads EP arranged in the vicinity of the midpoint of each side. And the electrode pad EP.

FIG. 12 is a plan view showing an example of the arrangement of crack detection units CDU in the semiconductor chip SC according to the third embodiment.

As shown in FIG. 20, the semiconductor chip SC is mounted on the package substrate PS and covered with the resin 100. Then, as shown in FIG. 12, the electrode pads EP are arranged on the outer peripheral portion of the semiconductor chip SC.

The first electrode pad 70 is the electrode pad EP in which the crack detection unit CDU is arranged in the insulating layer below the electrode pad EP based on the mechanism of crack generation that the inventors have clarified. The second electrode pad 71 is an electrode pad EP in which the crack detection unit CDU is not arranged in the insulating layer below the electrode pad EP.

Since the frequency of occurrence of cracks in the insulating layer is high in the corner region of the semiconductor chip SC, the crack detection unit CDU is disposed in the insulating layer below the electrode pad EP disposed in the corner region of the semiconductor chip SC as shown in FIG. Has been done.

In FIG. 12, four first electrode pads 70 are arranged in each of the four corner regions of the semiconductor chip SC. The first electrode pads 70 arranged in each corner region are the pair of first electrode pads 70 closest to the diagonal line of the semiconductor chip SC and the pair of first electrode pads 70 closest to the second. Here, the crack detection unit CDU arranged in the insulating layer below the first electrode pad 70 is connected to a crack detection circuit CDCA (not shown). The crack detection circuit CDCA is composed of the same circuit as the crack detection circuit CDCA described in the first embodiment. The crack detection circuit CDCA can detect an impedance change such as disconnection of the crack detection unit CDU by a logic circuit having a small circuit scale using MOS transistors.

The four crack detection units CDU arranged in each corner region of the semiconductor chip SC may be connected to different crack detection circuits CDCA or may be connected to one crack detection circuit CDCA.

Further, all of the crack detection units CDU arranged in each corner area of the semiconductor chip SC may be connected to one crack detection circuit CDCA.

Further, all of the crack detection units CDU arranged in each corner area may be connected to the plurality of crack detection circuits CDCA in any combination.

In the configuration in which all of the crack detection units CDU arranged in the respective corner regions of the semiconductor chip SC are connected to one crack detection circuit CDCA, the crack detection circuit CDCA prevents the crack detection circuit CDCA from decreasing while suppressing a decrease in crack detection rate. Since the area occupied by the semiconductor chip SC can be reduced, the semiconductor chip SC can be miniaturized.

There may be one crack detection unit CDU arranged in each corner region of the semiconductor chip SC, or a form in which the crack detection unit CDU is arranged in at least one corner region. When the crack detection unit CDU is arranged in one corner area of the semiconductor chip SC, the crack detection unit CDU is arranged in the corner area of the semiconductor chip SC closest to the corner of the resin 100.

When the crack detection unit CDU is arranged only in a specific corner region, the crack detection unit CDU is arranged below the electrode pad EP having the low density via region LVD among the electrode pads EP in the corner region. It's good. This makes it possible to reduce the size of the crack detection unit CDU without reducing the crack detection rate of the crack detection device CDD.

The crack detection circuit CDCA may be arranged in the core region of the semiconductor chip SC, or may be arranged in a corner portion of the semiconductor chip SC which is an empty region in a normal integrated circuit. Further, it may be arranged in a region below the electrode pad EP.

The crack detection circuit CDCA may be provided in the core region, and the circuit element forming the crack detection circuit CDCA may also serve as a circuit element forming another circuit arranged in the core region.

The position where the crack detection unit CDU and the crack detection circuit CDCA are arranged on the semiconductor chip SC, and the connection between the crack detection unit CDU and the crack detection circuit CDCA are not particularly limited. At the time of designing, the optimal position and connection should be appropriately considered in consideration of the mechanism of crack generation which the inventors have clarified, the reliability of the semiconductor chip SC, the electrical characteristics of the circuit mounted on the semiconductor chip SC, and the like. You can

In the semiconductor device according to the third embodiment, the crack detection unit CDU is selected in the corner region of the semiconductor chip SC where the crack of the semiconductor chip SC is likely to occur, based on the mechanism of the crack generation of the insulating layer which the inventors have clarified. Will be placed in the target. By selectively arranging the crack detection unit CDU in the corner area of the semiconductor chip SC, the area occupied by the crack detection unit CDU in the semiconductor chip SC can be prevented without lowering the crack detection rate of the crack detection device CDD. It is possible to reduce.

Furthermore, according to the present embodiment, by connecting a plurality of crack detection units CDU to one crack detection circuit CDCA, it is possible to further reduce the area occupied by the crack detection circuit CDCA in the semiconductor chip SC.

As described above, according to the present embodiment, the area occupied by the crack detection unit CDU and the crack detection circuit CDCA in the semiconductor chip SC can be reduced. It is possible to realize a compact crack detection device CDD while maintaining the crack detection rate by the crack detection device CDD. As a result, the area of the semiconductor chip SC that can be occupied by other circuits can be widened, so that the degree of freedom in layout at the time of layout design can be increased and the design efficiency can be improved.

[Modification of Third Embodiment]
Next, a modification of the third embodiment will be described. In the above-described third embodiment, the semiconductor device in which one semiconductor chip SC is mounted on the package substrate PS has been described. In the modified example of the third embodiment, a semiconductor device in which a plurality of semiconductor chips SCA and SCB are mounted on the package substrate PS will be described based on the mechanism of crack generation in the insulating layer that has been clarified by the inventor.

FIG. 13 is a plan view showing an example of the arrangement of crack detection units CDU in two semiconductor chips SCA and SCB according to the modification of the third embodiment. The two semiconductor chips are the first semiconductor chip SCA and the second semiconductor chip SCB, respectively. The two semiconductor chips SCA and SCB are mounted adjacent to each other on the package substrate PS, and the resin 100 is formed on the package substrate PS so as to cover the semiconductor chips SCA and SCB. The first semiconductor chip SCA is, for example, a memory chip, and the second semiconductor chip SCB is, for example, a communication RFIC. In the first semiconductor chip SCA and the second semiconductor chip SCB, a plurality of electrode pads EP are arranged along the outer peripheral portion of each chip.

As shown in FIG. 13, the crack detection unit CDU is formed on the insulating layer below the electrode pad EP located near the corner of the resin 100 among the electrode pads EP located in the corner regions of the semiconductor chips SCA and SCB. Will be placed. That is, of the plurality of corner regions of the first semiconductor chip SCA and the second semiconductor chip SCB, the first semiconductor chip SCA and the second semiconductor that are located away from the regions where the two chips are adjacent to each other. The first electrode pad 70 is arranged in the corner region of the chip SCB. The first electrode pad 70 is the electrode pad EP in which the crack detection unit CDU is arranged in the insulating layer below the electrode pad EP.

Note that this modified example is also based on the mechanism of crack generation in the insulating layer that has been clarified by the inventor, and the crack detection unit CDU is located at a position overlapping with a region where the electrode pad EP and the bonding wire BW are connected in a plan view. It is located in.

In the semiconductor device according to the modification of the present embodiment, two semiconductor chips SCA and SCB are mounted on the package substrate PS, and cracks among the plurality of electrode pads EP arranged on the two semiconductor chips SCA and SCB. The crack detection unit CDU is provided in a region below the electrode pad EP where the occurrence frequency of the cracks is high. This makes it possible to effectively detect cracks generated in the insulating layer.

The position where the crack detection circuit CDCA and the crack detection unit CDU are arranged on the semiconductor chip SC, and the connection method between the crack detection circuit CDCA and the crack detection unit CDU are not particularly limited as in the third embodiment. At the time of layout design, the crack detection circuit CDCA and the crack detection unit CDU can be appropriately positioned and connected in consideration of the reliability and electrical characteristics of the semiconductor chip SC. Further, in the modification of the present embodiment, the case where the number of semiconductor chips SC is two is described as an example of mounting a plurality of semiconductor chips SC, but the present invention is not limited to this.

The semiconductor device according to the modification of the present embodiment can achieve the same effect as the semiconductor device according to the third embodiment.

Further, among the plurality of electrode pads EP arranged on the plurality of semiconductor chips SC, the crack detection unit CDU is provided in a region below the electrode pad EP with a high occurrence frequency of cracks, thereby reducing the crack detection rate. Without this, a compact crack detection device CDD can be realized.

[Embodiment 4]
In the first and second embodiments, the presence/absence of a crack in the insulating layer is determined by using the crack detection via CDV arranged in the insulating layer. More specifically, it has been used that the impedance of the crack detection via CDV changes due to disconnection of the crack detection via CDV. Further, a binary digital signal is used for the data signal DS input to the crack detection via CDV and the detection signal DETS output from the crack detection via CDV.

In the fourth embodiment, it is not essential to use the crack detection via CDV, but two crack detection electrodes DE are used. The presence or absence of a crack in the insulating layer is determined by examining the change in impedance between the crack detection electrodes DE. The signal applied to the crack detection electrode DE is not a binary digital signal but an AC signal.

FIG. 14 is a cross-sectional view showing an example of the arrangement of the crack detection electrode DE and the connection between the crack detection electrode DE and the crack detection circuit CDCB according to the fourth embodiment. The crack detection electrode DE is used instead of the crack detection via CDV of the first embodiment, and is connected to the crack detection circuit CDCB. Note that, as in the first embodiment, the semiconductor chip SC includes six insulating layers, first to sixth, and five wiring layers, first to fifth. The material of the insulating layer is also the same as that of the first embodiment.

In the figure, the first crack detection electrode DE1 and the second crack detection electrode DE2 are arranged so as to sandwich a specific region of the third insulating layer 12 having a high crack occurrence frequency. The first crack detection electrode DE1 is connected to the crack detection circuit CDCB, and the second crack detection electrode DE2 is electrically connected to the ground potential terminal of the crack detection circuit CDCB.

The first crack detection electrode DE1 and the second crack detection electrode DE2 are arranged in different wiring layers so as to face each other, and the first crack detection electrode DE1 and the second crack detection electrode DE2 are bonded to the electrode pad EP in plan view. The wire BW is arranged at a position overlapping with a region to which the wire BW is connected.

FIG. 15 is a circuit diagram showing an example of the crack detection circuit CDCB of FIG.

The crack detection circuit CDCB includes an operational amplifier OPA having a differential amplifier circuit, a feedback resistor R1 connected between the inverting input terminal and the output terminal of the operational amplifier OPA, a non-inverting input terminal of the operational amplifier OPA, and a ground potential terminal. It has an AC signal generator ACG connected between them and a DC power supply DCS connected between the AC signal generator ACG and a ground potential terminal, and the first crack detection electrode DE1 is provided at the inverting input terminal of the operational amplifier OPA. The second crack detection electrode DE2 is connected to the ground potential terminal. The output terminal of the operational amplifier OPA is connected to a signal determination circuit SDC (not shown).

At the inverting input terminal of the operational amplifier OPA, an AC signal having the same voltage value as the signal obtained by superimposing the AC reference signal RAS generated by the AC signal generating unit ACG on the DC voltage generated by the DC power supply DCS is the inverting input terminal voltage. Occurs as. Therefore, an AC current corresponding to the impedance between the first crack detection electrode DE1 and the second crack detection electrode DE2 will flow, and accordingly, an AC voltage waveform is generated at the output terminal of the operational amplifier OPA. This AC voltage waveform is input to the signal determination circuit SDC as the detection signal DETS, and it is determined whether or not a crack is generated in the insulating layer between the first crack detection electrode DE1 and the second crack detection electrode DE2.

It is used that the impedance between the detection electrodes changes due to the crack generated in the insulating layer between the first crack detection electrode DE1 and the second crack detection electrode DE2.

The AC reference signal RAS changes according to the crack generated in the insulating layer between the first crack detection electrode DE1 and the second crack detection electrode DE2, and is output as the detection signal DETS. Since an AC signal based on the AC reference signal RAS is applied to the first crack detection electrode DE1 and the second crack detection electrode DE2, by analyzing the reactance component, it is possible to determine not only whether or not a crack has occurred but also a crack. The size of can be estimated.

It is difficult to estimate the difference or change in the size of the crack by the method of detecting the crack by using the change in the voltage value of DC, whereas in the crack detection circuit CDCB of the present embodiment, the size of the crack is large. It is possible to estimate the differences and changes in.

Therefore, by accumulating and analyzing the temporal change information of the amplitude level of the detection signal DETS, it can be useful for estimating the occurrence of cracks and the expansion speed of the crack region. By this estimation, it is possible to predict the time when the crack region expands and affects the operation of the circuit of the semiconductor chip SC.

The crack detection circuit CDCB may be operated periodically after the semiconductor device is shipped as a product, or when the change in the temperature of the resin 100 is larger than a predetermined change range.

When the voltage level difference of the voltage waveform input to the signal determination circuit SDC is small between the time when the crack is generated and the time when the crack is not generated and the crack detection accuracy in the signal determination circuit SDC is low, A crack detection via CDV may be provided in the insulating layer between the first crack detection electrode DE1 and the second crack detection electrode DE2 so as to connect the first crack detection electrode DE1 and the second crack detection electrode DE2.

When the crack detection via CDV is broken due to a crack, the impedance changes more greatly than in the state in which there is no break, so that it is possible to increase the accuracy of the determination as to whether or not a crack has occurred.

The crack detection circuit CDCB is not limited to the configuration shown in FIG. 15, and various other impedance measurement circuits may be applied.

The semiconductor device according to this embodiment can achieve the same effects as those of the first, second, and third embodiments. Further, in the semiconductor device according to the present embodiment, since the detection signal DETS is AC, it is possible to measure the impedance including the reactance between the first crack detection electrode DE1 and the second crack detection electrode DE2. Therefore, it has a remarkable effect that it is effective in predicting a failure of a product after shipping.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

10 1st insulating layer 11 2nd insulating layer 12 3rd insulating layer 13 4th insulating layer 14 5th insulating layer 15 6th insulating layer 20 1st wiring layer 21 2nd wiring layer 22 3rd wiring layer 23 4th wiring layer 24 5th wiring layer 30 1st crack detection wiring 31 2nd crack detection wiring 32 3rd crack detection wiring 33 4th crack detection wiring 34 5th crack detection wiring 35 6th crack detection wiring 36 7th Crack detection wiring 37 eighth crack detection wiring 38 ninth crack detection wiring 40 first crack detection via 41 second crack detection via 42 third crack detection via 43 fourth crack detection via 44 fifth Crack detection via 45 Sixth crack detection via 46 Seventh crack detection via 47 Eighth crack detection via 50 First register 51 Second register 52 Register circuit 53 Register reference clock circuit 54 Inverter 55 Transfer gate 60 High temperature Resin outline 61 Resin outline at room temperature 70 First electrode pad 71 Second electrode pad 100 Resin ACG AC signal generator BW Bonding wire CDCA, CDCB Crack detection circuit CDD Crack detector CDU Crack detector CDV Crack detection via CDW Crack detection wiring DCS DC power supply DE1 First crack detection electrode DE2 Second crack detection electrode DETS Detection signal DIS Ball bonding part diameter DS Data signal EP Electrode pad FB1 Force applied to bonding wire FB21, FB22 Tensile stress HVD High density via area JRA, JRB Junction area LVD Low-density via area OPA Operational amplifier PS Package substrate R1 Feedback resistance RAS AC reference signal SC Semiconductor chip SCA First semiconductor chip SCB Second semiconductor chip SDC Signal judgment circuit SS Semiconductor substrate

Claims (18)

A semiconductor substrate,
A plurality of insulating layers formed on the semiconductor substrate,
A plurality of wiring layers respectively provided on the plurality of insulating layers,
An electrode pad arranged on a multilayer wiring structure composed of the plurality of wiring layers and the plurality of insulating layers, to which a bonding wire is connected,
A first via that is arranged in a first insulating layer of the plurality of insulating layers below the electrode pad and is connected to the plurality of wiring layers;
A detection unit including the first via and a wiring connected to the first via;
A detection circuit electrically connected in series to the detection unit,
The semiconductor device, wherein the first via is arranged at a position overlapping with a region where the electrode pad and the bonding wire are connected in a plan view. The semiconductor device according to claim 1, wherein the detection circuit is connected to the detection unit in order to detect a conduction state of the detection unit. The detection circuit is
A first circuit connected to one end of the first via;
A second circuit connected to the other end of the first via;
Equipped with
The second circuit outputs, from the other end of the first via, a detection signal in which the data signal transmitted from the first circuit to the one end of the first via is changed according to the impedance of the first via. The semiconductor device according to claim 1, which receives. 4. The semiconductor device according to claim 3, wherein the first circuit and the second circuit are register circuits each including a transfer gate circuit formed of a transistor and an inverter circuit. The semiconductor device is
further,
A reference clock circuit that outputs a reference clock signal,
Equipped with
The semiconductor device according to claim 4, wherein the data signal is output from the first circuit based on the reference clock signal. The reference clock signals output from the reference clock circuit are a first reference clock signal and a second reference clock signal having a complementary relationship with each other,
The semiconductor device according to claim 5, wherein the first reference clock signal and the second reference clock signal are input to a gate of a transistor forming the transfer gate circuit. The region where the electrode pad and the bonding wire are connected is a first bonding region where a part of the bonding wire and the electrode pad is alloyed,
The shape of the first bonding region in plan view is a circular shape or an elliptical shape,
The semiconductor device according to claim 1, wherein the first via is arranged at a position overlapping the circular or elliptical region in a plan view. The direction of the major axis of the elliptical shape, which is one of the shapes of the first bonding region in plan view, is a direction along a direction perpendicular to the extending direction of the bonding wire in plan view, The semiconductor device according to claim 7. The semiconductor device is
further,
At least one second via arranged at a position different from the first via in plan view,
At least one first detection line connecting the first via and the second via;
Equipped with
The first via and the second via are linearly arranged in a plan view in a first direction along the longitudinal direction of the first detection wiring,
The semiconductor device according to claim 1, wherein the first direction is along a direction perpendicular to the extending direction of the bonding wire in a plan view. 10. The semiconductor device according to claim 9, wherein the second via is arranged at a position overlapping a region where the electrode pad and the bonding wire are connected in a plan view. The plurality of insulating layers below the electrode pad are
A region of the first via density,
A second via density region having a lower via density than the first via density region;
Have
The semiconductor device according to claim 1, wherein the first via is arranged at a position overlapping the region of the second via density in a plan view. The plurality of insulating layers each include at least one via in a region overlapping with the electrode pad in a plan view,
The number of vias provided in a region of the first insulating layer that overlaps with the electrode pad in a plan view is equal to that of the plurality of insulating layers that are different from the first insulating layer in a region that overlaps with the electrode pad in a plan view. The semiconductor device according to claim 1, wherein the number of vias provided is less than the number of vias provided. Of the plurality of insulating layers, the uppermost insulating layer provided with the electrode pad is formed of a first insulating film material having a higher relative dielectric constant than SiO ₂ .
The insulating layer provided below the uppermost insulating layer is formed of a second insulating film material having a lower relative dielectric constant than SiO ₂ .
The semiconductor device according to claim 1, wherein the first insulating layer is an insulating layer formed of the second insulating film material. A semiconductor chip,
A package substrate on which the semiconductor chip is mounted,
A resin formed on the package substrate so as to cover the semiconductor chip,
Equipped with
The semiconductor chip is
A semiconductor substrate, and at least one or more insulating layers on the semiconductor substrate;
Wiring layers respectively provided on the insulating layer,
A plurality of electrode pads arranged along the edge of the main surface of the upper part of the semiconductor chip, to which bonding wires are connected,
A via formed in at least one insulating layer of the insulating layer and connecting different wiring layers;
Equipped with
The via includes a first via for detecting conduction and non-conduction between different wiring layers,
The electrode pad includes a first electrode pad arranged at a position overlapping the position where the first via is arranged in a plan view,
The first via is arranged at a position overlapping with a region where the first electrode pad and the bonding wire are joined in a plan view,
The semiconductor device, wherein the first electrode pad is disposed in at least one corner region of the semiconductor chip. The semiconductor device includes a detection circuit connected to the first via,
15. The semiconductor device according to claim 14, wherein the detection circuit transmits a data signal and receives the detection signal in which the data signal changes according to the impedance of the first via. 15. The semiconductor device according to claim 14, wherein the position where the first electrode pad is arranged is a corner region of a plurality of the corner regions of the semiconductor chip, which is close to a corner of the resin. A semiconductor substrate,
At least one insulating layer formed on the semiconductor substrate;
At least one or more wiring layers respectively provided on the insulating layer,
An electrode pad formed on the uppermost wiring layer of the at least one wiring layer and having a bonding wire connected thereto;
A detection circuit for detecting the impedance of the insulating layer,
A first electrode electrically connected to the detection circuit;
A second electrode formed on a wiring layer different from the first electrode and connected to a ground potential;
Equipped with
The first electrode is formed on a first wiring layer of the wiring layers,
The second electrode is formed on a second wiring layer of the wiring layer different from the first wiring layer so as to face the first electrode,
The semiconductor device, wherein the first electrode and the second electrode are arranged at positions overlapping with a region where the electrode pad and the bonding wire are connected in a plan view. A first AC signal is transmitted from the detection circuit to the first electrode,
The detection circuit receives, from the second electrode, a second AC signal in which the first AC signal is changed according to the impedance between the first electrode and the second electrode,
18. The semiconductor device according to claim 17, wherein the detection circuit detects an impedance between the first electrode and the second electrode based on the first AC signal and the second AC signal.