JP2020092108A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of improving the joint reliability between a support layer and a wiring layer.SOLUTION: A semiconductor device includes a support layer 10 having a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z, a wiring layer 20 joined to the main surface 10A, a semiconductor element 40 which is located on the side opposite to the support layer 10 with respect to the wiring layer 20 in the thickness direction z, and is bonded to the wiring layer 20, and a bonding layer 19 interposed between the main surface 10A and the wiring layer 20, and the wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19.SELECTED DRAWING: Figure 12

Description

The present invention relates to a semiconductor device including a semiconductor element, and particularly to a semiconductor device in which the semiconductor element is a switching element.

Conventionally, a semiconductor device having a semiconductor element such as a MOSFET or an IGBT mounted thereon is widely known. Patent Document 1 discloses an example of a semiconductor device mounting such a semiconductor element. In the semiconductor device, the heat spreader corresponding to the wiring layer is joined to the insulating sheet corresponding to the support layer (see FIG. 1 of Patent Document 1). The semiconductor element is bonded to the heat spreader.

In the semiconductor device disclosed in Patent Document 1, the insulating sheet is made of a material containing an inorganic material such as alumina and an epoxy resin. On the other hand, the heat spreader is generally a metal plate. Therefore, in the semiconductor device, the insulating sheet made of a non-metal material and the heat spreader made of a metal material are joined to each other by intermolecular force joining using solder or the like. If such dissimilar materials are bonded to each other, there is a fear of interfacial peeling between the insulating sheet and the heat spreader when the semiconductor device is used, and therefore improvement is desired.

JP, 2014-216459, A

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device capable of improving the bonding reliability between a support layer and a wiring layer.

According to the present invention, a support layer having a main surface and a back surface facing opposite sides in the thickness direction, a wiring layer bonded to the main surface, and the support layer with respect to the wiring layer in the thickness direction. A semiconductor element located on the opposite side to and joined to the wiring layer; and a joining layer interposed between the main surface and the wiring layer, the wiring layer interposing the joining layer. A semiconductor device is provided, which is bonded to the main surface by the molecular bonding described above.

In the practice of the present invention, preferably, the supporting layer has an insulating portion including the back surface, a supporting portion including the main surface, and an intermediate portion interposed between the insulating portion and the supporting portion. The supporting portion is joined to the insulating portion by molecular joining via the intermediate portion.

In the practice of the present invention, preferably, the Young's modulus of the support portion in the thickness direction is smaller than the Young's modulus of the wiring layer in the thickness direction.

In the practice of the present invention, preferably, the thickness of the supporting portion is smaller than the thickness of the wiring layer.

In the practice of the present invention, preferably, the supporting portion is made of a material containing graphite, and the wiring layer is made of a material containing copper.

In the practice of the invention, preferably, the Young's modulus of the insulating portion in the thickness direction is higher than the Young's modulus of the supporting portion in the thickness direction.

In the practice of the present invention, preferably, the thickness of the insulating portion is smaller than the thickness of the wiring layer and larger than the thickness of the supporting portion.

In the practice of the present invention, preferably, the insulating portion is a ceramic containing aluminum nitride.

In the practice of the present invention, preferably, the support layer is an insulating plate, the wiring layer is made of a material containing carbon, and a base layer bonded to the main surface, and laminated on the base layer, and the semiconductor A conductive layer to which the element is bonded, and the thickness of the base layer is larger than the thickness of the support layer.

In the practice of the present invention, preferably, the base layer is made of a material containing single crystal graphite, and the in-plane direction of the single crystal graphite is parallel to the thickness direction.

In the practice of the present invention, preferably, a sealing resin covering the wiring layer and the semiconductor element and a part of the support layer is further provided, and the back surface is exposed from the sealing resin.

In the practice of the present invention, preferably, the support layer includes a first support layer and a second support layer that are separated from each other in a direction orthogonal to the thickness direction, and the wiring layer is formed on the first support layer. A first wiring layer bonded to the first wiring layer, and a second wiring layer including a first wiring layer bonded to the second support layer; and a second wiring layer bonded to the second support layer. A second input element connected to the first wiring layer, a second input terminal connected to the second wiring element, and a second input element connected to the second wiring layer. Further comprising: an output terminal; and a conductive member joined to the first element and the second wiring layer, wherein the sealing resin includes the conductive member, the first input terminal, and the second input terminal. And a part of each of the output terminals.

In the practice of the present invention, preferably, the area of the first support layer is larger than the area of the first wiring layer and the area of the second support layer is the same as the area of the second support layer when viewed along the thickness direction. It is larger than the area of the second wiring layer.

In the practice of the present invention, preferably, the area of the first support layer is smaller than the area of the first wiring layer and the area of the second support layer is the same as viewed in the thickness direction. It is smaller than the area of the second wiring layer.

In implementation of the present invention, preferably, a part of each of the first input terminal and the second input terminal is exposed from the sealing resin on one side in one direction orthogonal to the thickness direction, and the output is provided. A part of the terminal is exposed from the sealing resin on the other side in the one direction.

In implementation of the present invention, preferably, the first input terminal and the second input terminal are separated from each other in the thickness direction, and the first input terminal has a first terminal portion exposed from the sealing resin. The second input terminal has a second terminal portion exposed from the sealing resin, and at least a part of the second terminal portion is the first terminal portion when viewed along the thickness direction. Overlaps with.

According to the semiconductor device of the present invention, it is possible to improve the joint reliability between the support layer and the wiring layer.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. It is a top view of the semiconductor device shown in FIG. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 (transmission of a sealing resin). FIG. 4 is a plan view of the semiconductor device shown in FIG. 3 in which a second input terminal and a plurality of conductive members are further transparent. It is a bottom view of the semiconductor device shown in FIG. 2 is a right side view of the semiconductor device shown in FIG. 1. FIG. FIG. 3 is a left side view of the semiconductor device shown in FIG. 1. It is a front view of the semiconductor device shown in FIG. It is sectional drawing which follows the IX-IX line of FIG. It is sectional drawing which follows the XX line of FIG. FIG. 4 is a partially enlarged view of FIG. 3. It is sectional drawing which follows the XII-XII line of FIG. It is sectional drawing which follows the XIII-XIII line of FIG. It is a top view (transmission of a sealing resin) of a semiconductor device concerning a 2nd embodiment of the present invention. FIG. 15 is a bottom view of the semiconductor device shown in FIG. 14. It is sectional drawing which follows the XVI-XVI line of FIG. It is sectional drawing which follows the XVII-XVII line of FIG. It is sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. FIG. 19 is a cross-sectional view of the semiconductor device shown in FIG. 18. FIG. 19 is a partially enlarged view of FIG. 18. FIG. 20 is a partially enlarged view of FIG. 19. 19 is a schematic diagram of a crystal structure of graphite forming a base layer of the wiring layer of the semiconductor device shown in FIG. 18. FIG. It is sectional drawing of the semiconductor device concerning 4th Embodiment of this invention. It is sectional drawing of the semiconductor device shown in FIG.

A mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
A semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor device A10 includes a support layer 10, a bonding layer 19, a wiring layer 20, a first input terminal 31, a second input terminal 32, an output terminal 33, an insulating material 39, a plurality of semiconductor elements 40, a plurality of conductive members 50, and A sealing resin 60 is provided. In addition to these, the semiconductor device A10 includes a pair of insulating layers 23, a pair of gate wiring layers 24, a pair of detection wiring layers 25, a pair of gate terminals 34, a pair of detection terminals 35, a plurality of dummy terminals 36, and a plurality of gates. The wire 51, the plurality of detection wires 52, the pair of first wires 531 and the pair of second wires 532 are further included. The semiconductor device A10 shown in these drawings is a power conversion device (power module) in which the plurality of semiconductor elements 40 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The semiconductor device A10 is used for a motor drive source, an inverter device for various electric products, a DC/DC converter, and the like. Here, in FIG. 3, for convenience of understanding, the sealing resin 60 is transmitted. 4, the second input terminal 32 and the plurality of conductive members 50 are further transmitted to FIG. 3 for convenience of understanding. These elements, which are transparent in FIGS. 3 and 4, are indicated by imaginary lines (two-dot chain lines).

In the description of the semiconductor device A10, the thickness direction of the support layer 10 is referred to as “thickness direction z”. The direction orthogonal to the thickness direction z is called the "first direction x". A direction orthogonal to both the thickness direction z and the first direction x is referred to as a “second direction y”. As shown in FIGS. 1 and 2, the semiconductor device A10 has a rectangular shape when viewed in the thickness direction z. The first direction x corresponds to the longitudinal direction of the semiconductor device A10. The second direction y corresponds to the lateral direction of the semiconductor device A10. In the description of the semiconductor device A10, the side where the first input terminal 31 and the second input terminal 32 are located in the first direction x is referred to as “one side of the first direction x” for convenience. The side where the output terminal 33 is located in the first direction x is referred to as “the other side in the first direction x”. The "thickness direction z", "first direction x", "second direction y", "one side of the first direction x" and "the other side of the first direction x" are the semiconductor devices A20 to The same applies to the description of the semiconductor device A40.

The support layer 10 supports the wiring layer 20, as shown in FIGS. 9 and 10. The support layer 10 has a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z. Of these, the main surface 10A faces the wiring layer 20. As shown in FIG. 5, the back surface 10B is exposed from the sealing resin 60. When the semiconductor device A10 is attached to the heat sink, the back surface 10B faces the heat sink. In the semiconductor device A10, the support layer 10 has an insulating portion 11, a support portion 12, and an intermediate portion 13.

As shown in FIGS. 12 and 13, the insulating portion 11 includes the back surface 10B. The insulating portion 11 is, for example, a ceramic containing aluminum nitride (AlN). The thickness t1 of the insulating portion 11 is smaller than the thickness t3 of the wiring layer 20 and larger than the thickness t2 of the supporting portion 12. The Young's modulus of the insulating portion 11 in the thickness direction z is higher than the Young's modulus of the supporting portion 12 in the thickness direction z.

As shown in FIGS. 12 and 13, the support portion 12 includes a main surface 10A. The support 12 is a sheet made of a material containing graphite and an epoxy resin, for example. In addition, the support portion 12 may be a sheet made of a material containing silicone rubber. The thickness t2 of the support portion 12 is smaller than the thickness t3 of the wiring layer 20. The Young's modulus of the support portion 12 in the thickness direction z is smaller than the Young's modulus of the wiring layer 20 in the thickness direction z.

As shown in FIGS. 12 and 13, the intermediate portion 13 is interposed between the insulating portion 11 and the support portion 12. The support portion 12 is joined to the insulating portion 11 by molecular joining via the intermediate portion 13. The intermediate portion 13 is derived from a molecular bonding agent containing triazinedithiol. The thickness of the intermediate portion 13 is about 10 nm. The intermediate portion 13 is transparent.

A method of molecular bonding between the insulating portion 11 and the supporting portion 12 via the intermediate portion 13 will be described. First, the surface of the insulating portion 11 is subjected to plasma treatment to roughen the surface and generate hydroxy groups on the surface. Next, a molecular bonding agent containing triazinedithiol is applied to the surface of the plasma-treated insulating portion 11. The molecular bonding agent is, for example, an aqueous solution of 6-(3-triethoxysilylpropylamino)-1,3,5-triazine-2,4-dithiol monosodium salt. Next, the insulating part 11 having the surface coated with the molecular bonding agent is heat-treated, whereby the hydroxy group generated in the insulating part 11 and the organic compound contained in the molecular bonding agent are chemically bonded. As a result, triazinedithiol chemically bonded to the insulating portion 11 is generated on the surface of the insulating portion 11. Finally, the supporting portion 12 is brought into close contact with the surface of the insulating portion 11 on which the triazinedithiol is generated, and the supporting portion 12 is subjected to heat and pressure treatment, so that the supporting portion 12 is subjected to molecular bonding through the intermediate portion 13 so that the insulating portion 11 is formed. To be joined to. For example, when the support 12 is a sheet made of a material containing graphite and an epoxy resin, the thiol group contained in the triazinedithiol and the epoxy group contained in the support 12 are chemically bonded. The organic compound that is interposed between the insulating portion 11 and the supporting portion 12 and is chemically bonded to both the insulating portion 11 and the supporting portion 12 serves as the intermediate portion 13.

As shown in FIGS. 3, 9 and 10, the support layer 10 includes a first support layer 101 and a first support layer 101 which are separated from each other in a direction orthogonal to the thickness direction z (first direction x in the example shown by the semiconductor device A10). The second support layer 102 is included. The first support layer 101 and the second support layer 102 have a rectangular shape with the longer side in the second direction y when viewed along the thickness direction z.

The wiring layer 20 is joined to the main surface 10A of the support layer 10 as shown in FIGS. 9 and 10. The wiring layer 20, together with the first input terminal 31, the second input terminal 32, the output terminal 33, and the plurality of conductive members 50, form a conductive path between the outside of the semiconductor device A10 and the plurality of semiconductor elements 40. In the semiconductor device A10, the wiring layer 20 is made of a material containing copper. The wiring layer 20 is, for example, a copper plate. The thickness t3 of the wiring layer 20 shown in FIGS. 11 and 12 is, for example, 1 mm or more. On the surface of the wiring layer 20 facing the plurality of semiconductor elements 40, for example, silver (Ag) plating, or a plurality of types of metal plating in which an aluminum (Al) layer, a nickel (Ni) layer, and a silver layer are laminated in this order is used. May be given.

As shown in FIGS. 3, 9 and 10, the wiring layer 20 includes a first wiring layer 201 and a second wiring layer 202. The first wiring layer 201 is joined to the first support layer 101. The second wiring layer 202 is joined to the second support layer 102. Therefore, the first wiring layer 201 and the second wiring layer 202 are separated from each other in the first direction x. In the semiconductor device A10, the area of the first support layer 101 is larger than the area of the first wiring layer 201 when viewed along the thickness direction z. The area of the second support layer 102 is larger than the area of the second wiring layer 202 when viewed along the thickness direction z. Thereby, in the semiconductor device A10, a part of the main surface 10A of the support layer 10 is covered with the sealing resin 60.

As shown in FIGS. 12 and 13, the bonding layer 19 is interposed between the main surface 10A of the support layer 10 and the wiring layer 20. The wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. The bonding layer 19 is derived from a molecular bonding agent containing triazinedithiol. The bonding layer 19 has a thickness of about 10 nm. The bonding layer 19 is transparent. The method of molecular bonding between the main surface 10A and the wiring layer 20 via the bonding layer 19 is the same as the method of molecular bonding between the insulating portion 11 and the support portion 12 via the intermediate portion 13 described above. This is similar to the case of changing to 20. The organic compound that is interposed between the main surface 10A and the wiring layer 20 and that is chemically bonded to both the main surface 10A and the wiring layer 20 serves as the bonding layer 19.

The pair of insulating layers 23 are arranged on each of the first wiring layer 201 and the second wiring layer 202, as shown in FIGS. 3, 9, and 10. The pair of insulating layers 23 are separated from each other in the first direction x. The pair of insulating layers 23 has a strip shape extending in the second direction y. The insulating layer 23 located on one side of the first direction x is arranged in the first wiring layer 201. The insulating layer 23 located on the other side in the first direction x is arranged in the second wiring layer 202. The insulating layer 23 is, for example, ceramics or glass epoxy resin.

The pair of gate wiring layers 24 are arranged on the pair of insulating layers 23, as shown in FIGS. 3, 9, and 10. The pair of gate wiring layers 24 have a strip shape extending in the second direction y. The widths of the pair of gate wiring layers 24 are substantially the same. The gate wiring layer 24 is, for example, a metal foil made of copper or a copper alloy. The surface of the gate wiring layer 24 may be plated with silver, for example.

The pair of detection wiring layers 25 are arranged on the pair of insulating layers 23, as shown in FIGS. 3, 9 and 10. The pair of detection wiring layers 25 have a strip shape extending in the second direction y. The width of each of the pair of detection wiring layers 25 is substantially equal to the width of the gate wiring layer 24. In the insulating layer 23 located on one side of the first direction x, the detection wiring layer 25 is located on one side of the gate wiring layer 24 in the first direction x. In the insulating layer 23 located on the other side in the first direction x, the detection wiring layer 25 is located on the other side in the first direction x than the gate wiring layer 24. The detection wiring layer 25 is, for example, a metal foil made of copper or a copper alloy. The surface of the detection wiring layer 25 may be plated with silver, for example.

The first input terminal 31 and the second input terminal 32 are located on one side in the first direction x, as shown in FIGS. 2 to 5. Direct current power (voltage) that is a power conversion target is input to the first input terminal 31 and the second input terminal 32. The first input terminal 31 is a positive electrode (P terminal). The second input terminal 32 is a negative electrode (N terminal). As shown in FIG. 10, the second input terminal 32 is arranged apart from both the first input terminal 31 and the first wiring layer 201 in the thickness direction z. The first input terminal 31 and the second input terminal 32 are metal plates made of copper or copper alloy.

As shown in FIG. 4, the first input terminal 31 has a first connection portion 311 and a first terminal portion 312. In the first input terminal 31, the boundary between the first connection portion 311 and the first terminal portion 312 is a surface along the second direction y and the thickness direction z, and is located on one side of the first direction x. The sealing resin 60 passes through a surface including the first side surface 63A (details will be described later). The entire first connecting portion 311 is covered with the sealing resin 60. The other side of the first connection portion 311 in the first direction x has a comb tooth shape. The comb-shaped portion is connected to the first wiring layer 201 by soldering or ultrasonic bonding. As a result, the first input terminal 31 is electrically connected to the first wiring layer 201.

As shown in FIGS. 4 and 5, the first terminal portion 312 extends from the sealing resin 60 to one side in the first direction x. The first terminal portion 312 has a rectangular shape when viewed along the thickness direction z. Both sides of the first terminal portion 312 in the second direction y are covered with the sealing resin 60. The other portion of the first terminal portion 312 is exposed from the sealing resin 60. As a result, the first input terminal 31 is supported by both the first wiring layer 201 and the sealing resin 60.

The second input terminal 32 has a second connecting portion 321 and a second terminal portion 322, as shown in FIG. The boundary between the second connecting portion 321 and the second terminal portion 322 in the second input terminal 32 is the first connecting portion 311 and the first terminal portion 312 in the first input terminal 31 when viewed along the thickness direction z. Match the boundaries of.

As shown in FIG. 3, the second connecting portion 321 has a connecting portion 321A and a plurality of extending portions 321B. The connecting portion 321A has a strip shape extending in the second direction y. One side of the connecting portion 321A in the first direction x is connected to the second terminal portion 322. The plurality of extending portions 321B extend from the connecting portion 321A toward the other side in the first direction x. The plurality of extending portions 321B have a strip shape extending in the first direction x.

As shown in FIGS. 2 and 3, the second terminal portion 322 extends from the sealing resin 60 to one side in the first direction x. The second terminal portion 322 has a rectangular shape when viewed along the thickness direction z. Both sides of the second terminal portion 322 in the second direction y are covered with the sealing resin 60. The other portion of the second terminal portion 322 is exposed from the sealing resin 60. As shown in FIG. 4, the second terminal portion 322 overlaps the first terminal portion 312 of the first input terminal 31 when viewed along the thickness direction z. As shown in FIG. 10, the second terminal portion 322 is separated from the first terminal portion 312 in the thickness direction z on the side where the main surface 10A of the support layer 10 faces. In the example illustrated by the semiconductor device A10, the shape of the second terminal portion 322 is the same as the shape of the first terminal portion 312.

As shown in FIG. 10, the insulating material 39 is interposed between the first input terminal 31 and the second input terminal 32 in the thickness direction z. The insulating material 39 is a flat plate. The insulating material 39 is made of, for example, insulating paper. When viewed along the thickness direction z, the entire first input terminal 31 overlaps the insulating material 39. In the second input terminal 32, a part of the connecting portion 321A of the second connecting portion 321 and the entire second terminal portion 322 overlap the insulating material 39 when viewed in the thickness direction z. Therefore, when viewed along the thickness direction z, the portion of the second input terminal 32 that overlaps the first input terminal 31 is in contact with the insulating material 39. As a result, the first input terminal 31 and the second input terminal 32 are electrically insulated from each other. A part of the insulating material 39 (the other side in the first direction x and both sides in the second direction y) is covered with the sealing resin 60.

As shown in FIGS. 3, 4 and 10, the insulating material 39 has an interposition part 391 and an extension part 392. The interposition part 391 is sandwiched between the first terminal part 312 of the first input terminal 31 and the second terminal part 322 of the second input terminal 32. The extending portion 392 extends from the interposition portion 391 toward the one side in the first direction x further than the first terminal portion 312 and the second terminal portion 322. Both sides of the extending portion 392 in the second direction y are covered with the sealing resin 60.

The output terminal 33 is located on the other side in the first direction x, as shown in FIGS. From the output terminal 33, AC power (voltage) that has been power-converted by the plurality of semiconductor elements 40 is output. The output terminal 33 is a metal plate made of copper or a copper alloy. The output terminal 33 has a connecting portion 331 and a terminal portion 332. The boundary between the connection portion 331 and the terminal portion 332 is the surface along the second direction y and the thickness direction z, and the first side surface 63A of the sealing resin 60 located on the other side in the first direction x. Pass through the containing plane. The entire connection portion 331 is covered with the sealing resin 60. A comb tooth portion 331A is provided on one side of the connection portion 331 in the first direction x. The comb tooth portion 331A is connected to the second wiring layer 202 by soldering or ultrasonic bonding. As a result, the output terminal 33 is electrically connected to the second wiring layer 202. As shown in FIGS. 2 and 5, the terminal portion 332 extends from the sealing resin 60 to the other side in the first direction x. When viewed along the thickness direction z, the terminal portion 332 has a rectangular shape. Both sides of the terminal portion 332 in the second direction y are covered with the sealing resin 60. The other part of the terminal portion 332 is exposed from the sealing resin 60. Thereby, the output terminal 33 is supported by both the second wiring layer 202 and the sealing resin 60.

As shown in FIGS. 9 and 10, the plurality of semiconductor elements 40 are located on the side opposite to the support layer 10 with respect to the wiring layer 20 in the thickness direction z. The plurality of semiconductor elements 40 are joined to the wiring layer 20. All of the plurality of semiconductor elements 40 are the same element. The semiconductor element 40 is, for example, a MOSFET composed of a semiconductor material mainly containing silicon carbide (SiC). The semiconductor element 40 is not limited to the MOSFET and may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor). In the description of the semiconductor device A10, the case where the semiconductor element 40 is an n-channel type MOSFET is targeted.

As shown in FIG. 3, the plurality of semiconductor elements 40 include a plurality of first elements 401 and a plurality of second elements 402. 3 and 9 the plurality of first elements 401 are joined to the first wiring layer 201. The plurality of first elements 401 are arranged at predetermined intervals along the second direction y. The plurality of first elements 401 form an upper arm circuit (high voltage region) of the semiconductor device A10. In the first wiring layer 201, the plurality of first elements 401 are located on the other side in the first direction x with respect to the insulating layer 23.

As shown in FIGS. 3 and 10, the plurality of second elements 402 are joined to the second wiring layer 202. The plurality of second elements 402 are arranged at predetermined intervals along the second direction y. The plurality of second elements 402 form a lower arm circuit (low voltage region) of the semiconductor device A10. In the second wiring layer 202, the plurality of second elements 402 are located on one side of the insulating layer 23 in the first direction x.

As shown in FIG. 3, the plurality of first elements 401 and the plurality of second elements 402 are arranged in a staggered manner on the wiring layer 20 as a whole. In the example shown by the semiconductor device A10, the number of each of the first element 401 and the second element 402 is four. The number of each of the first element 401 and the second element 402 is not limited to this configuration, and can be set freely according to the performance required for the semiconductor device A10.

As shown in FIGS. 11 to 13, each of the plurality of semiconductor elements 40 has a first surface 40A, a second surface 40B, a first electrode 41, a second electrode 42, a gate electrode 43, and an insulating film 44. The first surface 40A and the second surface 40B face opposite sides in the thickness direction z. The first surface 40A faces the same side as the main surface 10A of the support layer 10 in the thickness direction z. Therefore, the second surface 40B faces the wiring layer 20.

As shown in FIGS. 11 to 13, the first electrode 41 is provided on the first surface 40A. A source current flows from the inside of the semiconductor element 40 to the first electrode 41.

As shown in FIGS. 12 and 13, the second electrode 42 is provided over the entire second surface 40B. A drain current flows through the second electrode 42 toward the inside of the semiconductor element 40. The second electrode 42 is bonded to the wiring layer 20 by a conductive bonding layer 49 having conductivity. Specifically, the second electrodes 42 of the plurality of first elements 401 are bonded to the first wiring layer 201 by the conductive bonding layer 49. The second electrodes 42 of the plurality of second elements 402 are bonded to the second wiring layer 202 by the conductive bonding layer 49. The conductive bonding layer 49 is, for example, lead-free solder whose main component is tin (Sn), or baked silver. As a result, the first input terminal 31 is electrically connected to the second electrodes 42 of the plurality of first elements 401 via the first wiring layer 201. The output terminal 33 is electrically connected to the second electrodes 42 of the plurality of second elements 402 via the second wiring layer 202.

As shown in FIGS. 11 to 13, the gate electrode 43 is provided on the first surface 40A. A gate voltage for driving the semiconductor element 40 is applied to the gate electrode 43. The size of the gate electrode 43 is smaller than that of the first electrode 41.

As shown in FIGS. 11 to 13, the insulating film 44 is provided on the first surface 40A. The insulating film 44 has electrical insulation. The insulating film 44 surrounds the first electrode 41 and the gate electrode 43 when viewed in the thickness direction z. The insulating film 44 is formed by stacking, for example, a silicon dioxide layer, a silicon nitride (Si ₃ N ₄ ) layer, and a polybenzoxazole (PBO) layer in this order from the first surface 40A. In the insulating film 44, a polyimide layer may be used instead of the polybenzoxazole layer.

The plurality of conductive members 50 are bonded to the first electrodes 41 of the plurality of first elements 401 and the second wiring layer 202, as shown in FIGS. 3, 9, and 12. When viewed along the thickness direction z, the plurality of conductive members 50 have a strip shape extending in the first direction x. The conductive member 50 is a metal piece made of copper or a copper alloy. The ends of the plurality of conductive members 50 located on one side in the first direction x are bonded to the first electrodes 41 of the plurality of first elements 401 by the conductive bonding layer 49. The ends of the plurality of conductive members 50 located on the other side in the first direction x are bonded to the second wiring layer 202 by the conductive bonding layer 49. As a result, the output terminal 33 is electrically connected to the first electrodes 41 of the plurality of first elements 401 via the second wiring layer 202. The conductive member 50 may be composed of a plurality of wires. The wire is made of aluminum or aluminum alloy, for example.

As shown in FIGS. 3, 10 and 13, the ends of the plurality of extending portions 321B of the second input terminal 32, which are located on the other side in the first direction x, are provided with the plurality of second elements by the conductive bonding layer 49. It is connected to the first electrode 41 of 402. As a result, the second input terminal 32 is electrically connected to the first electrodes 41 of the plurality of second elements 402.

As shown in FIG. 3, the plurality of gate wires 51 include a plurality of first gate wires 511 and a plurality of second gate wires 512. The plurality of first gate wires 511 are connected to the gate electrodes 43 of the plurality of first elements 401 and one gate wiring layer 24 located on the first wiring layer 201 (see FIGS. 3 and 11). ). As a result, the gate electrodes 43 of the plurality of first elements 401 are electrically connected to the gate wiring layer 24. The plurality of second gate wires 512 are connected to the gate electrodes 43 of the plurality of second elements 402 and the other gate wiring layer 24 located on the second wiring layer 202 (see FIGS. 3 and 11). ). As a result, the gate electrodes 43 of the plurality of second elements 402 are electrically connected to the gate wiring layer 24. The gate wire 51 is made of, for example, gold (Au), aluminum, or aluminum alloy.

As shown in FIG. 3, the plurality of detection wires 52 include a plurality of first detection wires 521 and a plurality of second detection wires 522. The plurality of first detection wires 521 are connected to the first electrodes 41 of the plurality of first elements 401 and one detection wiring layer 25 located on the first wiring layer 201 (FIGS. 3 and 11). reference). Thereby, the first electrodes 41 of the plurality of first elements 401 are electrically connected to the detection wiring layer 25. The plurality of second detection wires 522 are connected to the first electrodes 41 of the plurality of second elements 402 and the other detection wiring layer 25 located on the second wiring layer 202. Thereby, the first electrodes 41 of the plurality of second elements 402 are electrically connected to the detection wiring layer 25. The detection wire 52 is made of aluminum or aluminum alloy, for example.

As shown in FIG. 3, the pair of gate terminals 34, the pair of detection terminals 35, and the plurality of dummy terminals 36 are adjacent to the wiring layer 20 in the second direction y. These terminals are arranged along the first direction x. The pair of gate terminals 34, the pair of detection terminals 35, and the plurality of dummy terminals 36 are all composed of the same lead frame.

As shown in FIG. 3, one of the pair of gate terminals 34 is adjacent to the first wiring layer 201 and the other is adjacent to the second wiring layer 202. A gate voltage for driving the plurality of first elements 401 is applied to the gate terminal 34 adjacent to the first wiring layer 201. A gate voltage for driving the plurality of second elements 402 is applied to the gate terminal 34 adjacent to the second wiring layer 202. Each of the pair of gate terminals 34 has a connection portion 341 and a terminal portion 342. The connection portion 341 is covered with the sealing resin 60. As a result, the pair of gate terminals 34 are supported by the sealing resin 60. The surface of the connecting portion 341 may be plated with silver, for example. The terminal portion 342 is connected to the connection portion 341 and is exposed from the sealing resin 60 (see FIG. 3). As shown in FIG. 1, the terminal portion 342 has an L shape when viewed along the first direction x.

As shown in FIG. 3, the pair of detection terminals 35 are adjacent to the pair of gate terminals 34 in the first direction x. The voltage applied to the first electrodes 41 of the plurality of first elements 401, that is, the voltage corresponding to the source current is detected at the detection terminal 35 adjacent to the first wiring layer 201. The voltage applied to the first electrodes 41 of the plurality of second elements 402 is applied to the detection terminal 35 adjacent to the second wiring layer 202. Each of the pair of detection terminals 35 has a connection portion 351 and a terminal portion 352. The connection portion 351 is covered with the sealing resin 60. As a result, the pair of detection terminals 35 are supported by the sealing resin 60. The surface of the connection portion 351 may be plated with silver, for example. The terminal portion 352 is connected to the connection portion 351 and is exposed from the sealing resin 60 (see FIG. 3). As shown in FIG. 1, the terminal portion 352 has an L shape when viewed along the first direction x.

As shown in FIG. 3, the plurality of dummy terminals 36 are located on the opposite side of the pair of detection terminals 35 in the first direction x from the pair of gate terminals 34. In the example shown by the semiconductor device A10, the number of dummy terminals 36 is six. Of these, the three dummy terminals 36 are located on one side in the first direction x. The remaining three dummy terminals 36 are located on the other side in the first direction x. The number of dummy terminals 36 is not limited to this configuration. Furthermore, the semiconductor device A10 may not have the plurality of dummy terminals 36. Each of the plurality of dummy terminals 36 has a connecting portion 361 and a terminal portion 362. The connection portion 361 is covered with the sealing resin 60. Thereby, the plurality of dummy terminals 36 are supported by the sealing resin 60. The surface of the connecting portion 361 may be plated with silver, for example. The terminal portion 362 is connected to the connection portion 361 and is exposed from the sealing resin 60 (see FIG. 3). As shown in FIGS. 1, 6 and 7, the terminal portion 362 has an L shape when viewed along the first direction x. The shape of each of the terminal portions 342 of the pair of gate terminals 34 and the terminal portion 352 of the pair of detection terminals 35 is the same as the shape of the terminal portion 362.

As shown in FIG. 3, the pair of first wires 531 are individually connected to the pair of gate terminals 34 and the pair of gate wiring layers 24. As a result, the one gate terminal 34 adjacent to the first wiring layer 201 is electrically connected to the gate electrodes 43 of the plurality of first elements 401. The other gate terminal 34 adjacent to the second wiring layer 202 is electrically connected to the gate electrodes 43 of the plurality of second elements 402. The first wire 531 is made of, for example, aluminum or aluminum alloy.

As shown in FIG. 3, the pair of second wires 532 are individually connected to the pair of detection terminals 35 and the pair of detection wiring layers 25. As a result, the one detection terminal 35 adjacent to the first wiring layer 201 is electrically connected to the first electrodes 41 of the plurality of first elements 401. The other detection terminal 35 adjacent to the second wiring layer 202 is electrically connected to the first electrodes 41 of the plurality of second elements 402. The second wire 532 is made of, for example, aluminum or aluminum alloy.

As shown in FIG. 9 and FIG. 10, the sealing resin 60 includes the support layer 10, the first input terminal 31, the second input terminal 32, and the output terminal 33, a part thereof, the wiring layer 20, and the plurality of semiconductor elements. 40 and a plurality of conducting members 50 are covered. The sealing resin 60 includes a pair of insulating layers 23, a pair of gate wiring layers 24, a pair of detection wiring layers 25, a plurality of gate wires 51, a plurality of detection wires 52, a pair of first wires 531 and a pair of second wires. 532 is covered. Further, the sealing resin 60 covers a part of each of the pair of gate terminals 34, the pair of detection terminals 35, and the plurality of dummy terminals 36. The sealing resin 60 is derived from, for example, a black epoxy resin. As shown in FIGS. 2 to 8, the sealing resin 60 includes a top surface 61, a bottom surface 62, a pair of first side surfaces 63A, a pair of second side surfaces 63B, a plurality of third side surfaces 63C, and a plurality of fourth side surfaces 63D. , A plurality of notches 63E and a plurality of mounting holes 64.

As shown in FIGS. 9 and 10, the top surface 61 faces the same side as the main surface 10A of the support layer 10 in the thickness direction z. The bottom surface 62 faces the side opposite to the top surface 61 in the thickness direction z. As shown in FIG. 5, the back surface 10B of the support layer 10 (insulating portion 11) is exposed from the bottom surface 62.

As shown in FIGS. 2 to 7 and 10, the pair of first side surfaces 63A is connected to both the top surface 61 and the bottom surface 62, and faces the first direction x. From the first side surface 63A located on one side of the first direction x, the first terminal portion 312 of the first input terminal 31 and the second terminal portion 322 of the second input terminal 32 are placed on one side of the first direction x. Extending towards. The terminal portion 332 of the output terminal 33 extends from the first side surface 63A located on the other side in the second direction y toward the other side in the first direction x. As described above, a part of each of the first input terminal 31 and the second input terminal 32 is exposed from the sealing resin 60 on one side in the first direction x. In addition, part of the output terminal 33 is exposed from the sealing resin 60 on the other side in the first direction x.

As shown in FIGS. 2 to 8, the pair of second side surfaces 63B is connected to both the top surface 61 and the bottom surface 62 and faces the second direction y. The terminal portions 342 of the pair of gate terminals 34, the terminal portions 352 of the pair of detection terminals 35, and the terminal portions 362 of the plurality of dummy terminals 36 are exposed from either one of the pair of second side surfaces 63B.

As shown in FIGS. 2 to 7 and 10, the plurality of third side surfaces 63C are connected to both the top surface 61 and the bottom surface 62 and face the second direction y. The plurality of third side surfaces 63C includes a pair of third side surfaces 63C located on one side in the first direction x and a pair of third side surfaces 63C located on the other side in the first direction x. On each of the one side and the other side of the first direction x, the pair of third side surfaces 63C faces each other in the second direction y. Further, on each of the one side and the other side of the first direction x, the pair of third side faces 63C is connected to both ends of the first side face 63A in the second direction y.

As shown in FIGS. 2 to 10, the plurality of fourth side surfaces 63D are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. The plurality of fourth side surfaces 63D are located outside the semiconductor device A10 in the first direction x with respect to the pair of first side surfaces 63A. The multiple fourth side surfaces 63D include a pair of fourth side surfaces 63D located on one side in the first direction x and a pair of fourth side surfaces 63D located on the other side in the first direction x. On each of the one side and the other side of the first direction x, both ends of the pair of fourth side surfaces 63D in the second direction y are connected to the pair of second side surfaces 63B and the pair of third side surfaces 63C.

As shown in FIGS. 2 and 5, each of the plurality of cutout portions 63E is located at the boundary between the first side surface 63A and the third side surface 63C. When viewed along the thickness direction z, each of the plurality of cutout portions 63E is inclined with respect to both the first direction x and the second direction y.

As shown in FIG. 9, the plurality of mounting holes 64 penetrate the sealing resin 60 from the top surface 61 to the bottom surface 62 in the thickness direction z. The plurality of attachment holes 64 are used when attaching the semiconductor device A10 to the heat sink. As shown in FIGS. 2 and 5, when viewed along the thickness direction z, the hole edges of the plurality of mounting holes 64 are circular. The plurality of mounting holes 64 are located at the four corners of the sealing resin 60 when viewed in the thickness direction z.

Next, the function and effect of the semiconductor device A10 will be described.

The semiconductor device A10 includes a support layer 10 having a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z, a wiring layer 20 bonded to the main surface 10A, and a portion between the main surface 10A and the wiring layer 20. And a bonding layer 19 interposed therebetween. The wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. As a result, the bonding state between the main surface 10A and the wiring layer 20 is stronger and more heat resistant than the intermolecular force bonding using solder or the like. Therefore, according to the semiconductor device A10, it is possible to improve the joint reliability between the support layer 10 and the wiring layer 20.

The support layer 10 of the semiconductor device A10 has an insulating portion 11 including the back surface 10B, a supporting portion 12 including the main surface 10A, and an intermediate portion 13 interposed between the insulating portion 11 and the supporting portion 12. The support portion 12 is joined to the insulating portion 11 by molecular joining via the intermediate portion 13. Therefore, the joined state between the insulating portion 11 and the support portion 12 is stronger than the intermolecular force joining and is more resistant to heat. In this case, the Young's modulus of the support portion 12 in the thickness direction z is smaller than the Young's modulus of the wiring layer 20 in the thickness direction z. Thereby, the thermal stress caused by the heat generated from the semiconductor element 40 and acting on the interface between the main surface 10A and the wiring layer 20 can be relaxed.

As shown in FIGS. 12 and 13, the thickness t1 of the insulating portion 11 is larger than the thickness t2 of the supporting portion 12. In other words, the thickness t2 of the support portion 12 is smaller than the thickness t1 of the insulating portion 11. Thereby, the heat conducted from the wiring layer 20 to the supporting portion 12 can be conducted to the insulating portion 11 more quickly.

As shown in FIGS. 12 and 13, each of the thickness t1 of the insulating portion 11 and the thickness t2 of the supporting portion 12 is smaller than the thickness t3 of the wiring layer 20. In other words, the thickness t3 of the wiring layer 20 is larger than each of the thickness t1 of the insulating portion 11 and the thickness t2 of the supporting portion 12. Thereby, the thermal resistance per unit length of the wiring layer 20 in the direction orthogonal to the thickness direction z is reduced as compared with the case of using a metal foil, for example. As a result, the heat generated from the semiconductor element 40 is relieved from being locally concentrated in the wiring layer 20, and the heat is more easily transmitted in a wider range.

The semiconductor device A10 further includes a sealing resin 60 that covers the wiring layer 20, the semiconductor element 40, and a part of the support layer 10. The back surface 10B of the support layer 10 is exposed from the sealing resin 60. Thereby, the heat dissipation of the semiconductor device A10 can be further improved.

In the semiconductor device A10, the area of the first support layer 101 is larger than the area of the first wiring layer 201 when viewed along the thickness direction z. In addition, the area of the second support layer 102 is larger than the area of the second wiring layer 202 when viewed along the thickness direction z. As a result, the withstand voltage of the semiconductor device A10 can be improved.

The semiconductor device A10 further includes a first input terminal 31 connected to the first wiring layer 201 and a second input terminal 32 connected to the second element 402. The first input terminal 31 and the second input terminal 32 are located on one side in the first direction x. The first input terminal 31 and the second input terminal 32 are separated from each other in the thickness direction z. When viewed along the thickness direction z, at least a portion (second terminal portion 322) of the second input terminal 32 overlaps the first input terminal 31. Accordingly, when the semiconductor device A10 is used, the self-inductance of the first input terminal 31 can be reduced by the magnetic field generated from the second input terminal 32, so that the reduction in the power conversion efficiency of the semiconductor device A10 is suppressed. ..

[Second Embodiment]
A semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. In these figures, the same or similar elements of the semiconductor device A10 described above are designated by the same reference numerals, and duplicated description will be omitted. Here, in FIG. 14, for convenience of understanding, the sealing resin 60 is transparent. The transparent sealing resin 60 is shown by an imaginary line.

The semiconductor device A20 is different from the semiconductor device A10 described above in the configurations of the support layer 10 and the wiring layer 20.

As shown in FIGS. 14 to 17, in the semiconductor device A20, the area of the first support layer 101 is smaller than the area of the first wiring layer 201 when viewed along the thickness direction z. The area of the second support layer 102 is smaller than the area of the second wiring layer 202 when viewed along the thickness direction z. Thereby, in the semiconductor device A20, a part of the sealing resin 60 is interposed between the bottom surface 62 of the sealing resin 60 and the wiring layer 20.

Next, the function and effect of the semiconductor device A20 will be described.

The semiconductor device A20 includes a support layer 10 having a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z, a wiring layer 20 bonded to the main surface 10A, and a portion between the main surface 10A and the wiring layer 20. And a bonding layer 19 interposed therebetween. The wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. Therefore, also in the semiconductor device A20, it is possible to improve the joint reliability between the support layer 10 and the wiring layer 20.

In the semiconductor device A20, the area of the first support layer 101 is smaller than the area of the first wiring layer 201 when viewed along the thickness direction z. In addition, the area of the second support layer 102 is smaller than the area of the second wiring layer 202 when viewed along the thickness direction z. As a result, a part of the surface of the wiring layer 20 facing the same side as the back surface 10B of the support layer 10 in the thickness direction z is in contact with the sealing resin 60. Therefore, even if the back surface 10B is exposed from the bottom surface 62 of the sealing resin 60, it is possible to prevent the support layer 10 and the wiring layer 20 from falling off the bottom surface 62.

[Third Embodiment]
A semiconductor device A30 according to the third embodiment of the present invention will be described with reference to FIGS. In these figures, the same or similar elements of the semiconductor device A10 described above are designated by the same reference numerals, and duplicate description is omitted. Here, the cross-sectional position in FIG. 18 is the same as the cross-sectional position in FIG. 9 of the semiconductor device A10 described above. The sectional position of FIG. 19 is the same as the sectional position of FIG. 10 of the semiconductor device A10 described above.

In the semiconductor device A30, the configurations of the support layer 10 and the wiring layer 20 are different from those of the semiconductor device A10 described above.

As shown in FIGS. 18 to 21, in the semiconductor device A30, the support layer 10 is an insulating plate that does not have the insulating portion 11, the supporting portion 12, and the intermediate portion 13. The support layer 10 is, for example, a ceramic containing aluminum nitride.

As shown in FIGS. 18 to 21, in the semiconductor device A30, the wiring layer 20 has a base layer 21 and a conductive layer 22. The base layer 21 occupies most of the volume of the wiring layer 20. The base layer 21 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. The base layer 21 is made of a material containing carbon. In the semiconductor device A30, the base layer 21 is made of a material containing single crystal graphite. The material of the base layer 21 may include, for example, carbon fiber reinforced plastic (CFRP). As shown in FIG. 22, the in-plane direction of the single crystal graphite, which is the direction in which the crystals 21A of the single crystal graphite are continuous, is parallel to the thickness direction z. The out-of-plane direction of the single crystal graphite, which is the direction in which the crystals 21A of the single crystal graphite are stacked, is parallel to the direction orthogonal to the thickness direction z (the second direction y in the example shown by the semiconductor device A30). .. As shown in FIGS. 20 and 21, the thickness t5 of the base layer 21 is larger than the thickness t4 of the support layer 10.

As shown in FIGS. 18 to 21, the conductive layer 22 is laminated on the base layer 21. The plurality of semiconductor elements 40 are joined to the conductive layer 22. The conductive layer 22 includes a metal thin film layer formed by a sputtering method and a plating layer formed by electrolytic plating. These are laminated on the base layer 21 in the order of the metal thin film layer and the plating layer. The metal thin film layer contains titanium (T) and copper. The plating layer contains copper.

A method of molecular bonding between the main surface 10A of the support layer 10 and the base layer 21 of the wiring layer 20 via the bonding layer 19 will be described. First, each of the main surface 10A and the surface of the base layer 21 of the wiring layer 20 is subjected to plasma treatment to roughen these surfaces and generate hydroxy groups on these surfaces. Then, a molecular binder containing triazinedithiol is applied to these surfaces. The molecular bonding agent is the same as the specific example of the molecular bonding agent used for the molecular bonding of the semiconductor device A10 described above. Next, the support layer 10 and the base layer 21 are heat-treated to chemically bond the hydroxy groups formed therein and the organic compound contained in the molecular bonding agent. As a result, triazinedithiol chemically bonded to the insulating portion 11 is generated on the main surface 10A. Similarly, triazinedithiol chemically bonded to the base layer 21 is generated on the surface of the base layer 21 coated with the molecular bonding agent. Finally, the main surface 10A on which triazinedithiol is produced and the surface of the base layer 21 are brought into close contact with each other and subjected to heating and pressure treatment, so that the triazinedithiols are disulfide-bonded to each other. Thereby, the base layer 21 is bonded to the main surface 10A by molecular bonding via the bonding layer 19.

Next, the function and effect of the semiconductor device A30 will be described.

The semiconductor device A30 includes a support layer 10 having a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z, a wiring layer 20 bonded to the main surface 10A, and a portion between the main surface 10A and the wiring layer 20. And a bonding layer 19 interposed therebetween. The wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. Therefore, also in the semiconductor device A30, it is possible to improve the joint reliability between the support layer 10 and the wiring layer 20.

In the semiconductor device A30, the support layer 10 is an insulating plate. The wiring layer 20 has a base layer 21 bonded to the main surface 10A of the support layer 10 and a conductive layer 22 laminated on the base layer 21 and bonded to the semiconductor element 40. The base layer 21 is made of a material containing single crystal graphite. As shown in FIG. 22, the in-plane direction of the single crystal graphite is parallel to the thickness direction z. As shown in FIGS. 20 and 21, the thickness t5 of the base layer 21 is larger than the thickness t4 of the support layer 10. This reduces the thermal resistance per unit length of the wiring layer 20 in both the thickness direction z and one direction (first direction x in the example shown by the semiconductor device A30) orthogonal to the thickness direction z. be able to. The thermal conductivity in the in-plane direction of single crystal graphite is about 4 times the thermal conductivity of copper (398 W/(m·K)). Therefore, the heat dissipation of the semiconductor device A30 can be further improved as compared with the semiconductor device A10 described above.

[Fourth Embodiment]
A semiconductor device A40 according to the fourth embodiment of the present invention will be described with reference to FIGS. In these figures, the same or similar elements of the semiconductor device A10 described above are designated by the same reference numerals, and duplicated description will be omitted. Here, the sectional position of FIG. 23 is the same as the sectional position of FIG. 9 of the semiconductor device A10 described above. The sectional position of FIG. 24 is the same as the sectional position of FIG. 10 of the semiconductor device A10 described above.

In the semiconductor device A40, the configurations of the support layer 10 and the wiring layer 20 are different from those of the semiconductor device A30 described above.

As shown in FIGS. 23 and 24, in the semiconductor device A40, the area of the first support layer 101 is smaller than the area of the first wiring layer 201 when viewed along the thickness direction z. The area of the second support layer 102 is smaller than the area of the second wiring layer 202 when viewed along the thickness direction z. Thus, in the semiconductor device A40, a part of the sealing resin 60 is interposed between the bottom surface 62 of the sealing resin 60 and the wiring layer 20.

Next, the function and effect of the semiconductor device A40 will be described.

The semiconductor device A40 includes a support layer 10 having a main surface 10A and a back surface 10B facing opposite sides in the thickness direction z, a wiring layer 20 bonded to the main surface 10A, and a portion between the main surface 10A and the wiring layer 20. And a bonding layer 19 interposed therebetween. The wiring layer 20 is bonded to the main surface 10A by molecular bonding via the bonding layer 19. Therefore, also by the semiconductor device A40, it is possible to improve the joint reliability between the support layer 10 and the wiring layer 20.

The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be modified in various ways.

A10, A20, A30, A40: Semiconductor device 10: Support layer 10A: Support surface 10B: Bottom surface 101: First support layer 102: Second support layer 11: Insulating portion 12: Support portion 13: Intermediate portion 19: Bonding layer 20 : Wiring layer 201: First wiring layer 202: Second wiring layer 23: Insulating layer 24: Gate wiring layer 25: Detection wiring layer 31: First input terminal 311: First connecting portion 312: First terminal portion 32: Second 2 input terminal 321: 2nd connection part 321A: connection part 321B: extension part 322: 2nd terminal part 33: output terminal 331: connection part 331A: comb tooth part 332: terminal part 34: gate terminal 341: connection part 342 : Terminal part 35: Detection terminal 351: Connection part 352: Terminal part 36: Dummy terminal 361: Connection part 362: Terminal part 39: Insulating material 391: Interposition part 392: Extension part 40: Semiconductor element 40A: First surface 40B : Second surface 401: First element 402: Second element 41: First electrode 42: Second electrode 43: Gate electrode 44: Insulating film 49: Conductive bonding layer 50: Conductive member 51: Gate wire 511: First gate Wire 512: Second gate wire 52: Detection wire 521: First detection wire 522: Second detection wire 531: First wire 532: Second wire 60: Sealing resin 61: Top surface 62: Bottom surface 63A: First side surface 63B: Second side surface 63C: Third side surface 63D: Fourth side surface 63E: Notch portion 64: Mounting hole t1, t2, t3: Thickness t4, t5: Thickness z: Thickness direction x: First direction y: First 2 directions

Claims (16)

A support layer having a main surface and a back surface facing each other in the thickness direction,
A wiring layer bonded to the main surface,
A semiconductor element located on the side opposite to the support layer with respect to the wiring layer in the thickness direction, and joined to the wiring layer,
A bonding layer interposed between the main surface and the wiring layer,
The semiconductor device, wherein the wiring layer is bonded to the main surface by molecular bonding via the bonding layer. The supporting layer has an insulating portion including the back surface, a supporting portion including the main surface, and an intermediate portion interposed between the insulating portion and the supporting portion,
The semiconductor device according to claim 1, wherein the support part is bonded to the insulating part by molecular bonding via the intermediate part. The semiconductor device according to claim 2, wherein the Young's modulus of the supporting portion in the thickness direction is smaller than the Young's modulus of the wiring layer in the thickness direction. The semiconductor device according to claim 3, wherein the thickness of the support portion is smaller than the thickness of the wiring layer. The support part is made of a material containing graphite,
The semiconductor device according to claim 3, wherein the wiring layer is made of a material containing copper. The semiconductor device according to claim 3, wherein the Young's modulus of the insulating portion in the thickness direction is higher than the Young's modulus of the supporting portion in the thickness direction. The semiconductor device according to claim 6, wherein the thickness of the insulating portion is smaller than the thickness of the wiring layer and larger than the thickness of the supporting portion. The semiconductor device according to claim 6, wherein the insulating portion is a ceramic containing aluminum nitride. The support layer is an insulating plate,
The wiring layer is made of a material containing carbon, and has a base layer bonded to the main surface, and a conductive layer laminated on the base layer and bonded to the semiconductor element,
The semiconductor device according to claim 1, wherein the base layer has a thickness greater than that of the support layer. The base layer is made of a material containing single crystal graphite,
The semiconductor device according to claim 9, wherein the in-plane direction of the single crystal graphite is parallel to the thickness direction. Further comprising a sealing resin that covers the wiring layer and the semiconductor element, and a part of the support layer,
The semiconductor device according to claim 1, wherein the back surface is exposed from the sealing resin. The support layer includes a first support layer and a second support layer separated from each other in a direction orthogonal to the thickness direction,
The wiring layer includes a first wiring layer joined to the first support layer and a second wiring layer joined to the second support layer,
The semiconductor element includes a first element joined to the first wiring layer and a second element joined to the second wiring layer,
A first input terminal connected to the first wiring layer;
A second input terminal connected to the second element;
An output terminal connected to the second wiring layer,
A conductive member joined to the first element and the second wiring layer,
The semiconductor device according to claim 11, wherein the sealing resin covers the conductive member and a part of each of the first input terminal, the second input terminal, and the output terminal. When viewed along the thickness direction, the area of the first support layer is larger than the area of the first wiring layer, and the area of the second support layer is larger than the area of the second wiring layer. The semiconductor device according to claim 12, which is large. When viewed along the thickness direction, the area of the first support layer is smaller than the area of the first wiring layer, and the area of the second support layer is smaller than the area of the second wiring layer. The semiconductor device according to claim 12, which is small. Part of each of the first input terminal and the second input terminal is exposed from the sealing resin on one side in one direction orthogonal to the thickness direction,
15. The semiconductor device according to claim 12, wherein a part of the output terminal is exposed from the sealing resin on the other side in the one direction. The first input terminal and the second input terminal are separated from each other in the thickness direction,
The first input terminal has a first terminal portion exposed from the sealing resin,
The second input terminal has a second terminal portion exposed from the sealing resin,
The semiconductor device according to claim 15, wherein at least a part of the second terminal portion overlaps with the first terminal portion when viewed along the thickness direction.

Images