JP2020091318A - Thin-film transistor substrate and display panel - Google Patents

Abstract

To provide a TFT substrate that has a structure in which a plurality of gate signal lines and a plurality of gate leader lines and a plurality of dummy gate leader lines intersect with each other, and still has a high degree of freedom in wiring layout, and a display panel.SOLUTION: A thin-film transistor substrate comprises: a thin-film transistor 20 and a pixel electrode 30 that are provided in each of a plurality of pixels constituting a pixel area 2a; a plurality of gate signal lines 11 that extend in a first direction in the pixel area 2a; a plurality of gate leader lines 13 and a plurality of dummy gate leader lines 14 that extend in a second direction in the pixel area 2a; a plurality of common lines 15 that extend in at least one of the first direction and second direction in the pixel area 2a and are applied with a common potential; and a common electrode 40 that is electrically connected to the plurality of common lines 15. The plurality of gate leader lines 13 are connected to the gate signal lines 11, and the plurality of dummy gate leader lines 14 are applied with the common potential.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a thin film transistor substrate and a display panel including the same.

A display panel such as a liquid crystal display panel or an organic EL (Electro Luminescence) display panel includes a thin film transistor substrate (hereinafter, referred to as a “TFT substrate”) provided with a thin film transistor (TFT; Thin Film Transistor).

In particular, an active matrix drive type display panel includes an active matrix substrate having a TFT provided for each pixel in a pixel region as a TFT substrate. An active matrix driving type liquid crystal display panel includes, for example, a TFT substrate provided with a TFT for each pixel, a counter substrate facing the TFT substrate, and a liquid crystal layer arranged between the TFT substrate and the counter substrate. ing.

In addition to the TFTs, a plurality of wirings such as gate signal lines and source signal lines are formed in the pixel region of the TFT substrate. A gate driver that supplies a gate signal to the gate signal line and a source driver that supplies a video signal to the source signal line are mounted on the TFT substrate.

As a mounting method of the gate driver and the source driver, for example, a COF (Chip On Film) method in which a TCP (Tape Carrier Package) in which the gate driver and the source driver are mounted on a flexible wiring substrate is connected to a frame region of the TFT substrate, or , COG (Chip On Glass) method in which the gate driver and the source driver are directly mounted on the TFT substrate. Therefore, in the frame region of the TFT substrate, a gate terminal portion including a plurality of gate terminal electrodes electrically connected to the gate driver and a source terminal including a plurality of source terminal electrodes electrically connected to the source driver. And a section are provided.

Generally, the gate terminal portion and the source terminal portion are provided on two adjacent sides in the frame area of the rectangular TFT substrate, but in recent years, the gate terminal portion and the source terminal portion are provided for the purpose of narrowing the frame of the display panel and the like. A technique has been proposed in which the source terminal portion is provided on the same side of the frame region (for example, Patent Document 1).

Japanese Patent Publication No. 2008-501138 U.S. Patent Application Publication No. 2010/0188378

When the gate terminal portion and the source terminal portion are provided on the same side of the frame region, for example, the gate terminal portion and the source terminal portion may be provided on only one of the pair of long sides.

In this case, in order to electrically connect the gate terminal portion and the gate signal line extending in the row direction (direction parallel to the short side), a plurality of gate signal lines extending in the column direction (direction parallel to the long side) are connected. A gate lead-out line is separately formed in the pixel region, and a plurality of gate lead-out lines and a plurality of gate signal lines that are orthogonal to each other are connected through a contact hole. In this way, by providing a gate lead line that intersects with the gate signal line in a three-dimensional manner, even if the gate terminal portion and the source terminal portion are provided on the same long side of the frame region, the gate lead line is used to provide a gate. The terminal portion and the gate signal line can be electrically connected. That is, the gate driver and the gate signal line can be electrically connected.

In this case, since the number of pixels arranged in the row direction is different from the number of pixels arranged in the column direction in the horizontally long rectangular TFT substrate, the gate leader lines extending in the column direction are different from each other in the pixel region. It does not need to be formed in the entire area inside, but is partially formed in the pixel area. As a result, a difference in density of the wiring patterns of the gate lead lines occurs in the pixel area.

Therefore, conventionally, in a TFT substrate having a structure in which a plurality of gate signal lines and a plurality of gate lead lines cross each other, in order to suppress a loading effect due to a difference in density of wiring patterns of the gate lead lines, There is proposed a technique of forming a plurality of dummy gate lead lines in parallel with the above (Patent Document 2).

However, in the structure disclosed in Patent Document 2, in order to apply a predetermined potential to the plurality of dummy gate lead lines, all the dummy gate lead lines are brought close to the frame region and then connected to the gate terminal portion. Therefore, the degree of freedom of layout in the frame region of various lines such as the gate lead line, the dummy gate lead line, and the source signal line is low.

In particular, when the gate terminal portion and the source terminal portion are provided on the same side of the frame region, various wirings such as the source signal lines as well as the gate lead lines are concentrated on one side. Layout restrictions are increased. Further, when the gate driver and the source driver are directly mounted in the frame area by the COG method, the degree of freedom in the layout of the layout of the gate driver and the source driver is reduced, and various wirings such as the gate lead line and the source signal line are not provided. The degree of freedom in wiring layout is further reduced.

The present disclosure has been made to solve such a problem, and has a wiring layout having a structure in which a plurality of gate signal lines intersects a plurality of gate lead lines and a plurality of dummy gate lead lines. It is an object of the present invention to provide a TFT substrate and a display panel that have high flexibility.

In order to achieve the above object, one mode of a TFT substrate according to the present disclosure is a thin film transistor substrate having a pixel region configured by a plurality of pixels and a frame region surrounding the pixel region, wherein A thin film transistor and a pixel electrode provided in each pixel, a plurality of gate signal lines extending in the first direction in the pixel region and supplying a gate signal to the thin film transistor in each of the plurality of pixels, and in the pixel region, A plurality of gate leader lines and a plurality of dummy gate leader lines extending in a second direction different from the first direction, and a plurality of dummy gate leader lines extending in at least one of the first direction and the second direction in the pixel region, and having a common potential. A plurality of common lines to be applied and a common electrode provided facing the pixel electrode and electrically connected to the plurality of common lines are provided, and the plurality of gate lead lines are provided to the plurality of gate signals. A line is connected to the gate signal line at least at one of a plurality of intersections of the plurality of gate lead lines, and the common potential is applied to the plurality of dummy gate lead lines.

Further, an aspect of the display panel according to the present disclosure includes the above-described thin film transistor substrate and an opposite substrate facing the thin film transistor substrate.

According to the present disclosure, a TFT substrate, a display panel, or the like having a high degree of freedom in wiring layout while having a structure in which a plurality of gate signal lines intersect with a plurality of gate lead lines and a plurality of dummy gate lead lines are provided. Can be realized.

It is a figure which shows typically the schematic structure of the image display apparatus which concerns on embodiment. FIG. 6 is a plan view showing a configuration of a pixel of the display panel according to the embodiment. FIG. 6 is a plan view showing a configuration around a gate terminal portion and a source terminal portion in the display panel according to the embodiment. FIG. 4 is a sectional view taken along line IV-IV in FIG. 2. It is sectional drawing in the VV line of FIG. It is sectional drawing in the VI-VI line of FIG. It is sectional drawing in the VII-VII line of FIG. It is sectional drawing in the VIII-VIII line of FIG. 9 is a partial cross-sectional view of a display panel according to Modification 1. FIG. FIG. 11 is a plan view showing a schematic configuration of a display panel according to Modification 2. FIG. 11 is a partial cross-sectional view taken along the line XI-XI of FIG. 10. FIG. 11 is a partial cross-sectional view of a display panel according to Modification 3. 16 is a plan view showing a schematic configuration of a display panel according to Modification 4. FIG. FIG. 11 is a partial cross-sectional view of a display panel according to Modification 5. FIG. 16 is a diagram showing another configuration of the display panel according to Modification 5.

Hereinafter, embodiments of the present disclosure will be described. It should be noted that each of the embodiments described below shows a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, and the arrangement positions and connection forms of the constituent elements shown in the following embodiments are merely examples and do not limit the present disclosure. Therefore, among the constituent elements in the following embodiments, the constituent elements that are not described in the independent claims showing the highest concept of the present disclosure will be described as arbitrary constituent elements.

Each drawing is a schematic diagram, and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each drawing. In addition, in each drawing, the same reference numerals are given to substantially the same configurations, and overlapping description will be omitted or simplified.

(Embodiment)
First, a schematic configuration of the image display device 1 according to the embodiment will be described with reference to FIGS. FIG. 1 is a diagram schematically showing a schematic configuration of an image display device 1 according to an embodiment. FIG. 2 is a plan view showing the configuration of the pixel PX of the display panel 2 according to the embodiment. Note that FIG. 2 shows the configuration of the pixel PX in the second region A2 in which the gate lead line 13 is formed in the pixel region 2a. Further, FIG. 3 is a plan view showing the configuration around the gate terminal portion 71 and the source terminal portion 72 in the display panel 2 according to the embodiment. Note that FIG. 3 shows a state in which neither the gate driver 3a nor the source driver 3b nor the flexible wiring board 4 is mounted on the gate terminal portion 71 and the source terminal portion 72.

The image display device 1 displays an image (video) in a pixel area composed of a plurality of pixels. The image displayed on the image display device 1 may be either a still image or a moving image.

As shown in FIG. 1, the image display device 1 includes a display panel 2, a gate driver 3a and a source driver 3b provided as drivers for driving the display panel 2, and a flexible wiring board 4 connected to the display panel 2. , And a circuit board 5 connected to the flexible wiring board 4.

The image display device 1 further includes a timing controller 6 that outputs control signals to the gate driver 3a and the source driver 3b, and a power supply circuit that generates various control voltages to be supplied to the gate driver 3a, the source driver 3b, and the display panel 2. 7 and an image processing circuit 8 for outputting image data to the timing controller 6 based on the input video signal.

In this embodiment, the timing controller 6 and the power supply circuit 7 are mounted on the circuit board 5. The circuit board 5 is a substantially rectangular plate-shaped printed circuit board (PCB; Printed Circuit Board), and the circuit board 5 is mounted with a plurality of electronic components constituting a timing controller 6, a power supply circuit 7, and the like. The circuit board 5 has a function of transmitting various signals output from the timing controller 6 and various control voltages output from the power supply circuit 7 to the gate driver 3a, the source driver 3b, and the display panel 2.

In the present embodiment, the image display device 1 is a liquid crystal display device, so the display panel 2 is a liquid crystal display panel. Therefore, although not shown, the image display device 1 includes a backlight arranged on the back side of the display panel 2.

The display panel 2 is a liquid crystal display panel that displays a color image, and includes a liquid crystal cell in which a liquid crystal layer is provided between a pair of substrates, and a pair of polarizing plates that sandwich the liquid crystal cell.

One of the pair of substrates sandwiching the liquid crystal layer is a TFT substrate 100 (first substrate) on which TFTs and wirings are formed, and the other of the pair of substrates is R (red), G (green) and B (blue). 2) is a CF substrate 200 (second substrate) on which each color filter (CF) is formed.

In the present embodiment, since the display panel 2 is an active matrix drive type display panel, the TFT substrate 100 is an active matrix substrate (TFT array substrate) in which a plurality of TFTs are provided in a matrix or the like. The liquid crystal driving method of the display panel 2 is a lateral electric field method such as an IPS (In Plane Switching) method or an FFS (Fringe Field Switching) method, but is a VA (Vertical Alignment) method or a TN (Twisted Nematic) method. May be.

As shown in FIG. 1, the display panel 2 has a pixel region 2a composed of a plurality of pixels and a frame region 2b surrounding the pixel region 2a. That is, the TFT substrate 100 and the CF substrate 200 have the pixel region 2a and the frame region 2b. The pixel area 2a is a display area (effective area) in which an image is displayed, and is composed of, for example, a plurality of pixels arranged in a matrix. The frame region 2b is a peripheral region of the display panel 2 and is a region located outside the pixel region 2a. The frame area 2b is a non-display area (invalid area) in which no image is displayed. In the present embodiment, the plan view shape of the display panel 2 is a rectangular shape. Specifically, the planar shapes of the TFT substrate 100 and the CF substrate 200 are rectangular. Therefore, the pixel area 2a has a rectangular shape, and the frame area 2b has a rectangular frame shape.

The TFT substrate 100 has, as wiring, a plurality of gate signal lines 11 (scanning signal lines), a plurality of source signal lines 12 (data lines), a plurality of gate lead lines 13, and a plurality of dummy gate lead lines 14. And a plurality of common lines 15. The plurality of gate signal lines 11, the plurality of source signal lines 12, the plurality of gate lead lines 13, the plurality of dummy gate lead lines 14 and the plurality of common lines 15 are formed at least in the pixel region 2a.

The plurality of gate signal lines 11 extend in the first direction in the pixel region 2a. In the present embodiment, the first direction is the horizontal row direction (direction parallel to the long side of the rectangular TFT substrate 100), and therefore the plurality of gate signal lines 11 extend in the row direction. ing. The plurality of gate signal lines 11 are formed in parallel with each other in the pixel region 2a.

The plurality of source signal lines 12 extend in the pixel area 2a in a second direction different from the first direction. In the present embodiment, the second direction is a direction orthogonal to the first direction and is a vertical column direction (direction parallel to the short side of the rectangular TFT substrate 100). The signal line 12 extends in the column direction. Therefore, the plurality of source signal lines 12 and the plurality of gate signal lines 11 cross each other. The plurality of source signal lines 12 are formed in parallel with each other in the pixel region 2a.

Each of the plurality of pixels forming the pixel region 2a is a region surrounded by the gate signal line 11 extending in the row direction and the source signal line 12 extending in the column direction.

As shown in FIG. 2, one gate signal line 11 is provided at each boundary between two pixels PX (sub-pixels) adjacent to each other in the column direction. Each gate signal line 11 is connected to each TFT 20 of the plurality of pixels PX arranged in the row direction, and supplies a gate signal to each TFT. Specifically, each gate signal line 11 is connected to the gate electrode GT of the TFT 20 of each pixel PX.

One source signal line 12 is provided at each boundary between two pixels PX that are adjacent in the row direction. Each source signal line 12 is connected to the plurality of TFTs 20 of each of the plurality of pixels PX arranged in the column direction, and supplies a data signal to each TFT. Specifically, each source signal line 12 is connected to one of the pair of source/drain electrodes SD of each TFT 20. In each pixel PX, the other of the source/drain electrodes SD of the TFT 20 is connected to the pixel electrode 30.

As shown in FIG. 2, a TFT 20, a pixel electrode 30, and a common electrode (common electrode) 40 are provided in each of the plurality of pixels PX forming the pixel region 2a. The TFT 20 has a gate electrode GT and a pair of source/drain electrodes SD. One of the pair of source/drain electrodes SD is a source electrode and the other is a drain electrode.

One TFT 20 and one pixel electrode 30 are provided for each pixel PX. Specifically, each of the red pixel PXR, the green pixel PXG, and the blue pixel PXB is provided with one TFT 20 and one pixel electrode 30. It should be noted that the TFT 20 and the pixel electrode 30 may be provided in plural in each pixel PX.

The common electrode 40 is provided so as to face the pixel electrode 30. The common electrode 40 and the pixel electrode 30 may face each other in the stacking direction, or may face each other in a direction intersecting the stacking direction.

Further, the common electrode 40 is provided over the plurality of pixels PX. Specifically, the common electrode 40 is provided over all the pixels PX in the pixel region 2a. That is, the common electrode 40 is one planar electrode common to all the pixels PX, and is formed over the entire pixel region 2a. The common electrode 40 may be provided for each pixel PX.

As shown in FIG. 1, a plurality of gate lead lines 13 are formed on the TFT substrate 100. The plurality of gate lead lines 13 extend in the second direction in the pixel region 2a. Specifically, the plurality of gate lead lines 13 extend in the column direction (vertical direction). The plurality of gate lead lines 13 are formed in parallel with each other in the pixel region 2a. That is, the plurality of gate lead lines 13 are formed in parallel with the plurality of source signal lines 12, and are orthogonal to the plurality of gate signal lines 11. Therefore, the plurality of gate lead lines 13 and the plurality of gate signal lines 11 cross each other.

Each gate lead-out line 13 supplies the gate signal output from the gate driver 3 a to the gate signal line 11 corresponding to the gate lead-out line 13. Therefore, the plurality of gate lead lines 13 are connected to the gate signal line 11 at least at one of a plurality of intersections between the plurality of gate signal lines 11 and the plurality of gate lead lines 13. That is, each of the plurality of gate signal lines 11 is electrically connected to one or more gate lead lines 13. Specifically, the plurality of gate signal lines 11 and the plurality of gate lead lines 13 are at least one of a plurality of three-dimensional intersections of the plurality of gate signal lines 11 and the plurality of gate lead lines 13 in the pixel region 2a. The connection is made at one location through the gate contact hole 11a.

For example, one gate signal line 11 and one gate lead line 13 are connected at one place. Therefore, each gate signal line 11 is connected to one gate lead line 13 at one gate contact hole 11a.

Note that one gate signal line 11 may be connected to two gate lead lines 13. In this case, one gate signal line 11 is connected to two gate lead lines 13 at two gate contact holes 11a. Further, the number of gate contact holes 11a in one gate signal line 11 is not limited to one or two, and may be three or more, and at least one is required. That is, one gate signal line 11 may be connected to at least one gate lead line 13.

As shown in FIG. 2, the gate lead line 13 is provided between two pixels PX adjacent to each other in the row direction. For example, the gate lead line 13 is partially provided for each of the three pixels PX that are adjacent in the row direction. As an example, the gate lead line 13 is provided for each of the three sub-pixels with the three sub-pixels of the red pixel PXR, the green pixel PXG, and the blue pixel PXB as one unit. The gate lead lines 13 may be formed between arbitrary pixels in the pixel region 2a according to the number of the plurality of gate signal lines 11 extending in the row direction.

As described above, the display panel 2 is provided with the gate signal line 11 which is a horizontal gate line extending in the row direction as a wiring (gate line) for a gate signal output from the gate driver 3a. A gate lead line 13 which is a vertical gate line extending in the column direction is provided.

In addition, as shown in FIG. 1, a plurality of dummy gate lead lines 14 are formed on the TFT substrate 100. The plurality of dummy gate lead lines 14 extend in the first direction in the pixel region 2a. Specifically, the plurality of dummy gate lead lines 14 extend in the column direction (vertical direction) like the plurality of source signal lines 12 and the plurality of gate lead lines 13. The plurality of dummy gate lead lines 14 are formed in parallel with each other in the pixel region 2a. That is, the plurality of dummy gate lead lines 14 are formed in parallel with the plurality of source signal lines 12 and the plurality of gate lead lines 13, and are orthogonal to the plurality of gate signal lines 11. Therefore, the plurality of dummy gate lead lines 14 and the plurality of gate signal lines 11 cross each other.

Unlike the gate lead line 13, the plurality of dummy gate lead lines 14 are not connected to the gate signal line 11. Further, the plurality of dummy gate lead lines 14 are not connected to the gate lead line 13 either. That is, the gate signal is not supplied to each of the plurality of dummy gate lead lines 14. As will be described later in detail, the common potential applied to the common line 15 is applied to the plurality of dummy gate lead lines 14.

The dummy gate lead-out line 14 is formed for the purpose of suppressing the reduction in display quality due to the difference in the density of the wiring patterns of the gate lead-out line 13. Therefore, the dummy gate lead-out line 14 is preferably formed in the same layout as the gate lead-out line 13 in the region of the pixel region 2a where the gate lead-out line 13 is not formed.

For example, one dummy gate lead-out line 14 may be provided for every three pixels PX adjacent to each other in the row direction, similarly to the gate lead-out line 13. As an example, one dummy gate lead line 14 is provided for each of the three sub-pixels with the three sub-pixels of the red pixel PXR, the green pixel PXG, and the blue pixel PXB as one unit.

In the present embodiment, the plurality of gate lead lines 13 are formed so as to have a unity. Further, the plurality of dummy gate lead lines 14 are also formed so as to have a unity. That is, in the pixel region 2a, a region in which only a plurality of gate lead lines 13 among the gate lead lines 13 and the dummy gate lead lines 14 are formed together and a dummy of the gate lead lines 13 and the dummy gate lead lines 14 are formed. There is a region in which only a plurality of gate lead lines 14 are formed together.

Specifically, as shown in FIG. 1, the pixel region 2a is divided into three regions, a first region A1, a second region A2, and a third region A3, along the first direction (row direction in the present embodiment). In this case, the plurality of gate lead lines 13 are collectively formed in the second area A2, and the plurality of dummy gate leader lines 14 are collectively formed in each of the first area A1 and the third area A3. ..

That is, only the gate lead-out line 13 of the gate lead-out line 13 and the dummy gate lead-out line 14 is formed in the second region A2, and the dummy gate lead-out line 14 is not formed. The second region A2 is a gate connection region in which a gate contact hole 11a for connecting the gate lead line 13 and the gate signal line 11 is formed.

On the other hand, the first area A1 and the third area A3 are dummy areas in which only the dummy gate lead-out line 14 of the gate lead-out line 13 and the dummy gate lead-out line 14 is formed. , The gate lead line 13 is not formed.

In the present embodiment, the first area A1 is one end area in the row direction of the pixel area 2a, and the third area A3 is the other end area in the row direction of the pixel area 2a. The second area A2 is an area between the first area A1 and the third area A3. Specifically, the second region A2 is a central region including the center of the TFT substrate 100, and is a region in which all the plurality of gate lead lines 13 connected to the two gate terminal portions 71 are formed. The widths of the first area A1, the second area A2, and the third area A3 may be the same or different.

The common line 15 extends in at least one of the first direction and the second direction in the pixel region 2a. As shown in FIG. 1, in the present embodiment, the plurality of common lines 15 are arranged in the column direction (vertical direction) like the plurality of source signal lines 12, the plurality of gate lead lines 13 and the plurality of dummy gate lead lines 14. ), and are formed in parallel with each other in the pixel region 2a. That is, the plurality of common lines 15 are formed in parallel with the plurality of source signal lines 12, the plurality of gate lead lines 13 and the plurality of dummy gate lead lines 14, and are orthogonal to the plurality of gate signal lines 11. There is. Therefore, the plurality of common lines 15 and the plurality of gate signal lines 11 cross each other.

As shown in FIG. 2, in the present embodiment, the common line 15 is provided between two pixels PX that are adjacent to each other in the row direction. Specifically, one pixel is provided for every three pixels PX that are adjacent in the row direction. For example, like the gate lead line 13, the common line 15 is provided for each of the three sub-pixels, with the three sub-pixels of the red pixel PXR, the green pixel PXG, and the blue pixel PXB as one unit. ing. The common line 15 is formed over the entire area of the pixel area 2a. That is, the common line 15 is formed in each of the first area A1, the second area A2, and the third area A3.

The common line 15 may be provided between all pixels. Further, the common line 15 is not limited to extend only in the column direction, but may extend only in the row direction, or may extend in both the row direction and the column direction.

As shown in FIG. 2, in the second region A2, the common line 15 extends in the column direction so as to overlap the gate lead line 13 in a plan view. Although not shown, the common line 15 extends in the column direction so as to overlap the dummy gate lead line 14 in the plan view in the first area A1 and the third area A3. The common line 15 may be formed so as not to overlap the gate lead line 13 and the dummy gate lead line 14 in a plan view.

A common potential is applied to the plurality of common lines 15. In the present embodiment, the plurality of common lines 15 are connected to the common bus line 50 to which the common potential is applied. That is, the common potential is applied to the plurality of common lines 15 from the common bus line 50. Further, the common line 15 and the common electrode 40 are in contact with each other, and the common potential is applied to the common electrode 40. That is, the common line 15 and the common electrode 40 are set to have the same potential. Further, the common line 15 and the dummy gate lead-out line 14 have the same potential.

The common bus line 50 is formed in the frame region 2b of the TFT substrate 100. In the present embodiment, the common bus line 50 is formed so as to surround the pixel region 2a. Specifically, the common bus wiring 50 is formed in a rectangular frame shape. The shape of the common bus wiring 50 is not limited to the frame shape as long as the common bus wiring 50 and all the common lines 15 are connected.

A shield electrode 60 is also formed in the frame area 2b of the TFT substrate 100. The shield electrode 60 is also formed so as to surround the pixel region 2a. In the present embodiment, shield electrode 60 is formed so as to surround common bus line 50. Specifically, the shield electrode 60 is formed on the outermost periphery of the frame region 2b of the rectangular TFT substrate 100, and is formed over the long side and the short side of the frame region 2b. As an example, the shield electrode 60 is formed over at least three sides except the side where the gate terminal portion 71 and the source terminal portion 72 are provided.

By thus providing the shield electrode 60, signal noise can be suppressed. Therefore, it is preferable that a constant potential is applied to the shield electrode 60. In the present embodiment, the common potential is applied to the shield electrode 60. That is, the shield electrode 60, the common bus line 50, and the common line 15 are set to the same potential. Further, the shield electrode 60 has the same potential as the dummy gate lead line 14.

A plurality of slit-shaped or circular openings may be formed in the shield electrode 60. As an example, the shield electrode 60 is formed in a mesh shape having innumerable openings. In this way, by forming a plurality of openings in the shield electrode 60, even when a sealing member for sealing the liquid crystal layer between the TFT substrate 100 and the CF substrate 200 is laminated on the shield electrode 60, the sealing member is sealed. The stop member can be easily cured. For example, when the material of the sealing member is an ultraviolet curable resin, the sealing member applied on the shield electrode 60 can be irradiated with ultraviolet rays through the opening of the shield electrode 60 to cure the sealing member.

As described above, the TFT substrate 100 is provided with the plurality of gate signal lines 11, the plurality of source signal lines 12, the plurality of gate lead lines 13, the plurality of dummy gate lead lines 14, and the common line 15 as wiring. There is.

Since the source signal line 12, the gate lead line 13, the dummy gate lead line 14 and the common line 15 and the gate signal line 11 are orthogonal to each other, the source signal line 12, the gate lead line 13, the dummy gate lead line 14 and the common line 15 are connected to each other. The gate signal line 11 is formed in a metal layer (wiring layer) different from each other. The source signal line 12, the gate lead line 13 and the dummy gate lead line 14 are formed in the same metal layer.

In the present embodiment, the first metal layer on which the gate signal line 11 is formed is located below the second metal layer on which the source signal line 12, the gate lead line 13 and the dummy gate lead line 14 are formed. Specifically, the gate signal line 11 is covered with a gate insulating film, and the source signal line 12, the gate lead line 13 and the dummy gate lead line 14 are arranged on the gate insulating film. Specifically, interlayer insulation is provided between the first metal layer on which the gate signal line 11 is formed and the second metal layer on which the source signal line 12, the gate lead line 13 and the dummy gate lead line 14 are formed. A gate insulating film is formed as the film. The common line 15 is located above the second metal layer in which the source signal line 12, the gate lead line 13, and the dummy gate lead line 14 are formed.

The gate signal generated by the gate driver 3 a is supplied to the gate signal line 11 through the gate lead line 13. Further, the data signal generated by the source driver 3b is supplied to the source signal line 12.

As shown in FIG. 1, the gate driver 3a and the source driver 3b are mounted on the TFT substrate 100 by the COG method. Specifically, the gate driver 3a is mounted on the gate terminal portion 71 provided in the frame region 2b of the TFT substrate 100. The source driver 3b is mounted on the source terminal portion 72 provided in the frame region 2b of the TFT substrate 100.

In the present embodiment, the gate terminal portion 71 and the source terminal portion 72 are mounted on one of a pair of sides in the frame region 2b of the TFT substrate 100. That is, the gate terminal portion 71 and the source terminal portion 72 are provided on the same side of the frame region 2b.

Specifically, the gate terminal portion 71 and the source terminal portion 72 are only one of a pair of long sides (lower long side in FIG. 1) of the four sides of the frame region 2b in the rectangular TFT substrate 100. It is provided in. Therefore, the gate driver 3a and the source driver 3b are also mounted on only one of the pair of long sides of the frame region 2b on the TFT substrate 100. That is, the gate driver 3a and the source driver 3b are mounted on the same long side.

As an example, two gate terminal portions 71 are provided on one long side of the pair of long sides in the frame region 2b. Therefore, two gate drivers 3a are provided on one long side of the pair of long sides in the frame region 2b. Further, four source terminal portions 72 are provided on the same long side as that on which the gate terminal portion 71 is provided. Therefore, four source drivers 3b are mounted on the same long side on which the gate driver 3a is mounted. Each gate terminal portion 71 is provided between two adjacent source terminal portions 72. That is, each gate driver 3a is mounted between two adjacent source drivers 3b.

As shown in FIG. 3, the gate terminal portion 71 includes a plurality of gate terminal electrodes 71 a electrically connected to the plurality of gate signal lines 11. Specifically, each of the plurality of gate terminal electrodes 71a is electrically connected to each gate signal line 11 via the gate lead line 13 corresponding to each gate terminal electrode 71a. The plurality of gate terminal electrodes 71a are electrically connected to the plurality of gate signal lines 11 on a one-to-one basis.

In addition, the source terminal portion 72 includes a plurality of source terminal electrodes 72a electrically connected to the plurality of source signal lines 12. Specifically, the plurality of source terminal electrodes 72a are electrically connected to the plurality of source signal lines 12 on a one-to-one basis.

The gate driver 3 a mounted on the gate terminal portion 71 is electrically connected to the gate signal line 11. In the present embodiment, the gate driver 3a is electrically connected to the gate signal line 11 via the gate lead line 13. Specifically, the gate driver 3 a is electrically connected to the gate signal line 11 and the gate lead line 13 by the gate relay wiring 16 provided in the frame region 2 b of the TFT substrate 100.

The gate relay wiring 16 connects the gate lead wire 13 and the gate terminal electrode 71 a of the gate terminal portion 71. The gate relay wiring 16 is formed in a metal layer different from that of the gate lead wire 13, and is connected to the gate lead wire 13 via the contact hole 16a. Further, the gate relay wiring 16 is connected to the gate terminal electrode 71a through the contact hole 16b. In the present embodiment, the gate relay wiring 16 is formed in the same layer as the gate signal line 11. Therefore, the contact holes 16a and 16b are formed between the first metal layer on which the gate relay wiring 16 and the gate signal line 11 are formed and the second metal layer on which the source signal line 12 and the gate lead line 13 are formed. It is formed on the insulating film.

The gate driver 3a supplies a voltage corresponding to the timing signal supplied from the timing controller 6 as a gate signal to each gate signal line 11 in the pixel region 2a. Specifically, when the timing signal generated by the timing controller 6 is supplied to the gate driver 3a via the flexible wiring board 4 and the source terminal unit 72, the gate driver 3a outputs data according to the timing signal. An on-voltage V _ON (gate-on voltage) for turning on the TFT of a pixel to which a signal is written and an off-voltage V _OFF for _turning off the TFT are generated as gate signals. The gate signal generated by the gate driver 3a is supplied to the gate signal line 11 via the gate relay wiring 16 and the gate lead wire 13. The gate driver 3a is, for example, a gate driver IC composed of an IC chip.

The source driver 3b mounted on the source terminal portion 72 is electrically connected to the source signal line 12. In the present embodiment, the source driver 3b is electrically connected to the source signal line 12 by the source relay wiring 17 provided in the frame region 2b of the TFT substrate 100.

The source relay wiring 17 connects the source signal line 12 and the source terminal electrode 72 a of the source terminal portion 72. The source relay wiring 17 is formed in the same metal layer as the source signal line 12 and in a layer different from the gate relay wiring 16. As a result, the source relay wiring 17 and the gate relay wiring 16 can cross each other in the frame region 2b. Further, since the source relay wiring 17 and the source signal line 12 are formed in the same metal layer, the source relay wiring 17 and the source signal line 12 are continuously formed without a contact hole.

The source driver 3b supplies a voltage corresponding to the video signal representing the gradation value of each pixel supplied from the timing controller 6 to each source signal line 12 of the pixel region 2a as a data signal. Specifically, when the video signal generated by the timing controller 6 is supplied to the source driver 3b, the source driver 3b causes the gate driver 3a to select the gate selected based on the voltage corresponding to the video signal. A data signal supplied to each of the TFTs connected to the signal line 11 is generated. The data signal generated by the source driver 3b is supplied to each source signal line 12 in the pixel region 2a. As a result, the data signal is written in the pixel corresponding to the selected gate line. The source driver 3b is, for example, a source driver IC composed of an IC chip.

The flexible wiring board 4 is a wiring cable in which a plurality of pattern wirings are formed on a flexible board such as an FFC (Flexible Flat Cable) or an FPC (Flexible Printed Cable). In this embodiment, neither the gate driver 3a nor the source driver 3b is mounted on the flexible wiring board 4.

One end of the flexible wiring substrate 4 is connected to the frame region 2b of the TFT substrate 100 by, for example, ACF (Anisotropic Conductive Film) pressure bonding. On the other hand, the other end of the flexible wiring board 4 is connected to the circuit board 5 by ACF pressure bonding. As a result, the gate terminal portion 71 and the source terminal portion 72 provided in the frame area 2b of the TFT substrate 100, the timing controller 6 and the power supply circuit 7 of the circuit board 5 are electrically connected via the flexible wiring board 4. ..

In the present embodiment, the flexible wiring board 4 is connected only to the source terminal portion 72 of the gate terminal portion 71 and the source terminal portion 72. Therefore, various control signals and various control voltages supplied from the circuit board 5 are input only to the source terminal section 72 via the flexible wiring board 4. Therefore, various control signals and various control voltages supplied from the circuit board 5 to the gate terminal portion 71 are input to the gate terminal portion 71 via the source terminal portion 72. In this case, in addition to the source terminal electrode 72a to which the video signal from the timing controller 6 is input, the timing signal supplied from the timing controller 6 to the gate driver 3a via the gate terminal portion 71 is input to the source terminal portion 72. And a plurality of control signal terminal electrodes and control voltage terminal electrodes to which the control signals and control voltages supplied from the power supply circuit 7 to the gate driver 3a and the source driver 3b are input. ..

In the present embodiment, the source terminal portion 72 further includes a common terminal electrode 72b for applying a common potential to the common line 15. The common terminal electrode 72b is electrically connected to the power supply circuit 7 of the circuit board 5 via the flexible wiring board 4. The common voltage V _COM is input from the power supply circuit 7 to the common terminal electrode 72b. The common voltage V _COM supplied to the common terminal electrode 72b is supplied to the shield electrode 60 via the common relay wiring 18 formed in the frame region 2b. The common relay wiring 18 connects the common terminal electrode 72b and the shield electrode 60.

As a result, the common potential (common voltage V _COM ) is applied to the shield electrode 60 via the common relay wiring 18. Further, since the shield electrode 60 and the common bus line 50 are connected, when the common potential is applied to the shield electrode 60, the common potential is also applied to the common bus line 50. Therefore, the common potential is applied to the plurality of common lines 15 connected to the common bus line 50. The common voltage V _COM is a constant voltage, which is, for example, 1 V to 7 V, but is not limited to this.

The timing controller 6 reads the correction data stored in the memory, performs various image signal processing such as color adjustment on the image data from the image processing circuit 8 based on the correction data, and the TFT substrate 100. A video signal and a timing signal indicating the gradation value of each pixel are generated as the control signal supplied to the. The timing signal generated by the timing controller 6 is supplied to the gate driver 3a via the flexible wiring board 4 and the gate terminal portion 71. The video signal generated by the timing controller 6 is supplied to the source driver 3b via the flexible wiring board 4 and the source terminal portion 72. The timing controller 6 is composed of, for example, an arithmetic processing circuit such as a CPU. As an example, the timing controller 6 is composed of an IC chip.

The power supply circuit 7 generates various control voltages. Specifically, the power supply circuit 7 generates a power supply voltage (driving voltage) and a ground voltage as well as various voltages such as a common voltage V _COM as control voltages for controlling the gate driver 3a and the source driver 3b. The control voltage (power supply voltage, ground voltage, common voltage, etc.) generated by the power supply circuit 7 is supplied to the gate driver 3a, the source driver 3b, and the TFT substrate 100 via the flexible wiring board 4. Further, the common voltage generated by the power supply circuit 7 is supplied to the common bus wiring 50 and the shield electrode 60 via the flexible wiring board 4.

The image processing circuit 8 receives an input video signal transmitted from an external system (not shown), performs image processing, and then outputs image data to the timing controller 6. The image processing circuit 8 is not mounted on the circuit board 5, but may be mounted on the circuit board 5. As an example, the timing controller 6 is composed of an IC chip.

Next, the sectional structure of the display panel 2 will be described with reference to FIGS. 1 to 3 and FIGS. 4 to 8 are partial cross-sectional views of the display panel 2 according to the embodiment. FIG. 4 is a sectional view taken along line IV-IV in FIG. FIG. 5 is a sectional view taken along line VV of FIG. FIG. 6 is a sectional view taken along line VI-VI in FIG. FIG. 7 is a sectional view taken along line VII-VII in FIG. FIG. 8 is a sectional view taken along line VIII-VIII of FIG.

As shown in FIGS. 4 to 7, the display panel 2 includes a TFT substrate 100, a CF substrate 200 facing the TFT substrate 100, and a liquid crystal layer 300 disposed between the TFT substrate 100 and the CF substrate 200. Prepare The liquid crystal layer 300 is sealed between the TFT substrate 100 and the CF substrate 200 by a frame-shaped sealing member 400 formed in the frame region 2b.

On the TFT substrate 100, the TFT 20, various wirings such as the gate signal line 11, the source signal line 12, the gate lead-out line 13, the dummy gate lead-out line 14 and the common line 15, and an interlayer insulating film formed between these wirings. The pixel electrode 30, the common electrode 40, the common bus line 50, and the shield electrode 60 are provided. These members are formed on the first transparent substrate 110. The first transparent substrate 110 is, for example, a transparent base material such as a glass substrate or a transparent resin substrate.

As shown in FIG. 4, the TFT 20 formed on the first transparent substrate 110 is composed of a gate electrode GT, a pair of source/drain electrodes SD, and a semiconductor layer SC serving as a channel layer. In the present embodiment, the TFT 20 is a TFT having a bottom gate structure, and includes a gate electrode GT formed on the first transparent substrate 110 and a first insulating film that is a gate insulating film formed on the gate electrode GT. The film 121 and the semiconductor layer SC formed above the gate electrode GT via the first insulating film 121 are provided. Note that the pair of source/drain electrodes SD are formed on the semiconductor layer SC.

The gate electrode GT may be made of, for example, a metal film having a two-layer structure of a molybdenum film and a copper film, or may be made of a single-layer metal film made of a copper film or the like. The first insulating film 121 may be formed of, for example, an insulating film having a two-layer structure of a silicon oxide film and a silicon nitride film, or a single insulating film of a silicon oxide film or a silicon nitride film. May be. The semiconductor layer SC may be composed of, for example, a semiconductor film having a two-layer structure of an i-amorphous silicon film and an n-amorphous silicon film, or may be composed of a single-layer semiconductor film. The pair of source/drain electrodes SD may be made of, for example, a metal film having a two-layer structure of a molybdenum film and a copper film, or may be made of a single-layer metal film made of a copper film or the like. ..

The materials of the gate electrode GT, the pair of source/drain electrodes SD, the semiconductor layer SC, and the first insulating film (gate insulating film) 121 are not limited to the above materials. For example, as the material of the semiconductor layer SC, an In-Ga-Zn-O-based oxide semiconductor or the like may be used.

As shown in FIG. 4, the gate signal line 11 is formed in the same layer as the gate electrode GT. That is, the gate signal line 11 and the gate electrode GT are formed in the same first metal layer, and are formed by patterning the same metal film. Therefore, the gate electrode GT and the gate signal line 11 are made of the same material. In the present embodiment, the gate electrode GT is a part of the gate signal line 11.

The source signal line 12, the gate lead line 13 and the dummy gate lead line 14 are formed in the same layer as the pair of source/drain electrodes SD. That is, the source signal line 12, the gate lead line 13, the dummy gate lead line 14, and the pair of source/drain electrodes SD are formed in the same second metal layer (source/drain layer), and the same metal film is patterned. Formed by. In the present embodiment, one of the pair of source/drain electrodes SD, which is connected to the source signal line 12, is a part of the source signal line 12.

Further, as shown in FIG. 5, a shield electrode 60 is formed on the second metal layer (source/drain layer) where the dummy gate lead-out line 14 is formed. That is, the shield electrode 60 is formed in the same layer as the source signal line 12, the gate lead line 13, the dummy gate lead line 14, and the pair of source/drain electrodes SD. Therefore, the shield electrode 60, the source signal line 12, the gate lead line 13, the dummy gate lead line 14, and the pair of source/drain electrodes SD are made of the same material.

The first metal layer on which the gate signal line 11 and the gate electrode GT are formed is located below the second metal layer on which the source signal line 12, the gate lead line 13 and the like are formed. Therefore, the gate signal line 11 and the gate electrode GT, the source signal line 12, the gate lead line 13, the dummy gate lead line 14, the pair of source/drain electrodes SD, and the shield electrode 60 are formed in different metal layers.

As shown in FIGS. 2 and 4, the gate signal line 11 and the gate lead line 13 formed in different metal layers are connected via the gate contact hole 11a. The gate contact hole 11a is a contact portion between the gate signal line 11 and the gate lead line 13, and as shown in FIG. 4, the first metal layer on which the gate signal line 11 is formed and the gate lead line 13 are formed. It is formed on the first insulating film 121 between the second metal layer.

Further, as shown in FIGS. 4 to 8, above the first transparent substrate 110, the second insulating film is formed so as to cover the source signal line 12, the gate lead line 13, the dummy gate lead line 14, and the shield electrode 60. 122 is formed. Specifically, the second insulating film 122 covers the second metal layer formed on the first insulating film 121. The second insulating film 122 is composed of, for example, an inorganic insulating film made of an inorganic material such as a silicon nitride film. The second insulating film 122, which is an inorganic insulating film, can be formed by, for example, a CVD (chemical vapor deposition) method.

Further, a third insulating film 123 is formed so as to cover the second insulating film 122. In the present embodiment, the thickness of the third insulating film 123 is thicker than the thickness of the second insulating film 122. Specifically, the thickness of the third insulating film 123 is 10 times or more the thickness of the second insulating film 122, and is 3000 nm as an example. Accordingly, the distance in the thickness direction between the wirings such as the gate signal line 11 and the source signal line 12 and the common electrode 40 can be increased, so that the wirings such as the gate signal line 11 and the source signal line 12 and the common electrode 40 can be increased. The parasitic capacitance formed by 40 and 40 can be reduced. Moreover, by thickening the third insulating film 123, it is possible to flatten the TFT layer having a laminated structure in which the TFT 20, the gate signal line 11, the source signal line 12, and the like are formed. As a result, the third insulating film 123 whose surface is flattened can be formed, so that the common electrode 40 immediately above the third insulating film 123 can be formed in a flat planar shape.

In the present embodiment, the third insulating film 123 is composed of an organic insulating film made of an organic material containing carbon. The third insulating film 123, which is an organic insulating film, can be formed, for example, by applying a liquid organic material and curing it. As a result, the third insulating film 123 can be easily thickened, so that the surface of the third insulating film 123 can be easily flattened over all the pixels PX. That is, the third insulating film 123 functions as a flattening layer.

The common electrode 40 and the pixel electrode 30 formed on the TFT substrate 100 are laminated so as to face each other with the fourth insulating film 124 interposed therebetween. In the present embodiment, the pixel electrode 30 is located above the common electrode 40. That is, the common electrode 40 is located below the pixel electrode 30.

Specifically, the common electrode 40 is formed on the third insulating film 123, and the fourth insulating film 124 is formed so as to cover the common electrode 40. Then, the pixel electrode 30 is formed on the fourth insulating film 124 in a predetermined shape. As an example, the pixel electrode 30 is formed in a comb shape for each pixel PX, but the invention is not limited to this.

The common electrode 40 and the pixel electrode 30 are transparent electrodes made of a transparent metal oxide such as indium tin oxide (ITO). The fourth insulating film 124 is made of, for example, an inorganic insulating film such as a silicon nitride film. The fourth insulating film 124, which is an inorganic insulating film, can be formed by, for example, a CVD method.

As described above, the common electrode 40 is a flat solid electrode formed over all the pixels PX. Thereby, the wirings such as the gate signal line 11 and the source signal line 12 are covered with the common electrode 40, so that the electric field generated in the wirings such as the gate signal line 11 and the source signal line 12 can be shielded by the common electrode 40. .. That is, the common electrode 40 can shield the electric field generated in the TFT layer. Therefore, the degree of freedom in designing the shape and size of the pixel electrode 30 formed on the common electrode 40 is improved, so that the light transmittance and the aperture ratio of the pixel PX can be easily improved.

The common electrode 40 is a thin-film planar solid electrode, but as shown in FIG. 2, in order to connect the source/drain electrode SD of the TFT 20 and the pixel electrode 30 on the gate signal line 11 in the common electrode 40. The opening 40a is formed. Therefore, the opening 40a of the common electrode 40 is provided with a contact hole penetrating the insulating layer of the three-layer structure of the second insulating film 122, the third insulating film 123, and the fourth insulating film 124, and each pixel PX. In, the source drain electrode SD of the TFT 20 and the pixel electrode 30 are connected through this contact hole.

As shown in FIG. 4, a plurality of common lines 15 are formed on the common electrode 40. In the present embodiment, each common line 15 is provided immediately above the common electrode 40. That is, each common line 15 contacts the common electrode 40 and is laminated on the common electrode 40. Therefore, the fourth insulating film 124 covers not only the common electrode 40 but also the common line 15 laminated on the common electrode 40.

Each common line 15 is made of a material having a lower resistance than the common electrode 40. For example, the common line 15 is a metal film made of a metal material and having a light blocking property and conductivity. In the present embodiment, the common line 15 is made of a copper film. Thus, by stacking the common line 15 on the common electrode 40, the time constant of the common electrode 40 can be reduced.

A common potential is applied to the common line 15 via the common bus line 50. As shown in FIG. 5, the common bus line 50 includes a first electrode 51 formed in the same layer as the common electrode 40, and a second electrode 52 formed in the same layer as the common line 15 and laminated on the first electrode 51. Have and. Therefore, the first electrode 51 is made of the same material as the common electrode 40, and the second electrode 52 is made of the same material as the common line 15. Like the common electrode 40 and the common line 15, the common bus line 50 is covered with the fourth insulating film 124.

Further, a fifth insulating film 125 is formed on the pixel electrode 30. The fifth insulating film 125 is formed on the fourth insulating film 124 so as to cover the pixel electrode 30. In the present embodiment, the fifth insulating film 125 is formed over all the pixels PX.

The fifth insulating film 125 is an inorganic insulating film made of an inorganic material or an organic insulating film made of an organic material. The fifth insulating film 125 may be an alignment film made of an organic insulating film. The alignment film is in contact with the liquid crystal layer 300 and controls the initial alignment angle of liquid crystal molecules of the liquid crystal layer 300. Specifically, the alignment film is subjected to a rubbing treatment in order to align the initial alignment angle of the liquid crystal molecules in a certain direction. Note that when the fifth insulating film 125 is not an alignment film, an alignment film may be separately formed over the fifth insulating film 125.

In this embodiment, the first insulating film 121, the second insulating film 122, the third insulating film 123, the fourth insulating film 124, and the fifth insulating film 125 are formed not only in the pixel region 2a but also in the frame region 2b. Has been done. Specifically, the first insulating film 121, the second insulating film 122, the third insulating film 123, the fourth insulating film 124, and the fifth insulating film 125 are formed on the entire surface of the first transparent substrate 110.

Here, the connection relationship between various wirings and electrodes will be described in detail. First, the connection relationship between members to which a common potential is applied will be described in detail. In the present embodiment, the common potential is applied to the dummy gate lead line 14, the common line 15, the common electrode 40, the common bus line 50, and the shield electrode 60.

As shown in FIG. 1, the display panel 2 (TFT substrate 100) includes a first connection wiring 81 that connects each of the plurality of dummy gate lead lines 14 and the shield electrode 60. That is, each dummy gate lead wire 14 and the shield electrode 60 are connected via the first connection wiring 81. Specifically, one end of the dummy gate lead wire 14 is connected to the shield electrode 60 by the first connection wiring 81.

As shown in FIG. 5, the first connection wiring 81 connects each of the plurality of dummy gate lead lines 14 and the shield electrode 60 through the first contact hole 81a formed in the frame region 2b. As a result, the common potential can be applied to the plurality of dummy gate lead lines 14 via the shield electrode 60.

In the present embodiment, the first connection wiring 81 is formed in the same layer as the pixel electrode 30. Therefore, the first connection wiring 81 is made of the same material as the pixel electrode 30. In this way, when the first connection wiring 81 that connects the dummy gate lead-out line 14 and the shield electrode 60 is formed in the same layer as the pixel electrode 30, the first contact hole 81a has the second insulating film 122 and the third insulating film. It is formed so as to penetrate the film 123 and the fourth insulating film 124.

In this case, the first contact hole 81a can be formed simultaneously with the process of forming the contact hole for connecting the pixel electrode 30 and the source/drain electrode of the TFT 20. Thereby, the first contact hole 81a can be formed without increasing the number of photomasks. Further, the first connection wiring 81 can be formed in a predetermined shape at the same time as the process of patterning the pixel electrode 30. The first contact holes 81a are formed in at least two locations on the dummy gate lead-out line 14 and the shield electrode 60 for one first connection wiring 81.

Further, in the present embodiment, the first contact hole 81a is formed in the other long side (the upper long side in FIG. 1) of the pair of long sides in the frame region 2b. That is, the first contact hole 81a is formed on the long side opposite to the long side where the gate terminal portion 71 and the source terminal portion 72 are provided (the lower long side in FIG. 1). Therefore, the first connection wiring 81 is formed on the long side opposite to the long side on which the gate terminal portion 71 and the source terminal portion 72 are provided.

On the other hand, as shown in FIG. 1, on the long side where the gate terminal portion 71 and the source terminal portion 72 are provided (the lower long side in FIG. 1), the other end portion of the dummy gate lead-out line 14 has a common potential. Is connected to the common bus line 50 to which is applied. Specifically, the display panel 2 (TFT substrate 100) includes a second connection wiring 82 that connects the plurality of dummy gate lead-out lines 14 and the common bus wiring 50. That is, the other end of each dummy gate lead-out line 14 and the common bus line 50 are connected via the second connection line 82. As shown in FIG. 6, the second connection wiring 82 connects each of the plurality of dummy gate lead-out lines 14 and the common bus wiring 50 through the second contact hole 82a formed in the frame region 2b. Specifically, the second connection wiring 82 is connected to the second electrode 52 by coming into contact with the upper surface of the second electrode 52 in the upper layer of the common bus wiring 50.

In the present embodiment, the second connection wiring 82 is formed in the same layer as the pixel electrode 30. That is, the second connection wiring 82 is formed in the same layer as the first connection wiring 81. Therefore, like the first connection wiring 81, the second connection wiring 82 is made of the same material as the pixel electrode 30. In this way, when the second connection wiring 82 that connects the dummy gate lead-out line 14 and the common bus wiring 50 is formed in the same layer as the pixel electrode 30, the second contact hole 82a is similar to the first contact hole 81a. It is formed so as to penetrate the second insulating film 122, the third insulating film 123, and the fourth insulating film 124.

Thus, like the first contact hole 81a, the second contact hole 82a can be formed at the same time as the process of forming the contact hole for connecting the pixel electrode 30 and the source/drain electrode of the TFT 20. Further, like the first connection wiring 81, the second connection wiring 82 can be formed in a predetermined shape at the same time as the process of patterning the pixel electrode 30. That is, the first connection wiring 81 and the second connection wiring 82 can be formed in the same process.

Although two first contact holes 81 a are formed for one first connection wiring 81, one second contact hole 82 a is formed for one second connection wiring 82. .. Specifically, the common bus line 50 has an opening 50a, and the second contact hole 82a is formed in this opening 50a. The opening 50a of the common bus wiring 50 can be formed by the process of patterning the common bus wiring 50.

In addition, in the present embodiment, the second contact hole 82a is formed on one long side (the lower long side in FIG. 1) of the pair of long sides in the frame region 2b. That is, the second contact hole 82a is formed on the long side where the gate terminal portion 71 and the source terminal portion 72 are provided. Therefore, the second connection wiring 82 is formed on the long side where the gate terminal portion 71 and the source terminal portion 72 are provided.

As described above, the dummy gate lead-out line 14 has one end connected to the shield electrode 60 by the first connection wiring 81 and the other end connected to the common bus wiring 50 by the second connection wiring 82. There is. That is, the dummy gate lead lines 14 are both connected to the shield electrode 60 and the common bus line 50 to which the common potential is applied, and the common potential is applied from both ends. Note that the dummy gate lead-out line 14 may not be applied with the common potential from both ends, and may be applied with the common potential from only one of both ends. That is, at least one of the first connection wiring 81 and the second connection wiring 82 may be provided.

As shown in FIG. 1, the common bus line 50 and the shield electrode 60 are connected to each other. Specifically, the display panel 2 (TFT substrate 100) includes a common connection wiring 83 (third connection wiring) that connects the common bus wiring 50 and the shield electrode 60. That is, the common bus wiring 50 and the shield electrode 60 are connected via the common connection wiring 83. As shown in FIG. 7, the common connection wiring 83 connects the common bus wiring 50 and the shield electrode 60 via the contact hole 83a formed in the frame region 2b.

In the present embodiment, the common connection wiring 83 is formed in the same layer as the pixel electrode 30. That is, the common connection wiring 83 is formed in the same layer as the first connection wiring 81 and the second connection wiring 82. Therefore, the contact hole 83a is formed so as to penetrate the second insulating film 122, the third insulating film 123, and the fourth insulating film 124, similarly to the first contact hole 81a and the second contact hole 82a. Thereby, like the first contact hole 81a and the second contact hole 82a, the contact hole 83a is formed at the same time as the process of forming the contact hole for connecting the pixel electrode 30 and the source/drain electrode of the TFT 20. You can Further, like the first connection wiring 81 and the second connection wiring 82, the common connection wiring 83 can be formed in a predetermined shape at the same time as the process of patterning the pixel electrode 30. That is, the first connection wiring 81, the second connection wiring 82, and the common connection wiring 83 can be formed in the same process.

Next, the connection relationship of the wiring around the gate terminal portion 71 and the source terminal portion 72 will be described.

As shown in FIG. 8, the gate lead line 13 is formed in the same layer as the source signal line 12, and the gate signal line 11 is formed in a layer different from the source signal line 12. The gate relay wiring 16 is formed in the same layer as the gate signal line 11. Therefore, the gate relay wiring 16 is connected to each of the gate lead line 13 and the gate terminal electrode 71a through the contact holes 16a and 16b formed in the first insulating film 121. As a result, the gate relay wiring 16 and the source relay wiring 17 can cross each other.

The method of routing the gate relay wiring 16 is not limited to the method shown in FIG. For example, the gate relay wiring 16 may be routed through the contact hole to the metal layer in which the common electrode 40 or the pixel electrode 30 is formed and then returned to the original metal layer to be connected to the gate lead line 13. ..

Next, the CF substrate 200 will be described. As shown in FIGS. 4 to 8, the CF substrate 200 is a counter substrate facing the TFT substrate 100. In the present embodiment, the CF substrate 200 is a color filter substrate having a color filter.

Although not shown, the CF substrate 200 has a second transparent substrate made of a transparent base material such as a glass substrate or a transparent resin substrate, and a color filter layer and a light shielding layer formed on the second transparent substrate.

The color filter layer has a color filter corresponding to each pixel PX. Specifically, the color filter layer includes a red color filter corresponding to the red pixel PXR, a green color filter corresponding to the green pixel PXG, and a blue color filter corresponding to the blue pixel PXB. These color filters are formed in the region between the light shielding layers (that is, the opening of the light shielding layer).

The light shielding layer is a black layer and is made of, for example, carbon black. The light shielding layer is formed at each boundary between two pixels PX that are adjacent in the column direction. Specifically, the light shielding layer is formed in a line shape along the row direction so as to cover at least the gate signal line 11. The light shielding layer may be formed along the column direction or in a line shape so as to cover the gate lead lines 13 and the source signal lines 12. In this case, the light shielding layer is a black matrix formed in a grid pattern.

A pair of polarizing plates (not shown) are attached to the display panel 2 thus configured. For example, one of the pair of polarizing plates is formed on the outer surface of the TFT substrate 100, and the other of the pair of polarizing plates is formed on the outer surface of the CF substrate 200. The pair of polarizing plates are arranged so that the polarization directions thereof are orthogonal to each other. A retardation plate may be attached to the pair of polarizing plates.

The display panel 2 is arranged such that the TFT substrate 100 is located on the backlight BL side and the CF substrate 200 is located on the viewer side. That is, the display panel 2 is arranged so that the CF substrate 200 is located in front of the TFT substrate 100.

As described above, the display panel 2 and the TFT substrate 100 according to the present embodiment include the plurality of gate signal lines 11, the plurality of gate lead lines 13 and the plurality of dummy gate lead lines 14 intersecting the plurality of gate signal lines. And a common potential is applied to the plurality of dummy gate lead lines 14. In this embodiment, the common potential is applied to the plurality of dummy gate lead lines 14 by utilizing the shield electrode 60 and the common bus line 50 to which the common potential is applied. Specifically, the common potential is applied to the plurality of dummy gate lead lines 14 by connecting the plurality of dummy gate lead lines 14 to the shield electrode 60 and the common bus line 50.

Thereby, even if the plurality of dummy gate lead lines 14 are not brought close to the frame region 2b and connected to the gate terminal portion 71 or the source terminal portion 72, a common potential is applied as a predetermined potential to the plurality of dummy gate lead lines 14. be able to. Therefore, compared with the case where a plurality of dummy gate lead lines 14 are drawn near the frame region 2b, the degree of freedom in layout in the frame region 2b of various wirings such as the gate lead line 13, the dummy gate lead line 14, and the source signal line 12 is increased. Can be suppressed.

In particular, when the gate terminal portion 71 and the source terminal portion 72 are provided on the same side of the frame region 2b, various wirings such as the gate lead wire 13 and the source signal line 12 are concentrated on one side, Layout restrictions are increased. Moreover, when the gate driver 3a and the source driver 3b are directly mounted in the frame region 2b by the COG method as in the present embodiment, not only the degree of freedom in the layout of the gate driver 3a and the source driver 3b is lowered. The degree of freedom in wiring layout of various wirings such as the gate lead-out line 13 and the source signal line 12 is further reduced.

On the other hand, in the display panel 2 and the TFT substrate 100 according to the present embodiment, the common potential is applied to the plurality of dummy gate lead lines 14 by using the shield electrode 60 and the common bus line 50 to which the common potential is applied. There is. As a result, even if the gate terminal portion 71 and the source terminal portion 72 are provided on the same side of the frame area 2b or the gate driver 3a and the source driver 3b are directly mounted on the frame area 2b by the COG method, the gate extraction is performed. It is possible to effectively suppress a reduction in the degree of freedom of the wiring layout of various wirings such as the line 13 and the source signal line 12.

As described above, according to the present embodiment, although the plurality of gate signal lines 11, the plurality of gate lead lines 13 and the plurality of dummy gate lead lines 14 intersect each other, the wiring layout has a high degree of freedom. The TFT substrate 100 and the display panel 2 can be realized.

(Modification 1)
Next, a first modification of the above embodiment will be described with reference to FIG. FIG. 9 is a partial cross-sectional view of the display panel 2A according to Modification 1. FIG. 9 corresponds to the cross-sectional portion of FIG. 5 of the display panel 2 in the above embodiment. In this modification, the configuration other than the first connection wiring 81A is the same as that of the above-described embodiment.

In the display panel 2 and the TFT substrate 100 in the above-described embodiment, the first connection wiring 81 that connects the dummy gate lead-out line 14 and the shield electrode 60 was formed in the same layer as the pixel electrode 30, but FIG. As shown, in the display panel 2A and the TFT substrate 100A in the present modification, the first connection wiring 81A that connects the dummy gate lead-out line 14 and the shield electrode 60 is formed in the same layer as the common electrode 40. Therefore, the first connection wiring 81A is made of the same material as the common electrode 40.

In this way, when the first connection wiring 81A connecting the dummy gate lead-out line 14 and the shield electrode 60 is formed in the same layer as the common electrode 40, the first contact hole 81a is formed in the second insulating film 122 and the third insulating film. It is formed so as to penetrate the film 123.

As described above, also in the display panel 2A and the TFT substrate 100A according to the present modified example, as in the display panel 2 and the TFT substrate 100 according to the above-described embodiments, a plurality of shield electrodes 60 and a common bus line 50 to which a common potential is applied are used. A common potential is applied to the dummy gate lead wire 14. As a result, it is possible to suppress a reduction in the degree of freedom in the wiring layout of various wirings such as the gate lead-out line 13 and the source signal line 12, and to realize the display panel 2A and the TFT substrate 100A having a high degree of freedom in the wiring layout. be able to.

(Modification 2)
Next, a second modified example of the above-described embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a plan view showing a schematic configuration of a display panel 2B according to Modification 2. FIG. 11 is a partial cross-sectional view taken along the line XI-XI of FIG. FIG. 11 corresponds to the cross-sectional portion of FIG. 6 of the display panel 2 in the above embodiment. In this modification, the configuration other than the first connection wiring 81B is the same as that of the above-described embodiment.

In the display panel 2 and the TFT substrate 100 in the above-described embodiment, the first connection wiring 81 connects the dummy gate lead-out line 14 and the shield electrode 60. However, as shown in FIGS. In the display panel 2B and the TFT substrate 100B in the example, the first connection wiring 81B connects the dummy gate lead-out line 14 and the common bus wiring 50.

That is, in this modification, both ends of each dummy gate lead-out line 14 are connected to the common bus line 50. Specifically, one end of each dummy gate lead wire 14 is connected to the common bus wiring 50 by the first connection wiring 81A through the first contact hole 81a, and the other end thereof is Similar to the display panel 2 and the TFT substrate 100 in the above embodiment, the common bus wiring 50 is connected by the second connection wiring 82 through the second contact hole 82a. The first connection wiring 81B and the second connection wiring 82 are both connected to the second electrode 52 by contacting the upper surface of the second electrode 52 in the upper layer of the common bus wiring 50.

Further, in the present modification, the first connection wiring 81B is formed in the same layer as the pixel electrode 30. That is, the first connection wiring 81B is formed in the same layer as the second connection wiring 82. Therefore, the first connection wiring 81B is made of the same material as the pixel electrode 30, like the second connection wiring 82. As described above, the process for patterning the pixel electrode 30 is performed by forming the first connection wiring 81B and the second connection wiring 82 that connect the dummy gate lead-out line 14 and the common bus wiring 50 in the same layer as the pixel electrode 30. At the same time, the first connection wiring 81B and the second connection wiring 82 can be formed in a predetermined shape. That is, the first connection wiring 81B, the second connection wiring 82, and the pixel electrode 30 can be formed in the same process.

As described above, also in the display panel 2B and the TFT substrate 100B in the present modified example, as in the display panel 2 and the TFT substrate 100 in the above-described embodiment, the plurality of dummy gate lead lines are utilized by using the common bus wiring 50 to which the common potential is applied. A common potential is applied to 14. As a result, it is possible to suppress a reduction in the degree of freedom of the wiring layout of various wirings such as the gate lead line 13 and the source signal line 12, and to realize the display panel 2B and the TFT substrate 100B having a high degree of freedom of the wiring layout. be able to.

In this modification, the common potential is applied to the plurality of dummy gate lead lines 14 without using the shield electrode 60. Therefore, even if the shield electrode 60 is not formed on the display panel 2B and the TFT substrate 100B, the common potential can be applied to the plurality of dummy gate lead lines 14.

(Modification 3)
Next, a modified example 3 of the above embodiment will be described with reference to FIG. FIG. 12 is a partial cross-sectional view of a display panel 2C according to Modification 3. FIG. 12 corresponds to the sectional portion of FIG. 6 of the display panel 2 in the above embodiment. In this modification, the configuration other than the peripheral structure of the second contact hole 82a is the same as that of the above-described embodiment.

In the display panel 2 and the TFT substrate 100 in the above-described embodiment, the other end of the dummy gate lead wire 14 is connected to the common bus wire 50 by the second connection wire 82. That is, a member formed in a layer different from the common bus line 50 was used as the second connection line 82, and the dummy gate lead-out line 14 and the common bus line 50 were connected via the second connection line 82.

On the other hand, in the display panel 2C and the TFT substrate 100C in the present modification, as shown in FIG. 12, the dummy gate lead-out line 14 is formed without using a member formed in a layer different from the common bus wiring 50. It is connected to the common bus wiring 50. That is, part of the common bus wiring 50 is used as the second connection wiring, and the dummy gate lead-out line 14 and the common bus wiring 50 are directly connected. Specifically, the common bus line 50 is connected to the dummy gate lead line 14 by the first electrode 51 in the lower layer of the common bus line 50 contacting the upper surface of the dummy gate lead line 14.

In this case, on one long side (the long side where the gate terminal portion 71 and the source terminal portion 72 are provided) of the pair of long sides in the frame area 2b, the plurality of dummy gate lead lines 14 are arranged in the frame area 2b. It is directly connected to the common bus line 50 through the formed second contact hole 82a.

As described above, also in the display panel 2C and the TFT substrate 100C in the present modification, as in the display panel 2 and the TFT substrate 100 in the above-described embodiment, the plurality of dummy gate lead lines are utilized by using the common bus wiring 50 to which the common potential is applied. A common potential is applied to 14. As a result, it is possible to suppress a reduction in the degree of freedom in the wiring layout of various wirings such as the gate lead-out line 13 and the source signal line 12, and to realize the display panel 2C and the TFT substrate 100C having a high degree of freedom in the wiring layout. be able to.

Note that this modification may be applied to the first contact hole 81a in Modification 2 described above. Specifically, in the other long side of the pair of long sides in the frame region 2b (the long side opposite to the long side where the gate terminal portion 71 and the source terminal portion 72 are provided), the first connection wiring The dummy gate lead-out line 14 and the common bus line 50 may be directly connected without using 81B.

(Modification 4)
Next, a modified example 4 of the above embodiment will be described with reference to FIG. FIG. 13 is a plan view showing a schematic configuration of a display panel 2D according to Modification 4. In this modification, the configuration other than the common relay wiring 18 is the same as that of the above-described embodiment.

In the display panel 2 and the TFT substrate 100 in the above-described embodiment, the common terminal electrode 72b included in the source terminal portion 72 is connected to the shield electrode 60 via the common relay wiring 18, but as shown in FIG. In the display panel 2D and the TFT substrate 100D in this modification, the common terminal electrode 72b is connected to the common bus wiring 50 via the common relay wiring 18D. That is, in this modification, the common relay wiring 18D connects the common terminal electrode 72b and the common bus wiring 50.

In this case, when the common potential is input from the power supply circuit 7 to the common terminal electrode 72b, the common potential is applied to the common bus wiring 50 via the common relay wiring 18D. As a result, the common potential is applied to the dummy gate lead-out line 14 and the common line 15. In this modification, a common potential is applied to the shield electrode 60 from the common bus line 50 via the common connection line 83. That is, the common potential is applied to the shield electrode 60 via the common bus line 50.

As described above, also in the display panel 2D and the TFT substrate 100D in the present modified example, as in the display panel 2 and the TFT substrate 100 in the above-described embodiment, the plurality of dummy gate lead lines are utilized by using the common bus wiring 50 to which the common potential is applied. A common potential is applied to 14. As a result, it is possible to suppress a reduction in the degree of freedom in the wiring layout of various wirings such as the gate lead-out line 13 and the source signal line 12, and realize the display panel 2D and the TFT substrate 100D having a high degree of freedom in the wiring layout. be able to.

(Modification 5)
Next, a fifth modified example of the above-described embodiment will be described with reference to FIG. FIG. 14 is a partial cross-sectional view of the display panel 2E according to Modification 5. FIG. 14 corresponds to the cross-sectional portion of FIG. 5 of the display panel 2 in the above embodiment.

In the display panel 2 and the TFT substrate 100 in the above-described embodiment, the pixel electrode 30 is located above the common electrode 40. However, in the display panel 2E and the TFT substrate 100E in this modification, the pixel electrode 30E is the common electrode. It is located below 40. That is, the common electrode 40 is located above the pixel electrode 30E. Specifically, the common electrode 40 is formed on the third insulating film 123 as in the above-described embodiment, but the pixel electrode 30E is not on the fourth insulating film 124 but on the second insulating film 124. It is formed on 122.

In this modification, the first connection wiring 81E that connects the dummy gate lead-out line 14 and the shield electrode 60 is formed in the same layer as the common electrode 40. Therefore, the first connection wiring 81E is made of the same material as the common electrode 40.

In this way, when the first connection wiring 81E that connects the dummy gate lead-out line 14 and the shield electrode 60 is formed in the same layer as the common electrode 40, the first contact hole 81a is formed in the second insulating film 122 and the third insulating film. It is formed so as to penetrate the film 123.

In addition, in the present modification, the other configurations are the same as those of the display panel 2E and the TFT substrate 100E in the above-described embodiment.

As described above, also in the display panel 2E and the TFT substrate 100E according to the present modified example, as in the display panel 2 and the TFT substrate 100 according to the above-described embodiment, a plurality of shield electrodes 60 and a common bus line 50 to which a common potential is applied are used. A common potential is applied to the dummy gate lead wire 14. As a result, it is possible to suppress a reduction in the degree of freedom in the wiring layout of various wirings such as the gate lead-out line 13 and the source signal line 12, and to realize the display panel 2A and the TFT substrate 100A having a high degree of freedom in the wiring layout. be able to.

Further, as shown in FIG. 15, in the present modification, the first connection wiring 81E may be formed in the same layer as the pixel electrode 30E. Accordingly, the first connection wiring 81E can be formed in a predetermined shape at the same time as the process of patterning the pixel electrode 30E. That is, the first connection wiring 81E and the pixel electrode 30E can be formed in the same process.

(Other modifications)
Although the TFT substrate, the display panel, and the like according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to the above embodiments.

For example, in the above embodiment, the common bus line 50 has a two-layer structure of the first electrode 51 and the second electrode 52, but the present invention is not limited to this. Specifically, the common bus line 50 may have a single-layer structure including only one of the first electrode 51 and the second electrode 52. In this case, when a part of the common bus wiring 50 is used as the first connection wiring or the second connection wiring, the first connection wiring or the second connection wiring is composed of only one of the first electrode 51 and the second electrode 52. May be.

In addition, in the above-described embodiment, the pixel area 2a is divided into three columns of areas including the first area A1, the second area A2, and the third area A3, but the invention is not limited to this. Specifically, the pixel region 2a may be divided into regions of four columns or more.

Further, in the above-described embodiment, the case where the gate signal line 11, the gate lead line 13, and the source signal line 12 are orthogonal (that is, intersect at 90°) in a plan view has been described, but the present invention is not limited to this. For example, the gate signal line 11, the gate lead line 13, and the source signal line 12 may intersect at an angle other than 90°.

Further, in the above embodiment, the gate driver 3a and the source driver 3b are mounted on the display panel 2 (TFT substrate 100) by the COG method, but the invention is not limited to this. For example, the gate driver 3a and the source driver 3b may be mounted on the display panel 2 (TFT substrate 100) by the COF method. In this case, when the source driver 3b is mounted by the COF method, the flexible wiring board 4 on which the source driver 3b is mounted may be connected to the TFT substrate 100.

Further, in the above-described embodiment, the common terminal electrode 72b to which the common potential from the power supply circuit 7 is input is included in the source terminal portion 72, but it is not limited to this. For example, the common terminal electrode 72b may be included in the gate terminal portion 71. Alternatively, the common terminal electrode 72b may not be included in either the source terminal portion 72 or the gate terminal portion 71, and may be independently provided in the frame region 2b of the TFT substrate 100.

Further, in the above embodiment, the liquid crystal display panel is used as the display panel 2, but the present invention is not limited to this. For example, the display panel 2 may be another display device such as an organic EL panel or an inorganic EL panel. That is, the TFT substrate 100 in the above embodiment can be applied to an organic EL panel, an inorganic EL panel, or the like.

In addition, modes obtained by making various modifications to those skilled in the art by those skilled in the art, and modes realized by arbitrarily combining the constituent elements and functions in the embodiments without departing from the spirit of the present disclosure Also included in the present disclosure.

1 image display device 2, 2A, 2B, 2C, 2D, 2E display panel 2a pixel region 2b frame region 3a gate driver 3b source driver 4 flexible wiring board 5 circuit board 6 timing controller 7 power supply circuit 8 image processing circuit 11 gate signal line 11a Gate contact hole 12 Source signal line 13 Gate lead line 14 Dummy gate lead line 15 Common line 16 Gate relay wiring 16a, 16b, 83a Contact hole 17 Source relay wiring 18, 18D Common relay wiring 20 TFT
30, 30E Pixel electrode 40 Common electrode 40a Opening 50 Common bus wiring 50a Opening 60 Shield electrode 71 Gate terminal 71a Gate terminal electrode 72 Source terminal 72a Source terminal 72b Common terminal 81, 81A, 81E First connection 81a 1 Contact Hole 82 Second Connection Wiring 82a Second Contact Hole 83 Common Connection Wiring 100, 100A, 100B, 100C, 100D, 100E TFT Substrate 110 First Transparent Substrate 121 First Insulating Film 122 Second Insulating Film 123 Third Insulating Film 124 Fourth Insulating Film 125 Fifth Insulating Film 200 CF Substrate 300 Liquid Crystal Layer 400 Sealing Member

Claims (23)

A thin film transistor substrate having a pixel region composed of a plurality of pixels and a frame region surrounding the pixel region,
A thin film transistor and a pixel electrode provided in each of the plurality of pixels;
A plurality of gate signal lines extending in the first direction in the pixel region and supplying a gate signal to the thin film transistors in each of the plurality of pixels;
A plurality of gate leader lines and a plurality of dummy gate leader lines extending in a second direction different from the first direction in the pixel region;
A plurality of common lines extending in at least one of the first direction and the second direction in the pixel region and to which a common potential is applied;
A common electrode provided facing the pixel electrode and electrically connected to the plurality of common lines,
The plurality of gate lead lines are connected to the gate signal line at at least one of a plurality of intersections of the plurality of gate signal lines and the plurality of gate lead lines,
The common potential is applied to the plurality of dummy gate lead lines,
Thin film transistor substrate. A plurality of source signal lines extending in the second direction in the pixel region and supplying a data signal to the thin film transistors in each of the plurality of pixels;
A gate terminal portion including a plurality of gate terminal electrodes connected to the plurality of gate lead lines,
A source terminal portion including a plurality of source terminal electrodes connected to the plurality of source signal lines,
The gate terminal portion and the source terminal portion are provided on one long side of a pair of long sides in the frame region of the thin film transistor substrate,
The thin film transistor substrate according to claim 1. further,
A shield electrode formed in the frame region and applied with the common potential;
A first connection wiring that connects each of the plurality of dummy gate lead lines and the shield electrode via a first contact hole formed in the frame region;
The thin film transistor substrate according to claim 2. The first connection wiring is formed in the same layer as the pixel electrode,
The thin film transistor substrate according to claim 3. The first connection wiring is formed in the same layer as the common electrode,
The thin film transistor substrate according to claim 3. The shield electrode is formed in the same layer as the source/drain electrode of the thin film transistor,
The thin film transistor substrate according to any one of claims 3 to 5. The shield electrode is formed in the same layer as the dummy gate lead line,
The thin film transistor substrate according to any one of claims 3 to 6. The shield electrode is formed in a mesh shape,
The thin film transistor substrate according to any one of claims 3 to 7. With respect to one of the first connection wirings, the first contact hole is formed at least at two positions on the dummy gate lead-out line and on the shield electrode.
The thin film transistor substrate according to any one of claims 3 to 8. The first contact hole is formed on the other long side of the pair of long sides,
The thin film transistor substrate according to any one of claims 3 to 9. A common bus line formed in the frame region and applied with the common potential;
A second connection wiring that connects each of the plurality of dummy gate lead-out lines to the common bus wiring through a second contact hole formed in the frame region,
The plurality of common wirings are connected to the common bus wiring,
The thin film transistor substrate according to claim 2. The second connection wiring is formed in the same layer as the pixel electrode,
The thin film transistor substrate according to claim 11. The common bus line has a first electrode formed in the same layer as the common electrode, and a second electrode laminated on the first electrode and formed in the same layer as the common line.
The thin film transistor substrate according to claim 11. The second contact hole is formed on the one long side,
The thin film transistor substrate according to any one of claims 11 to 13. The second contact hole is formed on the other long side of the pair of long sides,
The thin film transistor substrate according to any one of claims 11 to 13. The pixel electrode is located in a layer above the common electrode,
The common bus wiring has an opening,
The second contact hole is formed in the opening,
The thin film transistor substrate according to claim 11. A common bus line formed in the frame region and connected to the plurality of common lines;
A shield electrode formed in the frame region and to which the common potential is applied,
The common bus wiring is electrically connected to the shield electrode,
The plurality of dummy gate lead lines are also connected to the common bus line via a contact hole formed in the frame region,
The thin film transistor substrate according to claim 2. The contact hole is formed on the one long side,
The thin film transistor substrate according to claim 17. The contact hole is formed on the other long side of the pair of long sides,
The thin film transistor substrate according to claim 18. A common connection wiring for connecting the common bus wiring and the shield electrode through a contact hole formed in the frame region,
The common connection wiring is formed in the same layer as the pixel electrode,
The thin film transistor substrate according to claim 11. The gate terminal portion or the source terminal portion further includes a common terminal electrode for applying the common potential to the common line,
The thin film transistor substrate according to claim 1. The common electrode is located in a layer above the pixel electrode,
The thin film transistor substrate according to any one of claims 1 to 15 and 17 to 19. A thin film transistor substrate according to any one of claims 1 to 22,
A counter substrate facing the thin film transistor substrate,
Display panel.

Images