JP2020088481A - Solid-state imaging element and imaging device - Google Patents

Abstract

To reduce power consumption when an image is captured in a solid-state imaging element that detects the presence or absence of an address event.SOLUTION: A solid-state imaging element includes a plurality of pixels and an analog-digital conversion unit. In the solid-state imaging element, each of the plurality of pixels generates an analog signal by photoelectric conversion. Further, in the solid-state imaging element, the analog-digital conversion unit converts an analog signal of a pixel in which the amount of change in the amount of incident light is out of a predetermined range, among the plurality of pixels, into a digital signal.SELECTED DRAWING: Figure 13

Description

The present technology relates to a solid-state imaging device and an imaging device. More specifically, the present invention relates to a solid-state imaging device that compares the amount of incident light with a threshold value, and an imaging device.

2. Description of the Related Art Conventionally, a synchronous solid-state image pickup element that picks up image data (frame) in synchronization with a synchronizing signal such as a vertical synchronizing signal has been used in an image pickup apparatus. In this general synchronous type solid-state image sensor, image data can be acquired only at every cycle (for example, 1/60 seconds) of a synchronous signal, so that higher-speed processing can be performed in fields such as traffic and robots. It will be difficult to respond when requested. Therefore, an asynchronous solid-state image sensor that detects the presence or absence of an address event for each pixel has been proposed (for example, refer to Patent Document 1). Here, the address event means that the light amount of a pixel fluctuates at a certain pixel address and the fluctuation amount exceeds a threshold value. The address event is composed of an on-event indicating that the light amount of the pixel has changed and the amount of change exceeds a predetermined upper limit, and an off-event indicating that the amount of change has fallen below a predetermined lower limit. In the asynchronous solid-state image sensor, 2-bit data including a 1-bit on-event detection result and a 1-bit off-event detection result is generated for each pixel. A solid-state image sensor that detects the presence or absence of an address event for each pixel in this way is called a DVS (Dynamic Vision Sensor).

Japanese Patent Publication No. 2017-535999

The asynchronous solid-state image sensor (DVS) described above generates data at a much higher speed than the synchronous solid-state image sensor. However, in image recognition or the like, in addition to detection of the presence or absence of an address event, high-quality image data of 3 bits or more may be required for each pixel, and data having 2 bits for each pixel is generated. DVS cannot meet that requirement. In order to capture a higher quality image while detecting the presence or absence of an address event, a circuit similar to the synchronous solid-state image sensor may be added to the DVS, but the power consumption increases accordingly. , Not preferable.

The present technology is created in view of such a situation, and an object thereof is to further capture an image in a solid-state image sensor that detects the presence or absence of an address event.

The present technology has been made to solve the above-described problems, and a first aspect thereof is that a plurality of pixels each generate an analog signal by photoelectric conversion, and an incident light amount of the plurality of pixels A solid-state image sensor, comprising: an analog-digital conversion unit that converts the analog signal of a pixel having a change amount outside a predetermined range into a digital signal. This brings about the effect that the analog signal of the pixel in which the address event has occurred is converted into a digital signal.

Further, in the first aspect, the analog-to-digital conversion unit includes a selection unit that selects the analog signal of a pixel whose change amount is out of the predetermined range among the analog signals of the plurality of pixels, An analog-digital converter for converting the selected analog signal into the digital signal may be provided. This brings about the effect that the analog signal selected by the selection unit is converted into a digital signal.

Further, in the first aspect, the plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction, and the analog-digital conversion unit includes a fixed number of analog-digital converters for each column, The analog-digital converter may convert the analog signal of the pixel into the digital signal when the change amount of the pixel belonging to the corresponding column of the plurality of pixels is out of the predetermined range. .. This brings about the effect that the analog signal is converted into a digital signal by the analog-digital converter arranged for each column.

Further, in the first aspect, the plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction, and the analog-digital conversion unit is connected to a part of the predetermined number of columns. May be provided, and a second analog-digital conversion unit connected to the rest of the predetermined number of columns. This brings about an effect that an analog signal is converted into a digital signal in parallel by the first and second analog-to-digital converters.

Further, in the first aspect, each of the first and second analog-to-digital conversion units converts the analog signal of a column in which the change amount is out of the predetermined range among the analog signals of the corresponding column. A selection unit for selecting and an analog-digital converter for converting the selected analog signal into the digital signal may be provided. This brings about the effect that the selected analog signal is converted into a digital signal in each of the first and second analog-to-digital converters.

Further, in the first aspect, each of the first and second analog-to-digital converters includes a certain number of analog-to-digital converters for each corresponding column, and the analog-to-digital converters include the plurality of analog-to-digital converters. When the change amount of the pixel belonging to the corresponding column of the pixels is out of the predetermined range, the analog signal of the pixel may be converted into the digital signal. Thereby, in each of the first and second analog-to-digital converters, an analog-to-digital converter arranged for each column converts an analog signal into a digital signal.

In addition, in the first aspect, each of the plurality of pixels detects the pixel signal generation unit that generates the analog signal and whether or not the absolute value of the change amount exceeds a predetermined threshold value. The analog-to-digital conversion unit may convert the analog signal into the digital signal according to the enable signal, the detection unit generating a predetermined enable signal based on the result. This brings about an effect that an analog signal is converted into a digital signal in accordance with the enable signal from the pixel.

The first aspect further includes a row arbiter that arbitrates a first request from each of a predetermined number of rows arranged in a direction perpendicular to the predetermined direction, and the plurality of pixels are equal to the predetermined number. And each of the plurality of pixels may transmit the first request when the change amount is outside the predetermined range. This has the effect of arbitrating each request for a row.

The first aspect further includes a column arbiter that arbitrates a second request from each of a predetermined number of columns arranged in the predetermined direction, and each of the plurality of pixels includes a row arbiter. The second request may be transmitted based on the arbitration result. This has the effect that each request in the queue is arbitrated.

Further, in the first aspect, the column arbiter generates a predetermined enable signal based on the second request, and the analog-digital conversion unit converts the analog signal into the digital signal according to the enable signal. You may. This brings about the effect that the analog signal is converted into a digital signal in accordance with the enable signal from the column arbiter.

In addition, a second aspect of the present technology is to digitally convert a plurality of pixels, each of which generates an analog signal by photoelectric conversion, and the analog signal of a pixel in which the absolute value of the incident light amount is out of a predetermined range. The imaging device includes an analog-digital conversion unit that converts a signal, and a signal processing unit that processes the digital signal. As a result, the analog signal of the pixel in which the address event has occurred is converted into a digital signal, and the digital signal is processed.

It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. It is a figure showing an example of a layered structure of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a pixel in a 1st embodiment of this art. It is a top view showing an example of 1 composition of a pixel array part in a 1st embodiment of this art. It is a block diagram showing an example of composition of an address event primary detecting element in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a current voltage conversion part in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a subtractor and a quantizer in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a transfer part in a 1st embodiment of this art. It is a block diagram showing an example of composition of a column ADC (Analog to Digital Converter) in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of an AD conversion part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a control circuit in a 1st embodiment of this art. It is a figure for explaining read-out control in a 1st embodiment of this art. 5 is a timing chart showing an example of the operation of the solid-state image sensor according to the first embodiment of the present technology. It is a flow chart which shows an example of operation of the solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of composition of a pixel array part and column ADC in a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of an AD conversion part in a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 3rd embodiment of this art. It is a block diagram showing an example of composition of a pixel array part and lower side column ADC in a 3rd embodiment of this art. It is a block diagram showing an example of composition of a pixel array part and lower side column ADC in a 4th embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 5th embodiment of this art. It is a block diagram showing an example of composition of a pixel and an X arbiter in a modification of a 5th embodiment of this art. It is a block diagram showing a schematic example of composition of a vehicle control system. It is explanatory drawing which shows an example of the installation position of an imaging part.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (example of reading a pixel signal of a pixel in which an address event has occurred)
2. Second embodiment (an example of reading pixel signals of two rows in which an address event has occurred in parallel)
3. Third embodiment (example in which pixel signals of pixels in which an address event has occurred are read in parallel by the upper and lower column ADCs)
4. Fourth Embodiment (an example in which ADCs are arranged in every two columns in the upper and lower column ADCs and the pixel signal of a pixel in which an address event occurs is read out)
5. Fifth embodiment (an example in which an X arbiter is arranged and a pixel signal of a pixel in which an address event occurs is read)
6. Application example to mobile

<1. First Embodiment>
[Example of configuration of imaging device]
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The image pickup apparatus 100 includes an image pickup lens 110, a solid-state image pickup device 200, a recording unit 120, and a control unit 130. As the imaging device 100, a camera mounted on an industrial robot, a vehicle-mounted camera, or the like is assumed.

The imaging lens 110 collects incident light and guides it to the solid-state imaging device 200. The solid-state image sensor 200 photoelectrically converts incident light and images image data while detecting the presence or absence of an address event. The solid-state imaging device 200 executes predetermined signal processing such as image recognition processing on the imaged image data, and the data indicating the processing result is stored in the recording unit 120 via the signal line 209. Output.

The recording unit 120 records the data from the solid-state image sensor 200. The control unit 130 controls the solid-state image sensor 200 to capture image data.

[Configuration example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a detection chip 202 and a light receiving chip 201 stacked on the detection chip 202. These chips are electrically connected via a connection part such as a via. In addition to the vias, Cu-Cu bonding or bumps may be used for connection.

FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a drive circuit 211, a signal processing unit 212, a Y arbiter 213, a column ADC 220, and a pixel array unit 300.

In the pixel array unit 300, a plurality of pixels 310 are arranged in a two-dimensional lattice shape. Hereinafter, a set of pixels arranged in the horizontal direction is referred to as a “row”, and a set of pixels arranged in the direction perpendicular to the row is referred to as a “column”.

The pixel 310 generates an analog signal as a pixel signal by photoelectric conversion. Further, the pixel 310 detects the presence/absence of an address event depending on whether or not the amount of change in the amount of incident light exceeds a predetermined threshold value. Then, when an address event occurs, the pixel 310 outputs a request to the Y arbiter 213. Then, upon receiving the response to the request, the pixel 310 transmits a detection signal indicating the detection result of the address event to the drive circuit 211 and the column ADC 220.

The drive circuit 211 drives each of the pixels 310 to output a pixel signal to the column ADC 220.

The Y arbiter 213 arbitrates requests from a plurality of lines and returns a response based on the arbitration result. The Y arbiter 213 is an example of the row arbiter described in the claims.

The column ADC 220 converts, for each column, an analog pixel signal from the column into a digital signal. The column ADC 220 supplies the digital signal to the signal processing unit 212.

The signal processing unit 212 performs predetermined signal processing such as CDS (Correlated Double Sampling) processing and image recognition processing on the digital signal from the column ADC 220 and the detection signal from the pixel 310. The signal processing unit 212 supplies data indicating the processing result to the recording unit 120 via the signal line 209.

[Example of pixel configuration]
FIG. 4 is a block diagram showing a configuration example of the pixel 310 according to the first embodiment of the present technology. The pixel 310 includes a pixel signal generator 320, a light receiver 330, and an address event detector 400.

The light receiving section 330 photoelectrically converts incident light to generate a photocurrent. The light receiving unit 330 includes a transfer transistor 331, an OFG (OverFlow Gate) transistor 332, and a photoelectric conversion element 333. As the transfer transistor 331 and the OFG transistor 332, for example, N-type MOS (Metal-Oxide-Semiconductor) transistors are used.

The pixel signal generation unit 320 generates an analog signal having a voltage corresponding to the photocurrent as the pixel signal Vsig. The pixel signal generation unit 320 includes a reset transistor 321, an amplification transistor 322, a selection transistor 323, and a floating diffusion layer 324. For example, N-type MOS transistors are used as the reset transistor 321, the amplification transistor 322, and the selection transistor 323.

Further, each of the photoelectric conversion elements 333 is arranged on the light receiving chip 201. All the elements other than the photoelectric conversion element 333 are arranged on the detection chip 202. The elements arranged on the light receiving chip 201 and the detection chip 202 are not limited to this configuration. For example, the transfer transistor 331, the OFG transistor 332, or a part of the address event detection unit 400 may be further arranged in the light receiving chip 201.

The photoelectric conversion element 333 photoelectrically converts incident light to generate electric charges. The transfer transistor 331 transfers electric charge from the photoelectric conversion element 333 to the floating diffusion layer 324 according to the transfer signal TRG from the drive circuit 211. The OFG transistor 332 causes the photocurrent generated by the photoelectric conversion element 333 in accordance with the control signal OFG from the drive circuit 211 to flow to the address event detection unit 400.

The floating diffusion layer 324 accumulates electric charge and generates a voltage according to the amount of the electric charge. The reset transistor 321 initializes the charge amount of the floating diffusion layer 324 according to the reset signal RST from the drive circuit 211. The amplification transistor 322 amplifies the voltage of the floating diffusion layer 324. The selection transistor 323 outputs a signal of the amplified voltage as a pixel signal Vsig to the column ADC 220 via the vertical signal line 308 in accordance with the selection signal SEL from the drive circuit 211.

The address event detection unit 400 detects the presence or absence of an address event based on whether or not the amount of change in the photocurrent of the light receiving unit 330 exceeds a predetermined threshold value. This address event is composed of, for example, an on event indicating that the amount of change in photocurrent according to the amount of incident light exceeds the upper limit threshold value, and an off event indicating that the amount of change is below the lower limit threshold value. In other words, the address event is detected when the amount of change in the amount of incident light is outside the predetermined range from the lower limit to the upper limit. Further, the address event detection signal includes, for example, 1 bit indicating the detection result of the on event and 1 bit indicating the detection result of the off event. The address event detection unit 400 can also detect only an on event.

When the address event occurs, the address event detection unit 400 sends a request for sending the detection signal to the Y arbiter 213. Then, when the response to the request is received from the Y arbiter 213, the address event detection unit 400 transmits the detection signals DET+ and DET− to the drive circuit 211 and the column ADC 220. Here, the detection signal DET+ is a signal indicating the detection result of the presence or absence of an on event, and is transmitted to the column ADC 220 via the detection signal line 306, for example. The detection signal DET- is a signal indicating the detection result of the presence or absence of an off event, and is transmitted to the column ADC 220 via the detection signal line 307, for example.

Further, in synchronization with the selection signal SEL, the address event detection unit 400 sets the column enable signal ColEN to enable and transmits the signal to the column ADC 220 via the enable signal line 309. Here, the column enable signal ColEN is a signal for validating or invalidating AD (Analog to Digital) conversion for the pixel signal of the corresponding column. The address event detection unit 400 is an example of the detection unit described in the claims.

When the address event is detected in a certain row, the driving circuit 211 drives that row by the selection signal SEL or the like. Each of the pixels 310 in the driven row generates a pixel signal Vsig and sends it to the column ADC 220. In addition, the pixel 310 that has detected the address event in the driven row transmits the column enable signal ColEN set to enable to the column ADC 220. On the other hand, the column enable signal ColEN of the pixel 310 which has not detected the address event is set to be disabled.

FIG. 5 is a plan view showing a configuration example of the pixel array section 300 according to the first embodiment of the present technology. As illustrated in the drawing, in the pixel array unit 300, four detection signal lines 306 and 307, a vertical signal line 308, and an enable signal line 309 are wired for each column along the column direction. Each of the pixels 310 is connected to the detection signal lines 306 and 307 of the corresponding column, the vertical signal line 308, and the enable signal line 309.

[Configuration example of address event detector]
FIG. 6 is a block diagram showing a configuration example of the address event detection unit 400 according to the first embodiment of the present technology. The address event detection unit 400 includes a current/voltage conversion unit 410, a buffer 420, a subtractor 430, a quantizer 440, and a transfer unit 450.

The current-voltage conversion unit 410 converts the photocurrent from the light receiving unit 330 into its logarithmic voltage signal. The current-voltage converter 410 supplies the voltage signal to the buffer 420.

The buffer 420 outputs the voltage signal from the current-voltage converter 410 to the subtractor 430. With this buffer 420, the driving force for driving the subsequent stage can be improved. Further, the buffer 420 can ensure the isolation of noise associated with the switching operation in the subsequent stage.

The subtractor 430 lowers the level of the voltage signal from the buffer 420 according to the row drive signal from the drive circuit 211. The subtractor 430 supplies the reduced voltage signal to the quantizer 440.

The quantizer 440 quantizes the voltage signal from the subtractor 430 into a digital signal and outputs the digital signal to the transfer unit 450 as a detection signal.

The transfer unit 450 transfers the detection signal from the quantizer 440 to the signal processing unit 212 and the like. The transfer unit 450 transmits a request for transmitting a detection signal to the Y arbiter 213 when an address event is detected. Then, when the transfer unit 450 receives a response to the request from the Y arbiter 213, the transfer unit 450 supplies the detection signals DET+ and DET− to the drive circuit 211 and the column ADC 220. Further, when the selection signal SEL is transmitted, the transfer unit 450 transmits the column enable signal ColEN set to enable to the column ADC 220.

[Configuration Example of Current-Voltage Converter]
FIG. 7 is a circuit diagram showing a configuration example of the current-voltage conversion unit 410 according to the first embodiment of the present technology. The current-voltage conversion unit 410 includes N-type transistors 411 and 413 and a P-type transistor 412. For example, MOS transistors are used as these transistors.

The source of the N-type transistor 411 is connected to the light receiving section 330, and the drain is connected to the power supply terminal. The P-type transistor 412 and the N-type transistor 413 are connected in series between the power supply terminal and the ground terminal. The connection point between the P-type transistor 412 and the N-type transistor 413 is connected to the gate of the N-type transistor 411 and the input terminal of the buffer 420. Further, a predetermined bias voltage Vbias is applied to the gate of the P-type transistor 412.

The drains of the N-type transistors 411 and 413 are connected to the power supply side, and such a circuit is called a source follower. The two source followers connected in a loop form convert the photocurrent from the light receiving section 330 into a logarithmic voltage signal. Further, the P-type transistor 412 supplies a constant current to the N-type transistor 413.

[Example of configuration of subtractor and quantizer]
FIG. 8 is a circuit diagram showing a configuration example of the subtractor 430 and the quantizer 440 according to the first embodiment of the present technology. The subtractor 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. The quantizer 440 also includes comparators 441 and 442.

One end of the capacitor 431 is connected to the output terminal of the buffer 420, and the other end is connected to the input terminal of the inverter 432. The capacitor 433 is connected in parallel with the inverter 432. The switch 434 opens and closes a path connecting both ends of the capacitor 433 in accordance with the auto-zero signal AZ from the drive circuit 211.

The inverter 432 inverts the voltage signal input via the capacitor 431. The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441.

When the switch 434 is turned on, the voltage signal V _init is input to the buffer 420 side of the capacitor 431, and the opposite side becomes a virtual ground terminal. The potential of this virtual ground terminal is set to zero for convenience. At this time, the potential Q _init accumulated in the capacitor 431 is expressed by the following equation, where C1 is the capacitance of the capacitor 431. On the other hand, since both ends of the capacitor 433 are short-circuited, the accumulated charge becomes zero.
Q _init =C1×V _init Equation 1

Next, considering the case where the switch 434 is turned off and the voltage of the capacitor 420 on the buffer 420 side changes to V _after , the charge Q _after accumulated in the capacitor 431 is expressed by the following equation. ..
Q _after =C1×V _after ...Equation 2

On the other hand, the electric charge Q2 accumulated in the capacitor 433 is represented by the following equation when the output voltage is V _out .
Q2=−C2×V _out ...Equation 3

At this time, the total charge amount of the capacitors 431 and 433 does not change, and therefore the following equation holds.
Q _init =Q _after +Q2... Equation 4

By substituting the expressions 1 to 3 into the expression 4, and transforming the expression, the following expression is obtained.
V _out =−(C1/C2)×(V _after −V _init )...Equation 5

Expression 5 represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1/C2. Since it is usually desired to maximize the gain, it is preferable to design C1 large and C2 small. On the other hand, if C2 is too small, kTC noise may increase and noise characteristics may be deteriorated. Therefore, the capacity reduction of C2 is limited to a range in which noise can be allowed. Further, since the address event detection unit 400 including the subtractor 430 is mounted for each pixel block, there is a restriction on the area of the capacitors C1 and C2. In consideration of these, the values of the capacitors C1 and C2 are determined.

The comparator 441 compares the voltage signal from the subtractor 430 with the upper limit voltage Vbon applied to the inverting input terminal (−). Here, the upper limit voltage Vbon is a voltage indicating an upper limit threshold. The comparator 441 outputs the comparison result COMP+ to the transfer unit 450. The comparator 441 outputs a high-level comparison result COMP+ when an ON event occurs, and outputs a low-level comparison result COMP+ when there is no ON event.

The comparator 442 compares the voltage signal from the subtractor 430 with the lower limit voltage Vboff applied to the inverting input terminal (−). Here, the lower limit voltage Vboff is a voltage indicating a lower limit threshold. The comparator 442 outputs the comparison result COMP− to the transfer unit 450. The comparator 442 outputs a high-level comparison result COMP- when an off event occurs, and outputs a low-level comparison result COMP- when there is no off event.

[Configuration example of transfer unit]
FIG. 9 is a circuit diagram showing a configuration example of the transfer unit 450 according to the first embodiment of the present technology. The transfer unit 450 includes AND (logical product) gates 451 and 453, an OR (logical sum) gate 452, and flip-flops 454 and 455.

The AND gate 451 outputs the logical product of the comparison result COMP+ of the quantizer 440 and the response AckY from the Y arbiter 213 to the column ADC 220 as the detection signal DET+. The AND gate 451 outputs a high-level detection signal DET+ when an ON event occurs and outputs a low-level detection signal DET+ when there is no ON event.

The OR gate 452 outputs the logical sum of the comparison result COMP+ and the comparison result COMP− of the quantizer 440 to the Y arbiter 213 as a request ReqY. The OR gate 452 outputs a high-level request ReqY when an address event occurs, and outputs a low-level request ReqY when there is no address event. Further, the inverted value of the request ReqY is input to the input terminal D of the flip-flop 454.

The AND gate 453 outputs a logical product of the comparison result COMP- of the quantizer 440 and the response AckY from the Y arbiter 213 to the column ADC 220 as a detection signal DET-. The AND gate 453 outputs a high-level detection signal DET- when an off event occurs, and outputs a low-level detection signal DET- when there is no off event.

The flip-flop 454 holds the inverted value of the request ReqY in synchronization with the response AckY. The flip-flop 454 outputs the held value as an internal signal ColEN′ to the input terminal D of the flip-flop 455.

The flip-flop 455 holds the internal signal ColEN′ in synchronization with the selection signal SEL from the drive circuit 211. The flip-flop 455 outputs the held value to the column ADC 220 as the column enable signal ColEN.

[Example of configuration of column ADC]
FIG. 10 is a block diagram showing a configuration example of the column ADC 220 according to the first embodiment of the present technology. In this column ADC 220, an AD conversion unit 230 is arranged for each K (K is an integer of 2 or more) columns. For example, the AD conversion unit 230 is provided for every two columns. In this case, assuming that the number of columns is 2M (M is an integer), the number of AD conversion units 230 is M.

The AD conversion unit 230 converts an analog pixel signal from at least one of the corresponding two columns into a digital signal.

[Configuration Example of AD Converter]
FIG. 11 is a block diagram showing a configuration example of the AD conversion unit 230 according to the first embodiment of the present technology. The AD conversion unit 230 includes a multiplexer 231, an ADC 232, and a control circuit 240. Two columns corresponding to the AD conversion unit 230 are a 2m-1 (m is an integer of 1 to M) column and a 2m column.

Multiplexer 231, in accordance with a control signal from the control circuit 240, a pixel signal _{Vsig 2m-1} of 2m-1 columns, and outputs the ADC232 as a pixel signal _{Vsig SEL} selects one of the pixel signal Vsig _2m of 2m rows Is. The switching signal SW and the multiplexer enable signal MuxEN are input to the multiplexer 231 as control signals. The multiplexer 231 is an example of the selection unit described in the claims.

The ADC 232 converts the pixel signal Vsig _SEL into a digital signal Dout. The ADC 232 includes a comparator 233 and a counter 234. The ADC 232 is an example of the analog-digital converter described in the claims.

The comparator 233 compares a predetermined reference signal RMP with the pixel signal Vsig _SEL according to the comparator enable signal CompEN from the control circuit 240. As the reference signal RMP, for example, a ramp signal that changes in a slope shape is used. The comparator enable signal CompEN is a signal for enabling or disabling the comparison operation of the comparator 233. The comparator 233 supplies the comparison result VCO to the counter 234.

The counter 234 counts the count value in synchronization with the clock signal CLK until the comparison result VCO is inverted in accordance with the counter enable signal CntEN from the control circuit 240. The counter enable signal CntEN is a signal for enabling or disabling the counting operation of the counter 234. The counter 234 outputs a digital signal Dout indicating the count value to the signal processing unit 212.

The control circuit 240 controls the multiplexer 231 and the ADC 232 according to the column enable signals ColEN _2m-1 and ColEN _{2m of the 2m-} 1th column and the 2mth column, respectively. Details of the control contents will be described later.

Further, the detection signals DET+ and DET− of each column are output to the signal processing unit 212 via the AD conversion unit 230.

Although a single-slope ADC including the comparator 233 and the counter 234 is used as the ADC 232, the present invention is not limited to this configuration. For example, a delta-sigma type ADC can be used as the ADC 232.

FIG. 12 is a block diagram showing a configuration example of the control circuit 240 according to the first embodiment of the present technology. The control circuit 240 includes an OR (logical sum) gate 241, a level shifter 242, an AND (logical product) gate 243, a demultiplexer 244, and a switching control unit 245.

The OR gate 241 outputs the logical sum of the column enable signals ColEN _2m-1 and ColEN _2m and the extra enable signal ExtEN to the level shifter 242 and the AND gate 243. The extra enable signal ExtEN is a signal for instructing to validate AD conversion regardless of the presence or absence of an address event, and is set according to a user operation or the like. For example, the high level is set to the extra enable signal ExtEN when it is enabled, and the low level is set when it is disabled.

The level shifter 242 converts the voltage of the output signal of the OR gate 241. The converted signal is input to the demultiplexer 244.

The AND gate 243 outputs the logical product of the output signal of the OR gate 241 and the block control signal Crtl1 to the counter 234 as the counter enable signal CntEN. The block control signal Crtl1 is a signal for invalidating the counter 234 regardless of the presence or absence of an address event. For example, regardless of the presence or absence of an address event, the block control signal Crtl1 is set to low level when the counter 234 is invalidated, and is set to high level otherwise.

The demultiplexer 244 distributes the output signal of the level shifter 242 to the multiplexer 231 and the comparator 233 according to the block control signal Crtl2. The block control signal Crtl2 is a signal for invalidating at least one of the multiplexer 231 and the comparator 233 regardless of the presence or absence of an address event.

For example, regardless of the presence/absence of an address event, when only the multiplexer 231 is invalidated, a binary number "10" is set to the block control signal Crtl2. At this time, the output signal of the level shifter 242 is output to the comparator 233 as the comparator enable signal CompEN. When disabling only the comparator 233, a binary number "01" is set to the block control signal Crtl2. At this time, the output signal of the level shifter 242 is output to the multiplexer 231 as the multiplexer enable signal MuxEN. When both the multiplexer 231 and the comparator 233 are invalidated, "00" is set, and otherwise "11" is set. When “11” is set, the output signal of the level shifter 242 is output to both the multiplexer 231 and the comparator 233.

The switching control unit 245 switches the pixel signal output from the multiplexer 231 based on the column enable signals ColEN _2m-1 and ColEN _2m . When the enable is set to only one, the switching control unit 245 causes the multiplexer 231 to select the pixel signal of the enabled column by the switching signal SW. When enable is set for both of the two columns, the switching control unit 245 causes the multiplexer 231 to select the pixel signal of one column by the switching signal SW, and then selects the pixel signal of the other column.

FIG. 13 is a diagram for explaining the read control in the first embodiment of the present technology. In the figure, a and b are diagrams for explaining the read control when an address event occurs in only one of the 2m-1 column and the 2m column. C in the figure is a diagram for explaining the read control when an address event occurs in both the 2m-1th column and the 2mth column.

When an address event occurs in one of the 2m−1th column and the 2mth column and there is no address event in the other column, only the pixel 310 of the column in which the address event occurs transmits the column enable signal ColEN that is enabled. On the other hand, the column enable signal ColEN of the column having no address event is set to be disabled.

In this case, the control circuit 240 in the column ADC 220 causes the multiplexer 231 to select the enabled column by the switching signal SW. For example, when the 2m-1 column is enabled, the control circuit 240 causes the multiplexer 231 to select the column by the switching signal SW, as illustrated in a in the figure. On the other hand, when the 2m-th column is enabled, the control circuit 240 causes the multiplexer 231 to select that column, as illustrated in b in the figure.

Further, the control circuit 240 sets the ADC 232 to be enabled by the comparator enable signal CompEN and the counter enable signal CntEN over a certain AD conversion period.

When an address event occurs in both the 2m-1th column and the 2mth column, the pixel 310 in each column transmits the enable column enable signal ColEN. In this case, the control circuit 240 causes the multiplexer 231 to select one of the 2m-1 column and the 2m column, and then the other, as illustrated in c in the figure. In addition, the control circuit 240 enables the ADC 232 during the AD conversion periods of the 2m-1th column and the 2mth column. The column ADC 220 is an example of the analog-digital conversion unit described in the claims.

Further, when both the 2m-1th column and the 2mth column are disabled, the control circuit 240 sets the ADC 232 to be disabled.

As described above, the AD conversion unit 230 AD-converts only the pixel signal of the pixel 310 in which the address event has occurred among the pixels 310 in the row in which the address event has occurred, and does not AD-convert the remaining pixels. As a result, power consumption can be reduced as compared with the case where all pixel signals in the row in which the address event has occurred are AD-converted.

[Operation example of solid-state image sensor]
FIG. 14 is a timing chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. At timing T0, the drive circuit 211 sets the control signal OFG to the high level to drive the OFG transistor 332. As a result, the detection of the presence or absence of the address event is started.

When an address event (such as an on event) occurs at timing T1, the pixel 310 transmits a high-level request ReqY to the Y arbiter 213.

At the timing T2 immediately after the timing T1, the Y arbiter 213 holds the request ReqY as the request ReqY′. Further, the Y arbiter 213 arbitrates the request and returns the response AckY. The pixel 310 receiving this response AckY outputs, for example, a high-level detection signal DET+. Further, the pixel 310 inverts the request ReqY and holds it in the flip-flop 455 as an internal signal ColEN′.

The drive circuit 211 that has received the detection signal DET+ supplies the high-level auto-zero signal AZ at timing T3 to initialize the address event detection unit 400. Subsequently, the drive circuit 211 sets the control signal OFG to the low level and supplies the reset signals RST and TRG of the high level at the timing T4. As a result, exposure is started.

The drive circuit 211 supplies the high-level reset signal RST to initialize the floating diffusion layer 324 at a timing T5 immediately before the end of exposure in synchronization with the horizontal synchronization signal XHS. Then, at timing T6, the drive circuit 211 supplies the high-level selection signal SEL. The pixel 310 supplies a high level column enable signal ColEN in synchronization with the selection signal SEL. As a result, the reset level is AD converted. Here, the reset level is the level of the pixel signal when the floating diffusion layer 324 is initialized.

Next, at timing T7, the drive circuit 211 supplies the high-level transfer signal TRG to transfer the charges to the floating diffusion layer 324. As a result, the signal level is AD converted. Here, the signal level is the level of the pixel signal at the end of exposure.

FIG. 15 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when an application for detecting and imaging an address event is executed. The solid-state imaging device 200 detects the presence or absence of an address event (step S901), and determines whether an address event has occurred (step S902). When an address event occurs (step S902: Yes), the column ADC 220 AD-converts only the pixel signal of the pixel 310 having the address event (step S903).

When the address event has not occurred (step S902: No), or after step S903, the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps.

As described above, according to the first embodiment of the present technology, the pixel signal of the pixel 310 in which the amount of change in the amount of incident light is outside the range from the lower limit to the upper limit (that is, the address event has occurred) is AD-converted. Therefore, the number of AD conversions can be minimized. That is, focusing on a certain row, when an address event occurs in any of the plurality of pixels in the row, only the pixel signal of that pixel is AD-converted. This makes it possible to reduce the power consumption required for AD conversion when capturing an image, as compared with the case where AD conversion is performed on the pixel signals of all pixels in a row. Therefore, it becomes easy to capture a high-quality image while detecting the presence or absence of an address event.

<2. Second Embodiment>
In the above-described first embodiment, when the address event occurs in both the 2m−1th column and the 2mth column, the multiplexer 231 sequentially selects the columns one by one and AD-converts the pixel signal. However, in this control method, since AD conversion is performed column by column, the speed of AD conversion (that is, reading) is slower than in the case where only one column is AD converted. The solid-state image sensor 200 of the second embodiment differs from that of the first embodiment in that a plurality of pixel signals are read in parallel without using the multiplexer 231.

FIG. 16 is a block diagram showing a configuration example of the pixel array unit 300 and the column ADC 220 according to the second embodiment of the present technology. In the pixel array section 300 of the second embodiment, detection signal lines 302, 303, 306 and 307, vertical signal lines 304 and 308, and enable signal lines 305 and 309 are wired for each column. .. The pixels 310 of 2n (n is an integer of 1 to N) rows, where the number of rows is 2N (N is an integer), are connected to the detection signal lines 306 and 307, the vertical signal line 308, and the enable signal line 309. It On the other hand, the pixels 310 in the 2n−1th row are connected to the detection signal lines 302 and 303, the vertical signal line 304, and the enable signal line 305.

Further, in the column ADC 220, two AD conversion units 230 are arranged for each column. One of the two AD conversion units 230 AD-converts the pixel signal of the 2n-th row of the corresponding column, and the other AD-converts the 2n−1-th row.

FIG. 17 is a block diagram showing a configuration example of the AD conversion unit 230 according to the second embodiment of the present technology. The AD conversion unit 230 of the second embodiment is different from that of the first embodiment in that the multiplexer 231 and the control circuit 240 are not arranged.

The ADC 232 of the second embodiment AD-converts the pixel signal Vsig of the corresponding column according to the column enable signal ColEN of the corresponding column.

With the configuration illustrated in FIGS. 16 and 17, when an address event occurs in both the 2m−1th column and the 2mth column, the 2m−1th column AD conversion unit 230 and the 2mth column AD conversion unit 230 are arranged in parallel. AD conversion can be performed. When an address event occurs in both 2n-1 rows and 2n columns, the AD conversion unit 230 corresponding to 2n-1 rows and the AD conversion unit 230 corresponding to 2n rows perform AD conversion in parallel.

Although the two AD conversion units 230 are arranged for each column, one AD conversion unit 230 may be arranged for each column. Further, a configuration may be adopted in which three or more AD conversion units 230 are arranged for each column and three or more rows are AD-converted in parallel.

As described above, according to the second embodiment of the present technology, since the two AD conversion units 230 perform AD conversion on the pixel signals in the 2n−1th row and the 2nth row in parallel for each column, the AD conversion is performed for each row. The speed of AD conversion (reading) can be improved as compared with the case of performing.

<3. Third Embodiment>
In the above-described second embodiment, all the AD conversion units 230 are arranged in the column ADC 220, but the circuit scale of the column ADC 220 increases as the number of pixels increases. The solid-state imaging device 200 of the third embodiment is different from that of the second embodiment in that a plurality of AD converters 230 are dispersedly arranged in the upper column ADC and the lower column ADC.

FIG. 18 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the third embodiment of the present technology. In the solid-state imaging device 200 of the third embodiment, an upper column ADC 221 and a lower column ADC 222 are arranged instead of the column ADC 220, and an upper signal processing unit 214 and a lower signal processing unit instead of the signal processing unit 212. The part 215 is arranged.

The upper column ADC 221 AD-converts the pixel signal of the 2nth row, and the upper signal processing unit 214 processes the digital signal and the detection signal of the row. On the other hand, the lower column ADC 222 AD-converts the pixel signals in the 2n−1th row, and the lower signal processing unit 215 processes the digital signal and the detection signal in that row.

FIG. 19 is a block diagram showing a configuration example of the pixel array unit 300 and the lower column ADC 222 according to the third embodiment of the present technology. The configuration of the pixel array section 300 of the third embodiment is similar to that of the second embodiment. However, the pixels 310 in the 2nth row are connected to the upper column ADC 221, and the pixels 310 in the 2n−1th row are connected to the lower column ADC 222.

In the lower column ADC 222, the AD conversion unit 230 is arranged for each column. The configuration of the AD conversion unit 230 of the third embodiment is similar to that of the second embodiment without the multiplexer 231. In the upper column ADC 221, similarly, the AD conversion unit 230 is arranged for each column.

With the configurations illustrated in FIGS. 18 and 19, when the address event occurs in both the 2n−1th row and the 2nth column, the upper column ADC 221 and the lower column ADC 222 can perform AD conversion in parallel. The upper column ADC 221 is an example of a first analog-digital conversion unit described in the claims, and the lower column ADC 222 is an example of a second analog-digital conversion unit described in the claims. ..

As described above, according to the third embodiment of the present technology, the 2N AD conversion units 230 are dispersedly arranged in the upper column ADC 221 and the lower column ADC 222, so that the circuit scale per column ADC is reduced. be able to.

<4. Fourth Embodiment>
In the above-described third embodiment, the AD conversion unit 230 is arranged for each column in each of the upper column ADC 221 and the lower column ADC 222. However, as the number of pixels increases, the circuit scale of each column ADC increases. Will increase. The solid-state imaging device 200 according to the fourth embodiment is different from the solid-state imaging device 200 according to the third embodiment in that AD converters 230 are arranged every two columns in each of the upper column ADC 221 and the lower column ADC 222.

FIG. 20 is a block diagram showing a configuration example of the pixel array unit 300 and the lower column ADC 222 according to the fourth embodiment of the present technology. In the pixel array section 300 according to the fourth embodiment, four signal lines are wired for each column as in the first embodiment. Further, assuming that the number of rows is 4M, 4m rows and 4m-2 rows are connected to the upper column ADC 221, and 4m-1 rows and 4m-3 rows are connected to the lower column ADC 222.

In the lower column ADC 222 of the fourth embodiment, an AD conversion unit 230 is arranged for every K columns for a total of 2M columns connected. When K is “2”, M AD conversion units 230 are arranged. The configuration of the AD conversion unit 230 of the fourth embodiment is similar to that of the first embodiment provided with the multiplexer 231. Similarly, in the upper column ADC 221 of the fourth embodiment, the AD conversion units 230 are arranged every two columns.

As described above, according to the fourth embodiment of the present technology, since the AD conversion units 230 are arranged for every two columns, the upper column ADC 221 and the lower column ADC 221 are arranged as compared with the case where the AD conversion units 230 are arranged for each column. The circuit scale of each of the side column ADCs 222 can be reduced.

<5. Fifth Embodiment>
In the above-described first embodiment, the Y arbiter 213 in the solid-state image sensor 200 arbitrated requests from a plurality of rows, but did not adjust requests from a plurality of columns. With this configuration, when address events occur at a plurality of pixels in a row at substantially the same time, the detection signals of those pixels are output to the signal processing unit 212 at substantially the same time, which increases the processing load of the signal processing unit 212. The solid-state image sensor 200 of the fifth embodiment differs from that of the first embodiment in that the X arbiter adjusts requests from a plurality of columns.

FIG. 21 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the fifth embodiment of the present technology. The solid-state imaging device 200 of the fifth embodiment differs from that of the first embodiment in that an X arbiter 216 is further provided.

The X arbiter 216 arbitrates a request from each of a plurality of columns and returns a response based on the arbitration result. By arbitrating requests from a plurality of columns, when address events occur at a plurality of pixels in a row substantially at the same time, the detection signals of those pixels can be sequentially supplied to the column ADC 220. The X arbiter 216 is an example of the column arbiter described in the claims.

The pixel 310 of the fifth embodiment transmits a request to the Y arbiter 213 when detecting an address event, and transmits a request to the X arbiter 216 when receiving a response from the Y arbiter 213. Then, the pixel 310 outputs a detection signal when receiving a response from the X arbiter 216.

The configurations of the second to fourth embodiments can also be applied to the solid-state image sensor 200 of the fifth embodiment.

As described above, according to the fifth embodiment of the present technology, the X arbiter 216 arbitrates requests from each of a plurality of columns, so that when an address event occurs at a plurality of pixels in a row at substantially the same time. , The detection signals of those pixels can be sequentially supplied.

[Modification]
In the above-described fifth embodiment, the pixel 310 generates the column enable signal ColEN. However, in this configuration, a circuit (OR gate 452, flip-flops 454 and 455, etc.) for generating the column enable signal ColEN needs to be arranged for each pixel, and accordingly, the circuit scale of the pixel array unit 300 is increased accordingly. Will increase. The solid-state imaging device 200 of the modified example of the fifth embodiment is different from the fifth embodiment in that the X arbiter 216 generates the column enable signal ColEN instead of the pixel 310.

FIG. 22 is a block diagram showing a configuration example of the pixel 310 and the X arbiter 216 in the modification example of the fifth embodiment of the present technology. In the pixel 310 of the modified example of the fifth embodiment, the address event detection unit 400 does not generate the column enable signal ColEN. Instead, the X arbiter 216 generates the column enable signal ColEN of the column in which the address event occurs and supplies it to the column ADC 220.

Note that the configurations of the second to fourth embodiments can also be applied to the solid-state image sensor 200 of the modification of the fifth embodiment.

As described above, in the modified example of the fifth embodiment of the present technology, since the X arbiter 216 generates the column enable signal ColEN, it is necessary to arrange a circuit for generating the column enable signal ColEN in the pixel 310. Disappears. As a result, the circuit scale of the pixel 310 can be reduced.

<6. Application to mobiles>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. May be.

FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, and a steering angle of the vehicle. It functions as a steering mechanism for adjusting and a control device such as a braking device for generating a braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a winker, or a fog lamp. In this case, the body system control unit 12020 can be input with radio waves or signals of various switches transmitted from a portable device that substitutes for a key. The body system control unit 12020 receives input of these radio waves or signals and controls the vehicle door lock device, power window device, lamp, and the like.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the image capturing unit 12031 to capture an image of the vehicle exterior and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The image pickup unit 12031 can output the electric signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects in-vehicle information. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether or not the driver is asleep.

The microcomputer 12051 calculates the control target value of the driving force generation device, the steering mechanism or the braking device based on the information on the inside and outside of the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes functions of ADAS (Advanced Driver Assistance System) including collision avoidance or impact mitigation of a vehicle, follow-up traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, vehicle lane departure warning, and the like. It is possible to perform cooperative control for the purpose.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, or the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, thereby It is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of antiglare such as switching the high beam to the low beam. It can be carried out.

The voice image output unit 12052 transmits an output signal of at least one of a voice and an image to an output device capable of visually or audibly notifying information to a passenger of the vehicle or the outside of the vehicle. In the example of FIG. 23, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 24, the image capturing unit 12031 includes image capturing units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle. The image capturing unit 12101 provided on the front nose and the image capturing unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 included in the side mirrors mainly acquire images of the side of the vehicle 12100. The image capturing unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that FIG. 24 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, and the imaging range 12114 indicates The imaging range of the imaging part 12104 provided in a rear bumper or a back door is shown. For example, by overlaying the image data captured by the image capturing units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera including a plurality of image capturing elements or may be an image capturing element having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). In particular, the closest three-dimensional object on the traveling path of the vehicle 12100, which travels in the substantially same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), can be extracted as a preceding vehicle. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, which autonomously travels without depending on the operation of the driver.

For example, the microcomputer 12051 uses the distance information obtained from the image capturing units 12101 to 12104 to convert three-dimensional object data regarding a three-dimensional object to other three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, telephone poles, and the like. It can be classified, extracted, and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or more than the set value and there is a possibility of collision, the microcomputer 12051 outputs the audio through the audio speaker 12061 and the display unit 12062. A driver can be assisted for avoiding a collision by outputting an alarm to the driver and performing forced deceleration or avoidance steering through the drive system control unit 12010.

At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian is present in the images captured by the imaging units 12101 to 12104. To recognize such a pedestrian, for example, a procedure for extracting a feature point in an image captured by the image capturing units 12101 to 12104 as an infrared camera and pattern matching processing on a series of feature points indicating the contour of an object are performed to determine whether or not the pedestrian is a pedestrian. The procedure for determining When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 causes the recognized pedestrian to have a rectangular contour line for emphasis. The display unit 12062 is controlled so as to superimpose. Further, the audio image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian or the like at a desired position.

The example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, the power consumption of the image capturing unit 12031 can be reduced, and thus the power consumption of the entire vehicle control system can be reduced.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a correspondence relationship. Similarly, the matters specifying the invention in the claims and the matters having the same names in the embodiments of the present technology have a correspondence relationship. However, the present technology is not limited to the embodiments and can be embodied by making various modifications to the embodiments without departing from the scope of the invention.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, or as a program for causing a computer to execute the series of procedures or a recording medium storing the program. You can catch it. As the recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described in the present specification are merely examples and are not limited, and may have other effects.

In addition, the present technology may have the following configurations.
(1) a plurality of pixels each of which generates an analog signal by photoelectric conversion;
A solid-state image sensor, comprising: an analog-digital conversion unit that converts the analog signal of a pixel, of the plurality of pixels, in which the amount of change in incident light amount is outside a predetermined range, into a digital signal.
(2) The analog-digital converter is
A selection unit that selects the analog signal of the pixel whose variation amount is outside the predetermined range among the analog signals of each of the plurality of pixels;
The solid-state imaging device according to (1), further comprising: an analog-digital converter that converts the selected analog signal into the digital signal.
(3) The plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction,
The analog-digital conversion unit includes a fixed number of analog-digital converters for each column,
The analog-digital converter converts the analog signal of the pixel into the digital signal when the change amount of the pixel belonging to the corresponding column of the plurality of pixels is out of the predetermined range. ) The solid-state imaging device according to item 1.
(4) The plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction,
The analog-digital converter,
A first analog-digital converter connected to a part of the predetermined number of columns;
The solid-state imaging device according to (1), further including a second analog-digital conversion unit connected to the rest of the predetermined number of columns.
(5) Each of the first and second analog-to-digital converters,
A selection unit that selects the analog signal of the column in which the change amount is out of the predetermined range among the analog signals of the corresponding column,
The solid-state imaging device according to (4), further comprising: an analog-digital converter that converts the selected analog signal into the digital signal.
(6) Each of the first and second analog-to-digital converters includes a certain number of analog-to-digital converters for each corresponding column,
The analog-digital converter converts the analog signal of the pixel into the digital signal when the change amount of the pixel belonging to the corresponding column of the plurality of pixels is out of the predetermined range. ) The solid-state imaging device according to item 1.
(7) Each of the plurality of pixels is
A pixel signal generator that generates the analog signal;
A detection unit that detects whether or not the absolute value of the change amount exceeds a predetermined threshold value and generates a predetermined enable signal based on the detection result.
The solid-state imaging device according to any one of (1) to (6), wherein the analog-digital conversion unit converts the analog signal into the digital signal according to the enable signal.
(8) A row arbiter for arbitrating a first request from each of a predetermined number of rows arranged in a direction perpendicular to the predetermined direction is further provided.
The plurality of pixels are arranged in the predetermined number of rows,
The solid-state imaging device according to any one of (1) to (6), wherein each of the plurality of pixels transmits the first request when the amount of change is outside the predetermined range.
(9) A column arbiter for arbitrating a second request from each of a predetermined number of columns arranged in the predetermined direction is further provided.
The solid-state imaging device according to any one of (8), wherein each of the plurality of pixels transmits the second request based on an arbitration result of the row arbiter.
(10) The column arbiter generates a predetermined enable signal based on the second request,
The solid-state imaging device according to (9), wherein the analog-digital conversion unit converts the analog signal into the digital signal according to the enable signal.
(11) A plurality of pixels each of which generates an analog signal by photoelectric conversion,
An analog-to-digital converter that converts the analog signal of a pixel, of which the absolute value of the incident light amount is out of a predetermined range, of the plurality of pixels into a digital signal,
An image pickup apparatus comprising: a signal processing unit that processes the digital signal.

100 image pickup device 110 image pickup lens 120 recording unit 130 control unit 200 solid-state image pickup device 201 light receiving chip 202 detection chip 211 drive circuit 212 signal processing unit 213 Y arbiter 214 upper signal processing unit 215 lower signal processing unit 216 X arbiter 220 column ADC
221 Upper column ADC
222 Lower column ADC
230 AD converter 231 Multiplexer 232 ADC
233 comparator 234 counter 240 control circuit 241, 452 OR (logical sum) gate 242 level shifter 243, 451, 453 AND (logical product) gate 244 demultiplexer 245 switching control section 300 pixel array section 310 pixels 320 pixel signal generation section 321 reset Transistor 322 Amplification transistor 323 Selection transistor 324 Floating diffusion layer 330 Light receiving part 331 Transfer transistor 332 OFG transistor 333 Photoelectric conversion element 400 Address event detection part 410 Current/voltage conversion part 411, 413 N-type transistor 412 P-type transistor 420 Buffer 430 Subtractor 431 433 capacitor 432 inverter 434 switch 440 quantizer 441, 442 comparator 450 transfer unit 454, 455 flip-flop 12031 imaging unit

Claims (11)

A plurality of pixels each of which generates an analog signal by photoelectric conversion,
A solid-state image sensor, comprising: an analog-digital conversion unit that converts the analog signal of a pixel, of the plurality of pixels, in which the amount of change in incident light amount is outside a predetermined range, into a digital signal. The analog-digital converter,
A selection unit that selects the analog signal of the pixel whose variation amount is outside the predetermined range among the analog signals of each of the plurality of pixels;
The solid-state imaging device according to claim 1, further comprising an analog-digital converter that converts the selected analog signal into the digital signal. The plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction,
The analog-digital conversion unit includes a fixed number of analog-digital converters for each column,
The analog-digital converter converts the analog signal of the pixel into the digital signal when the variation amount of the pixel belonging to the corresponding column of the plurality of pixels is out of the predetermined range. The solid-state image sensor according to claim 1. The plurality of pixels are provided in a predetermined number of columns arranged in a predetermined direction,
The analog-digital converter,
A first analog-digital converter connected to a part of the predetermined number of columns;
The solid-state imaging device according to claim 1, further comprising a second analog-digital conversion unit connected to the rest of the predetermined number of columns. Each of the first and second analog-to-digital converters,
A selection unit that selects the analog signal of the column in which the change amount is out of the predetermined range among the analog signals of the corresponding column,
The solid-state image sensor according to claim 4, further comprising an analog-digital converter that converts the selected analog signal into the digital signal. Each of the first and second analog-to-digital converters includes a fixed number of analog-to-digital converters for each corresponding column,
The analog-digital converter converts the analog signal of the pixel into the digital signal when the variation amount of the pixel belonging to the corresponding column of the plurality of pixels is out of the predetermined range. The solid-state image sensor according to claim 1. Each of the plurality of pixels is
A pixel signal generator that generates the analog signal;
A detection unit that detects whether or not the absolute value of the change amount exceeds a predetermined threshold value and generates a predetermined enable signal based on the detection result.
The solid-state image sensor according to claim 1, wherein the analog-digital conversion unit converts the analog signal into the digital signal according to the enable signal. A row arbiter for arbitrating a first request from each of a predetermined number of rows arranged in a direction perpendicular to the predetermined direction,
The plurality of pixels are arranged in the predetermined number of rows,
The solid-state image sensor according to claim 1, wherein each of the plurality of pixels transmits the first request when the amount of change is outside the predetermined range. Further comprising a column arbiter that arbitrates a second request from each of a predetermined number of columns arranged in the predetermined direction,
The solid-state image sensor according to claim 8, wherein each of the plurality of pixels transmits the second request based on an arbitration result of the row arbiter. The column arbiter generates a predetermined enable signal based on the second request,
The solid-state image sensor according to claim 9, wherein the analog-digital conversion unit converts the analog signal into the digital signal according to the enable signal. A plurality of pixels each of which generates an analog signal by photoelectric conversion,
An analog-to-digital converter that converts the analog signal of a pixel, of which the absolute value of the amount of incident light is out of a predetermined range, to a digital signal,
An image pickup apparatus comprising: a signal processing unit that processes the digital signal.

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