JP2020087961A - Laminate structure and manufacturing method thereof - Google Patents

Abstract

To provide a highly reliable laminate structure and a manufacturing method thereof in which an active layer is less likely to deteriorate.SOLUTION: A laminate structure according to an embodiment of the present invention includes a conductive layer, an oxide semiconductor layer having an In-Ga-Zn-O-based material, an insulating film provided between the conductive layer and the oxide semiconductor layer, and first and second electrodes electrically connected to the oxide semiconductor layer, and having titanium. A surface layer portion of the oxide semiconductor layer opposite to the insulating film includes titanium oxide in a first region where the first and second electrodes are not connected.SELECTED DRAWING: Figure 1

Description

The present invention relates to a laminated structure and a method for manufacturing the laminated structure.

In the active layer used for the thin film transistor, IGZO (In-Ga-Zn-Oxide) has attracted attention as a substitute for amorphous silicon (see, for example, Patent Document 1). IGZO has a larger conductivity than amorphous silicon, and the use of IGZO has the advantage of simplifying the device structure.

In the process of manufacturing a thin film transistor using IGZO, a laminated structure having an active layer, a gate insulating film and a gate electrode made of IGZO is formed, and then the laminated structure is electrically connected to the active layer. A source electrode and a drain electrode to be connected are formed. Further, in the laminated structure, the active layer may be covered with a protective layer.

JP, 2013-064185, A

In the above laminated structure, after forming the active layer, the surface of the active layer may be inevitably exposed to the chemicals or the reactive species in the plasma when forming the layer to be deposited on the active layer. In such a case, if the resistance of the active layer to the reactive species is weak, the active layer is likely to deteriorate after the active layer is exposed to the reactive species.

In view of the above circumstances, an object of the present invention is to provide a highly reliable laminated structure and a method for manufacturing the laminated structure, in which the active layer is less likely to deteriorate.

In order to achieve the above object, a stacked structure according to one embodiment of the present invention includes a conductive layer, an oxide semiconductor layer including an In—Ga—Zn—O-based material, the conductive layer, and the oxide semiconductor layer. And an insulating film provided between the first and second electrodes, the first electrode and the second electrode being electrically connected to the oxide semiconductor layer and having titanium. The surface layer portion of the oxide semiconductor layer on the side opposite to the insulating film has titanium oxide in the first region where the first electrode and the second electrode are not connected.
According to such a laminated structure, the oxide semiconductor layer is less likely to deteriorate, and a highly reliable laminated structure is formed.

In the above laminated structure, the surface layer portion may include titanium oxide in a second region to which the first electrode and the second electrode are connected.
According to such a laminated structure, since titanium oxide is formed in the surface layer portion of the oxide semiconductor layer, the oxide semiconductor layer is less likely to deteriorate and a highly reliable laminated structure is formed.

In the above laminated structure, the titanium oxide may have crystallinity.
According to such a laminated structure, since the crystalline titanium oxide is formed in the surface layer portion of the oxide semiconductor layer, the oxide semiconductor layer is less likely to deteriorate and a highly reliable laminated structure is formed. It

In the above stacked structure, the oxide semiconductor layer may have an amorphous property.
According to such a laminated structure, since the oxide semiconductor layer is amorphous, appropriate mobility is ensured and a highly reliable laminated structure is formed.

The laminated structure may further include an insulating layer that covers the first region to which the first electrode and the second electrode are not connected.
According to such a laminated structure, the oxide semiconductor layer is protected by the insulating layer. Further, since the oxide semiconductor layer has resistance to active hydrogen when the insulating layer is formed, oxygen vacancies are unlikely to occur in the oxide semiconductor layer even when the oxide semiconductor layer is covered with the insulating layer.

In the above stacked structure, the conductive layer functions as a gate electrode, the oxide semiconductor layer functions as an active layer, the insulating film functions as a gate insulating film, and the first electrode is a source. The second electrode may function as an electrode, and the second electrode may function as a drain electrode to form a thin film transistor.
Such a laminated structure is applied to a thin film transistor.

In the above laminated structure, the insulating layer may function as a protective layer of the thin film transistor.
According to such a laminated structure, the insulating layer is applied to the protective layer of the thin film transistor.

To achieve the above object, in the method for manufacturing a laminated structure according to an aspect of the present invention, a conductive layer is patterned on the substrate. An insulating film is formed on the substrate and the conductive layer. An oxide semiconductor layer including an In—Ga—Zn—O-based material is patterned on the conductive layer with the insulating film interposed therebetween. An electrode layer containing titanium is formed over the insulating film and the oxide semiconductor layer. The electrode layer and the oxide semiconductor layer are heat-treated. The electrode layer is patterned by etching to form a first electrode and a second electrode electrically connected to the oxide semiconductor layer.
According to such a method for manufacturing a laminated structure, the oxide semiconductor layer is less likely to deteriorate and a highly reliable laminated structure is formed.

In the method for manufacturing a laminated structure described above, the heat treatment may be performed at a temperature of 200° C. or higher and 400° C. or lower.
According to such a method for manufacturing a laminated structure, a surface layer portion having high resistance is formed in the oxide semiconductor layer by the heat treatment.

In the above method for manufacturing a laminated structure, an insulating layer may be formed by a chemical vapor deposition method in a region of the oxide semiconductor layer where the first electrode and the second electrode are not connected.
According to such a method for manufacturing a laminated structure, since the oxide semiconductor layer has resistance to active hydrogen when the insulating layer is formed, even if the oxide semiconductor layer is covered with the insulating layer, the oxide semiconductor layer is not affected. Oxygen deficiency is unlikely to occur in the semiconductor layer.

As described above, according to the present invention, a highly reliable laminated structure and a method for manufacturing a laminated structure are provided.

FIG. 1A is a schematic cross-sectional view of the laminated structure according to this embodiment. FIG. 2B is a schematic cross-sectional view of the portion surrounded by the frame 1p in FIG. It is a flow figure showing an example of a manufacturing process of a layered structure. It is a schematic cross section which shows the manufacturing process of the laminated structure which demonstrated the flow chart concretely. It is a schematic cross section which shows the manufacturing process of the laminated structure which demonstrated the flow chart concretely. It is a typical sectional view showing an example of an effect of this embodiment. It is a schematic cross section which shows another example of the effect of this embodiment. It is a schematic cross section which shows the manufacturing process of a comparative example. FIG. 6A is a diagram showing an element concentration profile near the interface between the electrode and the oxide semiconductor layer. FIG. 6B is a TEM image near the interface between the electrode and the oxide semiconductor layer. It is a schematic cross section which shows a part of manufacturing process which manufactures the sample of a comparative example. It is a schematic cross section which shows a part of manufacturing process which manufactures the sample of an Example. FIG. 6A is a graph showing the VI curve of the example. FIG. 6B is a graph showing the VI curve of the comparative example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. XYZ axis coordinates may be introduced into each drawing. In addition, the same members or members having the same function are denoted by the same reference numerals, and the description thereof may be appropriately omitted after the description of the members.

FIG. 1A is a schematic cross-sectional view of the laminated structure according to this embodiment. FIG. 1B is a schematic cross-sectional view of the portion surrounded by the frame 1p of FIG.

The laminated structure 1 illustrated in FIG. 1A includes a conductive layer 13, an insulating film 12, an oxide semiconductor layer 11, a first electrode 16S, a second electrode 16D, and an insulating layer 15. The laminated structure 1 is applied to, for example, a bottom-gate thin film transistor.

The substrate 10 is a base of the laminated structure 1. The substrate 10 is an insulating substrate, for example, a glass substrate.

The conductive layer 13 is patterned on the substrate 10. The conductive layer 13 is preferably a Mo film, a Ti film, or an alloy film thereof. The thickness of the conductive layer 13 is set to several hundreds nm, for example.

The insulating film 12 is provided between the conductive layer 13 and the oxide semiconductor layer 11. The insulating film 12 is, for example, a two-layer insulating film. The insulating film 12 has a silicon oxide film on the oxide semiconductor layer 11 side (or the insulating layer 15 side) and a silicon nitride film on the conductive layer 13 side (or the substrate 10 side).

The oxide semiconductor layer 11 faces the conductive layer 13 with the insulating film 12 interposed therebetween. The oxide semiconductor layer 11 includes an amorphous layer 111 and a surface layer portion 110. The thickness of the oxide semiconductor layer 11 is 15 nm or more and 100 nm or less. The surface layer portion 110 has a thickness of 10 nm or more and 40 nm or less.

The amorphous layer 111 is a base layer that occupies most of the thickness of the oxide semiconductor layer 11 and includes an In—Ga—Zn—O-based material. The atomic ratio of In, Ga, and Zn is 1:1:1. Here, "amorphous" means that the amorphous component is more than the completely amorphous or crystalline component, and the "crystalline" is completely crystalline or crystalline than the amorphous component. It means that there are more ingredients.

Here, when a crystalline In—Ga—Zn—O-based material is used as the base layer of the oxide semiconductor layer 11 instead of the amorphous layer 111, the mobility of the oxide semiconductor layer 11 is amorphous. It is not preferable because it is lower than

The surface layer portion 110 is provided between the amorphous layer 111 and the insulating layer 15, between the amorphous layer 111 and the first electrode 16S, and between the amorphous layer 111 and the second electrode 16D. The surface layer portion 110 is a surface layer formed by inverting a part of the surface of the amorphous layer 111.

The surface layer portion 110 has a first region 11a and a second region 11b. The first region 11a is a region on the side opposite to the insulating film 12 and to which the first electrode 16S and the second electrode 16D are not connected. The second region 11b is a region where the first electrode 16S and the second electrode 16D are connected.

The surface layer part 110 has a laminated structure. For example, in the example of FIG. 1B, the surface layer portion 110 has a two-layer structure, and has a first surface layer portion 110a and a second surface layer portion 110b. The thickness of the first surface layer portion 110a is 6 nm or more and 20 nm or less. The thickness of the second surface layer portion 110b is 4 nm or more and 20 nm or less.

The first surface layer portion 110a is a crystalline layer that includes an In—Ga—Zn—O-based material in which both In and Zn are rich. In other words, the first surface layer portion 110a is a crystalline oxygen-deficient layer containing an In—Ga—Zn—O-based material. The second surface layer portion 110b is a layer having titanium oxide crystals. The crystallinity or amorphousness of each layer of this embodiment is confirmed by TEM or the like. The components in each layer of this embodiment are confirmed by EDX and the like. The TEM image and component analysis will be described later. In addition, the In-Ga-Zn-O-based material may be described as an IGZO-based material.

Each of the first electrode 16S and the second electrode 16D penetrates the insulating layer 15 and is electrically connected to the oxide semiconductor layer 11. Each of the first electrode 16S and the second electrode 16D is in contact with the side surface of the oxide semiconductor layer 11 and a part of the upper surface of the oxide semiconductor layer 11 continuous with the side surface. The first electrode 16S may include, for example, a Ti layer in contact with the surface of the oxide semiconductor layer 11, and a Cu layer or an Al layer may be formed on the Ti layer. The configuration of the second electrode 16D is the same as that of the first electrode 16S.

The insulating layer 15 covers the first region 11a of the oxide semiconductor layer 11 and the insulating film 12 to which the first electrode 16S and the second electrode 16D are not connected.

In the laminated structure 1, the conductive layer 13 functions as a gate electrode, the oxide semiconductor layer 11 functions as an active layer, the insulating film 12 functions as a gate insulating film, and the first electrode 16S functions as a source electrode. The second electrode 16D functions as a drain electrode, and when the insulating layer 15 functions as a protective layer, the laminated structure 1 functions as a thin film transistor.

Next, a manufacturing process of the laminated structure 1 will be described.

FIG. 2 is a flow chart showing an example of the manufacturing process of the laminated structure.
FIG. 3A to FIG. 4B are schematic cross-sectional views showing the manufacturing process of the laminated structure for which the flow diagram is specifically described.

For example, the conductive layer 13 is patterned on the substrate 10 (step S10). The conductive layer 13 is formed on the substrate 10 by, for example, a sputtering method and then patterned by wet etching.

Next, the insulating film 12 is formed on the substrate 10 and the conductive layer 13 by a chemical vapor deposition method such as a plasma CVD method (step S20).

Next, the oxide semiconductor layer made of the amorphous layer 111 is patterned on the conductive layer 13 via the insulating film 12 (step S30). The amorphous layer 111 includes an In-Ga-Zn-O-based material. For example, the amorphous layer 111 is patterned by wet etching after being formed by a sputtering method in an oxygen atmosphere. The sputtering method may be a magnetron sputtering method.

During the sputtering film formation of the amorphous layer 111, the temperature of the substrate 10 is set to 50° C. or higher and 200° C. or lower, for example, 100° C. Ar (argon) is used as the sputtering gas. The sputtering gas may contain 5% or more and 50% partial pressure of oxygen. In addition, after patterning the amorphous layer 111, in order to activate the amorphous layer 111, the amorphous layer 111 may be heated in the atmosphere at a temperature of 300° C. or higher and 500° C. or lower (for example, The heat treatment may be performed at 400° C.) for 0.5 hours or more and 2 hours or less. The state of the laminated body up to this point is shown in FIG.

Next, the electrode layer 16 containing titanium is formed on the oxide semiconductor layer including the insulating film 12 and the amorphous layer 111 (step S40). The electrode layer 16 is formed so as to cover the upper surface and the side surface of the amorphous layer 111. The electrode layer 16 is formed by, for example, a sputtering method. The sputtering method may be a magnetron sputtering method. The state of the laminated body up to this point is shown in FIG.

Next, the electrode layer 16 and the oxide semiconductor layer including the amorphous layer 111 are kept at a temperature of 200 °C to 400 °C inclusive (eg, 300 °C) for 0.5 hours to 2 hours inclusive (eg, 1 hour). Then, heat treatment (post-baking) is performed (step S50). Thus, the surface layer portion 110 is formed in part of the oxide semiconductor layer including the amorphous layer 111, and the oxide semiconductor layer including the surface layer portion 110 and the amorphous layer 111 is formed over the insulating film 12. 11 and 11 are formed. The surface layer portion 110 is located between the amorphous layer 111 and the electrode layer 16. In addition, the post-baking is performed in the above temperature range, so that the amorphous layer 111 maintains the amorphous state.

Further, in this heat treatment, titanium is diffused from the electrode layer 16 to the amorphous layer 111, and titanium and oxygen contained in the amorphous layer 111 are combined. As a result, the surface layer portion 110 includes the crystalline titanium oxide layer. That is, the surface layer portion 110 having the first surface layer portion 110a and the second surface layer portion 110b is formed on the upper surface and the side surface of the amorphous layer 111. The state of the laminated body up to this point is shown in FIG.

Next, the electrode layer 16 is patterned by wet etching to form the first electrode 16S and the second electrode 16D electrically connected to the oxide semiconductor layer 11 (step S60). The state of the laminated body up to this point is shown in FIG.

After that, the insulating layer 15 is formed in the region of the oxide semiconductor layer 11 to which the first electrode 16S and the second electrode 16D are not connected, by, for example, a chemical vapor deposition method such as a plasma CVD method (step S70). ). Thereby, the laminated structure 1 is formed. The laminated structure 1 is shown in FIG.

FIG. 5A to FIG. 5C are schematic cross-sectional views showing an example of the effects of this embodiment.

5A to 5C show how the first electrode 16S and the second electrode 16D connected to the oxide semiconductor layer 11 are formed. The first electrode 16S and the second electrode 16D are formed by wet etching the electrode layer 16 with the chemical solution 50. As the chemical solution 50, for example, a phosphorous nitrate acetic acid-based etchant (73% phosphoric acid, 3% nitric acid, 7% acetic acid, 17% water, manufactured by Kanto Chemical Co., Inc.) is used for the Al layer, and for the Cu layer. Is a nitric acid-fluoride-based etchant for a Ti layer. A nitric acid-fluoride-based etchant (less than 20% sulfuric acid, less than 10% nitric acid, less than 30% acetic acid, 40% or more water, manufactured by Kanto Chemical Co., Inc.) is used. An etchant (less than 5% nitric acid) and KSMF-240 (manufactured by Kanto Kagaku) are used.

For example, FIG. 5A shows a state in which the mask layer 40 is formed on the electrode layer 16. As shown in FIG. 5A, a part of the surface of the electrode layer 16 exposed from the mask layer 40 is starting to be wet-etched by the chemical solution 50.

Subsequently, as shown in FIG. 5B, when the wet etching of the electrode layer 16 proceeds, the oxide semiconductor layer 11 is exposed from the electrode layer 16 before the insulating film 12. This is because about 10% over-etching is performed on the surface of the oxide semiconductor layer 11 in order to reliably etch the surface.

Thereafter, as shown in FIG. 5C, when the wet etching of the electrode layer 16 progresses, the electrode layer 16 is separated and the first electrode 16S and the second electrode 16D are formed. However, the surface of the oxide semiconductor layer 11 is exposed to the chemical solution 50 until the first electrode 16S and the second electrode 16D are formed.

Even in such a case, since the titanium oxide crystal having high resistance to the chemical liquid 50 is provided on the surface of the oxide semiconductor layer 11, the resistance of the oxide semiconductor layer 11 to the chemical liquid 50 is high. That is, the wet etching rate (selection ratio) of the electrode layer 16 with respect to the wet etching rate of the oxide semiconductor layer 11 is significantly improved.

FIG. 6 is a schematic cross-sectional view showing another example of the effect of this embodiment.

FIG. 6 shows a state in which the formation of the insulating layer 15 by the plasma CVD method is started after the first electrode 16S and the second electrode 16D are formed. In plasma CVD, a silane-based gas is used as a source gas, so that active hydrogen such as hydrogen ions and hydrogen radicals exists in the plasma 51. In this case, the surface of the oxide semiconductor layer 11 is exposed to active hydrogen contained in the plasma 51 until the insulating layer 15 is deposited.

Even in such a case, the titanium oxide crystal having high resistance to active hydrogen is formed on the surface of the oxide semiconductor layer 11, so that the reduction resistance of the oxide semiconductor layer 11 is high. That is, oxygen deficiency is less likely to occur in the amorphous layer 111.

As described above, even if the manufacturing process is continued after the oxide semiconductor layer 11 is formed, the chemical resistance and the reduction resistance of the oxide semiconductor layer 11 are high. Maintain the characteristics of. Further, since the chemical resistance and the reduction resistance of the oxide semiconductor layer 11 are high, the process margin in the wet etching step and the plasma CVD step is expanded.

7A to 7C are schematic cross-sectional views showing the manufacturing process of the comparative example.

For example, in the comparative example, as shown in FIG. 7A, the insulating layer 15 is formed on the amorphous layer 111 and the insulating film 12. Next, as shown in FIG. 7B, holes 16h for forming the first electrode 16S and the second electrode 16D are formed in the insulating layer 15. Next, as shown in FIG. 7C, the first electrode 16S and the second electrode 16D are formed in the hole 16h.

However, after such a manufacturing process, since the insulating layer 15 is formed on the amorphous layer 111, the surface layer portion 110 is not formed on the surface of the amorphous layer 111. Therefore, when the amorphous layer 111 is exposed to active hydrogen contained in the plasma 51, oxygen deficiency is likely to occur in the amorphous layer 111 due to the reducing action of active hydrogen. As a result, in the comparative example, the characteristics of the amorphous layer 111 as a semiconductor may deteriorate.

FIG. 8A is a diagram showing an element concentration profile near the interface between the electrode and the oxide semiconductor layer. FIG. 8B is a TEM image near the interface between the electrode and the oxide semiconductor layer. FIG. 8A shows a concentration profile of Ti (titanium) and oxygen (O) as an example of element concentration. The horizontal axis of FIG. 8A represents the depth from the sample surface, and the vertical axis represents the normalized value of the concentration. The judgment of the crystallinity of each layer has been confirmed from the electron diffraction pattern of TEM. The components of each layer have been confirmed by EDX analysis.

In the concentration profile shown in FIG. 8A, a region where the titanium concentration is substantially uniform and a region where the oxygen concentration is substantially uniform are observed in the depth direction (horizontal axis). It is considered that the region where the titanium concentration is substantially uniform corresponds to the first electrode 16S and the region where the oxygen concentration is substantially uniform corresponds to the amorphous layer 111 composed of the IGZO layer.

Further, it can be seen that a region in which oxygen is deficient in the amorphous layer 111 is provided between the first electrode 16S and the amorphous layer 111. Since this region is adjacent to the amorphous layer 111, it is considered to correspond to the first surface layer portion 110a which is an oxygen deficient layer.

On the other hand, between the first electrode 16S and the first surface layer portion 110a, the titanium concentration is lower than that of the first electrode 16S, but the titanium concentration rises, and the oxygen concentration is higher than that of the amorphous layer 111. There are areas that will not be high. Considering that two oxygen atoms are bound to titanium in the stoichiometric ratio of titanium oxide, this region is considered to correspond to the second surface layer portion 110b.

The bottom layer of the TEM image shown in FIG. 8B is an amorphous layer 111 composed of an amorphous IGZO layer, and the top layer of the TEM image corresponds to the first electrode 16S composed of Ti. To do. It is observed that there are two layers between the amorphous layer 111 and the first electrode 16S. When the TEM image and the concentration profile are associated with each other, it can be seen that the first surface layer portion 110a formed of a crystalline oxygen-deficient IGZO layer is formed on the side of the amorphous layer 111 of the two layers. ..

From the TEM image observation, it can be seen that a striped pattern is seen in some places in the first surface layer portion 110a as compared with the amorphous layer 111, and the IGZO layer is crystallized. Further, when the TEM image and the concentration profile are associated with each other, it is found that the second surface layer portion 110b containing crystalline titanium oxide is formed between the first surface layer portion 110a and the first electrode 16S. .. In other words, it has been confirmed from the results of FIGS. 8A and 8B that the surface layer portion 110 contains titanium oxide.

As a TFT (Thin Film Transistor) active layer, two samples were prepared: a sample for a comparative example having no surface layer portion 110 and a sample for an example having a surface layer portion 110.

9A to 9D are schematic cross-sectional views showing a part of the manufacturing process for manufacturing the sample of the comparative example. 10A to 10D are schematic cross-sectional views showing a part of the manufacturing process for manufacturing the sample of the example.

In the comparative example, a resist pattern 60 is formed on the amorphous layer 111 made of IGZO and the insulating film 12 (FIG. 9A). Holes 16h for forming the first electrode 16S and the second electrode 16D are formed in the resist pattern 60. Next, the electrode layer 16 made of titanium is formed on the resist pattern 60 so as to fill the holes 16h (FIG. 9B). Next, the resist pattern 60 is removed by lift-off, and the first electrode 16S and the second electrode 16D embedded in the hole 16h are left (FIG. 9C). Next, the insulating film 15 is formed on the amorphous layer 111 and the insulating film 12 by plasma CVD (FIG. 9D).

In the comparative example, when the surface of the amorphous layer 111 is exposed (FIG. 9C), since the surface layer portion 110 is not formed on the surface of the amorphous layer 111, the amorphous layer 111 is directly formed. It will be exposed to plasma gas.

On the other hand, in the example, the electrode layer 16 made of titanium is formed on the amorphous layer 111 made of IGZO and the insulating film 12 (FIG. 10A). 111 is post-baked for 1 hour at 300° C. Thereby, the oxide semiconductor layer 11 in which a part of the surface of the amorphous layer 111 becomes the surface layer portion 110 is formed (FIG. 10B). Next, the electrode layer 16 exposed from the mask 40 is patterned by nitric acid-fluoride type etchant (nitric acid less than 5%) and KSMF-240 (manufactured by Kanto Kagaku Co., Ltd.), whereby the first electrode 16S and the second electrode 16D. Then, the insulating layer 15 is formed on the oxide semiconductor layer 11 and the insulating film 12 by the plasma CVD method (FIG. 10D).

The process conditions common to the comparative example and the example are as follows.
Sputtering conditions for the amorphous layer 111;
Target: IGZO (metal composition ratio: 1:1:1 (stoichiometric ratio))
Discharge power: 1 to 5 W/cm ² , for example, 3 W/cm ^2.
Substrate temperature: room temperature to 200°C, for example, 100°C
CVD conditions for the insulating film 15;
Raw material gas: SiH ₄ , O ₂ , N ₂ O
Discharge power: 0.1~1W / cm ^2, for example, 0.6 W / cm ²
Substrate temperature: 100°C to 300°C, for example, 200°C

FIG. 11A is a graph showing the VI curve of the example. FIG. 11B is a graph showing the VI curve of the comparative example. Here, “1” is the VI curve when the gate electrode is changed from the negative potential to the positive potential, and “1r” is the V− curve when the gate electrode is changed from the positive potential to the negative potential. It is an I curve. The source-drain voltage is 5V.

As shown in FIG. 11A, in the example, an appropriate VI characteristic observed in the on/off operation of the transistor was obtained. That is, in the example, it was found that the sample normally turned on and off. For example, the on-voltage is −1.4V. On the other hand, in the comparative example, the transistor characteristics could not be obtained. It was found that normally on, that is, the oxide semiconductor layer was conductive.

Table 1 shows the hole mobility (cm ² /V·sec) after formation of the electrodes (first electrode 16S, second electrode 16D) and carrier density (number/piece/piece) for the examples and the comparative examples. cm ³ ), hole mobility after formation of the insulating layer 15, and carrier density after formation of the insulating layer 15.

In the comparative example, the hole mobility after forming the electrode was 9.2 cm ² /V·sec and the carrier density was 8.8×10 ¹³ pieces/cm ³ , whereas the hole mobility after forming the insulating layer was The mobility was increased to 25.8 cm ² /V·sec and the carrier density was increased to 7.5×10 ²¹ particles/cm ³ .

On the other hand, in the example, the hole mobility after forming the electrode was 10.1 cm ² /V·sec and the carrier density was 1.8×10 ¹⁴ pieces/cm ³ , and even after forming the insulating layer, the holes were formed. The mobility remained at 12.5 cm ² /V·sec and the carrier density remained at 6.9×10 ¹⁶ particles/cm ³ .

In the comparative example, the surface layer portion 110 is not formed on the surface of the amorphous layer 111 when the insulating layer 15 is formed by plasma CVD. Therefore, when the amorphous layer 111 is exposed to the active hydrogen contained in the plasma, oxygen deficiency easily occurs in the amorphous layer 111 due to the reducing action of the active hydrogen, and the amorphous layer 111 changes from a semiconductor to a metal. It is thought to approach. This is supported by the fact that the VI curve was not obtained in the comparative example. Thus, in the comparative example, the characteristics as a semiconductor deteriorate.

On the other hand, in the example, the surface layer portion 110 containing crystalline titanium oxide is formed on the surface of the oxide semiconductor layer 11. Therefore, even when the oxide semiconductor layer 11 is exposed to active hydrogen contained in plasma when the insulating layer 15 is formed, the surface layer portion 110 has resistance to the reducing action of active hydrogen. Therefore, it is considered that oxygen deficiency is unlikely to occur in the amorphous layer 111 and the amorphous layer 111 maintains the semiconductor property. Furthermore, even when the oxide semiconductor layer 11 is exposed to a chemical when the electrode layer 16 is processed with a chemical liquid, the surface layer portion 110 also has chemical resistance. This is supported by the fact that the hole mobility and carrier density after forming the electrodes are not much different from those of the comparative example.

From these results, an amorphous IGZO layer having higher hole mobility than the IGZO crystal layer is applied to the oxide semiconductor layer of the thin film transistor, and part of the oxide semiconductor layer, for example, the surface layer portion is crystallized. By applying the oxide semiconductor layer 11 described above, it can be predicted that a thin film transistor having higher hole mobility, chemical resistance, and active hydrogen resistance can be formed.

Although the embodiments of the present invention have been described above, it is needless to say that the present invention is not limited to the above-described embodiments and various changes can be made. Each embodiment is not limited to an independent form, and can be combined as technically possible.

DESCRIPTION OF SYMBOLS 1... Laminated structure 1p... Frame 10... Substrate 11a... 1st area|region 11b... 2nd area|region 11... Oxide semiconductor layer 12... Insulating film 13... Conductive layer 15... Insulating layer 16... Electrode layer 16S... 1st electrode 16D... Second electrode 16h... Hole portion 50... Chemical solution 51... Plasma 60... Resist pattern 110... Surface layer portion 110a... First surface layer portion 110b... Second surface layer portion 111... Amorphous layer

Claims (10)

A conductive layer,
An oxide semiconductor layer having an In-Ga-Zn-O-based material;
An insulating film provided between the conductive layer and the oxide semiconductor layer,
A first electrode and a second electrode electrically connected to the oxide semiconductor layer and having titanium;
Equipped with,
A laminated structure in which a surface layer portion of the oxide semiconductor layer opposite to the insulating film includes titanium oxide in a first region where the first electrode and the second electrode are not connected. The laminated structure according to claim 1,
A laminated structure in which the surface layer portion includes the titanium oxide in a second region to which the first electrode and the second electrode are connected. The laminated structure according to claim 1 or 2,
The titanium oxide has a crystalline laminated structure. The laminated structure according to any one of claims 1 to 3,
The oxide semiconductor layer has a layered structure having an amorphous property. The laminated structure according to any one of claims 1 to 4,
The laminated structure further comprising an insulating layer covering the first region where the first electrode and the second electrode are not connected. The laminated structure according to any one of claims 1 to 5,
The conductive layer functions as a gate electrode, the oxide semiconductor layer functions as an active layer, the insulating film functions as a gate insulating film, the first electrode functions as a source electrode, and the first electrode functions as a source electrode. The two electrodes function as drain electrodes to form a thin film transistor. The laminated structure according to claim 6,
A laminated structure in which the insulating layer functions as a protective layer of the thin film transistor. Patterning a conductive layer on the substrate,
An insulating film is formed on the substrate and the conductive layer,
Patterning an oxide semiconductor layer having an In-Ga-Zn-O-based material on the conductive layer through the insulating film;
An electrode layer containing titanium is formed on the insulating film and the oxide semiconductor layer,
Heat-treating the electrode layer and the oxide semiconductor layer,
A method for manufacturing a laminated structure, wherein the electrode layer is patterned using etching to form a first electrode and a second electrode electrically connected to the oxide semiconductor layer. A method of manufacturing a laminated structure according to claim 8, wherein
A method for manufacturing a laminated structure, wherein the heat treatment is performed at a temperature of 200° C. or higher and 400° C. or lower. The method for manufacturing a laminated structure according to claim 8 or 9,
A method for manufacturing a laminated structure, wherein an insulating layer is formed by a chemical vapor deposition method in a region of the oxide semiconductor layer to which the first electrode and the second electrode are not connected.

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