JP2014195077A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new semiconductor device using an oxide semiconductor.SOLUTION: A semiconductor device includes: a substrate 100 (for example, a substrate having an insulating surface); a first electrode layer 104 on the substrate; an oxide semiconductor layer 114 having a part located on the first electrode layer; a gate insulating layer 118 covering side surfaces of the oxide semiconductor layer; a second electrode layer 124 electrically connected to the oxide semiconductor layer at an opening of the gate insulating layer; and a third electrode layer 126 for applying a voltage to one side surface of the oxide semiconductor layer via the gate insulating layer.

Description

The technical field relates to a semiconductor device having a thin film transistor (hereinafter referred to as TFT) using an oxide semiconductor.

There are various metal oxides and they are used in various applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides exhibit semiconductor properties. A metal oxide exhibiting semiconductor characteristics is a kind of compound semiconductor. A compound semiconductor is a semiconductor formed by bonding two or more atoms by ionic bonds. In general, an ionic bond becomes an insulator by a strong electrostatic attraction between a cation and an anion. However, it is known that depending on the combination of cation and anion, the electrostatic attraction is weak and it becomes a semiconductor.

For example, among metal oxides, tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like are known to exhibit semiconductor characteristics. A thin film transistor using a transparent semiconductor layer formed of such a metal oxide as a channel formation region is disclosed (Patent Documents 1 to 4, Non-Patent Document 1).

By the way, not only single-component oxides but also multi-component oxides are known as metal oxides. For example,
InGaO ₃ (ZnO) _m (m: natural number) having a homologous phase is a known material (Non-Patent Documents 2 to 4).

It has been confirmed that the above-described In—Ga—Zn-based oxide can be applied as a channel layer of a thin film transistor (Patent Document 5, Non-Patent Documents 5 and 6).

JP 60-198861 A JP-A-8-264794 Japanese National Patent Publication No. 11-505377 JP 2000-150900 A JP 2004-103957 A

M.M. W. Princes, K.M. O. Grosse-Holz, G.G. Muller, J.M. F. M.M. Cillessen, J.M. B. Giesbers, R.A. P. Weening, and R.M. M.M. Wolf, “A Ferroelectric Transient Thin-Film Transistor”, Appl. Phys. Lett. 17 June 1996, Vol. 68 p. 3650 M.M. Nakamura, N .; Kimizuka, and T.K. Mohori, “The Phase Relations in the In 2 O 3 —Ga 2 ZnO 4 —ZnO System at 1350 ° C.”, J. Mol. Solid State Chem. 1991, Vol. 93, p. 298 N. Kimizuka, M .; Isobe, and M.M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In 2 O 3 (ZnO) m (m = 3,4, and 5), InGaO 3 (ZnO) 3, and Ga 2 O 3 (ZnO) 9 (m = 7, 8 and 16) in the In2O3-ZnGa2O4-ZnO System ", J. et al. Solid State Chem. 1995, Vol. 116, p. 170 Masaki Nakamura, Noboru Kimizuka, Naohiko Mouri, Mitsumasa Isobe, “Homologous Phase, Synthesis and Crystal Structure of InFeO 3 (ZnO) m (m: Natural Number) and Its Isomorphic Compounds”, Solid Physics, 1993, Vol. 28, no. 5, p. 317 K. Nomura, H .; Ohta, K .; Ueda, T .; Kamiya, M .; Hirano, and H.H. Hoson, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”, SCIENCE, 2003, Vol. 300, p. 1269 K. Nomura, H .; Ohta, A .; Takagi, T .; Kamiya, M .; Hirano, and H.H. Hoson, “Room-temperament fabrication of transparent flexible thin-film transducers using amorphous semiconductors”, NATURE, 2004, Vol. 432 p. 488

An object of one embodiment of the present invention disclosed in this specification and the like (including at least the specification, the claims, and the drawings) is to provide a new semiconductor device including an oxide semiconductor.

In one embodiment of the invention disclosed in this specification and the like, a transistor is formed using an oxide semiconductor material. More details are as follows.

One embodiment of the invention disclosed in this specification and the like includes a substrate (eg, a substrate having an insulating surface);
In the first electrode layer on the substrate, the oxide semiconductor layer part of which is on the first electrode layer, the gate insulating layer covering the side surface of the oxide semiconductor layer, and the opening of the gate insulating layer, A semiconductor device comprising: a second electrode layer electrically connected to the oxide semiconductor layer; and a third electrode layer that applies a voltage to a side surface of the oxide semiconductor layer through the gate insulating layer. It is.

Another embodiment of the invention disclosed in this specification and the like includes a substrate, a first electrode layer over the substrate, an insulating layer provided over the first electrode layer, and the first electrode layer. An oxide semiconductor layer covering the end portion and the end portion of the insulating layer, a gate insulating layer covering the oxide semiconductor layer, and a second electrode layer electrically connected to the oxide semiconductor layer in the opening of the gate insulating layer And a third electrode layer for applying a voltage to the oxide semiconductor layer through the gate insulating layer.

Note that in the above, it is preferable to use a material containing a metal with high oxygen affinity for the first electrode layer or the second electrode layer. The metal having a high oxygen affinity is preferably a material selected from one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium.

In the above, the region of the oxide semiconductor layer that is electrically connected to the first electrode layer or the second electrode layer has a smaller oxygen composition ratio than the other region of the oxide semiconductor layer. Is preferred.

Another embodiment of the invention disclosed in this specification and the like includes a substrate, a first electrode layer over the substrate, a first low-resistance semiconductor layer over the first electrode layer, and a part thereof being the first. An oxide semiconductor layer present on the low-resistance semiconductor layer, a second low-resistance semiconductor layer on the oxide semiconductor layer, a gate insulating layer covering a side surface of the oxide semiconductor layer, and a second low-resistance semiconductor layer And a third electrode layer that applies a voltage to the side surface of the oxide semiconductor layer through the gate insulating layer.

Another embodiment of the invention disclosed in this specification and the like includes a substrate, a first electrode layer over the substrate, a first low-resistance semiconductor layer over the first electrode layer, and a first low-resistance semiconductor layer. An insulating layer on the resistive semiconductor layer; a second low-resistance semiconductor layer on the insulating layer; an end portion of the first electrode layer; an end portion of the first low-resistance semiconductor layer;
An oxide semiconductor layer covering an end portion of the insulating layer and an end portion of the second low-resistance semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, and a second electrically connected to the second low-resistance semiconductor layer Two electrode layers;
And a third electrode layer for applying a voltage to the oxide semiconductor layer through the gate insulating layer.

Note that in the above, silicon is preferably added to the oxide semiconductor layer.
The oxide semiconductor layer preferably has an amorphous structure. The oxide semiconductor layer is preferably made of an oxide semiconductor containing indium, gallium, and zinc.

As an example of an oxide semiconductor that can be used in the invention disclosed in this specification and the like, I
Some are represented by nMO ₃ (ZnO) _m (m> 0). Here, M is gallium (G
a) One metal element or a plurality of metal elements selected from iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, the case where Ga is selected as M includes the case where the metal element other than Ga, such as Ga and Ni or Ga and Fe, is selected in addition to the case of Ga alone. In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements. In this specification and the like, the oxide semiconductor containing at least gallium as M is referred to as an In—Ga—Zn—O-based oxide semiconductor, and a thin film using the material is referred to as In—Ga—Zn—O. Sometimes referred to as a non-single crystal film.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and semiconductor circuits, display devices, electro-optical devices, light-emitting display devices, electronic devices, and the like are all included in semiconductor devices. included.

In this specification and the like, a display device refers to an image display device, a light-emitting device, or a light source (including a lighting device). Here, a connector, for example, FPC (Flexible p
printed circuit) and TAB (Tape Automated Bondi)
ng) A module with a tape, TCP (Tape Carrier Package), etc., a TAB tape, a module with a printed wiring board provided at the end of TCP, and an IC (integrated circuit) as a display element by a COG (Chip On Glass) system. All directly mounted modules are included in the display device.

In one embodiment of the invention disclosed in this specification and the like, a semiconductor device is manufactured using an oxide semiconductor. Thereby, an excellent semiconductor device can be provided.

It is sectional drawing and a top view of a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. It is sectional drawing and a top view of a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is sectional drawing and a top view of a semiconductor device. It is the top view and sectional drawing of a semiconductor device. It is sectional drawing of a semiconductor device. It is sectional drawing of a semiconductor device. It is sectional drawing of a semiconductor device. It is the top view and sectional drawing of a semiconductor device. It is a figure explaining the example of the usage pattern of electronic paper. It is an external view which shows the example of an electronic book. It is an external view which shows the example of a television apparatus and a digital photo frame. It is an external view showing an example of a gaming machine. It is an external view which shows the example of a mobile telephone. It is a figure which shows the density of states by calculation. It is a figure which shows the structure by calculation. It is a figure which shows the density of an atom before and behind calculation. It is a cross-sectional TEM image of a sample. It is a figure which shows the percentage of the structural element of a different phase.

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the embodiments described below, and it is obvious to those skilled in the art that modes and details can be variously changed without departing from the spirit of the invention disclosed in this specification and the like. . In addition, structures according to different embodiments can be implemented in appropriate combination. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure of a semiconductor device is described with reference to FIGS.

FIG. 1 shows an example of the configuration of the semiconductor device according to this embodiment. 1A is a cross-sectional view, and FIG. 1B is a plan view. FIG. 1A illustrates a cross section taken along line AB of FIG. In the plan view, a part of the configuration is omitted for simplicity.

A semiconductor device illustrated in FIG. 1 includes a substrate 100 (for example, a substrate having an insulating surface), and a substrate 100.
The upper first electrode layer 104, the first low-resistance semiconductor layer 112 on the first electrode layer 104, the oxide semiconductor layer 114 on the first low-resistance semiconductor layer 112, and the oxide semiconductor layer 114 Second above
A low-resistance semiconductor layer 116, a gate insulating layer 118 covering a side surface of the oxide semiconductor layer 114,
A second electrode layer 124 electrically connected to the second low-resistance semiconductor layer 116; and the gate insulating layer 1
The transistor 150 includes the third electrode layer 126 that applies a voltage to the side surface of the oxide semiconductor layer 114 through 18 (see FIGS. 1A and 1B). Here, the first electrode layer 104 functions as a source electrode (or drain electrode), the second electrode layer 124 functions as a drain electrode (or source electrode), and the third electrode layer 126 functions as a gate electrode. To do. Note that the functions of the source electrode and the drain electrode in the transistor are interchanged depending on the direction in which carriers flow, and thus the names of the source electrode and the drain electrode are merely convenient. That is, the functions of various conductive layers are not interpreted as being limited to the above names. Further, the various electrode layers may have a function as a wiring.

Although FIG. 1 illustrates an example of a structure in which the first low-resistance semiconductor layer 112 is present on the entire lower surface of the oxide semiconductor layer 114, one embodiment of the disclosed invention is not limited thereto. For example,
The first low-resistance semiconductor layer 112 may be provided only in a region between the first electrode layer 104 and the oxide semiconductor layer 114. In other words, at least part of the oxide semiconductor layer 114 only needs to exist on the first low-resistance semiconductor layer 112. Alternatively, the first low-resistance semiconductor layer 112 and the second low-resistance semiconductor layer 116 may be omitted. In this case, an oxide semiconductor layer is provided over the first electrode, and the second electrode layer is electrically connected to the oxide semiconductor layer. Similarly, other components can be appropriately changed in a mode in which the function as a semiconductor device can be secured.

In the case where the first low-resistance semiconductor layer 112 and the second low-resistance semiconductor layer 116 are not provided, the first electrode layer 104 or the second electrode layer 124 is made of a metal having high oxygen affinity. It is preferable that Examples of the metal having a high oxygen affinity include metals having a lower standard electrode potential than zinc, such as titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. Further, copper or the like may be used. In this manner, by performing heat treatment or the like so that the metal having high affinity for oxygen and the oxide semiconductor layer are in contact with each other, oxygen in the region in contact with the first electrode layer or the second electrode layer of the oxide semiconductor layer can be obtained. The composition ratio is smaller than that in other regions. Since the conductivity tends to be improved in the low oxygen region, it can have the same function as the low resistance semiconductor layer. Note that the metal having a high oxygen affinity is not limited to the above materials.

The above phenomenon is caused by the fact that a metal with high oxygen affinity extracts oxygen from the oxide semiconductor layer. Therefore, the composition ratio of oxygen in the electrode layer in contact with the oxide semiconductor layer is different from that in other regions. It is considered to be larger than that (that is, in this region, the electrode layer is oxidized)
. In consideration of this, the metal oxide formed in the electrode layer in a region in contact with the oxide semiconductor layer preferably has conductivity. For example, in the case where titanium is used as a metal having a high oxygen affinity, the composition ratio is close to that of one oxide (for example, 0.1% when TiOx is used).
Various treatments may be performed under conditions where an oxide of 5 <x <1.5) is formed. This is because titanium monoxide has conductivity, but titanium dioxide has insulating properties.

Here, the effect in the case of using a metal with high oxygen affinity as an electrode layer will be described based on computer simulation. Here, titanium is used as a metal with high oxygen affinity,
Although calculation is performed on the case where an In—Ga—Zn—O-based oxide semiconductor material is used for the oxide semiconductor layer, one embodiment of the disclosed invention is not limited thereto. Note that in the calculation, the composition of the In—Ga—Zn—O-based oxide semiconductor material was In: Ga: Zn: O = 1: 1.
1: 4.

First, the effect of oxygen loss from an oxide semiconductor in an amorphous state was verified.

First, In-G is obtained by a melt-quench method using classical MD (molecular dynamics) calculation.
An amorphous structure of an a-Zn—O-based oxide semiconductor was prepared. Here, calculation is performed for a structure having a total number of atoms of 84 and a density of 5.9 g / cm ³ . The calculation was performed with an NVT ensemble using the Born-Mayer-Huggins type potential between the metal-oxygen and oxygen-oxygen, and the Lennard-Jones type potential between the metal and metal. As a calculation program, Materials Explorer was used.

After that, the structure obtained by the classical MD calculation is optimized by first-principles calculation (quantum MD calculation) using plane wave-pseudopotential method based on density functional theory (DFT), and the density of states Asked. In addition, structure optimization was performed for a structure in which one arbitrary oxygen atom was removed, and the density of states was calculated. CASTEP was used as the calculation program, and GGA-PBE was used as the exchange correlation functional.

FIG. 24 shows the density of states of the structure obtained from the above calculation results. FIG. 24A shows the state density of a structure without oxygen vacancies, and FIG. 24B shows the state density of a structure with oxygen vacancies. Here, 0 (eV) represents energy corresponding to the Fermi level. FIG. 24 (A)
As shown in FIG. 24B, the Fermi level exists at the upper end of the valence band in the structure without oxygen vacancies, whereas the Fermi level exists in the conduction band in the structure with oxygen vacancies. I understand. In a structure with oxygen vacancies, since the Fermi level exists in the conduction band, the number of electrons contributing to conduction increases, and a structure with low resistance (high conductivity) can be obtained.

Next, it was confirmed that oxygen moves from an amorphous oxide semiconductor to a metal with high oxygen affinity by using a metal with high oxygen affinity as an electrode layer.

Here, a titanium crystal was stacked on the In—Ga—Zn—O-based amorphous structure obtained by the first-principles calculation described above, and quantum MD calculation was performed on the structure using an NVT ensemble.
CASTEP was used as the calculation program, and GGA-PBE was used as the exchange correlation functional. The temperature condition was 623 K (350 ° C.).

FIG. 25 shows the structure before and after the quantum MD calculation. FIG. 25A shows a structure before quantum MD calculation, and FIG. 25B shows a structure after quantum MD calculation. In the structure after quantum MD calculation, quantum MD
Compared to before the calculation, the number of oxygen bonded to titanium is increased. The structural change suggests that oxygen atoms move from the amorphous oxide semiconductor layer to the metal layer having high oxygen affinity.

FIG. 26 shows the density of titanium and oxygen before and after the quantum MD calculation. Each curve shows the density of titanium before quantum MD calculation (Ti_before), the density of titanium after quantum MD calculation (Ti_after), the density of oxygen before quantum MD calculation (O_before), and the quantum MD.
It represents the oxygen density (Ti_after) after calculation. FIG. 26 also shows that oxygen atoms move to a metal with high oxygen affinity.

In this manner, by performing heat treatment by bringing an oxide semiconductor layer into contact with a metal layer with high oxygen affinity, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density increases near the interface. Confirmed to do. This suggests that a low-resistance region is formed in the vicinity of the interface, and it can be said that the effect of reducing the contact resistance between the semiconductor layer and the electrode layer is brought about.

Subsequently, the effect of heat treatment was confirmed on a sample having a structure in which an amorphous oxide semiconductor and a metal having high oxygen affinity were stacked. Here, the heat treatment was performed at 350 ° C. Note that although experiments were performed using titanium as a metal with high oxygen affinity and using an In—Ga—Zn—O-based oxide semiconductor material as an amorphous oxide semiconductor, one embodiment of the disclosed invention Is not limited to this.

FIG. 27 shows cross-sectional TEM images of the sample before and after the heat treatment. FIG. 27A shows an image before the heat treatment, and FIG. 27B shows an image after the heat treatment. Each region in the drawing represents an amorphous oxide semiconductor layer (a-IGZO layer), a titanium layer (Ti layer), and a different layer (different layer).

As can be seen from FIG. 27, after heat treatment, a different layer is formed between the amorphous oxide semiconductor layer and the titanium layer. This is considered to be because oxygen atoms moved from the amorphous oxide semiconductor layer to the titanium layer. That is, the main component of the different layer is considered to be titanium oxide (or oxygen and titanium).

FIG. 28 shows the percentage of constituent elements of different phases formed between the amorphous oxide semiconductor layer and the titanium layer. As can be seen from FIG. 28, oxygen is 38.5 atomic% and titanium is 30.5 in the different layers.
Atomic% is included, and the ratio is close to 1: 1. Since titanium monoxide exhibits conductivity, it is understood that extremely good contact can be obtained with such a composition. It is needless to say that the different layer does not need to be titanium oxide in a strict sense, and may include carbon, silicon, an element constituting an oxide semiconductor, and the like.

In this manner, when heat treatment is performed by bringing an oxide semiconductor layer into contact with a metal layer with high oxygen affinity, oxygen atoms move from the oxide semiconductor layer to the metal layer, thereby reducing resistance (conductivity). It was confirmed that an oxide semiconductor region was formed and a conductive metal oxide layer was formed.

The oxide semiconductor layer 114 includes an In—Ga—Zn—O-based oxide semiconductor material, an In—
Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z
n-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn
Various oxide semiconductor materials such as an —O-based and a Zn—O-based material can be used.

The oxide semiconductor layer may contain an insulating impurity. Examples of the impurity include an insulating oxide typified by silicon oxide, an insulating nitride typified by silicon nitride, and an insulating oxynitride (nitride oxide) typified by silicon oxynitride and silicon nitride oxide. Applies. These impurities are added at a concentration that does not impair the electrical conductivity of the oxide semiconductor. For example, an oxide semiconductor layer to which silicon oxide is added is formed by a sputtering method using an oxide semiconductor target containing SiO _{2 in an amount} of 0.1 wt% to 10 wt%, preferably 1 wt% to 6 wt%. Can be formed. Of course, the method of adding impurities is not limited to the sputtering method.

Note that in this specification and the like, the term “oxynitride” refers to a composition whose oxygen content (number of atoms) is higher than that of nitrogen. For example, silicon oxynitride refers to oxygen at 50 atomic% or more and 70 Atomic% or less, nitrogen is 0.5 atomic% or more and 15 atomic% or less, and silicon is 25 atomic% or more 3
5 atomic percent or less, and hydrogen is contained in the range of 0.1 atomic percent to 10 atomic percent. In addition, a nitrided oxide indicates a composition whose nitrogen content (number of atoms) is higher than that of oxygen. For example, silicon nitride oxide refers to an oxygen content of 5 atomic% to 30 atomic% and nitrogen content. 2
This includes silicon atoms in the range of 0 atomic% to 55 atomic%, silicon in the range of 25 atomic% to 35 atomic%, and hydrogen in the range of 10 atomic% to 25 atomic%. However, the above range is Rutherford Backscattering Spec (RBS).
trometry and hydrogen forward scattering (HFS)
It is a thing at the time of measuring using Scattering. Further, the total content ratio of the constituent elements does not exceed 100 atomic%.

By including the above-described impurities in the oxide semiconductor, crystallization of the oxide semiconductor can be suppressed. By suppressing crystallization of the oxide semiconductor, characteristics of the transistor can be stabilized.

For example, by adding an impurity such as silicon oxide to an In—Ga—Zn—O-based oxide semiconductor, the oxide semiconductor can be crystallized or finely processed even when heat treatment at 300 ° C. to 600 ° C. is performed. Generation of crystal grains can be prevented. In a manufacturing process of a transistor in which an In—Ga—Zn—O-based oxide semiconductor layer is used as a channel formation region, heat treatment is performed to perform an S value (subthre
(should swing value) and field effect mobility can be improved, but even in such a case, the transistor can be prevented from being normally on. Further, even when thermal stress, bias stress, or the like is applied to the transistor, variation in threshold voltage can be prevented.

Note that although the case where an insulating impurity is added is described above, a material that generates an insulating impurity by being combined with oxygen may be added. As this material, for example,
There are silicon and nitrogen. Thereby, the effect similar to the case where an insulating impurity is added as mentioned above can be acquired.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing a semiconductor device will be described with reference to FIGS.

First, the conductive layer 102 is formed over the substrate 100 (for example, a substrate having an insulating surface) (
(See FIG. 2A).

As the substrate 100, for example, a glass substrate having visible light transparency used for a liquid crystal display device or the like can be used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used, for example. Other,
As the substrate 100, an insulating substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, a substrate obtained by coating the surface of a semiconductor substrate made of a semiconductor material such as silicon with an insulating material, or a conductor such as metal or stainless steel. A substrate whose surface is covered with an insulating material or the like can be used.

Although not illustrated, a base layer may be provided over the substrate 100. The underlayer has a function of preventing diffusion of alkali metals (Li, Cs, Na, etc.), alkaline earth metals (Ca, Mg, etc.) and other impurities from the substrate 100. That is, the problem of improving the reliability of the semiconductor device can be solved by providing the base layer. The base layer can be formed using one or a plurality of materials selected from silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, and the like. Note that the base layer may have a single-layer structure or a stacked structure.

The conductive layer 102 includes aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (
Au), silver (Ag), manganese (Mn), neodymium (Nd) and other metal materials, or alloy materials based on these metal materials, or nitrides containing these metal materials as components, A single-layer structure or a stacked structure can be used. Note that examples of a method for forming the conductive layer 102 include a vacuum evaporation method and a sputtering method; however, the present invention is not limited to these methods.

Next, a resist mask is formed over the conductive layer 102 and the conductive layer 10 is formed using the resist mask.
2 is selectively etched to form the first electrode layer 104 (see FIG. 2B). As the etching, either wet etching or dry etching may be used. Note that the resist mask is removed after the etching. The first electrode layer 104 may be formed to have a tapered end portion in order to improve coverage with an oxide semiconductor layer or the like to be formed later and to prevent disconnection. In this manner, by forming the first electrode layer 104 so as to have a tapered shape, a problem of improving the yield of the semiconductor device can be solved.

The first electrode layer 104 functions as a source electrode (or a drain electrode) of the transistor. Note that the function of the first electrode layer 104 is not limited to the designation of a source electrode or a drain electrode.

Next, the first low-resistance semiconductor layer 106 and the oxide semiconductor layer 1 are formed so as to cover the first electrode layer 104.
08 and the second low-resistance semiconductor layer 110 are sequentially stacked (see FIG. 2C).
Note that although the above stacked structure is formed so as to cover the first electrode layer 104 here, the disclosed invention is not limited thereto.

The oxide semiconductor layer 108 includes an In—Ga—Zn—O-based oxide semiconductor material, an In—
Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z
n-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn
It can be formed using various oxide semiconductor materials such as an -O-based and a Zn-O-based. For example, an oxide semiconductor target containing In, Ga, and Zn (In ₂ O ₃ : Ga ₂ O ₃ : ZnO
= 1: 1: 1), the oxide semiconductor layer 108 is formed by a sputtering method. The sputtering conditions include, for example, a distance between the substrate 100 and the target of 30 mm to 500 mm and a pressure of 0.1.
Pa to 2.0 Pa, direct current (DC) power source can be 0.25 kW to 5.0 kW (when using a target with a diameter of 8 inches), and the atmosphere can be an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen. . Note that the thickness of the oxide semiconductor layer 108 is 5 nm to 500 nm.
However, the present invention is not limited to this. Since the channel length (L) of the transistor is determined by the thickness of the oxide semiconductor layer 108, the thickness of the oxide semiconductor layer 108 can be set as appropriate depending on the demand for the channel length (L).

Examples of the sputtering method include an RF sputtering method using a high frequency power source as a sputtering power source, and D
A C sputtering method, a pulse DC sputtering method in which a direct current bias is applied in a pulsed manner, or the like can be used. Note that a pulse direct current (DC) power source is preferable because dust can be reduced and the film thickness can be uniform. In this case, problems such as improvement in yield and reliability of the semiconductor device can be solved.

Further, a multi-source sputtering apparatus that can install a plurality of targets made of different materials may be used. In a multi-source sputtering apparatus, a plurality of different films can be formed in the same chamber, or a single film can be formed by simultaneously sputtering a plurality of types of materials in the same chamber. Further, a method using a magnetron sputtering apparatus provided with a magnetic field generation mechanism inside the chamber (magnetron sputtering method), an ECR sputtering method using plasma generated using microwaves, or the like may be used. Alternatively, a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted during film formation to form a compound thereof, or a bias sputtering method in which a voltage is also applied to the substrate during film formation may be used. .

The first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) can be formed using a material and a manufacturing method similar to those of the oxide semiconductor layer 108. The first low resistance semiconductor layer 1
06 (or the second low-resistance semiconductor layer 110) and the material (constituent element) of the oxide semiconductor layer 108 may be the same or different. In the case where the same material is used, the film formation conditions of the first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) and the oxide semiconductor layer 108 need to be different. For example, the film formation condition of the first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) is such that the oxygen gas flow rate is smaller than the argon gas flow rate than the oxide semiconductor layer 108 film-formation condition. And Specifically, the film formation condition of the first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) is an atmosphere of a rare gas (such as argon or helium) or an oxygen gas of 10% or less. The atmosphere for forming the oxide semiconductor layer 108 is an oxygen atmosphere or an atmosphere having a flow rate ratio of oxygen gas to the rare gas of 1 or more. As described above, by changing the film formation conditions, two or more types of semiconductor layers having different conductivity can be formed.

Note that the first low-resistance semiconductor layer 106 and the second low-resistance semiconductor layer 110 may have any low resistance as compared with the oxide semiconductor layer 108, and the first low-resistance semiconductor layer 106 and the second low-resistance semiconductor layer 106
The low resistance semiconductor layer 110 is not limited to be equivalent. For example, the second low-resistance semiconductor layer 110 may have a lower resistance than the first low-resistance semiconductor layer 106, or vice versa. In addition, the thickness of the first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) may be approximately 2 nm to 200 nm, but is not limited thereto.

Note that before the first low-resistance semiconductor layer 106 is formed, plasma treatment may be performed on a surface where the first low-resistance semiconductor layer 106 is formed (eg, the surface of the first electrode layer 104). By performing the plasma treatment, dust or the like attached to the surface can be removed. Further, after the above plasma treatment is performed, the first low-resistance semiconductor layer 106 is formed without being exposed to the atmosphere.
Electrical connection between the first electrode layer 104 and the first low-resistance semiconductor layer 106 can be favorably performed. That is, it is possible to solve problems such as improvement in yield and reliability of semiconductor devices.

Note that in the case where the oxide semiconductor layer 108 is formed by a sputtering method, an insulating impurity may be included in the target. Examples of the impurities include insulating oxides typified by silicon oxide, germanium oxide, aluminum oxide, etc., insulating nitrides typified by silicon nitride, aluminum nitride, etc., silicon oxynitride, silicon nitride oxide, aluminum oxynitride, etc. An insulating oxynitride (nitride oxide) typified by the above may be used. These impurities are added at a concentration that does not impair the electrical conductivity of the oxide semiconductor layer 108. For example, I
In the case where the oxide semiconductor layer 108 is formed using an n-Ga-Zn-O-based oxide semiconductor material, 0.1 wt% of SiO ₂ is added to an oxide semiconductor target containing In, Ga, and Zn.
It may be contained in a proportion of 10 wt% or less (preferably 1 wt% or more and 6 wt% or less).

By including the above-described impurities in the oxide semiconductor layer 108, the oxide semiconductor layer 108 can be easily amorphized. Further, crystallization of the oxide semiconductor layer 108 can be suppressed. By suppressing crystallization of the oxide semiconductor layer 108, the characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved.

Note that although the case where an insulating impurity is added is described above, a material which generates an insulating impurity by being combined with oxygen may be used. Examples of the material include silicon, germanium, nitrogen, and aluminum. Thereby, the effect similar to the case where an insulating impurity is added as mentioned above can be acquired.

Further, the above-described impurities may be added to the first low-resistance semiconductor layer 106 and the second low-resistance semiconductor layer 110.

Next, a resist mask is formed over the second low-resistance semiconductor layer 110, and the first low-resistance semiconductor layer 106, the oxide semiconductor layer 108, and the second low-resistance semiconductor layer 110 are formed using the resist mask. The first low-resistance semiconductor layer 112 and the oxide semiconductor layer 11 are selectively etched.
4 and the second low-resistance semiconductor layer 116 are formed (see FIG. 2D). The first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 are formed in an island shape. Here, the oxide semiconductor layer 114 serves as an active layer of the transistor. In addition, the first low-resistance semiconductor layer 112 and the second low-resistance semiconductor layer 116 have an effect of realizing ohmic contact with the electrode layer. Therefore, by forming these low resistance semiconductor layers, the problem of improving the characteristics of the semiconductor device can be solved. Note that although the case where the first low-resistance semiconductor layer 112 and the second low-resistance semiconductor layer 116 are formed has been described in this embodiment mode, these are not essential components. That is, the first low-resistance semiconductor layer 112 and the second low-resistance semiconductor layer 116 may be omitted.

First low-resistance semiconductor layer 106, oxide semiconductor layer 108, and second low-resistance semiconductor layer 11
As the zero etching method, wet etching or dry etching can be used. Here, unnecessary portions of the stacked structure are removed by wet etching using a mixed solution of acetic acid, nitric acid, and phosphoric acid, whereby the first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second A low resistance semiconductor layer 116 is formed. Note that the resist mask is removed after the etching. An etchant (etching solution) that can be used for the wet etching is not particularly limited as long as it can etch the first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116. It is not limited to what you did.

When dry etching is performed, for example, a gas containing chlorine or a gas in which oxygen is added to a gas containing chlorine may be used. By using a gas containing chlorine and oxygen,
This is because the etching selectivity with respect to the conductive layer and the base layer can be easily obtained.

As an etching apparatus used for dry etching, reactive ion etching (RIE)
Etching apparatus using a method and ECR (Electron Cyclotron Re)
sound) and ICP (Inductively Coupled Plaza)
A dry etching apparatus using a high-density plasma source such as can be used. I
ECCP (Enha) which can obtain a uniform discharge over a wide area compared to a CP etching apparatus.
An etching apparatus of a nccapacitive coupled plasma) mode may be used. In the case of an ECCP mode etching apparatus, the substrate is the 10th.
It is easy to cope with the case of using a substrate after the generation.

Note that in this embodiment, the first low-resistance semiconductor layer 106, the oxide semiconductor layer 108,
The first low-resistance semiconductor layer 110 is stacked and formed by etching.
Although a process for forming a stacked structure of the low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 is described, one embodiment of the disclosed invention is not limited thereto. For example, the first low-resistance semiconductor layer 106 is formed over the conductive layer 102 and the first electrode layer 1
The first low-resistance semiconductor layer 106 and the second low-resistance semiconductor layer 110 are formed by etching the first low-resistance semiconductor layer 106 by etching for forming the first low-resistance semiconductor layer 112 and the oxide. The semiconductor layer 114 and the second low-resistance semiconductor layer 116 may be formed.
In this case, the first low-resistance semiconductor layer 112 may be formed only on the first electrode layer.

Next, a gate insulating layer 118 is formed so as to cover the first low-resistance semiconductor layer 112, the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 (see FIG. 3A).

The gate insulating layer 118 is a single-layer structure of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, or a tantalum oxide film. Or it can be set as a laminated structure. For example, a sputtering method or the like may be used to form a thickness of 10 nm to 500 nm. Here, a silicon oxide film is formed to a thickness of 100 nm by a sputtering method.

Next, a resist mask is formed over the gate insulating layer 118, and the gate insulating layer 118 is selectively etched using the resist mask to form a contact hole 120 (see FIG. 3).
B)). As the etching, either wet etching or dry etching may be used. Note that the resist mask is removed after the etching.

Next, a conductive layer 122 is formed over the gate insulating layer 118 (see FIG. 3C). Conductive layer 1
22 can be formed using a material and a manufacturing method similar to those of the conductive layer 102. Conductive layer 12
The details of 2 can be referred to the description of the conductive layer 102, and thus are omitted here.

Note that in the case where the conductive layer 102 and the conductive layer 122 are formed using the same material, the material and the manufacturing apparatus can be easily shared, which contributes to cost reduction and improvement in throughput. Note that the conductive layer 102 and the conductive layer 122 are not necessarily required to be formed using the same material; therefore, the conductive layer 102 and the conductive layer 122 may be formed using different materials.

Next, a resist mask is formed over the conductive layer 122, and the conductive layer 12 is formed using the resist mask.
2 is selectively etched, so that the second electrode layer 124 and the third electrode layer 126 are formed (see FIG. 3D). As the etching, either wet etching or dry etching may be used. Note that the resist mask is removed after the etching.

The second electrode layer 124 functions as a drain electrode (or a source electrode) of the transistor,
The third electrode layer 126 functions as a gate electrode of the transistor. The second electrode layer 1
The function of 04 is not interpreted as being limited to the designation of the source electrode or the drain electrode.

Thereafter, heat treatment is performed at 200 ° C. to 600 ° C., typically 300 ° C. to 500 ° C. Here, heat treatment is performed at 350 ° C. for one hour in a nitrogen atmosphere. By this heat treatment, the semiconductor characteristics of the oxide semiconductor layer 114 can be improved. The timing of the heat treatment is
There is no particular limitation as long as the oxide semiconductor layer 114 is formed. For example, the gate insulating layer 118
It is also possible to perform the heat treatment before forming.

Through the above steps, a semiconductor device including the stacked transistor 150 can be manufactured (see FIG. 3D).

As shown in this embodiment, an electrode layer and an oxide semiconductor layer are stacked to form the transistor 1.
The channel length (L) can be easily shortened by forming 50 channel formation regions in a direction perpendicular to the substrate surface (not necessarily strictly perpendicular). This gives the channel width (W)
/ Since the channel length (L) can be increased, the current-voltage characteristics of the transistor can be improved. As described above, according to one embodiment of the disclosed invention, a new semiconductor device with high performance can be provided.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a semiconductor device having a structure different from that of the above embodiment will be described with reference to FIGS. Note that the semiconductor device according to this embodiment is common in many parts to the semiconductor device according to the above embodiment. Therefore, in the following, description of overlapping configurations and the like is omitted.

FIG. 4 shows an example of the configuration of the semiconductor device according to this embodiment. 4A is a cross-sectional view, and FIG. 4B is a plan view. FIG. 4A illustrates a cross section taken along line AB of FIG. In the plan view, a part of the configuration is omitted for simplicity.

The semiconductor device shown in FIG. 4 is an example of a modification of the semiconductor device shown in FIG.
For example, a substrate having an insulating surface), a first electrode layer 204 over the substrate 200, a first low-resistance semiconductor layer 212 over the first electrode layer 204, and a first low-resistance semiconductor layer 212 Insulating layer 2
14, the second low-resistance semiconductor layer 216 over the insulating layer 214, and the end of the first electrode layer 204,
An oxide semiconductor layer 220 covering an end portion of the first low-resistance semiconductor layer 212, an end portion of the insulating layer 214, and an end portion of the second low-resistance semiconductor layer 216, and a gate insulating layer covering the oxide semiconductor layer 220 222, a second electrode layer 228 electrically connected to the second low-resistance semiconductor layer 216, a third electrode layer 230 that applies a voltage to the oxide semiconductor layer 220 through the gate insulating layer 222,
(See FIGS. 4A and 4B). Here, the first electrode layer 204 functions as a source electrode (or drain electrode), the second electrode layer 228 functions as a drain electrode (or source electrode), and the third electrode layer 230 functions as a gate electrode. To do.

One of the differences between the structure shown in FIG. 4 and the structure shown in FIG. 1 is the arrangement of the oxide semiconductor layers. On the other hand, the functions of the semiconductor device and the transistor 250 are not significantly changed. For details of the oxide semiconductor layer and the electrode layer, the corresponding portions in FIG. 1 can be referred to.

Next, a method for manufacturing a semiconductor device is described.

First, the conductive layer 202 is formed over the substrate 200 (see FIG. 5A). For details of the substrate 200 and the conductive layer 202, the details of the substrate and the conductive layer in the above embodiment can be referred to. Note that a base layer can be formed over the substrate 200 also in this embodiment mode.

Next, a resist mask is formed over the conductive layer 202, and the conductive layer 20 is formed using the resist mask.
2 is selectively etched to form the first electrode layer 204 (see FIG. 5B). First
For the details of the step of forming the electrode layer 204, the step of forming the first electrode layer in the above embodiment can be referred to. Note that the end portion of the first electrode layer 204 in this embodiment is preferably tapered in order to improve coverage with an oxide semiconductor layer to be formed later.

Next, a first low-resistance semiconductor layer 206, an insulating layer 208, and a second low-resistance semiconductor layer 210 are sequentially stacked to cover the first electrode layer 204 (see FIG. 5C). .

Regarding the step of forming the first low-resistance semiconductor layer 206 (or the second low-resistance semiconductor layer 210), the first low-resistance semiconductor layer 106 (or the second low-resistance semiconductor layer 110) in the above embodiment is used. The formation process can be referred to.

The insulating layer 208 is in contact with an oxide semiconductor layer to be formed later, and thus is preferably formed using a material similar to that of the gate insulating layer. Specifically, for example, a material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or tantalum oxide can be used. Although the insulating layer 208 preferably has a single-layer structure, it may have a stacked structure. In the case where the insulating layer 208 has a stacked structure, there is a possibility that semiconductor characteristics may change depending on the thickness of each layer, a combination of materials, and the like. By utilizing this, it is possible to design so as to obtain desired semiconductor characteristics. In the present embodiment, the insulating layer 20
8, a silicon oxide film having a thickness of 300 nm is formed by sputtering. Note that the thickness of the insulating layer 208 can be, for example, about 5 nm to 500 nm, but is not limited thereto. Since the channel length (L) of the transistor is determined by the thickness of the insulating layer 208 and the taper angle at the time of subsequent etching, the thickness of the insulating layer 208 is appropriately set in consideration of this point. Can do.

Next, a resist mask is formed over the second low-resistance semiconductor layer 210, and the first low-resistance semiconductor layer 206, the insulating layer 208, and the second low-resistance semiconductor layer 210 are formed using the resist mask.
Are selectively etched to form a first low-resistance semiconductor layer 212, an insulating layer 214, and a second low-resistance semiconductor layer 216 (see FIG. 5D). The first low-resistance semiconductor layer 212, the insulating layer 214, and the second low-resistance semiconductor layer 216 are formed in an island shape. Here, in order to improve electrical connection between the first low-resistance semiconductor layer 212 and the second low-resistance semiconductor layer 216, the first low-resistance semiconductor layer 212, the insulating layer 214, and the second low-resistance semiconductor layer 212 are provided. Low resistance semiconductor layer 2
16 is preferably formed to have a tapered shape. Note that the taper angle of the taper shape (the angle formed by the bottom surface and the side surface of the object) can be set based on the required channel length (L) and the thickness of the insulating layer 208.

Note that the first low-resistance semiconductor layer 212 and the second low-resistance semiconductor layer 216 have an effect of realizing ohmic contact with the electrode layer. Therefore, by forming these low resistance semiconductor layers, the problem of improving the characteristics of the semiconductor device can be solved. In the present embodiment, the first low-resistance semiconductor layer 212 and the second low-resistance semiconductor layer 21
Although the case where 6 is formed is described, these are not essential components. That means
The first low-resistance semiconductor layer 212 and the second low-resistance semiconductor layer 216 may be omitted. In particular, the first low-resistance semiconductor layer 212 can be easily omitted.

As a method for etching the first low-resistance semiconductor layer 206, the insulating layer 208, and the second low-resistance semiconductor layer 210, wet etching or dry etching can be used. Then, the resist mask is removed after the etching.

Next, an oxide semiconductor layer 218 is formed so as to cover the first electrode layer 204, the first low-resistance semiconductor layer 212, the insulating layer 214, and the second low-resistance semiconductor layer 216 (see FIG. 6A). ). For the step of forming the oxide semiconductor layer 218, the oxide semiconductor layer 108 in the above embodiment is used.
The formation process can be referred to. Note that in the structure according to this embodiment, the thickness of the oxide semiconductor layer 218 does not affect the channel length (L); therefore, the thickness of the oxide semiconductor layer 218 is preferably appropriate. For example, the thickness may be about 5 nm to 300 nm.

Note that also in this embodiment, the oxide semiconductor layer 218 can contain an impurity. Accordingly, the oxide semiconductor layer 218 can be easily amorphized. In addition, the oxide semiconductor layer 2
18 crystallization can be suppressed. By suppressing crystallization of the oxide semiconductor layer 218, characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved. Needless to say, impurities may be added to the first low-resistance semiconductor layer 206 and the second low-resistance semiconductor layer 210.

Next, a resist mask is formed over the oxide semiconductor layer 218, and the oxide semiconductor layer 218 is selectively etched using the resist mask to form the oxide semiconductor layer 220 (FIG. 6).
(See (B)). Here, the oxide semiconductor layer 220 serves as an active layer of the transistor. As an etching method, wet etching or dry etching can be used.
Then, the resist mask is removed after the etching. For the details of the etching, the above embodiment can be referred to.

Next, the gate insulating layer 222 is formed so as to cover at least the oxide semiconductor layer 220 (see FIG. 6C). For details of the gate insulating layer 222, the details of the gate insulating layer 118 in the above embodiment may be referred to. Here, a silicon oxide film is formed to a thickness of 100 nm by a sputtering method.

Next, a resist mask is formed over the gate insulating layer 222, and the gate insulating layer 222 is selectively etched using the resist mask to form a contact hole 224 (FIG.
D)). As the etching, either wet etching or dry etching may be used. Note that the resist mask is removed after the etching.

Next, a conductive layer 226 is formed over the gate insulating layer 222 (see FIG. 7A). Conductive layer 2
26 can be formed using a material and a manufacturing method similar to those of the conductive layer 202.

Next, a resist mask is formed over the conductive layer 226, and the conductive layer 22 is formed using the resist mask.
6 is selectively etched to form a second electrode layer 228 and a third electrode layer 230 (see FIG. 7B). As the etching, either wet etching or dry etching may be used. Note that the resist mask is removed after the etching.

Thereafter, heat treatment is performed at 200 ° C. to 600 ° C., typically 300 ° C. to 500 ° C. Here, heat treatment is performed at 350 ° C. for one hour in a nitrogen atmosphere. By this heat treatment, the semiconductor characteristics of the oxide semiconductor layer 220 can be improved. The timing of the heat treatment is
There is no particular limitation as long as the oxide semiconductor layer 220 is formed. For example, the gate insulating layer 222
It is also possible to perform the heat treatment before forming.

Through the above steps, a semiconductor device including the stacked transistor 250 can be manufactured (see FIG. 7B).

As shown in this embodiment, an electrode layer and an oxide semiconductor layer are stacked to form the transistor 2.
By forming 50 channel formation regions in a direction having a predetermined angle with respect to the substrate surface,
It becomes easy to shorten the channel length (L). Thus, channel width (W) / channel length (L
) Can be increased, so that the current-voltage characteristics of the transistor can be improved. As described above, according to one embodiment of the disclosed invention, a new semiconductor device with high performance can be provided.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a semiconductor device having a structure different from that in the above embodiment will be described with reference to FIGS. Note that the semiconductor device according to this embodiment is common in many parts to the semiconductor device according to the above embodiment. Therefore, in the following, description of overlapping configurations and the like is omitted.

8 to 11 show examples of the structure of the semiconductor device according to this embodiment. 8A, 9A, 10A, and 11A are cross-sectional views, and FIG. 8B, FIG. 9B, and FIG.
0 (B) and FIG. 11 (B) are plan views. (A) of each drawing represents the cross section in AB of (B). In the plan view, a part of the configuration is omitted for simplicity.

The semiconductor device illustrated in FIG. 8 is an example in which the semiconductor device illustrated in FIG.
For example, a substrate having an insulating surface), the first electrode layer 104 over the substrate 100, the oxide semiconductor layer 114 over the first electrode layer 104, and the gate insulating layer 118 covering the side surfaces of the oxide semiconductor layer 114 A second electrode layer 124 electrically connected to the oxide semiconductor layer 114, a third electrode layer 126 that applies a voltage to the side surface of the oxide semiconductor layer 114 through the gate insulating layer 118,
(See FIGS. 8A and 8B). Here, the first electrode layer 104 functions as a source electrode (or drain electrode), the second electrode layer 124 functions as a drain electrode (or source electrode), and the third electrode layer 126 functions as a gate electrode. To do.

One difference between the configuration shown in FIG. 8 and the configuration shown in FIG. 1 is the presence or absence of the first low-resistance semiconductor layer and the second low-resistance semiconductor layer. That is, the first low-resistance semiconductor layer and the second low-resistance semiconductor layer are not present in the configuration illustrated in FIG.

Here, the first electrode layer 104 and the second electrode layer 124 are preferably formed using a material containing a metal having a high oxygen affinity. By heat treatment or the like in the formation step, oxygen in the region 140 in contact with the first electrode layer 104 of the oxide semiconductor layer 114 (or the region 142 in contact with the second electrode layer 124) is extracted, so that resistance in the region is decreased. Because. Thereby, ohmic contact with the electrode layer can be realized. That is, the problem of improving the characteristics of the semiconductor device can be solved. In addition, as a metal with high oxygen affinity, metals with a small standard electrode potential compared with zinc, such as titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium, can be used, for example. Of course, the metal with high oxygen affinity is not limited to the above materials. Copper or the like can also be used.

The above phenomenon is caused by the fact that a metal with high oxygen affinity extracts oxygen from the oxide semiconductor layer. Therefore, the composition ratio of oxygen in the electrode layer in contact with the oxide semiconductor layer is different from that in other regions. It is considered to be larger than that (that is, in this region, the electrode layer is oxidized)
. In consideration of this, the metal oxide formed in the electrode layer in a region in contact with the oxide semiconductor layer preferably has conductivity. For example, in the case where titanium is used as a metal having a high oxygen affinity, the composition ratio is close to that of one oxide (for example, 0.1% when TiOx is used).
Various treatments may be performed under conditions where an oxide of 5 <x <1.5) is formed. This is because titanium monoxide has conductivity, but titanium dioxide has insulating properties.

The oxide semiconductor layer 114 may contain an insulating impurity. In this case, crystallization of the oxide semiconductor layer 114 can be suppressed. By suppressing crystallization of the oxide semiconductor layer 114, characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved.

Note that the functions of the semiconductor device and the transistor 150 are not significantly changed. For the oxide semiconductor layer, the electrode layer, and other details, the above embodiment can be referred to.

The semiconductor device illustrated in FIG. 9 is an example in which the semiconductor device illustrated in FIG.
For example, a substrate having an insulating surface), a first electrode layer 104 over the substrate 100, a first low-resistance semiconductor layer 112 over the first electrode layer 104, and a first low-resistance semiconductor layer 112 The oxide semiconductor layer 114, the second low-resistance semiconductor layer 116 over the oxide semiconductor layer 114, the gate insulating layer 118 covering the side surface of the oxide semiconductor layer 114, and the second low-resistance semiconductor layer 116 are electrically And a third electrode layer 126 that applies a voltage to the side surface of the oxide semiconductor layer 114 through the gate insulating layer 118 through the gate insulating layer 118 (see FIG. 9 (
A) and FIG. 9B). Here, the first electrode layer 104 functions as a source electrode (or drain electrode), the second electrode layer 124 functions as a drain electrode (or source electrode), and the third electrode layer 126 functions as a gate electrode. To do.

One difference between the configuration shown in FIG. 9 and the configuration shown in FIG. 1 is the planar layout. That is, in the configuration shown in FIG. 9, the third electrode layer 126 and the like have a substantially U-shape. Thereby, the channel width (W) can be expanded. That is, the problem of improving the semiconductor characteristics can be solved. Of course, the planar layout need not be limited to a substantially U-shape. For example, a substantially O-type planar layout can be adopted.

Note that, as a modification of the configuration illustrated in FIG. 9, a configuration in which the first low-resistance semiconductor layer and the second low-resistance semiconductor layer do not exist can be employed.

The oxide semiconductor layer 114 may contain an insulating impurity. In this case, crystallization of the oxide semiconductor layer 114 can be suppressed. By suppressing crystallization of the oxide semiconductor layer 114, characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved.

The semiconductor device illustrated in FIG. 10 is an example in which the semiconductor device illustrated in FIG. 9 is further modified, and includes a substrate 100 (for example, a substrate having an insulating surface), a first electrode layer 104 over the substrate 100, a first A first low-resistance semiconductor layer 112 on the first electrode layer 104, an oxide semiconductor layer 114 on the first low-resistance semiconductor layer 112, a second low-resistance semiconductor layer 116 on the oxide semiconductor layer 114, A conductive layer 182 over the second low-resistance semiconductor layer 116; a gate insulating layer 118 covering a side surface of the oxide semiconductor layer 114; a second electrode layer 124 electrically connected to the conductive layer 182; and a gate insulating layer A third electrode layer 126 for applying a voltage to the side surface of the oxide semiconductor layer 114 via 118;
(See FIGS. 10A and 10B). Where the first
The electrode layer 104 functions as a source electrode (or drain electrode), and the second electrode layer 124 is used.
Functions as a drain electrode (or source electrode), and the third electrode layer 126 functions as a gate electrode. Note that the difference from the semiconductor device shown in FIG. 9 is that the second low-resistance semiconductor layer 116.
The conductive layer 182 is formed thereon. Thereby, the second low-resistance semiconductor layer 116 is formed.
A uniform voltage can be applied to the entire surface.

The semiconductor device shown in FIG. 11 is an example in which the semiconductor device shown in FIG.
(For example, a substrate having an insulating surface), a first electrode layer 204 over the substrate 200, an insulating layer 214 over the first electrode layer 204, an end portion of the first electrode layer 204, and the insulating layer 214 An oxide semiconductor layer 220 covering an end portion of the oxide semiconductor layer, a gate insulating layer 222 covering the oxide semiconductor layer 220, a second electrode layer 228 electrically connected to the oxide semiconductor layer 220, and the gate insulating layer 222 The transistor 260 includes the third electrode layer 230 that applies voltage to the oxide semiconductor layer 220 (see FIGS. 11A and 11B). Here, the first electrode layer 204 functions as a source electrode (or drain electrode), the second electrode layer 228 functions as a drain electrode (or source electrode), and the third electrode layer 230 functions as a gate electrode. To do.

One difference between the configuration shown in FIG. 11 and the configuration shown in FIG. 4 is that the first low-resistance semiconductor layer and the second
The presence or absence of a low-resistance semiconductor layer. That is, the first low-resistance semiconductor layer and the second low-resistance semiconductor layer are not present in the configuration illustrated in FIG.

Here, the first electrode layer 204 and the second electrode layer 228 are preferably formed using a material containing a metal having high oxygen affinity. By heat treatment or the like during the formation process, oxygen in the region 240 in contact with the first electrode layer 204 (or the region 242 in contact with the second electrode layer 228) of the oxide semiconductor layer 220 is extracted, so that resistance in the region is decreased. Because. Thereby, ohmic contact with the electrode layer can be realized. That is, the problem of improving the characteristics of the semiconductor device can be solved. For details, the description of FIG. 8 can be referred to.

The oxide semiconductor layer 220 may contain an insulating impurity. In this case, crystallization of the oxide semiconductor layer 220 can be suppressed. By suppressing crystallization of the oxide semiconductor layer 220, characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved.

Note that the functions of the semiconductor device and the transistor 250 are not significantly changed. For the oxide semiconductor layer, the electrode layer, and other details, the above embodiment can be referred to.

The semiconductor device shown in FIG. 12 is an example in which the semiconductor device shown in FIG.
(For example, a substrate having an insulating surface), a first electrode layer 204 over the substrate 200, a first low-resistance semiconductor layer 212 over the first electrode layer 204, and a first low-resistance semiconductor layer 212 The insulating layer 214, the second low-resistance semiconductor layer 216 on the insulating layer 214, the end of the first electrode layer 204, the end of the first low-resistance semiconductor layer 212, the end of the insulating layer 214, And an oxide semiconductor layer 220 covering an end portion of the second low-resistance semiconductor layer 216, a gate insulating layer 222 covering the oxide semiconductor layer 220, and a second electrically connected to the second low-resistance semiconductor layer 216. A transistor 270 including a third electrode layer 230 that applies a voltage to the oxide semiconductor layer 220 through the gate insulating layer 222 (see FIGS. 12A and 12B). ). Here, the first electrode layer 204 functions as a source electrode (or drain electrode), and the second electrode layer 22
Reference numeral 8 functions as a drain electrode (or source electrode), and the third electrode layer 230 functions as a gate electrode.

One of the differences between the configuration shown in FIG. 12 and the configuration shown in FIG. 4 is the planar layout. That is, in the configuration shown in FIG. 12, the third electrode layer 230 and the like have a substantially U-shape. Thereby, the channel width (W) can be expanded. That is, the problem of improving the semiconductor characteristics can be solved. Of course, the planar layout need not be limited to a substantially U-shape. For example, a substantially O-type planar layout can be adopted.

Note that, as a modification of the configuration illustrated in FIG. 12, a configuration in which the first low-resistance semiconductor layer and the second low-resistance semiconductor layer are not present may be employed.

The oxide semiconductor layer 220 may contain an insulating impurity. In this case, crystallization of the oxide semiconductor layer 220 can be suppressed. By suppressing crystallization of the oxide semiconductor layer 220 , characteristics of the transistor can be stabilized. That is, the problem of improving the reliability of the semiconductor device can be solved.

A semiconductor device illustrated in FIG. 13 is an example in which the semiconductor device illustrated in FIG. 12 is further modified, and includes a substrate 200 (for example, a substrate having an insulating surface), a first electrode layer 204 over the substrate 200,
A first low-resistance semiconductor layer 212 on the first electrode layer 204; an insulating layer 214 on the first low-resistance semiconductor layer 212; a second low-resistance semiconductor layer 216 on the insulating layer 214; A conductive layer 282 on the low-resistance semiconductor layer 216, an end portion of the first electrode layer 204, and the first low-resistance semiconductor layer 21.
2, the end of the insulating layer 214, the end of the second low-resistance semiconductor layer 216, and the conductive layer 28.
2 and the gate insulating layer 22 covering the oxide semiconductor layer 220.
2, a second electrode layer 228 electrically connected to the conductive layer 282, and a third electrode layer 230 that applies voltage to the oxide semiconductor layer 220 through the gate insulating layer 222. (See FIGS. 13A and 13B). Here, the first electrode layer 204 functions as a source electrode (or drain electrode), the second electrode layer 228 functions as a drain electrode (or source electrode), and the third electrode layer 230 functions as a gate electrode. To do. Note that the difference from the semiconductor device illustrated in FIG. 12 is that the conductive layer 282 is formed over the second low-resistance semiconductor layer 216.
Is the point that is formed. Thereby, a uniform voltage can be applied to the entire surface of the second low-resistance semiconductor layer 216.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, the case where a thin film transistor is manufactured and a semiconductor device (display device) having a display function is manufactured using the thin film transistor in a pixel portion or a peripheral circuit portion (a driver circuit or the like) is described. A system-on-panel can be formed by forming part or all of the peripheral circuit portion on the same substrate as the pixel portion.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage. Specifically, an inorganic EL (Ele
ctro Luminescence), organic EL, and the like. Alternatively, a display medium whose contrast is changed by an electric effect, such as electronic ink, may be used.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel. Furthermore, the element substrate constituting the display device includes means for supplying current to the display element in each pixel portion. Specifically, the element substrate may be in a state where a pixel electrode of a display element is formed, or may be in a state before etching after forming a conductive layer to be a pixel electrode.

Hereinafter, in this embodiment, an example of a liquid crystal display device is described. FIG. 14 shows the first substrate 40.
21A is a plan view and a cross-sectional view of a panel in which a thin film transistor 4010, a thin film transistor 4011, and a liquid crystal element 4013 formed over 01 are sealed with a second substrate 4006 and a sealant 4005. FIG. Here, FIGS. 14A1 and 14A2 are plan views,
FIG. 14B corresponds to a cross-sectional view taken along line MN in FIGS. 14A1 and 14A2.

A sealant 4005 is provided so as to surround the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001. In addition, a second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. That is, the pixel portion 4002 and the scan line driver circuit 4004 include the first substrate 4001, the sealant 4005, and the second substrate 4006.
Are sealed together with the liquid crystal layer 4008. In addition, a signal line driver circuit 4003 formed using a single crystal semiconductor or a polycrystalline semiconductor is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. .

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used as appropriate. FIG. 14A1 shows CO
FIG. 14A2 illustrates an example in which the signal line driver circuit 4003 is mounted by the TAB method.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 are as follows:
In FIG. 14B, a thin film transistor 4010 included in the pixel portion 4002 and a thin film transistor 4011 included in the scan line driver circuit 4004 are included.
Is illustrated. The insulating layer 4 is formed over the thin film transistors 4010 and 4011.
020 is provided.

The transistors described in the above embodiments and the like can be applied to the thin film transistors 4010 and 4011. Note that in this embodiment, the thin film transistors 4010 and 4011 are n-channel transistors.

In addition, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4.
006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4
Through 008, a liquid crystal element 4013 is formed. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with an insulating layer 4032 and an insulating layer 4033 that function as alignment films, and the pixel electrode layer 4030 and the counter electrode layer 4031 sandwich the liquid crystal layer 4008 therebetween. It is pinched.

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, plastic, or the like can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) substrate, a PVF (polyvinyl fluoride) film, a polyester film, a polyester film, an acrylic resin film, or the like can be used. Also, thin aluminum
A sheet having a structure sandwiched between F films and polyester films can also be used.

A columnar spacer 4035 is provided in order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. The columnar spacer 4035 can be obtained by selectively etching the insulating film. A spherical spacer may be used instead of the columnar spacer. The counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. For example, the counter electrode layer 4031 and the common potential line can be electrically connected to each other through conductive particles arranged between a pair of substrates. Note that the conductive particles are preferably contained in the sealant 4005.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase due to temperature rise. Since the blue phase appears only in a narrow temperature range, it is preferable to use a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed. Thereby, the temperature range can be improved. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has characteristics such as a short response time of 10 μs to 100 μs, optical isotropy, no alignment treatment, and low viewing angle dependency. Have.

Note that although an example of a transmissive liquid crystal display device is shown in this embodiment mode, the present invention is not limited to this.
It may be a reflective liquid crystal display device or a transflective liquid crystal display device.

In the liquid crystal display device described in this embodiment, an example in which a polarizing plate is provided on the outside (viewing side) of a substrate and a colored layer and an electrode layer used for a display element are provided on the inside is described. It may be provided inside. In addition, the stacked structure of the polarizing plate and the colored layer is not limited to this embodiment mode, and may be set as appropriate depending on the material and manufacturing process conditions of the polarizing plate and the colored layer. Further, a black mask (black matrix) may be provided as a light shielding film.

In this embodiment, a structure in which the thin film transistor obtained in the above embodiment is covered with the insulating layer 4020 is employed to reduce the surface unevenness of the thin film transistor; however, the disclosed invention is not limited thereto. .

As the insulating layer 4020, an organic material having heat resistance such as polyimide, acrylic, polyimide, benzocyclobutene, polyamide, or epoxy can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the insulating layer 4020 may be formed by stacking a plurality of insulating films formed using these materials.

Here, the siloxane-based resin is a Si—O formed using a siloxane-based material as a starting material.
Corresponds to resin containing -Si bond. As a substituent, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. The organic group may have a fluoro group.

There is no particular limitation on the formation method of the insulating layer 4021, and a sputtering method, an SOG method, or the like can be used depending on the material.
Methods such as spin coating, dip coating, spray coating, droplet discharge methods (ink jet method, screen printing, offset printing, etc.), doctor knives, roll coaters, curtain coaters, knife coaters and the like can be used.

The pixel electrode layer 4030 and the counter electrode layer 4031 are formed using indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide,
Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO),
A light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Alternatively, a conductive composition containing a conductive high molecule (also referred to as a conductive polymer) may be used for the pixel electrode layer 4030 and the counter electrode layer 4031. The pixel electrode formed using the conductive composition is
Sheet resistance is 1.0 × 10 ⁴ Ω / sq. Hereinafter, the light transmittance at a wavelength of 550 nm is preferably 70% or more. Further, the resistivity of the conductive polymer contained in the conductive composition is 0.1.
It is preferable that it is below Ω · cm.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

Various signals supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, the pixel portion 4002, and the like are supplied from the FPC 4018.

The connection terminal electrode 4015 is formed using the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed using the same conductive film as the source and drain electrode layers of the thin film transistors 4010 and 4011. ing.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

Note that although FIG. 14 illustrates an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001, this embodiment mode is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or only part of the scan line driver circuit may be separately formed and mounted.

FIG. 15 illustrates an example in which a TFT substrate 2600 is used for a liquid crystal display module corresponding to one embodiment of a semiconductor device.

In FIG. 15, a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealant 2602, and an element layer 2603 including a TFT and the like, a liquid crystal layer 2604 including an alignment film and a liquid crystal layer, a colored layer 2605, a polarizing plate 2606, and the like are provided therebetween. As a result, a display area is formed. The colored layer 2605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. The light source includes a cold cathode tube 2610 and a reflection plate 2611. The circuit board 2612 is connected to the wiring circuit portion 2 of the TFT substrate 2600 by the flexible wiring board 2609.
Accordingly, external circuits such as a control circuit and a power supply circuit are incorporated in the liquid crystal module. Further, a retardation plate may be provided between the polarizing plate and the liquid crystal layer.

Liquid crystal driving methods include TN (Twisted Nematic) mode, IPS (I
n-Plane-Switching) mode, FFS (Fringe Field S)
switching) mode, MVA (Multi-domain Vertical A)
license) mode, PVA (Patterned Vertical Align)
nment), ASM (Axial Symmetrical Aligned Mic)
ro-cell) mode, OCB (Optical Compensated Wire)
fringe) mode, FLC (Ferroelectric Liquid C)
crystal) mode, AFLC (Antiferroelectric Liquid)
Crystal) or the like can be used.

Through the above steps, a high-performance liquid crystal display device can be manufactured. This embodiment can be combined with any of the other embodiments or examples as appropriate.

(Embodiment 6)
In this embodiment, an active matrix electronic paper which is an example of a semiconductor device is described with reference to FIGS. A thin film transistor 650 used for the semiconductor device can be manufactured in a manner similar to that of the transistor described in the above embodiment.

The electronic paper illustrated in FIG. 16 is an example of a paper that uses a twisting ball display system. In the twist ball display system, spherical particles that are separately painted in white and black are arranged between the first electrode layer and the second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer. By letting
In this method, the orientation of spherical particles is controlled for display.

A thin film transistor 650 provided over a substrate 600 is a transistor according to one embodiment of the disclosed invention, in which a semiconductor layer includes a source electrode layer or a drain electrode layer above and a source electrode layer or a drain electrode layer below the semiconductor layer. It has a sandwiched structure. Note that the source electrode layer or the drain electrode layer is formed through the first contact hole formed in the insulating layer.
The electrode layer 660 is electrically connected. The substrate 602 is provided with a second electrode layer 670, and spherical particles 680 having a black region 680 a and a white region 680 b are provided between the first electrode layer 660 and the second electrode layer 670. ing. The periphery of the spherical particle 680 is filled with a filler 682 such as resin (see FIG. 16). In FIG. 16, the first electrode layer 660 corresponds to a pixel electrode, and the second electrode layer 670 corresponds to a common electrode. The second electrode layer 670 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 650.

Instead of the twisting ball, an electrophoretic display element can be used. In that case, for example, a microcapsule having a diameter of about 10 μm to 200 μm in which transparent liquid, positively charged white fine particles, and negatively charged black fine particles are enclosed is used. When an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions to display white or black. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, an auxiliary light is unnecessary, and the display portion can be recognized even in a place where the brightness is not sufficient. Further, even when power is not supplied to the display portion, there is an advantage that an image once displayed can be held.

As described above, high-performance electronic paper can be manufactured by using the disclosed invention. Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 7)
In this embodiment, an example of a light-emitting display device is described as a semiconductor device. As a display element included in the display device, a light-emitting element utilizing electroluminescence is used here. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. The carriers (electrons and holes) recombine to emit light. From such a mechanism,
The light emitting element is called a current excitation type light emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a light emitting layer sandwiched between dielectric layers,
Furthermore, it has a structure in which it is sandwiched between electrodes, and the light emission mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

A structure of the light-emitting element will be described with reference to FIGS. Here, the cross-sectional structure of the pixel will be described with an example in which the driving TFT is an n-type. 17A, FIG. 17B, FIG.
The TFT 701, the TFT 711, and the TFT 721 used for the semiconductor device 7C can be manufactured in a manner similar to that of the transistor described in the above embodiment.

In the light emitting element, at least one of an anode and a cathode is transparent in order to extract light. Here, “transparent” means that the transmittance at least at the emission wavelength is sufficiently high.
As a light extraction method, a thin film transistor and a light emitting element are formed on a substrate, and an upper surface emission method (upper surface extraction method) in which light is extracted from a surface opposite to the substrate, or a lower surface emission in which light is extracted from a surface on the substrate side. There are a method (lower surface extraction method), a double-sided emission method (double-side extraction method) that extracts light from the substrate side and the opposite surface.

A top emission light-emitting element will be described with reference to FIG.

FIG. 17A is a cross-sectional view of a pixel in the case where light emitted from the light-emitting element 702 is emitted to the anode 705 side. Here, the conductive layer 70 electrically connected to the driving TFT 701 is used.
7, a light emitting element 702 is formed, and a light emitting layer 704 and an anode 705 are sequentially stacked on the cathode 703. As the cathode 703, a conductive film that has a small work function and reflects light can be used. For example, it is desirable to form the cathode 703 using a material such as Ca, Al, CaF, MgAg, or AlLi. Note that in the case where the conductive layer 707 has the function of the cathode 703, the cathode 703 can be omitted. The light emitting layer 704 may be configured as a single layer or may be configured such that a plurality of layers are stacked. In the case of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer may be stacked in this order on the cathode 703. Of course, it is not necessary to provide all of these layers. . The anode 705 is formed using a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide (hereinafter referred to as ITO).
Alternatively, a light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added may be used.

A structure in which the light-emitting layer 704 is sandwiched between the cathode 703 and the anode 705 can be referred to as a light-emitting element 702. In the case of the pixel shown in FIG. 17A, light emitted from the light-emitting element 702 is emitted to the anode 705 side as indicated by an arrow.

Next, a bottom emission type light-emitting element will be described with reference to FIG.

FIG. 17B is a cross-sectional view of a pixel in the case where light emitted from the light-emitting element 712 is emitted to the cathode 713 side. Here, the cathode 713 of the light-emitting element 712 is formed over the light-transmitting conductive layer 717 electrically connected to the driving TFT 711, and the light-emitting layer 714 and the anode 715 are sequentially stacked over the cathode 713. ing. Note that in the case where the anode 715 has a light-transmitting property, a light-blocking film 716 may be provided so as to cover the anode 715. The cathode 713 has the structure shown in FIG.
As in the case of A), a conductive material having a small work function can be used. However, the film thickness is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, 20nm
An aluminum film having a thickness of about a thickness can be used as the cathode 713. Light emitting layer 7
Similarly to FIG. 17A, 14 may be configured as a single layer or may be configured such that a plurality of layers are stacked. The anode 715 does not need to transmit light, but may be formed using a light-transmitting conductive material as in FIG. The light-blocking film 716 can be formed using a metal or the like that reflects light, but is not limited thereto. Note that light extraction efficiency can be improved by providing the light-blocking film 716 with a reflection function.

A structure in which the light-emitting layer 714 is sandwiched between the cathode 713 and the anode 715 can be referred to as a light-emitting element 712. In the case of the pixel illustrated in FIG. 17B, light emitted from the light-emitting element 712 is emitted to the cathode 713 side as indicated by arrows.

Next, a dual emission light-emitting element is described with reference to FIG.

FIG. 17C illustrates a light-transmitting conductive layer 727 electrically connected to the driving TFT 721.
A cathode 723 of the light-emitting element 722 is formed on the top, and a light-emitting layer 724 and an anode 725 are sequentially stacked on the cathode 723. As in the case of FIG. 17A, a conductive material having a low work function can be used for the cathode 723. However, the film thickness is set so as to transmit light. For example, an aluminum film having a thickness of 20 nm can be used as the cathode 723. As in FIG. 17A, the light-emitting layer 724 may be a single layer or a stack of a plurality of layers. The anode 725 can be formed using a light-transmitting conductive material as in FIG.

A structure in which the cathode 723, the light-emitting layer 724, and the anode 725 overlap with each other can be referred to as a light-emitting element 722. In the case of the pixel shown in FIG. 17C, light emitted from the light-emitting element 722 is emitted to both the anode 725 side and the cathode 723 side as indicated by arrows.

Note that although an organic EL element is described here as a light-emitting element, an inorganic E element is used as a light-emitting element.
An L element can also be provided. Although an example in which a thin film transistor (driving TFT) that controls driving of the light emitting element and the light emitting element are electrically connected is shown here, the driving T
A configuration in which a current control TFT is connected between the FT and the light emitting element may be employed.

Note that the semiconductor device described in this embodiment is not limited to the structure illustrated in FIG. 17 and can be modified in various ways.

Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of a semiconductor device, will be described with reference to FIGS. 18A and 18B are a plan view and a cross-sectional view of a panel in which a thin film transistor 4509, a thin film transistor 4510, and a light-emitting element 4511 formed over a first substrate 4501 are sealed with a second substrate 4506 and a sealant 4505. Here, FIG. 18A illustrates a plan view, and FIG. 18B corresponds to a cross-sectional view taken along line HI in FIG.

A pixel portion 4502 and signal line driver circuits 4503 a and 450 provided over the first substrate 4501.
3b, a sealant 4505 is provided so as to surround the scan line driver circuit 4504a and the scan line driver circuit 4504b. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuit 4503a, the signal line driver circuit 4503b, the scan line driver circuit 4504a, and the scan line driver circuit 4504b. That is, the pixel portion 4502 and the signal line driver circuit 4503
a, 4503b, the scan line driver circuit 4504a, and the scan line driver circuit 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. Thus, it is preferable to package (enclose) using a protective film (a bonded film, an ultraviolet curable resin film, or the like), a cover material, or the like that has high airtightness and low degassing.

In addition, a pixel portion 4502 provided over the first substrate 4501, a signal line driver circuit 4503a,
The signal line driver circuit 4503b, the scan line driver circuit 4504a, and the scan line driver circuit 4504b are
In FIG. 18B, a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 450 included in the signal line driver circuit 4503a are included.
9 is illustrated.

The transistors described in any of the above embodiments can be applied to the thin film transistors 4509 and 4510. Note that in this embodiment, the thin film transistors 4509 and 4510 are n-channel transistors.

4511 corresponds to a light-emitting element, and a first electrode layer 4517 which is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the second electrode 4512, the electroluminescent layer 4513, and the third electrode layer 4514; however, the structure is limited to the structure described in this embodiment. Not. The above structure can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4511 or the like.

A partition 4520 is formed using an organic resin film, an inorganic insulating film, organic polysiloxane, or the like.
In particular, it is preferable to form an opening on the first electrode layer 4517 using a photosensitive material so that the side wall of the opening becomes an inclined surface having a continuous curvature.

The electroluminescent layer 4513 may be configured as a single layer or may be configured such that a plurality of layers are stacked.

The third electrode layer 4 is used so that oxygen, hydrogen, water, carbon dioxide, or the like does not enter the light emitting element 4511.
A protective film may be formed over 514 and the partition 4520. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, the signal line driver circuit 4503a, the signal line driver circuit 4503b, and the scan line driver circuit 4504 are used.
a, various signals given to the scanning line driver circuit 4504b, the pixel portion 4502, and the like are FPC4
518a and FPC4518b.

In this embodiment, the connection terminal electrode 4515 is a first electrode layer 4517 of the light-emitting element 4511.
The terminal electrode 4516 is formed using the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistor 4509 or the thin film transistor 4510.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518a through an anisotropic conductive film 4519.

The substrate located in the direction in which light is extracted from the light-emitting element 4511 must have a light-transmitting property. Examples of the light-transmitting substrate include a glass plate, a plastic plate, a polyester film, and an acrylic film.

As the filler 4507, an ultraviolet curable resin, a thermosetting resin, or the like can be used in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), EV
A (ethylene vinyl acetate) or the like can be used. In this embodiment mode, an example in which nitrogen is used as a filler is shown.

If necessary, a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a phase difference plate (including a polarizing plate)
(λ / 4 plate, λ / 2 plate), an optical film such as a color filter may be provided. The surface may be subjected to antireflection treatment. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

The signal line driver circuit 4503a, the signal line driver circuit 4503b, the scan line driver circuit 4504a, and the scan line driver circuit 4504b may be formed of a single crystal semiconductor or a polycrystalline semiconductor over a separately prepared substrate. Further, only the signal line driver circuit or part thereof, or only the scanning line driver circuit or only part thereof may be separately formed and mounted, and this embodiment mode is not limited to the structure in FIG.

Through the above steps, a high-performance light-emitting display device (display panel) can be manufactured. Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 8)
The semiconductor device can be applied as electronic paper. Electronic paper can be used for electronic devices in various fields that display information. For example, electronic paper can be applied to an electronic book (electronic book), a poster, an advertisement in a vehicle such as a train, and a display portion of various cards such as a credit card. Examples of electronic devices are illustrated in FIGS.

FIG. 19A illustrates a poster 2631 made of electronic paper. When the advertisement medium is a printed matter of paper, the advertisement is exchanged manually. However, if electronic paper is used, the display of the advertisement can be changed in a short time. In addition, a stable image can be obtained without losing the display. Note that the poster may be configured to transmit and receive information wirelessly.

FIG. 19B illustrates an advertisement 2632 in a vehicle such as a train. When the advertisement medium is a printed matter of paper, the advertisement is exchanged manually. However, if electronic paper is used, the display of the advertisement can be changed in a short time without much labor. In addition, a stable image can be obtained without distorting the display. Note that the poster may be configured to transmit and receive information wirelessly.

FIG. 20 illustrates an example of an e-book reader 2700. For example, an e-book 2700
The housing 2701 is composed of two housings 2701 and 2703. The housing 2701 and the housing 2703 are integrated with a shaft portion 2711 and can be opened / closed using the shaft portion 2711 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, a sentence can be displayed on the right display unit (display unit 2705 in FIG. 20) and an image can be displayed on the left display unit (display unit 2707 in FIG. 20). .

FIG. 20 illustrates an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2
701 includes a power source 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation keys 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, external connection terminals (earphone terminal, USB terminal, or AC adapter and USB
A terminal that can be connected to various cables such as a cable), a recording medium insertion portion, and the like. Further, the e-book reader 2700 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 2700 may have a configuration capable of transmitting and receiving information wirelessly. By radio
It is also possible to purchase desired book data from an electronic book server and download it.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 9)
The semiconductor device can be applied to various electronic devices (including game machines). As an electronic device, for example, a television device (also referred to as a television or a television receiver),
Large game machines such as monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones and mobile phone devices), portable game machines, portable information terminals, sound playback devices, and pachinko machines Etc.

FIG. 21A illustrates an example of a television device 9600. Television device 96
00 includes a display portion 9603 incorporated in a housing 9601. The display portion 9703 can display an image. Further, here, a housing 9601 is provided by a stand 9605.
The structure which supported is shown.

The television device 9600 can be operated with an operation switch provided in the housing 9601 or a separate remote controller 9610. Channels and volume can be operated with operation keys 9609 provided in the remote controller 9610, and an image displayed on the display portion 9603 can be operated. The remote controller 9610 may be provided with a display portion 9607 for displaying information output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. The receiver can receive general TV broadcasts, and can be connected one-way (sender to receiver) or two-way (sender to receiver) by connecting to a priority or wireless communication network via a modem. It is also possible to perform information communication between each other or between recipients).

FIG. 21B illustrates an example of a digital photo frame 9700. For example, a digital photo frame 9700 has a display portion 9703 incorporated in a housing 9701. The display portion 9703 can display various images. For example, by displaying image data captured by a digital camera or the like, the display portion 9703 can function in the same manner as a normal photo frame.

Note that the digital photo frame 9700 includes an operation unit, an external connection terminal (USB terminal, US
A terminal that can be connected to various cables such as a B cable), a recording medium insertion portion, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory that stores image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

Further, the digital photo frame 9700 may be configured to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

FIG. 22A illustrates a portable game machine which includes two housings, a housing 9881 and a housing 9891, which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine shown in FIG.
6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9
888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature,
Including a function of measuring chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared), microphone 9889) and the like. Needless to say, the structure of the portable game machine is not limited to the above, and any structure including at least a semiconductor device may be used, and any other attached facilities may be provided as appropriate. The portable game machine shown in FIG. 22A shares information by reading a program or data recorded in a recording medium and displaying the program or data on a display unit, or by performing wireless communication with another portable game machine. It has a function. Note that the function of the portable game machine illustrated in FIG. 22A is not limited to this, and the portable game machine can have a variety of functions.

FIG. 22B illustrates an example of a slot machine 9900 which is a large-sized game machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 includes operation means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Needless to say, the configuration of the slot machine 9900 is not limited to that described above, and may be any configuration as long as it includes at least a semiconductor device.

FIG. 23A illustrates an example of a mobile phone 1000. The mobile phone 1000 includes a display unit 1002 incorporated in a housing 1001, an operation button 1003, an external connection port 10
04, a speaker 1005, a microphone 1006, and the like.

Information can be input to the cellular phone 1000 illustrated in FIG. 23A by touching the display portion 1002 with a finger or the like. In addition, operations such as making a call or typing an e-mail can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying images. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

For example, when making a phone call or creating an e-mail, the display unit 1002 may be set to a character input mode mainly for inputting characters and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display portion 1002.

Further, by providing a detection device having a sensor for detecting the inclination, such as a gyroscope or an acceleration sensor, in the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 is determined, and the screen display of the display unit 1002 Can be switched automatically.

Further, the screen mode is switched by touching the display portion 1002 or operating the operation button 1003 of the housing 1001. Further, switching can be performed depending on the type of image displayed on the display portion 1002. For example, if the image signal to be displayed on the display unit is moving image data, the mode is switched to the display mode.

Further, in the input mode, when a signal detected by the optical sensor of the display unit 1002 is detected and there is no input by a touch operation on the display unit 1002, the screen mode is switched from the input mode to the display mode. You may control.

The display portion 1002 can also function as an image sensor. For example, the display unit 10
By touching 02 with a palm or a finger, an image of a palm print, a fingerprint, or the like can be captured to perform personal authentication. In addition, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

FIG. 23B is also an example of a mobile phone. A mobile phone in FIG. 23B includes a housing 9411, a display device 9410 including a display portion 9412 and operation buttons 9413, a housing 9401, a scan button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and And a communication device 9400 including a light emitting portion 9406 that emits light when an incoming call is received. A display device 9410 having a display function can be attached to and detached from the communication device 9400 having a telephone function in two directions indicated by arrows. Therefore, the short axes of the display device 9410 and the communication device 9400 can be attached, or the long axes of the display device 9410 and the communication device 9400 can be attached. When only the display function is required, the display device 9410 can be detached from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each have a rechargeable battery.

Note that this embodiment can be combined with any of the other embodiments as appropriate.

100 substrate 102 conductive layer 104 electrode layer 106 low resistance semiconductor layer 108 oxide semiconductor layer 110 low resistance semiconductor layer 112 low resistance semiconductor layer 114 oxide semiconductor layer 116 low resistance semiconductor layer 118 gate insulating layer 120 contact hole 122 conductive layer 124 electrode Layer 126 electrode layer 140 region 142 region 150 transistor 160 transistor 170 transistor 180 transistor 182 conductive layer 200 substrate 202 conductive layer 204 electrode layer 206 low resistance semiconductor layer 208 insulating layer 210 low resistance semiconductor layer 212 low resistance semiconductor layer 214 insulating layer 216 low Resistive semiconductor layer 218 Oxide semiconductor layer 220 Oxide semiconductor layer 222 Gate insulating layer 224 Contact hole 226 Conductive layer 228 Electrode layer 230 Electrode layer 240 Region 242 Region 250 Transistor 260 Transistor Star 270 transistor 280 transistor 282 conductive layer 600 substrate 602 substrate 650 thin film transistor 660 electrode layer 670 electrode layer 680 spherical particles 680a black area 680b white region 682 filler 701 TFT
702 Light-emitting element 703 Cathode 704 Light-emitting layer 705 Anode 707 Conductive layer 711 TFT
712 Light-emitting element 713 Cathode 714 Light-emitting layer 715 Anode 716 Light-shielding film 717 Conductive layer 721 TFT
722 Light-emitting element 723 Cathode 724 Light-emitting layer 725 Anode 727 Conductive layer 1000 Mobile phone 1001 Case 1002 Display unit 1003 Operation button 1004 External connection port 1005 Speaker 1006 Microphone 2600 TFT substrate 2601 Counter substrate 2602 Sealing material 2603 Element layer 2604 Liquid crystal layer 2605 Coloring Layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit unit 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflecting plate 2612 Circuit board 2613 Diffusion plate 2631 Poster 2632 In-car advertisement 2700 Electronic book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Axis Portion 2721 power source 2723 operation key 2725 speaker 4001 substrate 4002 pixel portion 4003 signal line driver circuit 4004 scanning line driver circuit 4005 seal 4006 substrate 4008 liquid crystal layer 4010 thin film transistors 4011 TFT 4013 liquid crystal element 4015 connection terminal electrode 4016 terminal electrodes 4018 FPC
4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4501 Substrate 4502 Pixel portion 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scan line driver circuit 4504b Scanning Line driver circuit 4505 Sealant 4506 Substrate 4507 Filler 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electrode 4513 Electroluminescent layer 4514 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC
4518b FPC
4519 Anisotropic conductive film 4520 Bulkhead 9400 Communication device 9401 Case 9402 Scan button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting portion 9410 Display device 9411 Case 9412 Display portion 9413 Operation button 9600 Television device 9601 Case 9603 Display portion 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote controller 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 Display unit 9883 Display unit 9984 Speaker unit 9985 Operation key 9886 Recording medium insertion unit 9886 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Case 9893 Connection portion 9900 Slot machine 9901 Case 9903 Display portion

Claims (2)

A substrate,
A first electrode layer on the substrate;
An oxide semiconductor layer provided over the first electrode layer and the substrate; and an insulating layer covering the oxide semiconductor layer;
A second electrode layer on the insulating layer;
A third electrode layer covering a side surface of the oxide semiconductor layer with the insulating layer interposed therebetween;
The first electrode layer is electrically connected to the oxide semiconductor layer;
The second electrode layer is electrically connected to the oxide semiconductor layer through an opening of the insulating layer;
The first electrode layer functions as one of a source electrode and a drain electrode;
The second electrode layer functions as the other of the source electrode and the drain electrode;
The third electrode layer functions as a gate electrode;
When viewed from above, the first electrode layer has a U shape surrounding a part of the second electrode layer,
The first electrode layer or the second electrode layer is an alloy including any one of aluminum, tungsten, titanium, tantalum, molybdenum, nickel, platinum, copper, gold, silver, manganese, and neodymium. A semiconductor device. A substrate,
A first electrode layer on the substrate;
A first insulating layer on the first electrode layer;
An oxide semiconductor layer having a region covering a side surface of the first insulating layer and a side surface of the first electrode layer;
A second insulating layer covering the upper surface of the first insulating layer and the oxide semiconductor layer;
A second electrode layer on the second insulating layer;
A third electrode layer overlapping the oxide semiconductor layer with the second insulating layer interposed therebetween,
The first electrode layer is electrically connected to the oxide semiconductor layer;
The second electrode layer is electrically connected to the oxide semiconductor layer through an opening of the second insulating layer;
The first electrode layer functions as one of a source electrode and a drain electrode;
The second electrode layer functions as the other of the source electrode and the drain electrode;
The third electrode layer functions as a gate electrode;
When viewed from above, the third electrode layer has a U shape surrounding a part of the second electrode layer,
The first electrode layer or the second electrode layer is an alloy including any one of aluminum, tungsten, titanium, tantalum, molybdenum, nickel, platinum, copper, gold, silver, manganese, and neodymium. A semiconductor device.