JP2020073020A - Game machine - Google Patents

Abstract

To increase a free capacity of a ROM of a main control circuit, and use an increased free space of the ROM to enhance game properties.SOLUTION: A game machine executes, in count processing of a timer value of a software timer of two bytes, a predetermined update instruction with which an update instruction, a lower limit determination instruction, and a determination branch instruction can be executed with one instruction, so as to compare the current timer value and a lower limit value; and, if the current timer value is more than the lower limit value, subtracts the timer value for updating, and, if the current timer value is equal to or less than the lower limit value, holds the timer value at the lower limit value and then updates an update start address by two bytes. Interruption processing means executes evacuation processing of a register, executes count processing of the timer value after the execution of the evacuation processing, executes external signal output control processing after the execution of the count processing of the timer value, executes return processing of the register after the execution of the external signal output control processing, and ends the processing immediately after the execution of the return processing.SELECTED DRAWING: Figure 165

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called a pachi-slot provided with a plurality of reels provided with a plurality of symbols on each surface, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as "start operation") after a game medium such as a medal or coin has been inserted into the game machine, and the rotation of all reels is detected. Output a signal requesting start. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting stop of rotation of the corresponding reel. To do. The stepping motor transmits the driving force to the corresponding reel. In addition, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

  In such a gaming machine, when a start operation is detected, a lottery process using random numbers on the program (hereinafter referred to as “internal lottery process”) is performed, and the result of the lottery (hereinafter referred to as “internal winning combination”). ") And the timing of the stop operation, the rotation of the reel is stopped. Then, when the rotation of all the reels is stopped and the symbol combination (display combination) relating to the establishment of the winning is displayed, the privilege corresponding to the symbol combination is given to the player. As an example of a privilege given to a player, a payout of a game medium (medal, etc.) and a re-play (hereinafter also referred to as “replay”) operation in which the internal lottery process is performed again without consuming the game medium The operation of a bonus game, which increases the chances of paying out game media, can be cited.

  Further, conventionally, in the gaming machine having the above configuration, a function of navigating the establishment of a specific small winning combination (a winning combination relating to the payout of a game medium) by a lamp or the like, that is, an assist time (hereinafter referred to as “AT”) function A gaming machine equipped with it is being developed. Also, conventionally, when a specific symbol combination is displayed, a function in which a gaming state in which a winning probability of replay is higher than a normal time is activated, that is, a gaming machine having a function of a replay time (hereinafter, referred to as “RT”) is also developed. Has been done. Further, conventionally, a pachi-slot having a function of assist replay time (hereinafter, referred to as “ART”) in which AT and RT are simultaneously operated has been developed.

  The above-mentioned gaming machine is usually a main control in which a circuit (main control circuit) for controlling main gaming operations of the gaming machine such as determination of internal winning combination, rotation and stop of each reel, and determination of winning or not is mounted. A board and a sub-control board on which a circuit (sub-control circuit) for controlling a rendering operation such as image display is mounted. The game operation is controlled by a CPU (Central Processing Unit) mounted on the main control circuit. At this time, under the control of the CPU, the programs and various table data stored in the ROM (Read Only Memory) of the main control circuit are expanded in the RAM (Random Access Memory) of the main control circuit, and the processing relating to various game operations is executed. To be done.

  Further, conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine controlled by a timer subtraction process by software (for example, refer to Patent Document 1).

JP, 2004-041261, A

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above problems, and an object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to increase the free space of the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of enhancing the game playability by utilizing the free area of the ROM for the increased capacity.

  In order to solve the above problems, the present invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, a main CPU 101 described later) for performing arithmetic processing for controlling the game operation,
First storage means (for example, a main ROM 102 described later) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103 described later) in which information necessary for executing the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing unit has an interrupt processing unit (for example, an interrupt processing described later) that executes a process at a fixed time period,
The arithmetic processing means,
In the counting process of the timer value of the 2-byte soft timer (for example, the timer updating process described later),
By executing a predetermined update command (for example, a “DCPWLD” command described later) capable of executing the update command, the lower limit judgment command and the judgment branch command with one command, the current timer value of the soft timer and the timer value. When the current timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and the current timer value of the soft timer is less than or equal to the lower limit value. If there is, hold the timer value of the soft timer at the lower limit,
After that, the update start address of the soft timer in the second storage means is updated by 2 bytes,
The counting process of the timer value executed by the arithmetic processing unit is one of the processes executed by the interrupt processing unit,
The interrupt processing means first executes the saving process of the register, executes the counting process of the timer value after executing the saving process, and outputs the signal to the outside of the gaming machine after executing the counting process of the timer value. An external signal output control process for generating a register is executed, the register return process is executed after the external signal output control process is executed, and the process is terminated immediately after the register return process is executed. Amusement machine.

Further, in the gaming machine of the present invention, the first storage means has a first game area in which data relating to the progress of the game is stored, and a first non-regular area in which data not related to the progress of the game is stored. And have,
The second storage means has a second game area for storing data relating to the progress of the game and a second non-regular area for storing data not involved in the progress of the game.
The interrupt processing means is stored in the first game area and executes processing by using the second game area, but the external signal output control processing is performed in the first non-regulated area. It may be stored and executed using the second non-specified area.

  According to the gaming machine of the present invention having the above-described configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the free space of the ROM for the increased capacity. You can improve the game play by using.

It is a figure for explaining the functional flow of the game machine in one embodiment of the present invention. It is a perspective view showing the appearance structure of the game machine in one embodiment of the present invention. It is a figure showing the internal structure of the game machine in one embodiment of the present invention. It is a figure showing the internal structure of the game machine in one embodiment of the present invention. It is a figure which shows schematic structure of the various display screens displayed on the sub-display apparatus of one Embodiment of this invention. It is a figure which shows the example of a transition of the display screen of the sub display apparatus in one embodiment of this invention. It is a block diagram showing the whole circuit composition with which the game machine of one embodiment of the present invention is provided. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit in one Embodiment of this invention. It is a block diagram of various registers which the main CPU has in one embodiment of the present invention. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the bonus state and non-bonus state of the pachi-slot in one embodiment of this invention. It is a figure which shows the transition flow of the game state between the ART game state of pachi-slot, the non-ART game state, and the bonus state in one embodiment of this invention. It is a figure showing an example of a symbol arrangement table in one embodiment of the present invention. It is a figure showing an example of an internal lottery table in one embodiment of the present invention. It is a figure showing an example of an internal lottery table in one embodiment of the present invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one embodiment of this invention. It is a figure showing a correspondence of an internal winning combination and a stop symbol combination in one embodiment of the present invention. It is a figure showing a correspondence of an internal winning combination and a stop symbol combination in one embodiment of the present invention. It is a figure which shows an example of the reel stop initialization table in one Embodiment of this invention. It is a figure which shows an example of the attraction-in priority table in one Embodiment of this invention. It is a figure showing composition (the 1) of a hit demand flag storage area and a winning operation flag storage area in one embodiment of the present invention. It is a figure showing composition (the 2) of a hit demand flag storage area and a winning operation flag storage area in one embodiment of the present invention. It is a figure showing (3) of a hit demand flag storage area and a winning operation flag storage area in one embodiment of the present invention. It is a figure which shows the structure of the internal carryover combination storing area in one Embodiment of this invention. It is a figure showing composition of a game state flag storage area in one embodiment of the present invention. It is a figure showing composition of an operation stop button storage area in one embodiment of the present invention. It is a figure which shows the structure of the pressing order storage area in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one embodiment of this invention. It is a figure showing a correspondence table (the 1) of an internal winning combination and a sub flag in one embodiment of the present invention. It is a figure which shows the correspondence table (the 2) of an internal winning combination and a sub flag in one Embodiment of this invention. It is a figure for demonstrating the alerting | reporting operation | movement when the sub-flag EX "3 consecutive chili lip" or "reach eye lip" is won in the gaming machine of one embodiment of the present invention. It is a figure for explaining the flow of the game in the general game state in one embodiment of the present invention. It is a figure which shows an example of the normal medium-high probability random determination table in one embodiment of this invention. It is a figure showing an example of a CZ lottery table in one embodiment of the present invention. It is a figure which shows an example of the CZ1 middle mode up lottery table in one embodiment of this invention. It is a figure showing an example of a CZ2 middle point lottery table in one embodiment of the present invention. It is a figure which shows an example of ART lottery table in CZ (for CZ1, CZ2) in one embodiment of this invention. It is a figure which shows an example of the ART random determination table in CZ (for CZ3) in one embodiment of this invention. It is a figure for explaining the flow of the game in normal ART in one embodiment of the present invention. It is a figure which shows an example of the flag conversion lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium-high probability random determination table in one embodiment of this invention. It is a figure which shows an example of CT random determination table in ART in one Embodiment of this invention. It is a figure which shows an example of the normal lottery additional drawing lottery table in one embodiment of this invention. It is a figure for explaining the flow of the game in the CT state in one embodiment of the present invention. It is a figure which shows an example of the CT random determination table random determination table in one embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table during CT in one Embodiment of this invention. It is a figure which shows an example of the extra lottery table during CT in one embodiment of this invention. It is a figure which shows an example of the lottery table on which the number of sets in CT is added in one embodiment of the present invention. It is a figure for explaining the flow of the game in the bonus state in one embodiment of the present invention. It is a figure showing an example of the bonus classification lottery table in one embodiment of the present invention. It is a figure which shows an example of the bonus lot ART game number addition lottery table in one embodiment of this invention. It is a figure showing an example of a bonus lot end CT lottery table in one embodiment of the present invention. It is a diagram for explaining the flow of the game (other) during the general game state in one embodiment of the present invention. It is a figure showing an example of a flag conversion lottery table during non-ART in one embodiment of the present invention. It is a figure which shows the correspondence of the main side navigation data and the sub side navigation data in one Embodiment of this invention. It is a flow chart which shows an example of processing at the time of power-on (reset interruption) performed by the main control circuit of the game machine in one embodiment of the present invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the process at the time of power activation in one Embodiment of this invention. It is a flow chart which shows an example of game return processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of game return processing in one embodiment of the present invention. It is a flow chart which shows an example of the setting change confirmation processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. 7 is a flowchart showing an example of a setting change command generation / storage process according to the embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of a setting change command generation storage process in one Embodiment of this invention. It is a flow chart which shows an example of communication data storage processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of communication data storage processing in one embodiment of the present invention. It is a flow chart which shows an example of communication data pointer update processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of communication data pointer update processing in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of power failure (external) in one embodiment of the present invention. It is a flow chart which shows an example of checksum generation processing (out of regulation) in one embodiment of the present invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to the embodiment of the present invention, and a stack pointer update operation and a data read operation to a register executed in the checksum generation process FIG. It is a flow chart which shows an example of the sum check processing (out of regulation) in one embodiment of the present invention. It is a flow chart which shows an example of the sum check processing (out of regulation) in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the sum check process in one Embodiment of this invention. It is a flow chart which shows an example of main processing (main operation processing) performed by a main control circuit of a game machine in one embodiment of the present invention. It is a flow chart which shows an example of medal acceptance and start check processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the medal acceptance / start check process in one embodiment of the present invention. It is a flow chart which shows an example of medal insertion processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of medal insertion processing in one embodiment of the present invention. It is a flow chart which shows an example of medal insertion check processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. 6 is a flowchart showing an example of error processing according to the embodiment of the present invention. It is a figure which shows an example of a structure of the error table actually referred on the source program of the error process in one Embodiment of this invention. It is a flow chart which shows an example of random number acquisition processing in one embodiment of the present invention. It is a flow chart which shows an example of internal lottery processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of internal lottery processing in one embodiment of the present invention. It is a figure which shows an example of a structure of the internal lottery table (for general games) actually referred on the source program of the internal lottery process in one embodiment of this invention. It is a figure which shows an example of a structure of the lottery value selection table classified by RT state actually referred on the source program of the internal lottery process in one embodiment of this invention. An internal lottery value table selection table, a 1-byte internal lottery value table, a 2-byte internal lottery value table, and a 1-byte internal lottery value that are actually referred to on the source program of the internal lottery process according to the embodiment of the present invention. It is a figure which shows an example of a structure of a table and an internal lottery value table classified by 2 bytes. It is a flow chart which shows an example of design setting processing in one embodiment of the present invention. It is a figure showing a correspondence of a special prize (bonus) winning number and a small winning combination number, and an internal winning combination in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the symbol setting process in one embodiment of this invention. It is a figure which shows an example of a structure of the hit request flag table actually referred on the source program of the symbol setting process in one embodiment of this invention. 6 is a flowchart illustrating an example of compressed data storage processing according to an embodiment of the present invention. It is a flow chart which shows the example of the 2nd interface board control processing (outside regulation) in one embodiment of the present invention. It is a flow chart which shows the example of the 2nd interface board output processing in one embodiment of the present invention. It is a flow chart which shows an example of control processing according to a state in one embodiment of the present invention. It is a flow chart which shows an example of subflag conversion processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the sub-flag conversion process in one Embodiment of this invention. It is a figure which shows an example of a structure of the sub flag conversion table actually referred on the source program of the sub flag conversion process in one embodiment of this invention. It is a flow chart which shows an example of navigation set processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the navigation set process in one Embodiment of this invention. It is a figure which shows an example of a structure of the navigation data table actually referred on the source program of the navigation set process in one embodiment of this invention. It is a flow chart which shows an example of flag conversion processing in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of starting during normal in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of CZ start in one embodiment of the present invention. It is a flow chart which shows an example of processing during CZ1 (CZ2) in one embodiment of the present invention. It is a flow chart which shows an example of processing during CZ1 (CZ2) in one embodiment of the present invention. It is a flow chart which shows an example of processing during CZ3 in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of start during normal ART in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of start during CT in one embodiment of the present invention. It is a flow chart which shows an example of CT lottery processing during CT in one embodiment of the present invention. It is a flow chart which shows an example of table data acquisition processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of table data acquisition processing in one embodiment of the present invention. It is a figure which shows an example of a structure of the CT lottery table in CT actually referred on the source program of the table data acquisition process in one Embodiment of this invention. It is a flow chart which shows an example of 1-byte lottery processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the 1-byte lottery process in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of BB start in one embodiment of the present invention. It is a flow chart which shows an example of a pull-in priority storage processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the attraction-in priority storage process in one embodiment of this invention. It is a flow chart which shows an example of design code acquisition processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of design code acquisition processing in one embodiment of the present invention. On the source program of the symbol code acquisition process in the embodiment of the present invention, the first time cylinder (left reel) symbol arrangement table that is actually referred to, and the symbol reference that is referred to when the first case symbol arrangement table is set It is a figure showing an example of composition of a winning operation table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the second time cylinder (middle reel) symbol arrangement table that is actually referred to, and the symbol reference that is referred to when the second case symbol arrangement table is set It is a figure showing an example of composition of a winning operation table. On the source program of the symbol code acquisition processing in the embodiment of the present invention, the third time body (right reel) symbol arrangement table that is actually referred to, and the symbol reference that is referred to when the third body symbol arrangement table is set It is a figure showing an example of composition of a winning operation table. It is a flow chart which shows an example of the logical product operation processing in one embodiment of the present invention. It is a flowchart which shows the example of the attraction-in priority acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the attraction-in priority acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the acquisition priority acquisition process in one Embodiment of this invention. It is a figure which shows an example of a structure of the attraction priority table actually referred on the source program of attraction priority acquisition processing in one embodiment of this invention. It is a flow chart which shows an example of reel stop control processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of reel stop control processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of reel stop control processing in one embodiment of the present invention. It is a flow chart which shows an example of reel stop possible signal OFF processing (outside regulation) in one embodiment of the present invention. It is a flow chart which shows an example of reel stop possible signal ON processing (outside regulation) in one embodiment of the present invention. It is a flow chart which shows an example of non-specified port output processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the non-specified port output process in one embodiment of this invention. It is a flow chart which shows an example of winning a prize search processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of winning a prize search processing in one embodiment of the present invention. It is a figure which shows an example of a structure of the payout amount data table which is actually referred to on the source program of the winning a prize search processing in one embodiment of the present invention. It is a flow chart which shows an example of illegal hit check processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of illegal hit check processing in one embodiment of the present invention. It is a flow chart which shows an example of winning check and medal payout processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of a prize check and medal payout process in one embodiment of the present invention. It is a flow chart which shows an example of medal payout number check processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of medal payout number check processing in one embodiment of the present invention. It is a flow chart which shows an example of BB check processing in one embodiment of the present invention. It is a flow chart which shows an example of RT check processing in one embodiment of the present invention. It is a flow chart which shows an example of RT check processing in one embodiment of the present invention. It is a flow chart which shows an example of processing at the end of CZ / ART in one embodiment of the present invention. It is the flowchart which shows the example of the interruption processing which is executed by the main control circuit of the game machine in one execution form of this invention. It is a flow chart which shows an example of 7 segment LED drive processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of 7 segment LED drive processing in one Embodiment of this invention. It is a flow chart which shows an example of 7 segment display data generation processing in one embodiment of the present invention. It is a figure showing an example of a source program for performing various processings in a flow chart of 7 segment display data generation processing in one embodiment of the present invention. It is a figure which shows an example of a structure of the 7-segment cathode table actually referred on the source program of the 7-segment display data generation process in one Embodiment of this invention. It is a flow chart which shows an example of timer update processing in one embodiment of the present invention. It is a figure which shows an example of the source program for performing various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flow chart which shows an example of trial shooting test signal control processing (out of regulation) in one embodiment of the present invention. It is a flow chart which shows an example of rotation cylinder braking signal generation processing in one embodiment of the present invention. It is a flow chart which shows an example of special signal control processing in one embodiment of the present invention. It is a flow chart which shows an example of conditional device signal control processing in one embodiment of the present invention. It is a flow chart which shows an example of conditional device signal control processing in one embodiment of the present invention. It is a flow chart which shows an example of the sub side navigation control processing performed by the sub control circuit of the game machine in one embodiment of the present invention. It is a flow chart which shows an example of player registration processing in one embodiment of the present invention. It is a flow chart which shows an example of history management processing in one embodiment of the present invention. It is a figure which shows the flow of the game during CT precursor in the modification 1 of this invention. It is a figure which shows the correspondence of an internal winning combination and the stop symbol combination in the modification 2 of this invention. It is a figure which shows the correspondence of the main side navigation data and the sub side navigation data in the modification 3 of this invention. It is a figure which shows the correspondence of the pushing order and the lock state in the modification 5 of this invention.

  A pachi-slot is taken as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In the present embodiment, a pachi-slot having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachi-slot will be described with reference to FIG. In the pachi-slot of the present embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as the game medium.

  When a player inserts a medal into a pachi-slot and operates a start lever, one value (hereinafter, referred to as a random number value) is extracted from random numbers in a predetermined numerical value range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is one of various processing means (processing functions) included in the main control circuit described later. By the determination of the internal winning combination, the combination of symbols that is allowed to be displayed along the activated line (winning determination line) described later is determined. The types of symbol combinations include those related to "winning", in which benefits such as payout of medals, operation of replay (replay), and operation of bonus are given to the player, and other so-called "off" The related items are provided. In the following, the winning combination relating to the payout of medals is referred to as a "small winning combination", and the winning combination relating to the operation of the replay (replay) is referred to as a "replay winning combination". In addition, a winning combination (bonus game) is also referred to as a “bonus winning combination”.

  Further, when the start lever is operated, the plurality of reels are rotated. After that, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means controls the rotation of the corresponding reel based on the internal winning combination and the timing at which the stop button is pressed. To do. The reel stop control means is one of various processing means (processing functions) included in a main control circuit described later.

  In the pachi-slot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the “number of sliding pieces”. Then, in the present embodiment, when the prescribed period is 190 msec, the maximum number of sliding pieces (maximum sliding piece number) is set to four symbols.

  The reel stop control means, when the internal winning combination permitting the combination display of the symbols related to the winning is determined, the combination of the symbols is normally on the activated line within a prescribed time of 190 msec (for 4 symbols). The rotation of the reel is stopped so as to be displayed as much as possible. Further, the reel stop control means uses the specified time to stop the rotation of the reel so that a combination of symbols which is not permitted to be displayed by the internal winning combination is not displayed along the activated line.

  In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the activated line is related to winning. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, when the combination of displayed symbols is determined to be related to winning by the winning determination means, a bonus such as payout of medals is given to the player. In the pachi-slot, the above-described series of flows is performed as one game (unit game).

  In addition, in the pachi-slot, in the sequence of the game operation described above, various effects are displayed by using the display of images by a display device, the output of light by various lamps, the output of sound by the speaker, or a combination of these. Is done.

  Specifically, when the start lever is operated, a random number value for effect is extracted in addition to the random number value used for determining the internal winning combination described above. When the random number value for effect is extracted, the effect content determination means randomly determines the effect to be executed this time from among a plurality of types of effect content associated with the internal winning combination. The effect content determination means is one of various processing means (processing functions) included in the sub-control circuit described later.

  Next, when the effect content is determined by the effect content determining means, the effect executing means responds by interlocking with various triggers such as when the reel starts rotating, when each reel stops rotating, and when a prize is determined. To execute. In this way, in the pachi-slot, for example, by executing the effect contents associated with the internal winning combination, an opportunity to know or predict the determined internal winning combination (in other words, a combination of symbols to be aimed) is a game. It is provided to the player and the interest of the player can be improved.

<Structure of pachi-slot>
Next, the structure of a pachi-slot according to an embodiment of the present invention will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing an external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachi-slot 1 includes an exterior body (game machine body) 2. The exterior body 2 has a cabinet 2a that accommodates reels, circuit boards, and the like, and a front door 2b that is attached so that the opening of the cabinet 2a can be opened and closed.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display row) are arranged side by side in a row. Hereinafter, the reels 3L, 3C, 3R (main reels) are also referred to as the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. Each of the reels 3L, 3C, 3R has a reel body formed in a cylindrical shape, and a translucent sheet material mounted on the peripheral surface of the reel body. Then, on the surface of the sheet material, a plurality of (for example, 20) symbols are drawn at predetermined intervals along the circumferential direction (the rotation direction of the reel).

  The front door 2b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is openably and closably attached to the cabinet 2a using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachi-slot 1.

  The front panel 10 is provided above the door body 9. The front panel 10 is composed of a frame-shaped member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is arranged so as to face a display device 11 (described later) arranged inside the cabinet 2a.

  The display device cover 30 is made of black translucent synthetic resin. Therefore, the player can visually recognize the video (image) displayed on the display device 11 described later through the display device cover 30. In addition, in the present embodiment, the display device cover 30 is made of a black translucent synthetic resin to suppress the entry of external light into the cabinet 2a, and the image (image) displayed by the display device 11 is suppressed. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21a and 21b provided on the upper portion of the front panel 10 when viewed from the player side. Each of the lamps included in the lamp group 21 is configured by an LED (Light Emitting Diode) or the like (see an LED group 85 in FIG. 7, which will be described later), and turns on and off the light in a pattern corresponding to the effect contents.

  The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 includes a decorative panel on which an arbitrary image is drawn, and a light source (LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. In the pedestal portion 13, the symbol display area 4 and various devices to be operated by the player (medal slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, three stop buttons 17L, 17C, 17R, a settlement button (not shown), etc. are provided.

  The symbol display area 4 is an area overlapping with the three reels 3L, 3C, 3R as viewed from the front, and is arranged at a position closer to the player than the three reels 3L, 3C, 3R, and the three reels. It has a size that makes 3L, 3C, and 3R visible. The symbol display area 4 functions as a display window, and has a configuration in which the reels 3L, 3C, 3R provided behind it can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  The reel display window 4 has three reels 3L, 3C, 3R provided behind it, and when the rotations of the three reels 3L, 3C, 3R are stopped, among the plurality of symbols provided on the circumferential surface of each reel Two symbols are displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, in the frame of the reel display window 4, one symbol is provided in each of the upper, middle, and lower regions for each reel (a total of three symbols). ) Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In the present embodiment, a pseudo line (center line) connecting the middle region of the left reel 3L, the middle region of the middle reel 3C, and the middle region of the right reel 3R is formed in the frame of the reel display window 4. It is defined as an effective line that determines whether or not a prize is won.

  The reel display window 4 is formed by the opening of the frame member 31 provided in the pedestal portion 13. Further, below the frame member 31 that defines the reel display window 4, a pedestal region of a substantially horizontal plane is provided. When viewed from the player side, the medal slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1 bet button 15b are provided on the left side.

  The medal slot 14 is provided to receive medals that are dropped from the outside by the player onto the pachi-slot 1. The medals received from the medal insertion slot 14 are used in one game with a predetermined number (for example, 3) set in advance as an upper limit, and the number of medals exceeding the predetermined number is deposited inside the pachi-slot 1. It is possible (a so-called credit function (game medium storing means)).

  The MAX bet button 15a and the 1 bet button 15b are provided to determine the number of coins to be used for one game from the medals stored inside the cabinet 2a. A bet button LED (not shown) that lights up when a medal can be inserted is provided inside the MAX bet button 15a. The payment button is provided for pulling out (discharging) the medals stored inside the pachi-slot 1 to the outside.

  When the player presses the MAX bet button 15a, medals corresponding to the number of bets in the unit game (three) are inserted and the activated line is activated. On the other hand, each time the bet button 15b is pressed once, one medal is inserted. When the 1 bet button 15b is operated three times, the number of medals (three) for the unit game is inserted, and the activated line is activated.

  In the following, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting a medal into the medal insertion slot 14 (the operation of inserting a medal for playing a game) are all referred to as "insertion operation".

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided for stopping the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  Further, an information display 6 is provided at a substantially central portion of a pedestal area on a substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

  The information display 6 is a 2-digit 7-segment LED for digitally displaying (notifying) the number of medals paid out to the player as a privilege (hereinafter referred to as "payout number") to the player. Information for digitally displaying (notifying) the player (hereinafter, referred to as "7-segment LED") and information such as the number of medals stored in the pachi-slot 1 (hereinafter referred to as "credit number"). A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) the error occurrence and error type information to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the payout number of medals is switched from the display mode of the payout number to the display mode of the information on the error type.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying the information of the stop operation necessary for displaying the symbol combination corresponding to the winning combination determined as the internal winning combination along the activated line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. Then, on the instruction monitor, the 2-digit 7-segment LED is turned on, blinking, or turned off in a manner uniquely corresponding to the information on the stop operation to be notified, thereby informing the player of the necessary stop operation information. To do.

  Note that, here, the mode uniquely corresponding to the information of the stop operation to be notified means, for example, when the pressing order “1st (perform the first stop operation on the left reel 3L)” is notified. When the numerical value “1” is displayed on the instruction monitor and the pressing order “2nd (perform the first stop operation to the middle reel 3C)” is notified, the numerical value “2” is displayed on the instruction monitor and the pressing order In the case of notifying "3rd (perform the first stop operation on the right reel 3R)", a numerical value "3" is displayed on the instruction monitor. It should be noted that the notification mode of the stop operation information on the instruction monitor (navi data determined by the main side described later) will be described in detail later with reference to FIG. 63 described later.

  The information display 6 is electrically connected to the main control board 71 via the door relay board 68 and the game operation display board 81, as shown in FIG. 7 described later, and the display operation of the information display 6 is the main control. It is controlled by a main control circuit 90 described later in the substrate 71. Further, the control method of the various 7-segment LEDs described above is dynamic lighting control.

  In the pachi-slot 1 of the present embodiment, in addition to the instruction monitor controlled by the main control board 71, another configuration controlled by the sub-control board 72 is used to notify the stop operation information. Specifically, the information of the stop operation is notified by the display device 11 described later, which is configured by the projector mechanism 211 and the display unit 212 (see FIG. 3 and FIG. 7 described later) described later.

  When such a configuration is applied, the notification mode in the instruction monitor and the notification mode in other means controlled by the sub-control board 72 may be different modes. That is, in the instruction monitor, it is sufficient to notify in a manner that uniquely corresponds to the information of the stop operation to be notified, and it is not always necessary to directly notify the information of the stop operation (for example, the numerical value “1” in the instruction monitor). Even if is displayed, there is a possibility that the content of the notification cannot be specified depending on the player, and it cannot be said that it is a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, the information of the stop operation may be directly notified. For example, when the push order "1st" is notified, the numerical value "1" uniquely corresponding to the push order notified is displayed on the instruction monitor, but with other means (for example, the display device 11 or the like), the left reel 3L is displayed. Alternatively, the instruction information for performing the first stop operation may be directly notified.

  In the pachi-slot 1 having such a configuration, not only the control of the sub control board 72 but also the control of the main control board 71 can notify the information of the required stop operation according to the internal winning combination. Further, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, in the general game state (non-ART game state) described later, the stop operation information may not be notified, but in the ART game state described later (see FIG. 14 described later), the stop operation information may be notified.

  A sub display device 18 is provided to the left of the reel display window 4 as viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand substantially vertically from a pedestal region of a substantially horizontal surface of the pedestal portion 13 on the front surface of the door body 9. The sub display device 18 is composed of a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various kinds of information.

  Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates according to a predetermined operation principle such as an electrostatic capacitance method, and when a player's operation is received, it outputs a signal according to the operation as touch input information. The pachi-slot 1 of the present embodiment is capable of switching the display of the sub display device 18 in accordance with the player's operation (touch input information output from the touch sensor 19) received via the touch sensor 19. Have. The sub display device 18 is controlled by a sub control board 72 (see FIG. 7, which will be described later), which will be described later, based on touch input information output from the touch sensor 19.

  A medal payout opening 24, a medal receiving tray 25, two speaker holes 20L and 20R, etc. are provided in the lower portion of the door body 9. The medal payout opening 24 guides the medals discharged by driving a medal payout device 51, which will be described later, to the outside. The medal tray 25 stores the medals discharged from the medal payout opening 24. In addition, sound effects and sound such as music corresponding to the effect contents are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachi-slot 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure on the back side of the front door 2b.

  As shown in FIG. 3, the cabinet 2a includes a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. The display device 11 is arranged in the upper part of the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection target member 212a onto which the image light projected from the projector mechanism 211 is projected, and performs image display by projection mapping. Specifically, in the display device 11, image light is generated based on the position (projection distance, angle, etc.) and shape of the projection target member 212a, which is a three-dimensional object, and the projection light is projected by the projector mechanism 211. It is projected on the surface of 212a. By providing such an effect function, an advanced and powerful effect can be performed. Although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and one of the projected members is provided depending on the game state. , Used as a screen on which video light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the members to be projected according to the game state.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged in the lower part of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b of the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large amount of medals and discharging them one by one. The hopper device 51 pays out medals when, for example, the number of stored medals exceeds 50, or when the settlement button is pressed to perform settlement of medals. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

  The medal auxiliary storage 52 stores the medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 has a power switch 53a and a power board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side face plate 27c. The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device (not shown) into the power of the DC voltage required by each unit, and supplies the converted power to each unit.

  A sub-control board case 57 that accommodates a sub-control board 72 (see FIG. 7, which will be described later) is arranged above the power supply device 53 in the cabinet 2a. The sub-control board 72 housed in the sub-control board case 57 is mounted with a sub-control circuit 200 described later (see FIG. 10 described later). The sub-control circuit 200 is a circuit that controls execution of effects such as display of images. The specific configuration of the sub control circuit 200 will be described later.

  A sub relay board 61 is arranged above the sub control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and a main control board 71 described later is mounted. Further, the sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and the boards arranged around the sub control board 72 and various device parts (units) is mounted.

  Although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7, which will be described later) is provided in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 7 described later), and a medal payout count switch (not shown). It is a relay board on which wiring for connecting to and is mounted.

  As shown in FIG. 4, a middle door 41 is provided at the center of the rear surface of the front door 2b, and the reel display window 4 (see FIG. 2) is attached to the rear side of the front door 2b so as to be opened and closed. Although not shown in FIG. 4, three reels 3L, 3C, 3R are attached to the reel display window 4 side of the middle door 41, and the main control is provided on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 accommodating a board 71 (see FIG. 7 described later) is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, 3R via a gear having a predetermined reduction ratio.

  The main control board 71 housed in the main control board case 55 has a main control circuit 90 described later (see FIG. 9 described later). The main control circuit 90 (main control means) is a circuit for controlling the main flow of the game in the pachi-slot 1, such as determining an internal winning combination, rotating and stopping each reel 3L, 3C, 3R, and determining whether or not there is a prize. .. In the present embodiment, the main control circuit 90 also controls, for example, lottery processing for determining whether or not ART is determined, navigation information display processing on the instruction monitor, and various test signal transmission processing. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back surface side of the front door 2b. The speakers 65L and 65R are arranged at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

  Further, a selector 66 and a door opening / closing monitoring switch 67 are arranged above the speaker 65L. The selector 66 is a device for selecting whether or not the material and shape of the medal are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) that detects that a proper medal has passed is provided on the path of the medal in the selector 66.

  The door open / close monitor switch 67 is disposed diagonally below and to the left of the selector 66 when the front door 2b is viewed from the back side. The door opening / closing monitor switch 67 outputs a security signal for informing the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  Although not shown in FIG. 4, a door relay terminal board 68 is disposed below the reel display window 4 in a region where the front door 2b is opened and closed by the middle door 41 on the back surface (see a later-described diagram). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a test machine, and It is a relay board on which wiring for connecting to each of the second interface boards 302 for a tester is mounted. The various buttons and switches include, for example, a MAX bet button 15a, a 1 bet button 15b, a door opening / closing monitor switch 67, a BET switch 77, which will be described later, and a start switch 79.

<Display example of sub display device>
Here, various display screens displayed on the sub display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18.

  Various display screens are displayed on the sub-display device 18 by a player's touch operation, and as shown in FIGS. 5A to 5E, various types including a top screen 221, a menu screen 222, and game information screens 223, 224, 225. The display screen is displayed. These display screens are switched based on the operation signal of the player received via the touch sensor 19.

  The top screen 221 is an initial screen of the display screens displayed on the sub display device 18, and on the top screen 221, a "MENU" button 221a and an outline game history 221b are displayed. The “MENU” button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B, and when the player performs a predetermined operation (for example, tap) on the “MENU” button 221a, the menu screen 222 is called. Be done. Further, on the top screen 221, a partial game history (outline game history) of the pachi-slot 1 is displayed as the outline game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the outline game history 221b.

  The menu screen 222 is a screen for displaying a menu that can be displayed on the sub display device 18. On the menu screen 222, a “return” button 222a, a “register” button 222b, an “explanation” button 222c, and an “array payout” button 222d. , A "reach eye" button 222e, a "WEB site" button 222f, and a "volume" button 222g are displayed. The “return” button 222a is an operation button for calling the top screen 221. When the player operates the “return” button 222a, the top screen 221 is called. Further, the "register" button 222b to the "volume" button 222g are operation buttons for calling up the display screen of the corresponding menu contents, and when the player operates each button, the corresponding menu contents are displayed. The display screen is called.

  For example, when the “register” button 222b on the menu screen 222 is operated by the player, a registration screen (not shown) for registering the player who is playing the game is called up on the display screen of the sub display device 18. In recent years, in pachi-slot, a service is widely used in which a player is registered for each model and various information such as the achievement status of a predetermined mission is managed from the game history of the player. The registration screen called by the "registration" button 222b is a display screen for registering a player when receiving this service.

  Further, for example, when the “description” button 222c is operated by the player on the menu screen 222, the explanation screen (not shown) of the pachi-slot 1 is called up on the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, an explanation about the specification of the pachi-slot 1 such as a bonus winning probability and an ART winning probability for each set value, and an introduction explanation of a character appearing in the effect of the pachi-slot 1.

  Further, for example, when the “array payout” button 222d on the menu screen 222 is operated by the player, the array payout screen (not shown) of the pachi-slot 1 is called up on the display screen of the sub display device 18. On the array payout screen, for example, a correspondence relationship (payout table) between a combination of symbols determined to be a prize in the pachi-slot 1 and a privilege when a prize is determined, and each reel 3L, 3C, 3R are drawn. A symbol row (reel arrangement) or the like is displayed.

  Further, for example, when the “reach eye” button 222e on the menu screen 222 is operated by the player, the reach eye screen (not shown) of the pachi-slot 1 is called up on the display screen of the sub display device 18. On the reach eye screen, information of the symbol combination called "reach eye" set in the pachi-slot 1 is displayed. In addition, the symbol combination called “reach eye” is a symbol combination to which a special privilege is given by displaying the symbol combination along the activated line. The symbol combinations corresponding to the abbreviation “reach eye lip” shown in the content column of the winning operation flag storage area of 28 to 30 correspond. Then, in the present embodiment, when the symbol combination relating to the “reach eye lip” is displayed along the activated line, then a state advantageous to the player (for example, a bonus state, a normal ART or CT (see FIG. 14 described later). It is confirmed that the transition to ())) will be made.

  Further, for example, when the “WEB site” button 222f on the menu screen 222 is operated by the player, the WEB introduction screen (not shown) of the pachi-slot 1 is called up on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating the URL of an arbitrary WEB site such as a special WEB site provided for each model of the pachi-slot 1 or a WEB site of the manufacturer of the pachi-slot 1 Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

  In addition, for example, when the “volume” button 222g on the menu screen 222 is operated by the player, a volume display screen (not shown) that can adjust the volume of the sound output from the speakers 65L and 65R is displayed on the sub display device. The display screen of 18 is called. The player can adjust the volume of the effect sound of the pachi-slot 1 via the volume adjustment screen.

  Since the sub display device 18 is provided separately from the display device 11 (the projector mechanism 211 and the display unit 212) described above, it can be controlled separately from the display device 11. Therefore, in the pachi-slot 1 of the present embodiment, the display screen of the sub display device 18 can be switched by the player's operation even during the game (during execution of the effect by the display device 11). As a result, for example, when the player wants to know about a character that appears in the presentation on the display device 11, the player operates the “description” button 222c to call up the explanation screen, and It is possible to grasp information such as the relationship of the game during the game. In addition, for example, if the player wants to grasp the symbol that should be used as a guide for winning the rare role during reel rotation when the so-called “rare role” is won during the game, the player is By operating the "array payout" button 222d to call the array payout screen, the reel array can be grasped.

  The game information screens 223, 224, and 225 are display screens that display detailed game history information including a summary game history displayed on the top screen 221 of the game history of the pachi-slot 1.

  On the game information screen 223, a “return” button 223a, a “MENU” button 223b, a “previous” button 223c, a “next” button 223d, and a game history 223e are displayed. The “return” button 223a and the “MENU” button 223b are operation buttons for calling the top screen 221 and the menu screen 222 on the display screen of the sub display device 18, respectively, and correspond by operating each button by the player. The display screen is displayed. Further, the “previous” button 223c and the “next” button 223d are operation buttons for switching the game information screen in a predetermined order, and when the “previous” button 223c is operated by the player, the display screen is displayed. Is switched from the game information screen 223 to the game information screen 225, and when the “Next” button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. As the game history 223e, the number of games (number of games), number of bonuses, number of ARTs, and number of CZs (chance zone) are displayed as shown in FIG. 5C.

  A "return" button 224a, a "MENU" button 224b, a "previous" button 224c, a "next" button 224d, and a game history 214e are displayed on the game information screen 224. The “return” button 224a and the “MENU” button 224b are operation buttons for calling the top screen 221 and the menu screen 222 on the display screen of the sub display device 18, respectively, and correspond by the player operating each button. The display screen is displayed. Further, the “previous” button 224c and the “next” button 224d are operation buttons for switching the game information screen in a predetermined order, and when the “previous” button 224c is operated by the player, the display screen is displayed. When the information screen 224 is switched to the game information screen 223 and the "Next" button 224d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as the game history 224e, the number of rushes and the number of successes of CZ (chance zone) described later are displayed. As will be described later, in this embodiment, three types of CZ, CZ1, CZ2, and CZ3, are provided as CZ. Therefore, as the game history 224e, as shown in FIG. 5D, the number of rushes and the number of successes of each of CZ1 to CZ3 are displayed.

  On the game information screen 225, a "return" button 225a, a "MENU" button 225b, a "previous" button 225c, a "next" button 225d, and a game history 225e are displayed. The "return" button 225a and the "MENU" button 225b are operation buttons for calling up the top screen 221 and the menu screen 222 on the display screen of the sub display device 18, respectively, and correspond by the player operating each button. The display screen is displayed. Further, the "previous" button 225c and the "next" button 225d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the “Next” button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as the game history 225e, as shown in FIG. 5E, the number of winnings of the small winning combination and the winning probability (fraction where the numerator is 1) are displayed.

  As a method of switching the display screen displayed on the sub display device 18, for example, a method of switching based on a tap operation on an operation button displayed on each display screen may be adopted, or, for example, A method of switching based on a swipe operation on the display screen may be adopted.

<Various display screen switching functions on the sub display device>
Next, various switching functions of the display screen of the sub display device 18 in the pachi-slot 1 of the present embodiment will be described.

[Example of transition of display screen of sub display device]
First, a transition example (switching mode) of the display screen of the sub display device 18 in the pachi-slot 1 of the present embodiment will be described with reference to FIGS. 6A and 6B. 6A is a diagram showing a transition example of the display screen of the sub display device 18 in the situation where the player registration state is not set, and FIG. 6B is a sub display in the situation where the player registration state is set. FIG. 9 is a diagram showing a transition example of a display screen of the device 18.

  When the player registration state is not set, as shown in FIG. 6A, the display screen of the sub display device 18 transits between the top screen 221 and the menu screen 222 and from the menu screen 222 and the menu screen 222. It is possible to make transitions only with various possible display screens, and transitions between these display screens are controlled by the sub control board 72 (sub CPU 201 described later). For example, the sub-control board 72, between the top screen 221 and the menu screen 222, based on a touch operation (for example, a tap operation on a predetermined button or a swipe operation on the display screen) acquired via the touch sensor 19, Switch the display screen. However, when the player registration state is not set, the sub control board 72 controls so that the game information screens 223, 224, and 225 cannot be displayed. That is, the player cannot display the game information screens 223, 224, and 225 on the sub display device 18 when the player registration state is not set.

  On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and between the menu screen 222 and the menu screen 222. In addition to the various display screens that can be transitioned from, it is possible to transition between the menu screen 222 and the game information screens 223, 224, 225. It is controlled by the CPU 201). That is, the sub-control board 72, based on the touch operation acquired via the touch sensor 19, not only between the top screen 221 and the menu screen 222, but also each of the top screen 221 and the menu screen 222, and the game information screen. The display screen can be switched between 223, 224, and 225. Therefore, in the present embodiment, when the player registration state is set, the player can display the game information screens 223, 224, 225 on the sub display device 18.

  As shown in FIG. 6B, the transition order of the display screens among the top screen 221, the menu screen 222, and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, the configuration may be such that the top screen 221 can directly transit to the game information screens 223, 224, and 225, or the top screen 221 can be changed to the game information screens 223, 224, and 225 only through the menu screen 222. The configuration may be such that transition is possible.

  In the pachi-slot 1 of the present embodiment, a configuration capable of transitioning from the top screen 221 to the game information screens 223, 224, and 225 only through the menu screen 222 (a configuration in which the top screen 221 cannot directly transit to the game information screens 223, 224, and 225) ) Is adopted. In the pachi-slot 1 according to the present embodiment, when the player performs a swipe operation (not a menu selection operation) on the display screen on the menu screen 222, the display screen changes from the menu screen 222 to the game information screen 223. , 224, 225.

  In the present embodiment, the game information screens 223, 224, 225 are display screens that are completely independent of the menu screen 222. That is, in the pachi-slot 1 of the present embodiment, the information indicating the result of the game, which is the game history that the player has a strong interest in during the game, is independent as the information unrelated to the result of the game such as the payout arrangement and the volume adjustment. And display it. In the present embodiment, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222 in the situation where the player registration state is set. . Therefore, in the present embodiment, when the player registration state is set, it is possible to easily access the information on the game history desired by the player.

  Further, in the present embodiment, in the menu selection operation on the menu screen 222, the display screen cannot be changed to the game information screens 223, 224, 225, and the swipe operation on the menu screen 222 (specified in the menu display) The display screen cannot be changed to the game information screens 223, 224, and 225 unless an operation) is performed. Therefore, in the pachi-slot 1 of the present embodiment, the swipe operation for transitioning the display screen to the game information screens 223, 224, 225 can be treated as a hidden command in the situation where the player registration state is set. In this case, the player can see more detailed game history information, which cannot be seen by other players who have little knowledge, due to his / her own knowledge of the pachi-slot 1, so that it can be seen more than the other player. The game can be advantageously played, and as a result, the player can be expected to actively play the game.

[Display switching function from game information screen to top screen]
The pachi-slot 1 of the present embodiment has a function of changing the display screen of the sub display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in the present embodiment, when the "return" button is operated on the game information screens 223, 224, 225, the display screen changes from the game information screens 223, 224, 225 to the top screen 221 (manual transition). function). Further, in the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, 225 are displayed, the display screen is automatically changed to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

  More specifically, in the pachi-slot 1, in the state where the game information screens 223, 224, and 225 are displayed, an insertion operation (operation to the MAX bet button 15a, operation to the 1 bet button 15b, and the medal insertion slot 14) is performed. When the operation of inserting a medal) is performed, the display screen of the sub display device 18 automatically changes to the top screen 221. In addition, like the ART game state, in a game state in which the probability that a replay combination is determined as an internal winning combination is high (high-rep state), a medal is automatically inserted by the operation of the replay accompanying the winning of the replay combination. As a result, in the high-rip state, the chances of displaying the game information screens 223, 224, 225 may be limited. Therefore, in the pachi-slot 1 of the present embodiment, when a medal is automatically inserted by the operation of the replay, the display screen is automatically changed to the game information screen 223 when the start operation is used as a trigger instead of the medal insertion operation. , 224, 225 to the top screen 221.

  That is, in this embodiment, when the re-game is activated and the game information screens 223, 224, and 225 are displayed, the display screens are automatically displayed as the game information screens 223 and 224 with the start operation as a trigger. , 225 to the top screen 221. On the other hand, when the re-game is not operated, the display screen is automatically changed from the game information screens 223, 224, and 225 to the top screen 221 upon the input operation.

[Display switching function from the menu contents display screen to the top screen (or menu screen)]
The pachi-slot 1 of the present embodiment has various menu content display screens (registration screen, explanation screen, array payout screen, reach eye screen, WEB introduction) that can transit the display screen of the sub display device 18 by menu selection operation on the menu screen 222. Screen and volume adjustment screen), the player has a function of transiting to the top screen 221 (or menu screen 222) manually or automatically. Specifically, in the present embodiment, when a predetermined button (for example, a “return to TOP” button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 ( Manual transition function). Further, in the present embodiment, when a specific button (for example, a “return” button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the menu screen 222 (manual transition). function).

  Further, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically becomes the top screen 221 (or the menu screen 222) regardless of the player's operation. Transition (automatic transition function). At this time, the predetermined time that triggers the automatic transition to the top screen 221 (or the menu screen 222) differs depending on the type of the menu content display screen currently displayed. For example, when the volume adjustment screen for adjusting the volume output from the pachi-slot 1 is displayed for a long time, not only the volume may be adjusted to an unintended volume by an erroneous operation, but also another player may be erroneously operated by an erroneous operation. It may make you uncomfortable. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transit to the top screen 221 (or the menu screen 222) in a longer time than other menu content display screens in order to facilitate the registration of the player. ..

  That is, the elapsed time (automatic transition time) that triggers an automatic transition to the top screen 221 (or the menu screen 222) is appropriately set in each menu content display screen according to the type of the menu content display screen. The volume adjustment screen has an automatic transition time shorter than those of other menu content display screens, and the registration screen has a longer automatic transition time than those of other menu content display screens.

[Function for selecting whether to operate the menu]
In the pachi-slot 1 of the present embodiment, the display screen of the sub display device 18 is changed from the menu screen 222 to a registration screen, an explanation screen, an array payout screen, a reach screen, a WEB introduction screen, and a volume adjustment screen, thereby playing a game. A person can perform various operations according to these menu content display screens and can confirm various information. It should be noted that a function (a function of selecting whether or not to operate the menu) may be provided so that such a function that the player can select the menu can be restricted according to the setting on the game shop side.

  For example, the display screen may not be allowed to transition from the menu screen 222 to the volume control screen (for example, the “volume” button 222g is not displayed on the menu screen 222) depending on the setting at the game shop side. In this case, it is possible to prevent the player from adjusting the volume.

<Control system of pachi-slot>
Next, the control system included in the pachi-slot 1 will be described with reference to FIG. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachi-slot 1.

  The pachi-slot 1 has a main control board 71 provided on the middle door 41 and a sub-control board 72 provided on the front door 2b. Further, the pachi-slot 1 has a reel relay terminal plate 74, a setting key type switch 54 (setting switch), and a cabinet side relay substrate 44, which are connected to the main control substrate 71. Further, the pachi-slot 1 includes an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53, which are connected to the main control board 71 via the cabinet side relay board 44. Since the configuration of the hopper device 51 has been described above, the description thereof will be omitted here.

  The reel relay terminal plate 74 is arranged inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R and relays a signal output from the main control board 71 to the stepping motor.

  The setting key type switch 54 is provided on the main control board case 55. The setting key type switch 54 is used when changing the settings (setting 1 to setting 6) of the pachi-slot 1 or when confirming the settings of the pachi-slot 1.

  The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. Is. The external centralized terminal board 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachi-slot 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52 and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachi-slot 1.

  The power supply device 53 has a power supply board 53b and a power switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot 1. The power supply board 53 b is connected to the main control board 71 via the cabinet-side relay board 44 and is also connected to the sub-control board 72 via the sub-relay board 61.

  Further, the pachi-slot 1 includes a door relay terminal plate 68, and a selector 66, a door opening / closing monitoring switch 67, a BET switch 77, a settlement switch 78, which are connected to the main control board 71 via the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a test machine first interface board 301, and a test machine second interface board 302. The selector 66, the door open / close monitor switch 67, and the sub relay board 61 have been described above, and therefore their description is omitted here.

  The BET switch 77 (insertion operation detecting means) detects that the player has pressed the MAX bet button 15a or the 1 bet button 15b. The settlement switch 78 detects that the settlement button (not shown) is pressed by the player. The start switch 79 (start operation detection means) detects that the start lever 16 has been operated by the player (start operation).

  The stop switch board 80 (stop operation detection means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stoppable main reel with an LED or the like. A stop switch (not shown) is provided on the stop switch board 80. The stop switch detects that the stop buttons 17L, 17C, 17R are pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 has, for example, three LEDs for displaying the number of inserted medals (hereinafter, "first LED" to "LED", which are lit in correspondence with the number of medals inserted in this game (hereinafter, referred to as "inserted number"). LED for turning on a mark indicating that a medal can be inserted, a mark for indicating a game start, a mark for re-playing, etc. based on a signal input from the game operation display substrate 81. Etc. are included. In the first LED to the third LED (display means), when one medal is inserted, the first LED lights, when two medals are inserted, the first and second LEDs light, and three medals (game) When the number of sheets that can be started is input, the first to third LEDs are turned on. Since the information display 6 has been described above, the description thereof will be omitted here.

  Both the first interface board 301 for a test machine and the second interface board 302 for a test machine are relay boards used when outputting various signals relating to a game to the test machine in the verification test (testing test) of the pachi-slot 1 ( Since these relay boards are not mounted on the pachi-slot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for test machine and the test machine. Also, various electronic components necessary for connecting to the second interface board 302 are not mounted). For example, a test signal for controlling main operations related to the game (for example, internal lottery, reel stop control, etc.) is output via the first interface board 301 for a test machine, and is determined by the main control board 71, for example. A test signal or the like related to the pressed navigation that has been performed is output via the second interface board 302 for a tester.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. Further, the pachi-slot 1 has a speaker group 84, an LED group 85, a 24h door opening / closing monitoring unit 63, a touch sensor 19 and a display unit 212, which are connected to the sub control board 72 via the sub relay board 61. Since the touch sensor 19 has been described above, its description is omitted here.

  The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side, and the like. The 24h door opening / closing monitoring unit 63 stores the history information of opening / closing of the middle door 41. Further, the 24h door opening / closing monitoring unit 63 outputs a signal for displaying an error on the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projected member 212a that constitutes the display device 11, and another projected member that is provided on the back side of the projected member 212a and has a curved display surface.

  The pachi-slot 1 further includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub-control substrate 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub control board case 57 together with the sub control board 72.

  The ROM cartridge board 86 is a board for managing various control programs executed by the sub CPU 102, and images (video) for presentation, sounds (speaker group 84), light (LED group 85), and communication data. .. The liquid crystal relay board 87 is a board that relays the connection wiring between the sub control board 72, the projector mechanism 211 that constitutes the display device 11, and the sub display device 18. Since the projector mechanism 211 and the sub display device 18 have been described above, their explanations are omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for gaming machines. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes peculiar to the microprocessor 91 that can be defined on the source program (for example, an “LDQ” instruction described below: "Special instruction code") is provided. In the present embodiment, by using the instruction code dedicated to the main CPU 101, the efficiency of the processing and the reduction of the program capacity are realized. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by a main control circuit described later. To do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes the control program based on the input clock pulse signal.

  The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). Then, the power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the starting voltage value (10V) from 0V). When the power failure occurs (when the power supply voltage falls from 12V to the power failure voltage value (10.5V)), the power failure detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (starting signal) to the microprocessor 91 when the power is turned on (starting means), and when the power is interrupted, the microprocessor 91 detects the power failure (power failure signal). Also serves as a means for outputting (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of DC 5V) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing the internal configuration of the microprocessor 91.

  The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 105, an arithmetic circuit 107, It has a random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115. Then, each of these units constituting the microprocessor 91 are connected to each other via a signal bus 116.

  The main CPU 101 executes various control programs on the basis of the clock pulse generated by the clock circuit 105, and controls the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  After detecting the reel index, the main CPU 101 counts the number of times the pulse is output to the stepping motor of each reel 3L, 3C, 3L (main reel). Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has rotated once. The reel index includes, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting unit and the light receiving unit by the rotation of each main reel. It is detected by a reel position detector (not shown) provided.

  Here, the management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the pulse counter counts the output of the predetermined number of pulses necessary for the rotation of one symbol, the symbol counter provided in the main RAM 103 is incremented by one. The symbol counter is provided for each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detector (not shown).

  That is, in the present embodiment, by managing the symbol counter, it is managed how many symbols are rotated after the reel index is detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by executing the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail later with reference to FIG.

  The external bus interface 104 is for electrically connecting an external signal bus (not shown) to which various components (eg, reels) provided outside the microprocessor 91 are connected to the microprocessor 104. It is an interface circuit. The clock circuit 105 is configured to include, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is supplied to other components (for example, the timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or a WDT (watchdog timer) based on the reset signal input from the power management circuit 93. The arithmetic circuit 107 is configured to include a multiplication circuit and a division circuit. For example, when executing a “MUL (multiplication)” instruction (see later-described FIG. 93B) on the source program, the arithmetic circuit 107 executes a multiplication process based on the “MUL” instruction.

  The random number circuit 110 generates a random number within a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 stores a random number register 0 for obtaining a 2-byte hard latch random number, random number registers 1 to 3 for obtaining a 2-byte soft latch random number, and a 1-byte soft latch random number. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in the predetermined range generated by the random number circuit 110, for example, as a random number value for internal lottery. The parallel port 111 is a port (memory map I / O) for signals input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93 and the like) provided outside the microprocessor 91. .. The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to one of the input ports PI0 to PI4 of the parallel port 111, and at the timing (on edge) when the start switch 79 is turned on, a latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110. Is output. Then, in the random number circuit 110, the random number register 0 is latched by inputting the latch signal, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs an interrupt process by the main CPU 101 based on a power failure detection signal input from the power management circuit 93 via the parallel port 111 or a timeout signal input from the timer circuit 113 at a 1.1172 ms cycle. Control the execution timing of. When the power failure detection signal is input from the power management circuit 93 or the timeout signal is input from the timer circuit 113, the interrupt controller 112 outputs an interrupt request signal indicating an interrupt processing start command. Output to. The main CPU 101, based on an interrupt request signal input from the interrupt controller 112 in response to a time-out signal from the timer circuit 103, performs input port check processing, reel control processing, communication data transmission processing, 7-segment LED drive processing, timer. Various types of interrupt processing such as update processing (see FIG. 158 described later) are performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (a clock pulse signal having a frequency obtained by dividing the clock pulse signal for operating the main CPU by a frequency divider (not shown)) ( Count elapsed time). Then, the timer circuit 113 outputs a time-out signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when transmitting data (various control commands (commands)) from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls a serial transmission operation when transmitting data from the main control board 71 to the second interface for tester 302.

<Sub control circuit>
Next, the configuration of the sub control circuit 200 (sub control unit) mounted on the sub control board 72 will be described with reference to FIG. FIG. 10 is a block diagram showing a configuration example of the sub control circuit 200 of the pachi-slot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge board 86. The driver 205 is connected to the liquid crystal relay board 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  The control program executed by the sub CPU 201 is stored in the program storage area. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random number value for performance are extracted, and performance registration for determining and registering performance content (effect data) is performed. It contains various programs to perform tasks. Further, the control program includes a drawing control task for controlling the display of an image on the display device 11 based on the decided effect contents, a lamp control task for controlling the light output from the light source such as the LED group 85, and a sound by the speaker group 84. Various programs for executing a voice control task or the like for controlling the output of are also included.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to image creation. The data storage area also includes a storage area for storing sound data regarding BGM and sound effects, a storage area for storing lamp data regarding a pattern of turning on / off light.

  The sub RAM 202 is provided with a storage area for registering the determined effect contents and effect data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create a video according to the animation data specified by the effect contents, and the created video is displayed on the display device 11 (projector mechanism 211) and / or. Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM in accordance with the sound data specified by the effect contents. In addition, the sub CPU 201 controls the turning on and off of the LED group 85 according to the lamp data designated by the effect contents.

<Various registers of main CPU>
Next, various registers of the main CPU 101 will be described with reference to FIG. Note that FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 has, as main registers, an accumulator A (hereinafter referred to as “A register”), a flag register F (flag register), a general-purpose register B (hereinafter referred to as “B register”), and a general-purpose register C (hereinafter referred to as “ C register), general-purpose register D (hereinafter referred to as “D register”), general-purpose register E (hereinafter referred to as “E register”), general-purpose register H (hereinafter referred to as “H register”), and general-purpose register L (hereinafter referred to as “H register”) , "L register"). Further, the main CPU 101 serves as sub-registers such as an accumulator A ′, a flag register F ′, a general-purpose register B ′, a general-purpose register C ′, a general-purpose register D ′, a general-purpose register E ′, a general-purpose register H ′, and a general-purpose register L ′. As a general-purpose register. Each register is composed of a 1-byte register.

  Further, in this embodiment, the B register and the C register are used as a pair register (hereinafter referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter referred to as “DE register”). Further, in this embodiment, the H register and the L register are used as a pair register (hereinafter, referred to as “HL register”).

  As shown in FIG. 11, predetermined flag information indicating the result of arithmetic processing is set in each bit of the flag registers F and F '. For example, in bit 6 (D6), data (zero flag) indicating whether or not the operation result is “0” in the operation result determination process is set. Specifically, when the operation result is "0", the data "1" is set in the bit 6, and when the operation result is not "0", the data "0" is set in the bit 6. Then, in the determination process of the calculation result, the main CPU 101 refers to the data “0” / “1” of the bit 6 to make the determination (YES / NO).

  Further, the main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described later in various processing flows, various main CPU 101-dedicated instruction codes for addressing using the Q register are provided on the source program. Is used, the efficiency of the processing and the capacity reduction of the main ROM 102 are realized. Note that in various main CPU 101-dedicated instruction codes that specify addresses using the Q register, the Q register stores address data (address value) on the higher side of the address. Immediately after resetting the main CPU 101, "F0H" is set in the Q register as an initial value. In the "LD Q, n (8-bit data)" instruction using the Q register, the value of the Q register is changed by setting "n" to any 1-byte data and executing the instruction. be able to.

  Further, the main CPU 101 has an interrupt page address register I and a memory refresh register R formed of 1-byte registers, and an index register IX and an index register IY formed of 2-byte registers. , A stack pointer SP and a program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, with reference to FIG. 12A to FIG. 12C, an internal configuration (hereinafter referred to as “memory map”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

  In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the internal register area, and The XCS decode areas are arranged at predetermined addresses in this order with an unused area in between.

  In the memory map of the main ROM 102, as shown in FIG. 12B, from the head (0000H) side of the address of the main ROM 102, a program area, a data area, an unspecified area, a trademark recording area, a program management area, and a security setting area are In order, they are arranged at predetermined addresses.

  The program area stores control programs for various processes executed by the main CPU 101 in various control processes related to the game playability of the game performed by the player. In the data area, various data used by the main CPU 101 in various control processes related to the game play of the game performed by the player (for example, a data table such as an internal lottery table, various data for the sub control circuit 42). Data for transmitting control commands (commands) is stored. That is, the game ROM area (game storage area) including the program area and the data area is necessary for control processing (processing relating to game characteristics) related to the game characteristics of the game actually performed by the player at the game store. Various programs and various data are stored.

  In the non-regulated area, control programs and data of various processes (processes that do not affect the game play) that are not directly related to the game play of the game performed by the player are stored. For example, the programs and data used in the pachi-slot 1 certification test (testing test), the control programs and data used in the checksum generation process at the time of power failure, the sum check process at the time of power restoration, and the countermeasure program And the data and the like necessary for it are stored in the non-regulated area.

  In the memory map of the main RAM 103, as shown in FIG. 12C, from the head (F000H) side of the address of the main RAM 103, a game RAM area (predetermined storage area, game temporary storage area) and non-regular RAM area (non-regular temporary A storage area) is arranged at a predetermined address in this order.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the playability of the game executed by the player. .. Then, each of the various data is stored in a work area at a predetermined address in the game RAM area.

  Further, the non-regular RAM area is provided with an non-regular work area and a non-regular stack, which are work areas of various processes that are not directly related to the playability of the game performed by the player. In the present embodiment, by using this non-regular RAM area, various processes such as a sum check process that are not directly related to the game playability of the game performed by the player are executed.

  As described above, in the pachi-slot 1 of the present embodiment, in the main ROM 102, various programs and various data (tables) used for various processes that are not directly related to the playability of the game executed by the player are stored in the main ROM 102 for the game. The data is stored in a non-standard ROM area (non-standard storage area) located at an address different from the ROM area. In addition, various processes that are not directly related to the game playability of the game performed by such a player are performed in the main RAM 103 by using an unspecified RAM area arranged at an address different from the gaming RAM area. ..

  With such a configuration of the main ROM 102, programs and data unnecessary for the actual game played by the player are arranged in the ROM area (non-regular ROM area) where the conventional rules prohibit the arrangement of programs and the like. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the game ROM area.

<Game state transition flow>
Next, with reference to FIG. 13 and FIG. 14, various game states managed by the main control circuit 90 (main CPU 101) of the pachi-slot 1 of the present embodiment and transition flows thereof will be described. Note that FIG. 13A is a basic game state transition flow diagram of the pachi-slot 1, and FIG. 13B is a table summarizing the game state transition conditions. Further, FIG. 14A is a transition flow diagram of the game state in consideration of the presence or absence of the operation of the notification (ART) function, and FIG. 14B is a table summarizing the transition conditions of the game state.

[Basic game state transition flow]
In the pachi-slot 1 of the present embodiment, a big bonus (hereinafter referred to as “BB”) is provided as the type of bonus game. BB is an accessory continuous operation device related to a regular bonus (hereinafter, referred to as “RB”) called a type 1 special accessory, and continuously operates the RB.

  Therefore, in the present embodiment, the main control circuit 90 manages the game state based on the presence / absence of winning / operating (winning) of the bonus combination. Specifically, as shown in FIG. 13A, the main control circuit 90 determines whether or not there is a winning / acting (winning) of a bonus combination (an internal winning combination of names “F_BB1” and “F_BB2” described later). It manages three types of gaming states called "non-winning bonus state", "state between flags" and "bonus state".

  The bonus non-winning state is a state in which the bonus is non-winning and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, a state occurs in which the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, the bonus combination is won and the bonus is not activated.

  Whether or not the bonus combination is won is determined by data stored in a hit request flag storage area (see FIGS. 28 to 30 described later) and a carryover combination storage area (see FIG. 31 described later) provided in the main RAM 103. It is managed based on. In addition, the presence or absence of a bonus operation (winning) is managed based on data stored in a game state flag storage area (see FIG. 32 described below) provided in the main RAM 103.

  Further, in the present embodiment, as shown in FIG. 13A, in the gaming state in which the bonus is not operated (bonus non-winning state and state between flags), the type of the internal winning combination relating to the replay and its winning probability are different from each other, Six kinds of states (hereinafter referred to as "RT0 state" to "RT5 state"), RT0 gaming state to RT5 gaming state, are provided. The RT0 state, the RT2 state, and the RT5 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is low, and the RT1 state is the probability that the replay combination is determined as the internal winning combination. It is a game state with a medium probability. Further, the RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state of the bonus non-winning state is any one of the RT0 state to the RT4 state, and the RT state of the inter-flag state is the RT5 state.

  Therefore, in the present embodiment, the main control circuit 90 is based on the type of the internal winning combination relating to the replay and the winning probability thereof in the gaming state in which the bonus is not operated (the bonus non-winning state and the state between flags). Then, it also manages six types of states, RT1 state to RT5 state.

  The RT0 state to the RT5 state are managed based on data stored in a game state flag storage area (see FIG. 32 described later) provided in the main RAM 103, which will be described later. Specifically, the pachi-slot 1 of the present embodiment is provided with flags indicating five RT states, that is, an RT1 state flag to an RT5 state flag. By controlling the ON / OFF states of these flags by the main RAM 103, the RT state is set. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag in the ON state as the current RT state. If all the RT state flags are in the off state, the main control circuit 90 identifies that the current RT state is the RT0 state.

  As shown in FIGS. 13A and 13B, when a bonus combination (internal winning combination of names “F_BB1” and “F_BB2” described later) in the bonus non-winning state is determined as an internal winning combination (transition condition (1) is satisfied) ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the flag state. When the bonus combination is won in the flag state (when the shift condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the flag state to the bonus state.

  When the bonus state exceeds the specified number (216) in the bonus state and the bonus state ends (the transition condition (3) is satisfied), the main control circuit 90 changes the game state from the bonus state to the RT1 state ( It shifts to the bonus non-winning state).

  In the RT1 state, when 20 games have passed (when the shift condition (4) is satisfied), the main control circuit 90 shifts the game state from the RT1 state to the RT0 state. In addition, in the RT1 state, before 20 games have elapsed, when a symbol combination relating to the abbreviation "bell-shaped eyes" (see FIG. 28 described later) is displayed on the activated line (when the transition condition (5) is satisfied). , The main control circuit 90 shifts the game state from the RT1 state to the RT2 state.

  In the RT0 state, when the symbol combination related to the abbreviation "bell spilled eyes" is displayed on the activated line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the game state from the RT0 state to the RT2 state. Let In the RT2 state, when the symbol combination (refer to FIG. 28 described later) related to the abbreviation “RT3 shift lip” is displayed on the activated line (when the shift condition (6) is satisfied), the main control circuit 90 changes the game state. Transition from the RT2 state to the RT3 state.

  In the RT3 state, when the symbol combination (refer to FIG. 28 described later) related to the abbreviation “RT4 shift lip” is displayed on the activated line (when the shift condition (7) is satisfied), the main control circuit 90 changes the game state. Transition from the RT3 state to the RT4 state. Further, in the RT3 state, when a symbol combination (see FIG. 28 described later) related to the abbreviation “bell spilled eyes” or “RT2 shift lip” is displayed on the activated line (when the shift condition (8) is satisfied), The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Furthermore, in the RT4 state, when the symbol combination relating to the abbreviation "bell spilled eyes" or "RT2 shift lip" is displayed on the activated line (when the shift condition (8) is satisfied), the main control circuit 90 causes the game state. To shift the game state from the RT4 state to the RT2 state.

  In addition, the symbol combination related to the abbreviation “Bell Koboshi” is determined as an internal winning combination (small winning combination) related to the names “F_3 selection bell_1st”, “F_3 selection bell_2nd” or “F_3 selection bell_3rd”, which will be described later. Moreover, it is a combination of symbols displayed when the order of the stop operation is incorrect for the pushing order determined for each type of the small winning combination (see FIG. 24 described later). The symbol combination related to the abbreviation “RT2 transition lip” is determined as an internal winning combination (replay combination) related to the names “F_maintenance lip_1st”, “F_maintenance lip_2nd” or “F_maintenance lip_3rd” described later, and It is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the pushing order determined for each type of the replay combination.

  The symbol combination related to the abbreviation "RT3 transition rip" is determined as an internal winning combination (replay combination) related to the names "F_RT3 rep_1st", "F_RT3 rep_213", "F_RT3 rep_231" or "F_RT3 rep_3rd", which will be described later. And, it is a combination of symbols displayed when the order of the stop operation is correct with respect to the pressing order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation “RT4 transition rip” is an internal winning combination (replay combination) related to the names “F_RT4 rep_123”, “F_RT4 rep_132”, “F_RT4 rep_2nd” or “F_RT4 rep_3rd” described later. It is a combination of symbols that is determined and displayed when the order of the stop operation is correct with respect to the pressing order determined for each type of the replay combination.

[Game state transition flow considering whether the notification (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not the function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the operating / non-operating state of the ART function in the bonus non-operating state is also managed as the gaming state.

  In the pachi-slot 1 of the present embodiment, as shown in FIG. 14A, in the non-bonus operating state, the main control circuit 90 separates the "general game state" and the "ART game state" based on the presence or absence of the notification (ART). Managed as the game state of. That is, in the management of the game state in consideration of the presence or absence of the notification (ART), as shown in FIG. 14A, the main control circuit 90, as a major classification, "bonus state", "general game state" and "ART game state" It manages three types of game states.

  Note that the general game state is basically a game state (non-ART) in which the information of the stop operation advantageous to the player is not notified and is a disadvantageous game state to the player. In addition, the general gaming state is any state of RT0 to RT4, and is a gaming state of ART non-winning.

  On the other hand, the ART gaming state is a gaming state that informs information of a stop operation that is advantageous to the player, and is a gaming state that is advantageous to the player. Further, the ART gaming state is basically the RT4 state and the gaming state during the ART winning. In the present embodiment, after the winning of the ART, when the RT state shifts to the RT4 state, the ART game is started.

  Further, in the present embodiment, as shown in FIG. 14A, two types of states called “normal gaming state” and “CZ (chance zone)” are provided as the general gaming state.

  The normal game state is the most disadvantageous game state for the player, but in the game in the normal game state, the lottery for shifting to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal game state, when the winning of the lottery for transition to CZ is won (when the transition condition (A) is satisfied), the main control circuit 90 changes the game state to the normal game state. To CZ.

  CZ is a gaming state (chance zone) with a high degree of expectation for the transition to the ART gaming state, and the lottery for shifting to the ART is performed in the game during CZ. Then, as shown in FIGS. 14A and 14B, in the game during CZ, in the case where the lottery for the transition to the ART is non-winning (when the transition condition (B) is satisfied), the main control circuit 90 sets the game state. , CZ to the normal game state. On the other hand, in the game during the CZ, if the lottery for the transition to the ART is won (when the transition condition (C) is satisfied), the main control circuit 90 shifts the gaming state from the CZ to the ART gaming state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from the CZ to the ART gaming state (normal ART or CT described later) via an ART preparation state described later.

  The ART gaming state is started when the RT state shifts to the RT4 state after the ART winning as described above. Note that, as shown in FIG. 13A, the RT4 state shifts from the RT0 to RT2 states via the RT3 state, so the ART gaming state is not started immediately even after the ART winning. Therefore, in the pachi-slot 1 of the present embodiment, the gaming state during the period after the winning of the ART until the RT state shifts to the RT4 state is set as the ART preparation state. Then, in the game in the ART preparation state, the information of the stop operation necessary for shifting the RT state to the RT4 state is notified.

  In addition, in the present embodiment, as shown in FIG. 14A, as the ART game states, two types of states called “normal ART” and “CT (additional opportunity)” having different game characteristics are provided.

  Normally, ART is a stop operation advantageous for the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out, or a stop operation necessary for maintaining the RT4 state). Is a gaming state that is informed. In addition, in the game during the normal ART, a lottery for shifting to CT is performed.

  CT is a gaming state in which a stop operation that is advantageous to the player is notified, and it is possible to add the duration of normal ART for a specific period (a period of one set of 8 games), and functions as an additional chance zone. It is a game state to play. Also, during CT, a game is usually played without digesting the duration of ART. The game property during CT will be described later in detail with reference to FIGS.

  As shown in FIGS. 14A and 14B, in the game during the normal ART, if the transition lottery to CT is won (the transition condition (D) is satisfied), the main control circuit 90 changes the game state from the normal ART to the CT. Move the game state. Further, in the normal ART, when the continuation period of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the game state from the normal ART to the general game state (normal game state or CZ). Move. In the present embodiment, the duration of the normal ART is managed according to the number of games, but the present invention is not limited to this, and the method of managing the duration of the normal ART is arbitrary. For example, the duration of the normal ART may be managed by the number of medals paid out during the normal ART or the difference in the number of medals paid out during the normal ART, or by the number of times (navigation times) of notifications that affect the payout of medals during the normal ART. You may manage.

  As shown in FIGS. 14A and 14B, in the game during CT, when the CT continuation period (one set of eight games) ends (when the transition condition (F) is satisfied), the main control circuit 90 changes the game state to CT. To normal ART.

  Further, as shown in FIG. 14A, in the normal game state (normal game state or CZ) or the ART game state (normal ART or CT), if a bonus combination is won (the transition condition (2) described in FIGS. 13A and 13B) When is satisfied), the main control circuit 90 shifts the game state from the normal game state or the ART game state to the bonus state.

  In the game in the bonus state, as described above, the lottery for shifting to the ART is performed, and in the game in the bonus state, when the lottery for shifting to the ART is non-winning (when the transition condition (G) is satisfied). , The main control circuit 90 shifts the game state from the bonus state to the normal game state (normal game state or CZ). However, if the ART game state (normal ART or CT) has been shifted to the bonus state, the main control circuit 90 changes the game state even if the ART transition lottery is not won in the bonus state game. It shifts from the bonus state to the ART gaming state (normal ART or CT). On the other hand, in the game in the bonus state, if the lottery for the transition to the ART is won (the transition condition (H) is satisfied), the main control circuit 90 changes the game state from the bonus state to the ART game state (normal ART or CT). Move. As described above, at the end of the bonus state, the RT state shifts to the RT1 state. Therefore, when shifting the game state from the bonus state to the ART gaming state, the main control circuit 90 changes the gaming state to ART. Transition to the ART gaming state via the ready state.

<Structure of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 102 will be described with reference to FIGS. Note that various data tables used in various lottery related to game characteristics (CZ, normal ART, CT game characteristics) in the general game state and the ART game state will be described later together with the explanation of each game characteristic. ..

[Design placement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table, the position of each symbol in the respective rotation directions of the left reel 3L, the middle reel 3C, and the right reel 3R, and data for identifying the type of the symbol arranged at each position (hereinafter, symbol code (in FIG. 15) Refer to the symbol code table)))).

  In the symbol arrangement table, the position of the symbol located in the middle area of each reel in the frame of the reel display window 4 is defined as "0" when the reel index is detected. Then, in each reel, in the order of proceeding in the rotation direction of the reel (the direction from the symbol position "19" to the symbol position "0" in FIG. 15) with reference to the symbol position "0", the value of the symbol counter corresponds to " "0" to "19" are assigned to each symbol as symbol positions.

  That is, by referring to the value (“0” to “19”) of the symbol counter and the symbol arrangement table, the reels are displayed in the upper area, the middle area and the lower area of each reel in the frame of the reel display window 4. It is possible to specify the type of pattern that is present. In the present embodiment, as the design, "white 7", "blue 7", "chili top 1", "chili top 2", "chili bottom", "replay", "hat", "cactus 1", Ten types of designs, "Cactus 2" and "Cactus 3" are used.

  Further, in the present embodiment, as shown in the symbol code table, “00000001” is assigned as data to the symbol “white 7” (symbol code 1), and the symbol “blue 7” (symbol code 2), “00000010” is assigned as data. "00000011" is assigned as data to the symbol "Chili top 1" (symbol code 3), and "00000100" is assigned to data as the symbol "Chili top 2" (symbol code 4).

  The symbol “under Chile” (symbol code 5) is assigned “00000101” as data, and the symbol “Replay” (symbol code 6) is assigned “00000110” as data. "0000111" is assigned as data to the design "hat" (design code 7), and "00001000" is assigned to data as the design "cactus 1" (design code 8). Further, the symbol "Cactus 2" (symbol code 9) is assigned "00001001" as data, and the symbol "Cactus 3" (symbol code 10) is assigned "00001010" as data.

[Internal lottery table]
Next, with reference to FIG. 16 and FIG. 17, an internal lottery table that is referred to when determining an internal winning combination will be described. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. 17A is an internal lottery table referenced in the RT5 state, and FIG. 17B is an internal lottery table referenced in the bonus state.

  The internal lottery table is provided for each game state, and defines the correspondence relationship between various internal winning combinations and the lottery value when each internal winning combination is determined. The lottery value is defined for each setting (settings 1 to 6) for adjusting the preset expected value of the internal winnings such as a bonus combination and a small combination. This setting is changed using, for example, the reset switch 76 and the setting key type switch 54 (see FIG. 7).

  In the internal lottery process of the present embodiment, first, the random number register 0 of the random number circuit 110 assigns a random number value extracted from a predetermined numerical value range (for example, 0 to 65535) to each internal winning combination. The specified lottery value is added sequentially. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result overflows). Then, in the predetermined internal winning combination, if the lottery result exceeds 65535, it is determined that the internal winning combination has been won. In the internal lottery process of the present embodiment, an example of performing lottery by adding the lottery value to the extracted random number value has been described, but the present invention is not limited to this and subtracts the lottery value from the random number value. The winning / non-winning of the internal lottery may be determined by determining whether the subtraction result (lottery result) is less than “0” (whether the lottery result underflows).

  Therefore, in the internal lottery process of the present embodiment, the probability of being determined is higher for the internal winning combination having a larger numerical value defined as the lottery value. In addition, the winning probability of each internal winning combination can be represented by “lottery value defined for each winning number / the number of all random number values that may be extracted (random number denominator: 65536)”.

  In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, according to the type of the RT state, the type and the winning probability of the replay combination determined as the internal winning combination. Changes. For example, the replay combination associated with the names “F_Chililip (No. 25)” to “F_reach-eye lip D (No. 31)” is not determined as the internal winning combination in the RT0 state to the RT3 state, but in the RT4 state. Only determined as an internal winning combination. In the pachi-slot 1 of the present embodiment, the replay combination associated with the names “F_Chililip (No.25)” to “F_reach-eye lip D (No.31)” is determined as the internal winning combination during the RT4 state. In this case, specific control (flag conversion described later) is performed. This flag conversion will be described later in detail.

  In addition, as shown in FIG. 16, in the RT0 state to the RT3 state, the internal winning combinations of the names “F_reach eye lip A” to “F_reach eye lip D” are related to the name “F_BB1” or “F_BB2”. Although it may be decided in duplicate with the bonus combination (see Nos. 3 to 6 and 15 to 18), the internal winning combination (replay) of each of the names “F_reach eye lip A” to “F_reach eye lip D”. Role) is not determined as an internal winning combination alone. Therefore, in the present embodiment, when the replay combination associated with the names “F_reach eye lip A” to “F_reach eye lip D” is determined as the internal winning combination in the RT0 state to the RT3 state (from the player's perspective, When the symbol combination corresponding to the replay combination relating to "F_reach-eye lip A" to "F_reach-eye lip D" is displayed), the bonus combination (name "F_BB1" or "F_BB2") is simultaneously determined as the internal winning combination. Has been done.

  Further, the RT5 state, which is the state between flags, is a gaming state in which the bonus combination is carried over as an internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referred to in the RT5 state, the bonus combination carried over is always determined as the internal winning combination. Further, as shown in FIG. 17B, in the internal lottery table referred to in the bonus state, the internal winning combination associated with any of the names “F_RB winning combination 1” to “F_RB winning combination 4” is always won ( There is no chance of winning.

[Correspondence table between internal winning combination and symbol combination (winning symbol) (symbol combination determination table)]
Next, with reference to FIG. 18 to FIG. 23, a correspondence table (symbol combination determination table) between the internal winning combination and the symbol combination will be described. The symbol combination determination table defines the correspondence relationship between various internal winning combinations and the symbol combinations (combinations) that can be displayed on the activated line (center line) and are associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the activated line (the type of display combination that can be won) is uniquely determined.

  The various data described in the symbol combination column in each symbol combination determination table is for identifying the symbol combination which is allowed to be displayed along the activated line set across the left reel 3L, the middle reel 3C and the right reel 3R. The data. The relationship between each name described in the symbol combination (display combination) column and a specific symbol combination is shown in a winning operation flag storage area of FIGS. 28 to 30 described later.

  In addition, the mark “◯” described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the activated line in the determined internal winning combination, that is, a winning symbol. For example, when the internal winning combination “F_Chillilip” is determined, as shown in FIGS. 18 and 19, the combination names “C_maintenance lip A_01” to “C_maintenance lip G_01”, “C_chililip A_01” to “C_chililip” are selected. The symbol combination relating to “D_01” can be stopped and displayed. The symbol combination determination table does not define the case where the “internal winning combination” becomes “out”, but this is all symbols defined by the symbol combination table shown in FIGS. 18 to 23. Indicates that the display of combinations is not allowed.

  In the pachi-slot 1 of the present embodiment, the main control circuit 90 (main CPU 101) changes the stop control according to the internal winning combination and the game state, and when a predetermined winning combination is determined as the internal winning combination, The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the symbol combination (combination) having the correspondence relationship shown in FIG. 23 can be displayed. In addition, in the correspondence table shown in FIG. 18 to FIG. 23, all the symbol combinations that can be displayed for the determined internal winning combination are enumerated by “◯” marks, but the symbols marked with “◯” are listed. Even if it is a combination, it may not be displayed.

  In the present embodiment, there is a function of changing stop control (for example, a symbol to be preferentially drawn in) in accordance with a symbol combination that can be stopped and displayed or a current game state, and in terms of a symbol to be preferentially drawn in, "○" Even the marked symbol combination may not be displayed. The correspondence between the internal winning combination type and the symbol combination actually displayed will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between the winning combination in the non-flag state and the symbol combination that is stopped and displayed]
Here, with reference to FIG. 24, the correspondence relationship between the internal winning combination and the symbol combination that is stopped and displayed in the gaming state (non-flag state) excluding the flag state will be described. Note that FIG. 24 shows the correspondence relationship between various internal winning combinations that can be determined in the non-flag state and the symbol combination (abbreviation) that is stopped and displayed when determining each internal winning combination (some winning combinations are omitted). It is a figure. The name of the symbol combination described in FIG. 24 is the “abbreviation” described in the content column shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

  In the pachi-slot 1 of the present embodiment, a so-called "push order combination" is provided in which different symbol combinations are displayed depending on the order (pressing order) of stop operations by the player. Note that the symbol combination associated with the “press order correct answer” shown in FIG. 24 is a symbol combination that is advantageous to the player among the symbol combinations displayed according to the press order, and becomes “push order incorrect answer”. The associated symbol combination is a symbol combination that is disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous for the player, the correct pressing order is notified, and if the stop operation is performed in accordance with the notification, the symbol combination associated with the “correct pressing order” is displayed. In addition, even in the ART game state, an incorrect pressing order may be notified, the details of which will be described later.

  In addition, in the present embodiment, for some of the push order combinations, the correct push order is shown at the end of the name. Specifically, the last "1st" of the name of the internal winning combination means that the correct pressing order is that the first stop operation (first stop operation) is for the left reel 3L, The end "2nd" of the name of the internal winning combination means that the pushing order that is the correct answer is that the first stop operation is for the middle reel 3C, and the end "3rd" of the name of the internal winning combination is the correct answer. The pushing order means that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the correct push order is "left, middle, right", and the end "132" of the name of the internal winning combination is the correct answer. It means that the pushing order is "left, right, middle", and the last "213" of the name of the internal winning combination is that the correct pushing order is "middle, left, right". The end of the name of the internal winning combination “231” means that the correct pressing order is “left, right, middle”.

  Further, in the following, the stop operation order when the first stop operation is performed on the left reel 3L, specifically, the pressing order of "left, middle, right" and "left, right, middle" is referred to as " Also referred to as "press forward" Further, in the following, the stop operation sequence when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, "middle, left, right", "middle, right, left", The pressing order of "right, middle, left" and "right, left, middle" is also called "irregular pressing".

  In the present embodiment, as shown in FIG. 24, the internal winning combination “F_Chililip” is a push order combination in which different symbol combinations are displayed according to the pressing order, and when the pressing order is the correct answer, the abbreviation is “. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to “Cililip” (see FIG. 28 described later) is displayed along the activated line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) is along the activated line. Is displayed. When the internal winning combination “F_Chillilip” is determined, as shown in FIG. 18 to FIG. Or “two consecutive chililip”: corresponding to the abbreviation “Chillilip (no triple)” in FIG. 28 described later) can be displayed, but the combination name “C_chililip D_01” to “C_1 definite chililip D_01” (abbreviation) "Three consecutive chili lip": symbol combinations associated with the abbreviation "chili lip (three consecutive)" in FIG. 28 described later) cannot be displayed. In other words, the internal winning combination “F_Chiririp” is a role that cannot display the symbol combination related to the abbreviation “3 consecutive chilirips”.

  In addition, both the internal winning combination "F_ sure chiririp" and "F_1 sure chiririp" are push order combinations in which different symbol combinations are displayed according to the press order, and when the press order is correct, the abbreviation is "chiririp". Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) according to is displayed along the activated line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) is along the activated line. Is displayed. When the internal winning combination “F_probable chililip” or “F_1 probable chililip” is determined, as shown in FIGS. 18 to 23, the symbol combination related to the abbreviation “three consecutive chililip” can be displayed. That is, the internal winning combination "F_probable chililip" and "F_1 probable chililip" are the roles that can display the symbol combination related to the abbreviation "3 consecutive chilirips".

  Further, the internal winning combination "F_reach-eye lip A" to "F_reach-eye lip D" is a push order combination in which different symbol combinations are displayed according to the press order, and when the push order is correct, the abbreviations are used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIGS. 28 and 29 described later) related to the “reach eye lip” is displayed along the activated line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) is along the activated line. Is displayed.

  In the present embodiment, the internal winning combinations “F_chiririp”, “F_sure chiririp”, “F_1 sure chiripuripu” and “F_reach eye lip A” to “F_reach eye lip D” are pressed in the order of the correct answers at the time of winning. Is for performing a first stop operation on the left reel 3L. Therefore, for example, in the game in which the internal winning combination “F_reach-eye lip A” is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation “reach-eye lip” is given. The symbol combination concerned is stopped and displayed. Note that the present invention is not limited to this, and when the internal winning combination “F_chilirip”, “F_certain chililip”, “F_1 sure chililip” and “F_reach eye lip A” to “F_reach eye lip D” is won. The order of pushing the correct answers can be set arbitrarily.

  In addition, the internal winning combination “F_maintenance rep A” and “F_maintenance rep B” are both not the push order combination, and the figure of the symbol combination (see FIG. 28 described later) related to the abbreviation “Replay” regardless of the pressing order. Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the activated line.

  All of the internal winning combinations "F_maintenance rep_1st" to "F_maintenance rep_3rd" are push order combinations in which different symbol combinations are displayed according to the pressing order, and when the pressing order is correct, the abbreviations are used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) related to “Replay” is displayed along the activated line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “RT2 transition lip” (see FIG. 28 described later) is an effective line. Is displayed along with.

  Further, all of the internal winning combinations "F_RT3 Lip_1st" to "F_RT3 Lip_3rd" are push order combinations in which different symbol combinations are displayed according to the press order, and when the press order is correct, the abbreviation "RT3" is used. The symbol combination (see FIG. 28 described later) related to “migration lip” is displayed along the activated line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) is along the activated line. Is displayed.

  Further, all of the internal winning combinations "F_RT4 Lip_123" to "F_RT4 Lip_3rd" are push order combinations in which different symbol combinations are displayed according to the pressing order. When the pressing order is correct, the abbreviation "RT4" is used. The symbol combination (see FIG. 28 described later) related to “migration lip” is displayed along the activated line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) is along the activated line. Is displayed.

  All of the internal winning combinations "F_3 choice bell_1st" to "F_3 choice bell_1rd" are push order combinations in which different symbol combinations are displayed according to the push order, and when the push order is correct, the abbreviations are used. The symbol combination related to "bell" (see FIG. 19 described later) is displayed along the activated line. On the other hand, when the pressing order is not correct, a symbol combination relating to the abbreviation “bell spill” (see FIG. 28 described later) or a symbol combination relating to the abbreviation “first sheet” (see FIG. 30 described later) Is displayed.

  In addition, the internal winning combination "F_common bell" can be displayed as shown in Figs. 18 to 23 of the symbol combination (see Fig. 29 described later) related to the abbreviation "bell" regardless of the pressing order, not the pressing order combination. Any of the different symbol combinations is displayed along the activated line. In addition, the internal winning combinations “F_Sabo 1” and “F_Sabo 2” are not the push order combination, and are the same as those of the symbol combinations (see FIG. 30 to be described later) related to the abbreviation “Cactus” regardless of the pressing order. ~ Any of the displayable symbol combinations shown in Fig. 23 is displayed along the activated line.

  In addition, the internal winning combination "weak cherry" is not a press order combination, and can be displayed as shown in Figs. 18 to 23 of the symbol combination (see Fig. 30 described later) related to the abbreviation "weak cherry" regardless of the pressing order. Any of the different symbol combinations is displayed along the activated line. In addition, the internal winning combination "F_strong chili 1" and "F_strong chili 2" are not the push order combination, and are the symbol combinations related to the abbreviation "strong cherry" regardless of the pressing order (see FIG. 30 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the activated line.

[Correspondence between the winning combination in the inter-flag state and the symbol combination that is stopped and displayed]
Next, with reference to FIG. 25, the correspondence relationship between the internal winning combination and the symbol combination that is stopped and displayed in the inter-flag state will be described. Note that FIG. 25 is a diagram showing a correspondence relationship between the internal winning combination and the symbol combination that is stopped and displayed in the inter-flag state (some of the combinations are omitted), and in particular, the bonus combination during the inter-flag state ( It is a figure which shows whether the symbol combination (combination name "C_BB1" or "C_BB2") concerning BB combination can be displayed.

  In the correspondence table of FIG. 25, the "○" mark in the "BB establishment possibility" column indicates that the symbol combination related to the BB combination can be displayed, and the "x" mark indicates the symbol combination related to the BB combination. Indicates that cannot be displayed. When the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined as the internal winning combination overlapping with the bonus combination is displayed. For example, when the internal winning combination “F_BB1 + F_Cililip” is won (in the case where the internal winning combination “F_BB1” and the internal winning combination “F_Chililip” are won in a duplicated manner), as shown in FIG. 25, the internal winning combination “F_BB1”. It is not possible to stop and display the symbol combination related to “”, and the symbol combination related to the internal winning combination “F_Chillip” is stopped and displayed.

  Further, in the inter-flag state, when the symbol combination related to the BB combination cannot be displayed, and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described in FIG. 24 is performed. Only the symbol combination at the time of correct answer may be displayed, or only the symbol combination at the time of incorrect pressing order may be displayed.

  For example, when the internal winning combination “F_BB1 + F_3 choice bell_1st” is won, as shown in FIG. 25, it is not possible to stop and display the symbol combination related to the internal winning combination “F_BB1”. Therefore, the internal winning combination “F_3 choice bell_1st” is displayed. The symbol combination related to "is displayed in a stopped state, but at this time, only the symbol combination related to the abbreviation" Bell "that is displayed when the pressing order is correct can be displayed, and the abbreviation" bell spill "that is displayed when the pressing order is incorrect Alternatively, the symbol combination relating to “first page” may be made non-displayable (see FIG. 24). Further, for example, when the internal winning combination “F_BB1 + F_RT3 Lip_1st” is won, only the symbol combination related to the abbreviation “Replay” displayed when the pressing order is incorrect can be displayed, and the abbreviation “RT3” displayed when the pressing order is correct. The symbol combination relating to “transition lip” may not be displayed (see FIG. 24).

  In the inter-flag state, as shown in FIG. 25, the bonus winning combination (BB winning combination) and one of the internal winning combinations “off”, “F_special 1”, “F_special 2” and “F_special 3”. In the case of overlapping determinations, the symbol combination related to the BB combination can be stopped and displayed.

[Reel stop initial setting table]
Next, the reel stop initialization table will be described with reference to FIG. The reel stop initial setting table defines a correspondence relationship between an internal winning combination and various data used in a reel stop control process described later.

  The reel stop initialization table shown in FIG. 26 defines a correspondence relationship between an internal winning combination (small winning combination number), a pull-in priority table selection table number, a pull-in priority table number, and a stop table number. In addition, in FIG. 26, the game state to be referred to and the name of the internal winning combination are also described.

  The attraction priority table selection table number and attraction priority table number are data used in the attraction priority table selection processing. For example, if the pull-in priority table number corresponding to the stop table number is defined in the reel stop initialization table, it corresponds to the pull-in priority table number defined in the pull-in priority table (see FIG. 27 described later). It is possible to obtain data regarding the priority order of display combinations. On the other hand, if the attraction priority table number corresponding to the stop table number is not defined in the reel stop initialization table, the attraction priority table selection table (not shown) is referred to and the attraction priority table selection table number is set. The corresponding pull-in priority table number is determined.

  Here, the reel stop control (stop symbol position determination method) in the pachi-slot 1 of the present embodiment will be briefly described. In this embodiment, after the stop operation is detected by the stop switch, reel stop control is performed so that the rotation of the corresponding reel is stopped within 190 msec. Specifically, the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is added with one of the number of sliding symbols “0” to “4”, and the value is obtained. The symbol position is determined as a symbol position where the rotation of the reel stops (hereinafter, referred to as “scheduled stop position”). The symbol position corresponding to the value of the symbol counter corresponding to the reel when the stop operation is detected is the symbol position where the rotation of the reel starts to be stopped (hereinafter referred to as “stop start position”).

  That is, the number of sliding pieces is the amount of rotation of the reel after the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. In other words, it is the number of symbols passing through the middle region of the reel of the reel display window 4 in the period from when the stop operation is detected by the stop switch to when the rotation of the reel is stopped. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  With reference to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is tentative, and the obtained number of sliding pieces does not immediately determine the scheduled stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding pieces than the number of sliding pieces (hereinafter referred to as “slip piece number determination data”) acquired based on the stop table, a pull-in priority table (described later) 27), the number of sliding pieces is changed. Then, the number-of-slip-pieces determination data is referred to in order to determine the search order when comparing the priorities of the respective symbols from the stop start position to the symbol position which is the maximum number of four slides ahead.

[Importance priority table]
Next, the attraction priority table will be described with reference to FIG. The attraction-in priority table includes attraction-in data (award-action flag data) for each type of winning action flag storage area (see FIGS. 28 to 30 described later) in each of the attraction-priority table numbers “00” to “05”. ) And its predetermined priority order are defined.

  The pull-in priority table is used for searching whether or not there is a more appropriate number of sliding pieces in addition to the number of sliding pieces obtained based on the stop table (not shown). The priority order is data that defines the order in which the symbol combination (winning operation flag) related to winning a prize is preferentially stopped and displayed (pulled in). Further, in FIG. 27, for the sake of convenience of description, the combination name of the winning operation flag is described in the column of the winning data (winning operation flag data), but in the actual drawing priority table, each winning data is described below. As shown in the operation flag storage area (see FIGS. 28 to 30 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. ..

  In the reel stop control of this embodiment, first, the number of sliding pieces is acquired based on a stop table (not shown). However, if there is a more appropriate number of sliding pieces other than this number of sliding pieces based on the priority, the number of sliding pieces is changed to the appropriate number. That is, in the present embodiment, a more appropriate number of sliding pieces is determined based on the priority of the symbol combination that allows the stop display by the internal winning combination, regardless of the number of sliding pieces acquired from the stop table.

  In the present embodiment, the stop display of the symbol combination having the higher priority order (pull-in) is given priority over the stop display of the symbol combination having the lower priority order.

  Further, in the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) is different according to the attraction-in priority table number, but also the number of divisions of the priority is different. Specifically, when the attraction-in priority table number is "00", the number of divisions of the priority is set to 5, and when the attraction-in priority table number is "01" or "04", the priority ranking is set. The number of categories is set to 4. Further, when the attraction-in priority table number is “02” or “03”, the number of divisions of the priority is set to 2, and when the attraction-in priority table number is “05”, the number of divisions of the priority is Is 3.

  Here, the priority order when the attraction-in priority table number is “00” will be described, and the description of the priority order in the other attraction-in priority table numbers will be omitted. When the pull-in priority table number is “00”, the priority order “1” (highest priority order) includes the combination name “C_9 sheets A_01”, “C_1 sure Chile lip C_01”, “C_1 sure Chile lip D_01” and The pull-in data corresponding to "C_RT3 Rep_01" is defined.

  When the pull-in priority table number is “00”, the priority order “2” includes combination names “C_strong 2 sheets C_01” to “C_strong 2 sheets C_09”, “C_weak 2 sheets B_01” to “C_weak”. Corresponds to "2 sheets B_03", "C_3 sheets E_01", "C_3 sheets E_02", "C_9 sheets F_01" to "C_9 sheets F_03", "C_1 accurate Chile lip B_01", "C_ Chile lip D_01" and "C_ Chile lip C_01". The pull-in data is specified.

  When the pull-in priority table number is "00", the priority "3" includes the combination names "C_1 reliable Chile A_01", "C_ Chile Lip A_01", "C_ Chile Lip B_01", and "C_maintenance Lip E_01" to "C_maintain Lip E_01". The pull-in data corresponding to “C_maintenance rep E_04” is defined.

  When the pull-in priority table number is “00”, the priority order “4” includes combination names “C_SP1_01”, “C_SP2_01”, “C_reach eye lip P_01”, “C_reach eye lip P_02”, and “C_reach”. Eye lip O_01 "," C_reach eye lip O_02 "," C_reach eye lip N_01 "," C_reach eye lip N_02 "," C_reach eye lip M_01 "," C_reach eye lip M_02 "," C_reach eye lip " L_01 ”to“ C_reach eye lip L_03 ”,“ C_reach eye lip K_01 ”to“ C_reach eye lip K_03 ”,“ C_reach eye lip J_01 ”,“ C_reach eye lip I_01 ”to“ C_reach eye lip I_09 ”. , "C_reach eye lip H_01" to "C_reach eye lip H_03", "C_reach eye lip G_01" , "C_reach eye lip F_01", "C_reach eye lip F_02", "C_reach eye lip E_01", "C_reach eye lip D_01", "C_reach eye lip D_02", "C_reach eye lip C_01" to "C_reach eye lip D_02" C_reach eye lip C_03 "," C_reach eye lip B_01 "," C_reach eye lip B_02 "," C_reach eye lip A_01 "," C_maintenance lip F_01 "," C_maintenance lip F_02 "," C_maintenance lip D_01 " "-C_maintenance rep D_04", "C_maintenance rep C_01"-"C_maintenance rep C_03", "C_maintenance rep B_01", "C_maintenance rep B_02" and pull-in data corresponding to "C_maintenance rep A_01" are defined. To be done.

  When the attraction-in priority table number is "00", the attraction-in data corresponding to the combination names "C_BB1" and "C_BB2" is defined in the priority "5" (the lowest priority).

<Structure of storage area provided in main RAM>
Next, with reference to FIGS. 28 to 35, the configuration of various storage areas provided in the main RAM 103 will be described.

[Hit request flag storage area and winning action flag storage area]
First, the configurations of the hit request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIGS. 28 to 30. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (winning flag data storage area) have the same configuration.

  In the present embodiment, the hit request flag storage area is composed of hit request storage areas 0 to 11 each represented by 1-byte data, and the winning operation flag storage area is each winning operation represented by 1-byte data. It is composed of storage areas 0 to 11. Note that the data stored in each of the hit request flag storage area and the winning operation flag storage area is only 1-byte data in the “data” column in FIGS. 28 to 30, but in FIGS. For convenience of explanation, a symbol combination of each reel is associated with a bit of each storage area (in the drawing, a symbol of the left reel 3L, a symbol of the middle reel 3C, and a symbol of the right reel 3R are described in this order), The name (combination name) and abbreviation, and the number of paid-out medals are also described.

  In each of the hit request flag storage areas 0 to 11, when "1" is stored in a predetermined bit, it indicates that the internal winning combination corresponding to the predetermined bit has been internally won. Further, in each of the winning operation storage areas 0 to 11, when "1" is stored in a predetermined bit, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit has won. That is, when "1" is stored in the predetermined bit, it indicates that various symbol combinations of the internal winning combination corresponding to the predetermined bit are displayed on the activated line.

  Further, in the hit request flag storage area and the winning operation flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some have. That is, for such a flag, it means that there are a plurality of symbol combinations (combinations that can be won) that can be stopped and displayed.

  For example, in bit 5 of the hit request storage area 5 and the winning action storage area 5, the symbol combination “cactus 2”-“white 7”-“hat” (combination name “C_maintenance lip C_01”), the symbol combination “cactus 2” -"Chilli on 1"-"Hat" (combination name "C_Maintenance Lip C_02"), and pattern combination "Cactus 2"-"Cactus 2"-"Hat" (combination name "C_Maintenance Lip C_03") Three symbol combinations are assigned. Therefore, when "1" is stored in bit 5 of the hit request storage area 5, it indicates that these three symbol combinations can be stopped and displayed on the activated line. When "1" is stored in bit 5 of the winning operation storage area 5, it indicates that any one of these three symbol combinations is displayed on the activated line.

[Carry-over combination storage area]
Next, with reference to FIG. 31, the structure of the internal carryover combination storing area will be described. In this embodiment, the internal carryover combination storage area is composed of a 1-byte data storage area.

  As a result of the internal lottery, when the internal winning combination “F_BB1” or “F_BB2” is determined, the internal winning combination (BB combination) is stored in the carryover combination storing area as a carryover combination. The carryover combination stored in the carryover combination storing area is held without being cleared until the corresponding symbol combination is displayed on the activated line. Further, while the carryover combination is stored in the carryover combination storing area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

[Game status flag storage area]
Next, with reference to FIG. 32, the configuration of the game state flag storage area will be described. The game status flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, a unique bonus type or RT type is assigned to each bit of the game state flag storage area.

  When "1" is stored in the predetermined bit in the game state flag storage area, it indicates that the bonus game or the RT corresponding to the predetermined bit is being operated. For example, when "1" is stored in bit 0 of the game state flag storage area, the operation of the big bonus "BB" is performed, which indicates that the game state is the BB game state. Further, for example, when "1" is stored in bit 3 of the game state flag storage area, it indicates that the game state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operating state of the stop button is assigned to each bit.

  For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, "1" is stored in bit 0 of the operation stop button storage area. Further, for example, when the left stop button 17L is a stop button that has not been pressed yet, that is, a valid stop button, "1" is stored in bit 4. The main CPU 101 discriminates the stop button pressed this time and the stop button not pressed yet based on the data stored in the operation stop button storage area.

[Pressing order storage area]
Next, with reference to FIG. 34, the configuration of the pressing order storage area will be described. The pressing order storage area is composed of a 1-byte data storage area and stores a pressing order flag of 1 byte.

  In the press order flag, the type of the stop button press order is assigned to each bit. For example, if the pressing order of the stop buttons is "left, middle, right", "1" is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In the present embodiment, the symbol code storage area is composed of symbol code storage areas 0 to 11 each represented by 1-byte data. The symbol code storage area has the same structure as the hit request flag storage area and the winning operation flag storage area (see FIGS. 28 to 30).

  In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the activated line. After all reels are stopped, the symbol codes corresponding to the display combination (winning operation flag) are stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various sub-flags]
In the general gaming state and the ART gaming state, various data tables are referred to in various lottery by the main control circuit 90. As parameters used in this case, not only the internal winning combination but also the internal winning combination is used in this embodiment. Various parameters having different names (hereinafter, referred to as "sub-flag (first sub-flag)", "sub-flag EX (second sub-flag)" and "sub-flag D") are also used. Therefore, in the present embodiment, the main control circuit 90 performs a process of converting the internal winning combination into various sub-flags (see sub-flag conversion process, flag conversion process, sub-flag compression process in FIG. 104 described later). In the present embodiment, as the information (communication parameter) regarding the internal winning combination, the sub flag is set in the start command and transmitted from the main control circuit 90 to the sub control circuit 200.

  Here, with reference to FIG. 36 and FIG. 37, the correspondence relationship between the internal winning combination and various sub-flags will be described. FIG. 36 is a diagram showing a correspondence relationship between an internal winning combination (small winning combination number) and various sub-flags, and FIG. 37 is a diagram showing a correspondence relationship between an internal winning combination (special winning number) and sub-flags.

  In the flag conversion processing of this embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one sub-flag. In this embodiment, as a result of this flag conversion process, as shown in FIG. 36, 32 types of internal winning combinations (small winning numbers) related to small winning combinations and replay winning combinations are 18 types of sub-flags (“01” to “18”). : Flag data). For example, the internal winning combinations “F_Maintain Lip_1st (10: Small Winning Number)” to “F_Maintain Lip_3rd (12)” are grouped into a sub-flag “Press Order Lip 1 (09: Flag Data)”. The sub-flag “Loss (00)” is assigned to the internal winning combination “out”.

  Further, in the flag conversion processing of the present embodiment, as shown in FIG. 36, 19 types of sub-flags (“00” to “18”) including the sub-flag “Loss (00)” are changed to nine types of sub-flags EX (“00 To "08": flag data). Therefore, in this conversion process, the sub-flag data can be further compressed. At this time, in this embodiment, the sub-flag is converted into the sub-flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

  The sub-flag "Loss (00)" is converted into the sub-flag EX "Loss (00)" regardless of the result of the flag conversion lottery, and the sub-flag "2 consecutive chilirip (01)" is regardless of the result of the flag conversion lottery. The sub-flag EX is converted to "replay (01)".

  If the sub-flag “3 consecutive Chile Lips A (02)” and the sub flag “3 consecutive Chile Lips B (03)” are won in the flag conversion lottery (in the case of “with conversion” described later), the sub flag EX “Definite Winner (06)” Alternatively, when the flag conversion lottery is converted into “three consecutive re-rips (07)” and the flag conversion lottery is non-win (in the case of “no conversion” described later), the sub flag EX is converted into “replay (01)”.

  If the sub-flags "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are won in the flag conversion lottery, they are converted into sub-flags EX "determining hand (06)" or "reach eye lip (08)". When the flag conversion lottery is non-win, the sub-flag EX is converted to “replay (01)”.

  The sub-flags "replay (08)" and "push-order rep 1 (09)" to "push-order rep 3 (11)" are converted into sub-flags EX "replay (01)" regardless of the result of the flag conversion lottery. The sub-flags “push order bell (12)” and “common bell (13)” are converted to the sub-flag EX “bell (02)” regardless of the result of the flag conversion lottery.

  The sub-flags “cactus (14)”, “weak cherry (15)”, and “strong cherry (16)” are sub-flags EX “cactus (03)” and “weak cherry (04)”, regardless of the result of the flag conversion lottery. And “strong cherry (05)”. Further, the sub-flags "reach eye 1 (17)" and "reach eye 2 (18)" are converted into the sub-flag EX "miss (00)" regardless of the result of the flag conversion lottery.

  As described above, in the present embodiment, substantially, the sub-flags “three consecutive Chilelip A (02)”, “three consecutive Chilelip B (03)” and “reach eye lip 1 (04)” to “reach eye lip 4 (07). ) ”Is the target of the flag conversion lottery. The lottery table used for the above-mentioned flag conversion lottery will be described in detail later.

  Furthermore, in the flag conversion processing of the present embodiment, as shown in FIG. 36, nine types of sub-flags EX (“00” to “08”) are converted into seven types of sub-flags D (“00” to “06”). It Therefore, in this conversion process, the sub flag data can be further compressed. In this conversion process, lottery is not performed, and the sub-flag EX and the sub-flag D are associated with each other and converted as follows.

  The sub flags EX “Loss (00)”, “Replay (01)”, and “Bell (02)” are converted into sub flags D “Loss (00)”. The sub flag EX “cactus (03)” is converted to the sub flag D “cactus (01)”, the sub flag EX “weak cherry (04)” is converted to the sub flag D “weak cherry (02)”, and the sub flag EX “strong”. "Cherry (05)" is converted to the sub-flag D "Strong cherry (03)".

  Further, the sub-flag EX “determined hand (06)” is converted to the sub-flag D “determined hand (04)”, and the sub-flag EX “3 consecutive chili lip (07)” is converted to the sub flag D “3 consecutive chili lip (05)”. Then, the sub-flag EX “reach-eye lip (08)” is converted into the sub-flag D “reach-eye lip (06)”.

  Further, in the flag conversion processing of the present embodiment, as shown in FIG. 37, both of the internal winning combinations “F_BB1 (01: special winning number)” and “F_BB2 (02)” are converted into sub-flags “BB”. ..

[Playability at the time of sub-flag EX conversion]
Here, the process of the process of converting the above-mentioned internal winning combination into the sub flag and the sub flag EX, and an example of the game characteristic at the time of converting the sub flag EX will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination “F_probable Chilelip” or “F_1 probable Chilelip” is determined, and FIG. 38B is an internal winning combination “F_reach eye lip A” to “F_”. It is a figure which shows the flag conversion process when either of the reach eye lip D "is determined.

  In the pachi-slot 1 of the present embodiment, any one of the internal winning combinations “F_probable chililip”, “F_1 probable chililip” and “F_reach eye lip A” to “F_reach eye lip D” is independently played during the RT4 game state. When the internal winning combination is determined by, the flag conversion lottery is performed. Then, in the present embodiment, when the flag conversion lottery is won, a special privilege (for example, addition of the number of ART games or CT winning) is given.

  For example, when the internal winning combination “F_certain Chilelip” or “F_1 certain Chilelip” is determined, as shown in FIG. 38A, the internal winning combinations “F_certain Chilelip” and “F_1 certain Chilelip” are sub-flags “three consecutive”, respectively. Chillirip A (02) "and" three consecutive Chillirip B (03) ".

  Next, when the sub-flags "3 consecutive chili lip A (02)" and "3 consecutive chili lip B (03)" are won in the flag conversion lottery, the sub flag EX "3 consecutive chili lip (07)" or "determining hand (06)" is obtained. To be converted. On the other hand, when the flag conversion lottery is non-win, both the sub-flags “three consecutive chili-rips A (02)” and “three consecutive chili-rips B (03)” are converted to the sub-flag EX “replay (01)”. ..

  As described with reference to FIG. 24, when the internal winning combination “F_Sure Chillirip” or “F_1 Sure Chillirip” is won, the symbol combination related to the abbreviation “3 consecutive Chillirip” is displayed when the correct answer is in the push order, and the push order is incorrect. At the time of correct answer, the symbol combination related to the abbreviation “Replay” is displayed. Therefore, in the present embodiment, when the internal winning combination “F_certain Chilelip” or “F_1 certain Chilelip” is determined and the flag conversion lottery is won, the internal winning combinations “F_certain Chilelip” and “F_1 certain Chilelip”. Are treated as a combination of the sub-flag EX “three consecutive chiripuripu (07)” or “determined winning combination (06)”.

  When the internal winning combination “F_probable chililip” or “F_1 probable chililip” is converted into the sub-flag EX “3 consecutive chililip (07)” or “determined winning combination (06)” in this flag conversion process, the abbreviation “3 consecutive Information for displaying the symbol combination relating to "Chililip" is notified (for example, information indicating that the player can press the Chile pattern by pushing forward) is notified. On the other hand, in the flag conversion process, when the flag conversion lottery is non-winning and the internal winning combination “F_probable chililip” or “F_1 probable chililip” is converted to the sub-flag EX “replay (01)”, it is abbreviated to “replay”. Information for displaying such a symbol combination is notified (for example, a pressing order other than the normal pressing (irregular pressing) is notified).

  Further, for example, when any of the internal winning combinations "F_reach-eyes lip A" to "F_reach-eyes lip D" is determined, as shown in FIG. 38B, the internal winning combinations "F_reach-eyes lip A"-" The F_reach-eye lip D'is converted into sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)", respectively.

  Next, when the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are won in the flag conversion lottery, the sub-flag EX is changed to "reach-eye lip (08)" or "determining hand (06)". To be converted. On the other hand, when the flag conversion lottery is non-win, the sub-flags "reach eye rep 1 (04)" to "reach eye rep 4 (07)" are converted to the sub flag EX "replay (01)".

  As described in FIG. 24, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won, the symbol combination related to the abbreviation “reach eye lip” when the correct answer is in the pushing order. Is displayed, and the symbol combination related to the abbreviation “Replay” is displayed when the pressing order is incorrect. Therefore, in the present embodiment, when one of the internal winning combinations “F_reach-eye lip A” to “F_reach-eye lip D” is determined and the flag conversion lottery is won, the internal winning combination “F_reach-eye” is obtained. All of the “lip A” to “F_reach eye lip D” are handled as the sub flag EX “reach eye lip (08)” or “determined hand (06)”.

  Then, when the internal winning combination “F_reach-eye lip A” to “F_reach-eye lip D” is converted into, for example, the sub-flag EX “reach-eye lip (08)” or “determined hand (06)” by this flag conversion process. , Information for displaying the symbol combination relating to the abbreviation “reach eye lip” is notified (for example, information indicating that the player can press the symbol “white 7” by pressing forward) is notified. On the other hand, in the flag conversion process, when the flag conversion lottery is non-winning and the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is converted to the sub flag EX “replay (01)”, the abbreviation is given. Information for displaying the symbol combination related to "replay" is notified (for example, a pressing order other than the normal pressing (irregular pressing) is notified).

  Further, in the present embodiment, in the flag conversion process shown in FIG. 38A or 38B, if the player performs the stop operation according to the notification after winning the flag conversion lottery, the abbreviation “3 consecutive chiripuripu” or “reach eye lip” The symbol combination is stopped and displayed on the activated line, and a special privilege is given. In the process of this granting, in effect, the pachi-slot 1 gives a special privilege to the player in accordance with the fact that the pachi-slot 1 wins the flag conversion lottery, but for the player, the abbreviation "3" is given. It is possible to feel that a special privilege has been given by displaying the symbol combination related to "Renchiririp".

  In order to improve the pachislot's playability, it may be preferable that the appearance frequency of the symbol combination to which the privilege is given is different depending on the state, rather than being constant. Stop control (displayed symbol combination) is different depending on the type of internal winning combination, so as a method of changing the appearance frequency of the symbol combination to which the privilege is given according to the state, the winning probability of the internal winning combination is made different. A method can also be considered (in Pachi-slot 1, since the winning probability of the internal winning combination can be made different depending on whether the bonus is activated or the RT state, for example, only the RT4 state is set as the RT state corresponding to the ART gaming state. Instead, a method of providing other RT states such as RT6 state and RT7 state is also conceivable. However, since the triggers for changing the winning probabilities of the internal winning combinations (the transition triggers for the RT state) are limited, this method lacks flexibility from the viewpoint of improving the game play (entertainment).

  On the other hand, in the pachi-slot 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination without changing the winning probability of the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed. , It is possible to flexibly change the appearance frequency of the symbol combination to which the privilege is given according to the state. That is, in a state where it is easy to win the flag conversion lottery, it is possible to increase the appearance frequency of the symbol combination to which the privilege is given, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given. The frequency can be reduced.

<Playability during general gaming state>
Next, with reference to FIGS. 39A to 39C, the flow of the game in the general game state will be described. In the pachi-slot 1 of the present embodiment, during the general gaming state, the gaming state shifts from the normal gaming state to CZ, and then the gaming state shifts from CZ to the ART gaming state, so that the general gaming state (non-ART gaming state ) To the ART gaming state (see FIGS. 14A and 14B).

  FIG. 39A is a diagram showing a flow of a game when the game state shifts from the normal game state to the CZ during the normal game state. As shown in FIG. 39A, the normal gaming state has a low-probability state and a high-probability state as a lottery state of CZ. The low-probability state and the high-probability state are states in which expectations of winning the CZ lottery that are performed in the normal gaming state are different from each other, the low-probability state is a state in which it is difficult to win the CZ lottery, and the high-probability state is CZ. It is in a state where it is easy to win the lottery. When the CZ lottery performed in the game in the normal game state is won, the game state shifts from the normal game state to CZ.

  In the pachi-slot 1 of the present embodiment, a plurality of chance zones “CZ1”, “CZ2”, and “CZ3” are provided as CZ (chance zones). CZ1 to CZ3 are chance zones with different expectations for winning the ART lottery performed in the game during CZ, CZ3 is a chance zone that is sure to win the ART lottery, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In the CZ lottery performed in the game in the normal game state, not only the winning / non-winning of the CZ but also the type of the CZ to be transferred at the time of winning (one of CZ1 to CZ3) is determined (see FIG. 41 described later).

  FIG. 39B is a diagram showing a game flow when the game state shifts from the general game state CZ1 and CZ2 to the ART game state. Both CZ1 and CZ2 are composed of a first half and a second half. The first half is a period during which the rank of the expectation to win the ART lottery performed in the game during CZ is promoted, and the second half is the predetermined lottery result of the ART lottery based on the rank (in the present embodiment, the character (Battle production by).

  In CZ1, six rank modes (modes 1 to 6) are prepared, and the higher the mode, the higher the expectation of winning the ART lottery. In the first half of CZ1, a game is continuously played for a period of a first predetermined number of games (for example, 12 games at maximum), and a mode promotion lottery is performed based on an internal winning combination. Then, in the first game of the second half of CZ1, the ART lottery is performed based on the mode promoted in the first half (the mode at the end of the first half).

  Further, in CZ2, 10 stages of points are prepared as ranks, and the higher the points, the higher the expectation of winning the ART lottery. In the first half of CZ2, a game is continuously played for a period of a second predetermined number of games (for example, 15 games at the maximum), and a lottery for promotion of points is performed based on an internal winning combination. Then, in the first game of the second half of CZ2, the ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

  In the latter half of CZ1, a battle effect in which a teammate character and an enemy character A compete is performed, and in the latter half of CZ2, a battle effect in which a teammate character and an enemy character B compete. This battle effect is performed over the game for the period of the third predetermined number of games (for example, 4 games at the maximum). In addition, the win / loss of the battle effect is managed (determined) based on the result of the ART lottery. When the ART lottery is won, the ally character wins the battle effect, and when the lottery is not won, the battle is won. The enemy character wins in the production.

  In addition, in each of the second half of CZ1 and CZ2 (during battle production), the ART lottery is performed based on each game and the internal winning combination. Then, if this ART lottery is won, the result of the battle effect is rewritten. For example, when a so-called “rare” combination is determined as an internal winning combination during the battle effect, the ART lottery is performed, and the result of the battle effect is rewritten based on the result.

  In CZ1 and CZ2, in the case of not winning the ART, the player loses the battle effect in the latter half of the game, and basically the game state thereafter shifts to the normal game state. On the other hand, in CZ1 and CZ2, when the player wins the ART, the player wins in the battle effect in the second half, and then the game state shifts from CZ to the normal ART via the ART preparation state. In the present embodiment, in the game of the first half of CZ1 and CZ2, a freeze may occur, and in that case, the game state goes from CZ to the ART preparation state, and not CT (addition) Chance zone).

  FIG. 39C is a diagram showing a flow of a game when the game state shifts from CZ3 in the normal game state to the ART game state. CZ3 is played continuously for a period of a fourth predetermined number of games (for example, 17 games at maximum). Then, in the CZ3, the ART lottery is performed based on the internal winning combination in each game.

  The CZ3 ends at the time when the ART lottery is won, and after the next game, the game state shifts from the CZ3 to the CT (additional chance zone) via the ART preparation state. Further, in CZ3, a freeze may occur, and even in that case, the game state shifts from CZ3 to CT (additional chance zone) from the CZ3 via the ART preparation state. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 has passed without winning the ART lottery, the game state shifts from CZ3 to the normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state has been confirmed.

<Various data tables used during general gaming>
Next, with reference to FIG. 40 to FIG. 45, various data tables used in the lottery process relating to the game property performed in the general game state will be described. Various data tables described below are stored in the main ROM 102.

  Further, in the various data tables shown below, the lottery value information is conceptually shown. “0” in the data table means that the lottery value corresponding to the winning probability “0%” is defined, and “very low” indicates the lottery corresponding to the winning probability “0% to less than 1%”. It means that the value is defined, and “extremely low” means that the lottery value corresponding to the winning probability “1% to less than 10%” is defined. "Low" in the data table means that the lottery value corresponding to the winning probability "10% to less than 30%" is defined, and "middle" means the winning probability "30% to less than 60%". It means that the lottery value corresponding to “” is defined, and “High” means that the lottery value corresponding to the winning probability “60% to less than 80%” is defined. Further, "extremely high" in the data table means that the lottery value corresponding to the winning probability "80% to less than 99%" is defined, and "extremely high" means the winning probability "99% to 100%". The lottery value corresponding to "less than%" is defined, and the "determined" means that the lottery value corresponding to the winning probability "100%" is defined.

  Then, in the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts random numbers for lottery extracted from a predetermined range of numerical values (0 to 65535) by the specified lottery values. , The internal lottery is performed by determining whether the result of the subtraction is negative (whether a so-called “carry” has occurred). In addition, in the present embodiment, an example in which the lottery value is subtracted from the random number for lottery in the lottery process regarding the game property performed in the general gaming state to determine the winning / non-winning is described, but the present invention is not limited to this. Instead, the lottery value is added to the extracted random number for lottery, and it is determined whether or not the addition result exceeds 65536 (whether so-called "overflow" has occurred) and the winning / non-winning is determined. Good.

[Normal Medium / High Probability Lottery Table]
First, with reference to FIGS. 40A and 40B, the normal medium-high probability random determination table used in the transfer random determination of the CZ random determination state (low probability and high probability) will be described. In addition, in the pachi-slot 1 of the present embodiment, not only is the transition lottery of the CZ lottery state performed based on each game and the internal winning combination, but, for example, when the bonus is finished or the CZ or ART is finished, The transfer lottery in the lottery state is performed. FIG. 40A is a configuration diagram of a normal medium / high probability random determination table that is referred to for each game in the normal game state, and FIG. 40B is a normal medium / high level that is referred to when, for example, a setting is changed, when a bonus ends or when CZ, ART ends. It is a block diagram of a probability lottery table. The name of the internal winning combination shown in FIG. 40A corresponds to the name of the sub-flag described above.

  The normal medium / high probability random determination table shown in FIG. 40A shows each combination of the current CZ random determination state and the internal winning combination, the random determination result (low probability / high probability) of the CZ random determination state after the transition, and each random determination result. The correspondence relationship with the associated lottery value information is defined.

  As is clear from the normal medium / high probability random determination table shown in FIG. 40A, when the current CZ random determination state has a low probability, when the internal winning combination is the combination corresponding to the sub-flag “weak cherry”, The lottery state is likely to shift to a high probability. On the other hand, when the current CZ lottery state has a high probability, when the internal winning combination corresponds to one of the sub-flags “common bell”, “cactus”, “weak cherry” and “strong cherry” In addition, the lottery state of CZ is maintained with high probability.

  The normal medium / high probability random determination table shown in FIG. 40B includes each situation when referring to the table, the random determination result (low probability / high probability) in the random determination state of CZ after the transition, and the random determination associated with each random determination result. The correspondence with the value information is specified. As is clear from the normal medium / high probability lottery table shown in FIG. 40B, the lottery state of CZ always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, the CZ lottery table used in the CZ lottery will be described with reference to FIGS. 41A and 41B. FIG. 41A is a configuration diagram of a CZ lottery table used when performing a CZ lottery based on an internal winning combination during a normal game state, and FIG. 41B is a pullback of the CZ when the CZ fails or the ART ends, for example. It is a block diagram of a CZ lottery table used when performing CZ lottery whether or not to perform. The name of the internal winning combination shown in FIG. 41A corresponds to the name of the sub-flag described above.

  The CZ lottery table shown in FIG. 41A is a lottery associated with each combination of the current lottery state of the CZ and the internal winning combination, the winning / non-winning of CZ1, CZ2, and CZ3 (lottery result), and each lottery result. The correspondence with the value information is specified. As is clear from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state is in the high probability, the CZ lottery is won more than when the current CZ lottery state is in the low probability. The probability increases.

  The CZ lottery table shown in FIG. 41B has a correspondence relationship between winning / non-winning (lottery results) of CZ1, CZ2, and CZ3 and lottery value information associated with each lottery result at the time of CZ failure or ART end. Stipulate. At the time of CZ failure (at the time of non-winning in the ART lottery in CZ1 and CZ2) and at the end of the ART gaming state, the pullback lottery of the CZ is performed using this CZ lottery table.

[Mode up lottery table during CZ1]
Next, with reference to FIG. 42, a CZ1 middle mode up lottery table used in the CZ1 mode up lottery performed in the first half of the CZ1 will be described. FIG. 42 is a configuration diagram of a CZ1 medium mode up lottery table. The name of the internal winning combination shown in FIG. 42 corresponds to the name of the sub-flag described above.

  The CZ1 medium mode up lottery table has a correspondence relationship between each combination of the current mode and the internal winning combination, the result of the mode up lottery (winning / non-winning), and the lottery value information associated with each lottery result. Stipulate. As shown in FIG. 44A, which will be described later, in CZ1, the higher the mode (the higher the value of the mode), the higher the probability of winning the ART lottery, and when the mode rises to Mode 6, the ART lottery is surely won.

  The lottery result “mode 1UP” in FIG. 42 means that the mode of CZ1 is increased by one step, and the lottery result “mode 2UP” means that the mode of CZ1 is increased by two steps. Therefore, for example, in a situation where the current mode is mode 2, if the lottery result “mode 2UP” is won, the mode of CZ1 is increased from mode 2 to mode 4. In addition, for example, when the lottery result “mode 6UP_freeze occurrence” is won, a freeze occurs and the winning of the ART lottery and the grant of CT are determined.

[Point lottery table in CZ2]
Next, with reference to FIG. 43, a CZ2 middle point lottery table used in the CZ2 point-up lottery performed in the first half of the CZ2 will be described. FIG. 43 is a configuration diagram of a CZ2 medium point lottery table. The name of the internal winning combination shown in FIG. 43 corresponds to the name of the sub-flag described above.

  The CZ2 medium point lottery table shows the correspondence between each combination of the current points and the internal winning combination, the result of the point-up lottery (winning / non-winning), and the lottery value information associated with each lottery result. Stipulate. As shown in FIG. 44B, which will be described later, in CZ2, the higher the number of points, the higher the probability of winning the ART lottery, and when the number of points reaches “point 10,” the ART lottery is surely won. The lottery result “point 2UP” in FIG. 43 means that “2” is added to the current CZ2 point, and for example, in the situation where the current point is “2”, the lottery result “ If you win "Point 2UP", the point of CZ2 will increase from "2" to "4". In addition, for example, when the winning of the lottery result “Point 10UP_freeze occurrence” is won, a freeze occurs and the winning of the ART lottery and the grant of CT are determined.

[ART lottery table in CZ]
Next, the CZ in-art ART lottery table used in the ART lottery executed in the CZ will be described with reference to FIGS. Note that FIG. 44A is a configuration diagram of the CZ middle ART lottery table (for CZ1) used in the first game of the second half of CZ1, and FIG. 44B is the CZ middle ART used in the first game of the second half of CZ2. FIG. 44C is a configuration diagram of the lottery table (for CZ2), and FIG. 44C is a configuration diagram of the CZ mid ART lottery table (for both CZ1 and CZ2, during the second half battle) used in the second half of CZ1 and CZ2. In addition, FIG. 45 is a configuration diagram of the CZ in-art ART lottery table (for CZ3) used in the ART lottery executed in CZ3. The names of the internal winning combinations shown in FIGS. 44C and 45 correspond to the names of the sub-flags described above.

  The CZ ART lottery table (for CZ1) shown in FIG. 44A defines the correspondence relationship between the current mode, the ART lottery result (whether or not there is a lottery), and the lottery value information associated with each lottery result. .. The CZ ART lottery table (for CZ2) shown in FIG. 44B shows the correspondence between the current point, the ART lottery result (whether the lottery is won), and the lottery value information associated with each lottery result. Stipulate.

  As is clear from the CZ ART ART lottery table (for CZ1) and the CZ ART ART lottery table (for CZ2), the higher the rank (mode or point) of the first half of CZ1 and CZ2, the easier it is to win the ART lottery.

  The CZ ART ART lottery table (for both CZ1 and CZ2, during the second half battle) shown in FIG. 44C has an internal winning combination, an ART lottery result (whether or not there is a lottery), and lottery value information associated with each lottery result. Stipulate the correspondence relationship of. As is clear from the CZ ART ART lottery table (common to CZ1 and CZ2 during the second half battle), in the second half of CZ1 and CZ2, a rare role (a role corresponding to the subflag “weak cherry”, “cactus”, or “strong cherry”) ) Is determined as the internal winning combination, the ART lottery is won with a predetermined probability.

  The CZ ART ART lottery table (for CZ3) shown in FIG. 45 is a combination of each combination of the number of CZ3 digestion games and an internal winning combination, an ART lottery result (whether or not there is a lottery), and a lottery associated with each lottery result. The correspondence with the value information is specified. As is clear from the CZ ART ART lottery table (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Playability during normal ART>
Next, with reference to FIGS. 46A and 46B, a game flow during the game ART will be described. In the pachi-slot 1 of the present embodiment, as described above, the normal ART and CT are provided as the ART game state (see FIGS. 14A and 14B), and the CT is used as an additional chance zone. Therefore, in this embodiment, the player plays the game during the normal ART aiming at the transition to CT.

[Mode of transition from normal ART to CT]
FIG. 46A is a diagram showing a mode of transition of a game state from normal ART to CT. In the pachi-slot 1 of the present embodiment, as shown in FIG. 46A, when the CT lottery performed during the normal ART is won, the gaming state shifts from the normal ART to the CT. In the pachi-slot 1 of the present embodiment, as shown in FIG. 46A, an ART level and a CT lottery state are provided as parameters that affect various lottery normally performed during ART.

  As the ART level, four levels of level 1 to level 4 are provided, and the ART level is controlled (determined) mainly based on the number of continuous (digest) games during the normal ART. Then, the ART level influences the determination of the CT lottery state and the flag conversion lottery during the normal ART described later.

  As the CT lottery state, there are four stages of low-probability, normal, high-probability and ultra-high-probability states, and the CT lottery state is mainly controlled based on the ART level and an internal winning combination during normal ART ( It is determined. Then, the CT lottery state affects CT lottery performed during normal ART, flag conversion lottery during normal ART described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachi-slot 1 of the present embodiment, during the RT4 state, that is, during the ART game state, the internal winning combination “F_certain chililip”, “F_1 sure chililip” and “F_reach eye lip A” to “F_”. If any one of the reach eyes Lip D ”is independently determined as an internal winning combination, a flag conversion lottery is performed, and a special privilege (for example, addition of the number of ART games or CT winning) is given according to the lottery result. .. FIG. 46B is a diagram showing an outline of the method of the flag conversion lottery performed during the normal ART.

  In the present embodiment, as shown in FIG. 46B, flag conversion lottery is performed during normal ART with reference to the ART level and the CT lottery state. As a result, when winning the flag conversion lottery, a special privilege is given, and a symbol combination related to the abbreviation "3 consecutive chili lip" or a symbol combination related to the abbreviation "reach eye lip" is stopped and displayed on the activated line. A navigation for making the information (for example, notification of information that a predetermined symbol is aimed at by pressing the normal button) is performed. On the other hand, when the flag conversion lottery is non-win, the navigation for stopping and displaying the symbol combination related to the abbreviation “Replay” on the activated line (for example, notification of the pressing order other than the normal pressing) is performed.

  Then, when the player performs a stop operation according to this notification (navi), a symbol combination corresponding to the content of the notification is stopped and displayed on the activated line. Specifically, when winning in the flag conversion lottery, a symbol combination related to the abbreviation "3 consecutive chili lip" or a symbol combination related to the abbreviation "reach eye lip" is stopped and displayed on the activated line, and is not included in the flag conversion lottery. In the case of winning, the symbol combination related to the abbreviation “Replay” is stopped and displayed on the activated line.

<Various data tables used during normal ART>
Next, various data tables used in the lottery process during the normal ART will be described with reference to FIGS. 47 to 51. Various data tables described below are stored in the main ROM 102.

[ART flag conversion lottery table]
47A and 47B are block diagrams of an ART flag conversion lottery table used in the flag conversion lottery performed during normal ART.

  In the pachi-slot 1 according to the present embodiment, the flag conversion lottery during normal ART is performed in two stages. Specifically, when the internal winning combination “F_probable chiririp” or “F_1 probable chilirip” is won, first, the flag conversion lottery in the first stage is performed, and when the flag conversion lottery in the first stage is won, The flag conversion lottery in the second stage is performed. When the second-stage flag conversion lottery is won, the internal winning combination “F_probable chililip” or “F_1 probable chililip” is converted into the sub-flag EX “three consecutive chililip”. On the other hand, when the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-win, the internal winning combination “F_probable chililip” or “F_1 probable chililip” is converted to the sub-flag EX “replay”. (Handle as a normal replay role). If any of the internal winning combinations “F_reach-eye lip A” to “F_reach-eye lip D” is won, only the flag conversion lottery in the second stage is performed.

  FIG. 47A is a block diagram of an ART medium flag conversion lottery table used in the first-stage flag conversion lottery, and FIG. 47B is a block diagram of the ART medium flag conversion lottery table used in the second-stage flag conversion lottery. is there.

  The flag conversion lottery table during ART shown in FIG. 47A has an internal winning combination (“F_probable chilirip” or “F_1 probable chililip”) and a lottery result of the first-stage flag conversion lottery (no conversion / conversion (temporary)). And the lottery value information associated with each lottery result are defined.

  In the ART flag conversion lottery table shown in FIG. 47B, each combination of the internal winning combination, the ART level, and the CT lottery state, the lottery result (no conversion / conversion) of the second-stage flag conversion lottery, and each lottery result The relationship with the lottery value information associated with is defined. In addition, in the game until the player wins the CT once in the normal ART, the table of the “first time (until the player wins the CT once)” column of the item “ART level” in FIG. 47B is referred to.

  In the present embodiment, as shown in FIGS. 47A and 47B, in the flag conversion lottery in the second stage and the stage in which each of the ART flag conversion lottery tables is used, the random number value (0 to 0) with the probability denominator being “256”. 255) is used to carry out the lottery. Therefore, in the present embodiment, the above-described two-stage flag conversion lottery can be regarded as the lottery substantially the same as the one-time lottery using the random number value having the probability denominator of “65536”.

  In the recent pachi-slot, the lottery (ART lottery, etc.) related to the payout, which has conventionally been performed on the sub control board 72 side (hereinafter, referred to as “sub side”), is performed on the main control board 71 side (hereinafter, referred to as “main side”). Is required to do. However, since the capacity of the storage means (main ROM 102) on the main side is limited to a small capacity, there is a demand for a mechanism that enables lottery without impairing game play while suppressing an increase in processing capacity.

  In this regard, in the pachi-slot 1 of the present embodiment, the lottery with the probability denominator of “256” is performed in two stages, so that the lottery with the probability denominator of “65536” can be performed. It is possible to suppress an increase in capacity on the side. In the second stage lottery, since the ART level, the CT lottery state, etc. are referred to, not only the internal winning combination but also the flag conversion lottery according to the current state can be performed, and as a result, a variety of game play can be achieved. The flag conversion lottery you have can be performed.

[ART level determination table]
48A and 48B are configuration diagrams of an ART level determination table used when determining an ART level. The ART level determination processing is performed during the ART winning when it is decided to shift to the ART gaming state and during the normal ART. FIG. 48A is a configuration diagram of an ART level determination table used at the time of winning an ART, and FIG. 48B is a configuration diagram of an ART level determination table used during a normal ART.

  The ART level determination table shown in FIG. 48A defines a correspondence relationship between ART levels 1 to 4 (lottery result) and lottery value information associated with each ART level. In the present embodiment, if the freeze occurs at the time of winning the ART, the ART level 2 is determined as the ART level.

  The ART level determination table shown in FIG. 48B is a lottery associated with each combination of the current ART level and the number of elapsed (digest) games of the normal ART, each transfer destination ART level, and each transfer destination ART level. The correspondence with the value information is specified. Further, the ART level determination table shown in FIG. 48B is associated with each combination of the current ART level and the number of elapsed games of the normal ART at the time of entering the CT, various ART levels of the transfer destination, and each ART level of the transfer destination. It defines the correspondence relationship with the information of the lottery value. That is, in the normal ART, not only the ART level can be shifted at the timing when the number of elapsed (digest) games of the normal ART reaches the predetermined number of games, but also the ART level is changed at the timing when the CT is entered during the normal ART. It becomes possible to transfer.

[Normal ART medium / high probability lottery table]
FIG. 49 is a configuration diagram of a normal ART medium / high probability random determination table used when determining the CT random determination state during the normal ART.

  The normal ART medium-high probability random determination table shows a correspondence relationship between each combination of the current CT random determination state and the internal winning combination, various CT random determination states of the transfer destination, and the information of the random determination value associated with each CT random determination state. Stipulate. The name of the internal winning combination shown in FIG. 49 corresponds to the name of the sub-flag described above.

  As can be seen from the normal ART medium / high probability random determination table, the internal winning combination corresponding to the sub-flag "3 consecutive chilirips (3 consecutive chililip A and 3 consecutive chililip B)" and the subflag "reach eye lip (reach eye lip 1 to 4)" When it is won, the CT lottery state easily shifts (falls) to “low probability”. However, as shown in FIG. 50, which will be described later, when the internal winning combination corresponding to the sub-flag “3 consecutive chiripuripu” or “reach eye lip” is winning, even if the CT lottery state falls, CT It is designed to always win the lottery.

[CT lottery table during ART]
FIG. 50 is a configuration diagram of a CT lottery table during ART used in CT lottery performed during normal ART.

  The CT lottery table during ART is a combination of each of the current CT lottery state and the internal lottery, various lottery results of CT lottery (non-win / normal CT / high probability CT), and lottery associated with each lottery result. The correspondence with the value information is specified. The name of the internal winning combination shown in FIG. 50 corresponds to the name of the sub-flag described above.

  In the present embodiment, as the internal winning combination, sub-flags “cactus”, “weak cherry”, “strong cherry”, “three consecutive chililip (three consecutive chililip A and three consecutive chililip B)”, “reach eye lip (reach eye lip) 1 to 4) ”or“ BB ”is determined, in the CT lottery process using the CT lottery table during ART, the CT lottery using the random number value in the range where the probability denominator is“ 256 ”. Is done. If an internal winning combination other than these winning combinations is determined as the internal winning combination (for example, a combination corresponding to the sub-flags “replay”, “common bell”, “push order bell”, etc.), CT in ART In the CT lottery process using the lottery table, the CT lottery is performed using a random number value in the range where the probability denominator is “65536”.

  In the pachi-slot 1 of the present embodiment, two types of CT called “normal CT” and “high probability CT” are provided as CT. The expectation of the number of ART games to be added in CT (additional chance zone) is different between the normal CT and the high-probability CT, and the high-probability CT is a CT in which a larger number of ART games are more easily added than the normal CT. (See FIG. 55 described later).

[Addition lottery table during normal ART]
FIG. 51 is a configuration diagram of a normal ART mid-game additional lottery table used in the extra lottery of the ART games played during the normal ART. The name of the internal winning combination shown in FIG. 51 corresponds to the name of the sub-flag described above.

  The normal lottery table during ART defines the correspondence relationship between the internal winning combination, the various lottery results of the additional lottery (non-win / additional 10G to 300G), and the lottery value information associated with each lottery result.

<Game play during CT>
Next, with reference to FIGS. 52A to 52C, a game flow during CT will be described. 52A and 52B are diagrams mainly showing an outline of the game flow during CT when the sub-flag EX “3 consecutive chilirip” is won, and FIG. 52C shows an outline of flag conversion processing performed during CT. It is a figure.

[Game contents during CT]
In the pachi-slot 1 of the present embodiment, in CT, a set of eight games (eight games) is played. During the CT period, an additional lottery is performed for each game based on the internal winning combination. When the additional lottery is won, the unit game number (the number of games) of the CT game is not subtracted. On the other hand, when the additional lottery is non-win, the unit game number of the CT game (game Number) is subtracted. Therefore, during the CT period, CT does not end in a game in which the number of ART games has been added, and CT ends if a game in which the number of ART games is not added is executed eight times in the same set. ..

  Further, in the present embodiment, as shown in FIGS. 52A and 52B, when the sub-flag EX “three consecutive chilirips” is won during the CT period, that is, the internal winning combination “F_certain chililip” or “F_1 certain chililip” is won. And, and, if the flag conversion lottery is won, the CT game of 1 set 8 times is reset (stock). Then, the set of the CT game that is reset (stock) is started after the set of the CT game is finished.

  For example, CT is ended when a CT game in which the number of ART games is not added is played once after a unit game which is a non-winning lottery in addition to the number of ART games in the same set is played once, but in this game If the sub-flag EX “3 consecutive chiririp” has been won, the CT game is reset. As a result, after the CT game is reset, the CT will not be finished until the unit game which is the non-winning lottery in the number of ART games is played eight times. Therefore, the CT game period becomes longer as the sub-flag EX "3 consecutive chilirip" is won.

[Flag conversion during CT]
Next, with reference to FIG. 52C, a method of the flag conversion lottery performed during CT will be described. As described above, in the present embodiment, if the sub-flag EX “3 consecutive chilirips” is won during the CT period (the internal winning combination “F_probable chililip” or “F_1 probable chililip” is won, and the flag conversion lottery is won. Then, CT is reset (stock). Further, as shown in a flag conversion lottery table during CT of FIG. 54, which will be described later, when the internal winning combination “F_probable chilirip” or “F_1 probable chililip” is won during CT, the flag conversion lottery is surely won (the sub-flag EX “ It will always be converted to "Triple Chilelip"). That is, in the present embodiment, if the internal winning combination “F_probable chililip” or “F_1 probable chililip” is won during CT, the CT is always reset.

  In addition, in the flag conversion lottery in the case where any one of the internal winning combinations “F_reach-eyes lip A” to “F_reach-eyes lip D” is won, the flag is converted based on three types of flag conversion tables (tables 0-2). The winning probability of conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table that has the lowest probability of being converted into the sub-flag EX “reach-eye lip”, and table 1 is converted into the sub-flag EX “reach-eye lip”. The flag conversion table has the next lowest probability, and Table 2 is the flag conversion table having the highest probability of being converted into the sub-flag EX “reach eye lip”. If the sub-flag EX “reach-eye lip” is won during CT, a new CT is given as shown in a later-explained lottery table for the number of sets in CT in FIG. 56.

  Further, in the present embodiment, in normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high-probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, various data tables used in the lottery process performed during CT will be described with reference to FIGS. 53 to 56. Various data tables described below are stored in the main ROM 102.

[CT lottery table during CT]
FIG. 53 is a configuration diagram of a CT table lottery table used when determining a table used for the flag conversion lottery from the three-stage flag conversion table (tables 0 to 2).

  The CT table lottery table shows the correspondence relationship between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and the lottery value information associated with each type. Stipulate. The CT table lottery table is referred to when it is determined to win the CT lottery and shift to CT, or when the CT is started.

[CT flag conversion lottery table]
FIG. 54 is a configuration diagram of a CT flag conversion lottery table used in the flag conversion lottery performed during CT.

  The flag conversion lottery table during CT is an internal winning combination (one of “F_probable chilirip”, “F_1 probable chililip” and “F_reach eye lip A” to “F_reach eye lip D”) and each flag conversion table ( The correspondence relationship between the lottery result (no conversion / conversion) of the flag conversion lottery in Tables 0 to 2) and the lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination “F_Sure Chiririp” or “F_1 Sure Chiririp” is won during CT, the flag conversion lottery is surely won (always in the sub-flag EX “3 consecutive chiririp”). Converted).

[Addition lottery table during CT]
FIG. 55 is a configuration diagram of the extra lottery table during CT used in the additional lottery of the ART games performed during CT.

  The additional lottery table during CT is associated with each combination of the current CT state and the internal winning combination, various lottery results of additional lottery (non-win / additional 10 games /.../ additional 300 games), and each lottery result. The correspondence with the lottery value information is defined. The name of the internal winning combination shown in FIG. 55 corresponds to the name of the sub-flag described above, and when a winning combination other than the internal winning combination (sub-flag) shown in FIG. 55 is internally won, the additional lottery in CT is won. There is nothing to do.

  In addition, in the additional lottery during the normal CT of the present embodiment, the addition mode of the number of additional games changes depending on the number of winnings of the sub-flag “3 consecutive chillips” (internal winning combination “F_probable chillip” or “F_1 probable chillip”). To do.

  Specifically, when the number of winnings of the sub-flag “three consecutive chiririp” in the same CT set is 1 to 8, the lottery results “additional_10G” and “additional_20G” shown in FIG. 55 are given. The number of additional games is 10 and 20 respectively. Therefore, in this case, it is easy to determine 10 games as the number of games to be added to ART. Further, when the number of times the sub-flag “three consecutive Chilelip” is won in the same CT set is 9 to 16, the additional game given by the lottery results “additional_10G” and “additional_20G” shown in FIG. 55. Both will be 20 games. That is, the number of additional games (lottery result) corresponding to the lottery value “extremely high” of the sub-flag “three consecutive chiririp” in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games are easily determined as the number of games to be added to ART.

  Further, when the number of times the sub-flag “three consecutive Chilelip” is won in the same CT set is 17 to 24, the additional game given by the lottery results “additional_10G” and “additional_20G” shown in FIG. 55. Both will be 30 games. That is, the number of additional games (lottery result) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “three consecutive chiririp” in FIG. 55 is promoted to 30 games. Therefore, in this case, it is easy to determine “30 games” as the number of games to be added to ART. Further, when the number of winnings of the sub-flag “three consecutive chilirips” in the same CT set is 25 or more, the number of additional games given by the lottery results “additional_10G” and “additional_20G” shown in FIG. 55. Will be 50 games each. That is, the number of additional games (lottery result) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “three consecutive chiririp” in FIG. 55 is promoted to 50 games. Therefore, in this case, it is easy to determine “50 games” as the number of games to be added to the ART.

  As described above, in the pachi-slot 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one additional lottery according to the number of times of winning the sub-flag “3 consecutive chiririp” in CT. Further, as described above, in the present embodiment, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX “3 consecutive chilirip” is won, the CT is reset (stock). Is done. Therefore, in the present embodiment, as the CT continues, the player can be expected to increase the additional amount per game, and the interest during the CT can be improved. In addition, since the number of times of winning the sub-flag “3 consecutive chilirips” that triggers an increase in the amount to be added per game is a number (9 times or more) that is greater than the basic number of games (8 times) for one CT set, the player It is possible to prevent an excessive profit from being given to the player, and it is possible to balance the profit between the player and the game store.

  In the present embodiment, the number of winnings of the sub-flag “three consecutive chilirips” (internal winning combination “F_certain chililip” or “F_1 certain chililip”) described above is the number of times counted in the same CT set. The present invention is not limited to this. For example, a new CT given when a lottery is performed in addition to the number of sets performed during CT may be included in “during the same CT set”.

[Additional lottery table in CT]
FIG. 56 is a configuration diagram of a CT lot number addition lottery table used in CT lot addition lottery performed during CT.

  The number of sets to be added to the lottery table in CT is a combination of each of the current CT state and an internal winning combination (sub-flag “reach eye lip (reach eye lip 1 to 4)”) and various lottery results of the additional lottery (non-win / normal). (CT winning / high-probability CT winning) and the lottery value information associated with each lottery result are defined.

  As is clear from the lottery table with the number of sets in CT added, if any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won during CT, the lottery will be won in addition to the CT set. (CT sets are always stocked). It should be noted that the stocked CT set is started after the CT set currently in operation is completed.

<Playability in bonus state>
Next, with reference to FIGS. 57A to 57C, the flow of the game in the bonus state will be described. FIG. 57A is a diagram showing the flow of the game when the game state shifts to the bonus state during the general game state (ART non-win), and FIG. 57B shows the case where the game state shifts to the bonus state during the normal ART. FIG. 57C is a diagram showing the flow of the game in FIG. 57C, and is a diagram showing the flow of the game when the game state shifts to the bonus state during CT.

  Note that, in the pachi-slot 1 of the present embodiment, as shown in FIGS. 57A to 57C, in terms of playability, a normal BB and a special BB are provided as bonus types, and the bonus type is determined when shifting to the bonus state. To be done. At this time, if the special BB is determined, the game state shifts to CT after the bonus state ends via the ART preparation state. On the other hand, when the normal BB is determined, the game state of the transfer destination differs depending on the state before the transfer to the bonus state.

  When the game state shifts from the normal game state to the normal BB, as shown in FIG. 57A, in the game during the normal BB, the ART lottery is performed based on the internal winning combination. When this ART lottery is won, the game state shifts to the normal ART via the ART preparation state after the bonus state ends. In this case, in the game in the bonus state after winning the ART lottery, the lottery in addition to the number of ART games is performed.

  When the gaming state shifts from the normal ART to the normal BB, the CT lottery is performed at the end of the normal BB, as shown in FIG. 57B. The winning probability of this CT lottery is 50%, and when the winning is won, the gaming state shifts to CT via the ART preparation state after the bonus state ends. On the other hand, if the CT lottery is non-win, the game state shifts to the normal ART via the ART preparation state after the bonus state ends. In addition, in the game in the bonus state shifted from the normal ART, an additional lottery for the number of ART games is also performed.

  When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, after the bonus state ends, the gaming state shifts to CT via the ART preparation state. In addition, in the game in the bonus state which has been transferred from CT, the lottery in addition to the number of ART games is also performed.

<Various data tables used in games in bonus state>
Subsequently, various data tables used in the lottery process performed in the game in the bonus state will be described with reference to FIGS. 58 to 60. Various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type lottery table used when determining a bonus type (normal BB, special BB).

  The bonus type lottery table shows each game state (CT and other) before shifting to the bonus state, various lottery results (bonus type: normal BB / special BB), and lottery values associated with each lottery result. It defines the correspondence with information. The bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[Lottery table with bonus ART games added]
FIG. 59 is a configuration diagram of a bonus lottery number addition lottery table used in ART lottery and ART game number addition lottery performed in the game in the bonus state.

  The bonus lottery table for bonus ART games is associated with each combination of the current bonus type and the internal lottery, various lottery results of the additional lottery (non-winning / five games /.../ 300 games), and each lottery result. It defines the correspondence relationship with the information of the lottery value.

  In the present embodiment, in the ART non-winning state (the state until the winning in the ART lottery in the normal BB after the shift from the general game state), the bonus lot ART game number addition lottery table is used for the ART lottery. Specifically, when the number of additional games to be added is determined by lottery using the lottery table for adding ART number during bonus in the non-winning ART state, the number of additional games to be added is determined (50 or more in the example shown in FIG. 59). The lottery is won, and the corresponding number of games is given as the number of ART games. On the other hand, in the state after the winning of the ART, the lottery table for adding bonus ART games is used only for the additional lottery of ART games.

[CT lottery table at end of bonus]
FIG. 60 is a configuration diagram of a bonus lot end CT lottery table used in the CT lottery performed at the end of the bonus state.

  At the end of bonus CT lottery table, each combination of the bonus type (normal BB, special BB) and the game state (during normal CT, high probability CT) before shifting to the bonus state, and various lottery results of CT lottery ( The non-win / normal CT win / high probability CT win) and the lottery value information associated with each lottery result are defined. As is clear from the CT lottery table at the end of the bonus, for example, when the normal BB is performed during the normal ART, the CT is won at the probability of 50% at the end of the bonus state.

<Exceptional game play in the general game state>
Next, with reference to FIG. 61, an exceptional game flow in the normal game state will be described.

  In the flow of the basic gaming state in the pachi-slot 1 of the present embodiment, the gaming state shifts from the normal gaming state to CZ during the general gaming state, and the gaming state shifts to the ART gaming state by winning the ART lottery in CZ. To do. Then, in the present embodiment, the ART gaming state is realized by notifying in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, the transition control of the RT state is performed according to the symbol combination that is stopped and displayed.

  Note that the symbol combination for shifting the RT state is one that is stopped and displayed according to the player's stop operation sequence (pushing sequence) (see FIG. 24), so there is no notification. Even by accident, the RT state may shift to the RT4 state. Further, in the RT4 state, there is a possibility that any of the internal winning combinations “F_reach-eyes lip A” to “F_reach-eyes lip D” may be determined. Therefore, even in the general gaming state (non-ART), Reach eyes (symbol combination related to abbreviated "reach eye lip") to which a special privilege is given can be displayed.

  Therefore, in the pachi-slot 1 of the present embodiment, as shown in FIG. 61, the RT state accidentally shifts to the RT4 state during the general game state (non-ART), and the symbol combination relating to the abbreviation "reach eye lip" can be displayed. In such a state, the game state can be transferred to the ART game state (normal ART) without going through the CZ.

  More specifically, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined in the general game state and the RT4 state, the flag conversion lottery is performed, If the winning of the flag conversion lottery is won, a notification (navigation) for displaying the symbol combination related to the abbreviation "reach eye lip" is given and the right of ART is granted. On the other hand, in the general game state, and when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined during the RT4 state, if the flag conversion lottery is non-win, The notification for displaying the symbol combination related to the abbreviation "Replay" is performed, and the control is performed so that the symbol combination related to the abbreviation "Reach eye lip" is not displayed.

<Various data tables used in exceptional game control during general game state>
Next, with reference to FIG. 62, a data table used in the lottery process performed in the exceptional game control during the above-mentioned general game state will be described. The data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in the flag conversion lottery performed in the game in the normal game state and the RT4 state.

  The non-ART flag conversion lottery table shows the internal winning combination (“F_reach eye lip A” to “F_reach eye lip D”), the lottery result of the flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence relationship with the associated lottery value information is defined.

<Notification function by control on the main side>
In the conventional pachi-slot, information (navigation) of reel stop operation information (navigation order, etc.) is given by control on the sub (sub control board 72) side during ART. However, since the presence or absence of this notification affects the profit of the player (so-called payout), in recent years, the main (main control board 71) side that manages the profit of the player is required to make the notification. There is. Therefore, in the pachi-slot 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying the information of the stop operation, and by the control on the main side, A function of notifying information of the reel stop operation is provided.

  Here, in FIGS. 63A to 63D, in the pachi-slot 1 of the present embodiment, the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side is shown. Note that FIG. 63A is a diagram showing a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side in the ART preparation state, and FIG. 63B is during ART (normal ART or CT). FIG. 6 is a diagram showing a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side in FIG. Also, FIG. 63C is a diagram showing a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side in the RT5 state (between BB1 flags), and FIG. 63D is in the RT5 state. It is a figure which shows the correspondence of the notification (navi) performed by the main side and the notification (navi) performed by the sub side in (between BB2 flags).

  In this embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, the information of the reel stop operation is notified by displaying the numerical values of “1” to “11” on the instruction monitor. To do. The numerical values of "1" to "11" displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

  Specifically, the numerical values “1” to “3” respectively indicate the types of reels on which the first stop operation is performed, and the numerical value “1” means that the first stop operation is performed on the left reel 3L. However, the numerical value "2" means that the first stop operation is performed on the middle reel 3C, and the numerical value "3" means that the first stop operation is performed on the right reel 3R.

  Further, the numerical values “4” to “9” respectively indicate the pressing order informing, and the numerical value “4” means that the pressing order is “left, middle, right”, and the numerical value “5”. Means that the pressing order is "left, right, middle", numerical value "6" means that the pressing order is "middle, left, right", and numerical value "7" is The order is "middle, right, left", the numerical value "8" means that the pressing order is "right, left, middle", and the numerical value "9" is the pressing order. This means "right, middle, left" in that order.

  Further, the numerical values “10” and “11” respectively notify the bonus combination, and the numerical value “10” is the symbol combination (symbol “white 7” -symbol “white 7” -related to the combination name “C_BB1”. The symbol "white 7") is meant, and the numerical value "11" means the symbol combination (symbol "blue 7" -symbol "blue 7" -symbol "blue 7") related to the combination name "C_BB2".

  It should be noted that the numbers "1" to "11" notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, but all the players are clear based on the values. It is not always possible to understand the content of the notification. For example, there is a possibility that the player may not be able to comprehend the content of the notification just by displaying the numerical value "6" on the instruction monitor on the main side.

  Therefore, in the pachi-slot 1 of the present embodiment, in addition to the notification on the main side, information on the stop operation of the stop button is also notified on the sub side. Specifically, the display device 11 (the projector mechanism 211 and the display unit 212) controlled on the sub side is used to notify the information of the stop operation by the control on the sub side.

  For example, when notifying the pushing order of performing the first stop operation on the left reel 3L, the numerical value "1" is displayed on the instruction monitor on the main side, and the left reel in the display screen of the display device 11 is displayed on the sub side. The numerical value "1" is displayed above 3L to notify that the left reel 3L is the target of the first stop operation. Further, when notifying the pressing order "middle, left, right", the numerical value "6" is displayed on the instruction monitor on the main side, and the numerical value is displayed above the middle reel 3C in the display screen of the display device 11 on the sub side. "1" is displayed, the numerical value "2" is displayed above the left reel 3L, and the numerical value "3" is displayed above the right reel 3R. With this display, the pressing order is "middle, left, right". Is notified. When the internal winning combination “F_BB1” is determined, the main side displays the numerical value “10” on the instruction monitor, and the sub side displays “white 7”-“white 7” on the display screen of the display device 11. -Display the information about the symbol combination of "white 7" to inform the player of the symbol to be aimed at.

  The timing of notification on the main side can be set to any timing as long as it is at least one game period for notification. For example, the main side may be notified at the timing when the player's start operation is detected (accepted), the main side may be notified at the start of rotation of the reel, or the first stop operation to the third stop operation. The main side may be notified at the timing when any one of the stop operations is detected. On the other hand, it is preferable that the sub-side informs at least before the first stop operation. Therefore, in the pachi-slot 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or when the reel starts rotating. As a result, before the player performs the stop operation, the stop operation information is notified on both the instruction monitor on the main side and the display device 11 on the sub side.

  In the ART preparation state, as shown in FIG. 63A, by the control on the main side, notifications (navigation) called "bell navigation", "maintenance lip navigation", "RT3 transition lip navigation" and "RT4 transition lip navigation" are performed. In “Bernavi”, when the internal winning combination “F_3 choice bell_1st” to “F_3 choice bell_3rd” is determined, the symbol combination (see FIG. 29) related to the abbreviation “Bell” is stopped and displayed on the activated line. The pressing order of is notified. In "Maintenance Lip Navi", when the internal winning combination "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" is determined, the symbol combination (see FIG. 28) related to the abbreviation "Replay" is stopped and displayed on the activated line. The push order for is notified. In "RT3 transition Lip Navi", when the internal winning combination "F_RT3 transition Lip_1st" to "F_RT3 transition Lip_3rd" is determined, the symbol combination (see FIG. 28) relating to the abbreviation "RT3 transition Lip" is displayed on the activated line. The pressing order for the stop display is notified. Further, in the "RT4 transition Lip Navi", when the internal winning combinations "F_RT4 transition Lip_123" to "F_RT4 transition Lip_3rd" are determined, the symbol combination (see FIG. 28) relating to the abbreviation "RT4 transition Lip" is activated line. The pressing order for stopping and displaying the upper part is notified.

  Also, in the ART game state (normal ART or CT), as shown in FIG. 63B, by the control of the main side, a notification called "bell navigation", "maintenance lip navigation", "RT3 transition lip navigation" and "RT4 transition lip navigation" (Navi) is performed. In addition, the game in the ART game state (RT4 state), the flag conversion lottery is performed, and based on the lottery result, the symbol combination related to the abbreviation "3 consecutive chili lip", "reach eye lip" or "replay" is displayed. The pressing order for the notification is notified, but this notification is performed only on the sub side and not on the main side.

  As described above, since the symbol combination relating to the abbreviation “3 consecutive chili lip” or “reach eye lip” is related to the granting of a special privilege, the presence or absence of the notification influences the profit (ball payout) of the player. Although it seems to give, actually, in the pachi-slot 1 of the present embodiment, since the special privilege is given based on the lottery result of the flag conversion lottery, the displayed symbol combination is a privilege to be given. It does not affect it. Therefore, for example, even if the symbol combination related to the abbreviation “Replay” is stopped and displayed in the state where the flag conversion lottery is won, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation “three consecutive chili lip” or “reach eye lip” can be stopped and displayed in a state where the flag conversion lottery is not won, no special privilege is given. In the pachi-slot 1 of the present embodiment, when the symbol combination displayed in this way does not affect the player's profit (ball payout), it is controlled on the sub side without giving a notification on the instruction monitor on the main side. Notification is performed only on the display device 11.

  In addition, in the RT5 state (state between flags), as shown in FIGS. 63C and 63D, information that makes the player aim a symbol combination related to a bonus combination carried over as an internal winning combination is notified. For example, when the internal winning combination “F_BB1” is carried over, as shown in FIG. 63C, the notification (navi) called “white 7 navigation” is performed by the control of the main side, and the internal winning combination “F_BB2” is performed. 63D is carried over, a notification (navigation) called "blue 7 navigation" is performed by the control on the main side, as shown in FIG. 63D.

  In "White 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB1", that is, the symbol combination related to the combination name "C_BB1" ("White 7"-"White 7"-"White 7": see FIG. 28) Information of a stop operation for stopping and displaying the “” on the activated line is notified. In "Blue 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB2", that is, the symbol combination ("Blue 7"-"Blue 7"-"Blue 7") associated with the combination name "C_BB2": The information of the stop operation for stopping and displaying (see) is displayed on the activated line.

  In the inter-flag state, when the bonus combination and any one of the internal winning combinations “off”, “F_special 1”, “F_special 2” and “F_special 3” are determined, as described in FIG. 24. The symbol combination related to the bonus combination (BB combination) can be stopped and displayed on the activated line. However, if the internal winning combination other than the internal winning combination “off”, “F_special 1”, “F_special 2” and “F_special 3” and the bonus combination are won, the symbol combination relating to the bonus combination Cannot be stopped and displayed on the active line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the carried-over bonus combination and the internal winning combination “out”, “F_special combination 1”, “F_special combination 2” and “F_special combination”. Only when either "3" is winning, the notification called "white 7 navigation" or "blue 7 navigation" is performed by the control on the main side. Therefore, in the present embodiment, the notification (navi) called "white 7 navi" or "blue 7 navi" under the control of the main side can be performed at an appropriate timing when the bonus combination can be won.

  The pachi-slot 1 of the present embodiment is also provided with a function of giving a bonus notification by, for example, displaying a bonus confirmation screen or turning on a bonus confirmation lamp. Therefore, the main side may perform the navigation called "white 7 navigation" or "blue 7 navigation" only after notifying that the bonus combination is determined as the internal winning combination (bonus notification).

  As the bonus notification, for example, an effect is generally performed over a plurality of game periods (so-called continuous effect), and an effect of displaying a bonus confirmation screen according to the result of the continuous effect is generally performed. There is. If "white 7 navigation" or the like is performed on the main side during such continuous production, the result of the continuous production may be known on the way, which may spoil the interest. Therefore, in the present embodiment, the main control board 71 performs a notification (navigation) called "white 7 navi" or "blue 7 navi" by the control on the main side after the bonus notification is given.

  It should be noted that any method can be used so that the main side can grasp the timing at which the bonus notification is made. As one of the methods, when the bonus combination is determined as the internal winning combination, the main control board 71 determines the number of games required until the bonus notification ends, and after the game of this number of games is exhausted, the “white 7 navigation” or A method of giving notification (navigation) called "blue 7 navi" can be considered. More specifically, when the main control board 71 determines the number of games required until the end of the bonus notification, the main control board 71 notifies the sub-control board 72 of the number of games. The sub-control board 72 controls the effect according to the number of games, and displays the bonus confirmation screen at the timing when the game of the number of games has been exhausted, thereby grasping the timing at which the bonus notification is made on the main side. You can That is, the main control board 71 counts the number of unit games after determining the bonus combination as the internal winning combination in the state where the bonus combination is not carried over, and after the count result reaches a predetermined number, the bonus combination is performed. When any of the internal winning combinations “out”, “F_special winning combination 1”, “F_special winning combination 2”, and “F_special winning combination 3” is determined as the internal winning combination, “white 7 navigation” or “white 7 navigation” or “ Blue 7 Navi ”.

  Further, as another method, a method of controlling the bonus notification on the main side rather than the sub side can be considered. More specifically, the main control board 71 determines an effect (at least the number of games required for effect) to be executed on the display device 11 when the bonus combination is determined as an internal winning combination in a state where the bonus combination is not carried over. Notify the sub-control board 72. The sub control board 72 executes the notified effect and displays the bonus confirmation screen, so that the timing at which the bonus notification is made on the main side can be grasped.

  The main side may be able to recognize the timing at which the bonus notification is made by a method other than the above two methods. In this case, since the main control board 71 cannot receive a signal from the sub control board 72 or the like, it is necessary to grasp the timing of bonus notification based on the signal that the main control board 71 can receive. For example, when the main control board 71 can receive a signal associated with the stop operation, a predetermined stop operation (for example, other than the normal push) is performed while the bonus combination is determined as the internal winning combination. In addition, a method of giving a bonus notification may be considered. Specifically, the sub control board 72 acquires the information on the internal winning combination and the information on the stop operation from the main control board 71, and gives a bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the trigger for bonus notification can be grasped by the main control board 71 as well, so that the timing at which the bonus notification is made on the main side can be grasped.

<Description of operation of main control circuit>
Next, the contents of various processes executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS. 64 to 170.

[Process at power-on (reset interrupt)]
First, the power-on (reset interrupt) process of the pachi-slot 1 performed by the control of the main CPU 101 will be described with reference to FIGS. 64 and 65. FIG. 64 is a flowchart showing a procedure of processing at power-on (reset interrupt), and FIGS. 65A to 65C respectively show sources for executing the processing of S2, S7 and S8, and S13 in the flowchart. It is a figure which shows an example of a program. In the power-on (reset interrupt) processing shown in FIG. 64, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 is started, a reset signal is sent to the microprocessor 91. XSRST ”terminal, which is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 determines whether or not the power supply monitoring port (power supply monitoring means) is on (S1).

  In S1, when the main CPU 101 determines that the power supply monitoring port is in the on state (YES in S1), the main CPU 101 repeats the process of S1. It should be noted that the power monitoring port being turned on here means that the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

  On the other hand, when the main CPU 101 determines in S1 that the power supply monitoring port is not on (when S1 is NO), the main CPU 101 initializes the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 initializes the timer circuit 113. Specifically, the main CPU 101 sets a frequency division ratio in a timer prescaler register (not shown), sets interrupts in a timer control register (not shown), and sets a timer counter (not shown). Set the initial count value.

  Next, the main CPU 101 initializes the first serial communication circuit 114 (SCU1) for the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. Initialization processing is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 conducts a write test of the main RAM 103 (S5).

  Next, the main CPU 101 determines, as a result of the write test, whether or not writing to the main RAM 103 has been normally performed (S6).

  In S6, when the main CPU 101 determines that the writing to the main RAM 103 is not normally performed (NO in S6), the main CPU 101 performs the process of S13 described below. On the other hand, in S6, when the main CPU 101 determines that the writing to the main RAM 103 is normally performed (YES in S6), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. Is acquired (S7).

  Next, the main CPU 101 determines whether or not the current state is the timing at which interrupt processing occurs based on the obtained state of the timer control register (S8). Specifically, the main CPU 101 determines, based on the acquired state of the timer control register, whether or not 1.1172 ms has elapsed after the timer count was started.

  In this embodiment, when the timer time of 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the counting process of the CPU built-in timer is started. After that, the status of the timer circuit 113 can be obtained by reading the information in the timer control register (not shown). In the present embodiment, the control register for the timer has a bit (discrimination bit) capable of discriminating (reference) whether or not the current state is the timing at which the interrupt processing occurs (whether or not the timer is in the interrupt state). ) Is provided.

  Therefore, in the process of S7, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S8, the main CPU 101 turns on / off the determination bit in the timer control register ( By referring to "1" / "0"), it is determined whether or not the current state is the timing at which interrupt processing occurs. When 1.1172 ms have elapsed from the start of counting by the timer circuit 113 (when the count value of the timer circuit 113 is 0), the determination bit is turned on.

  In S8, when the main CPU 101 determines that the current state is not the timing at which the interrupt process occurs (NO in S8), the main CPU 101 returns the process to the process in S7 and repeats the processes from S7.

  On the other hand, in S8, when the main CPU 101 determines that the current state is the timing at which the interrupt process occurs (YES in S8), the main CPU 101 performs the sum check process (out of regulation) (S9). .. In this process, the main CPU 101 performs the sum check process of the main RAM 103, and the work of this process is performed in the non-regular work area (see FIG. 12C) in the main RAM 103. The program used in the sum check process is stored in the non-regulated area in the main ROM 102 (see FIG. 12B). The details of the sum check process will be described later with reference to FIGS. 79 and 80 described later.

  Further, when the main CPU 101 determines in S8 that the current state is the timing of occurrence of the interrupt process (when YES is determined in S8), the main CPU 101 performs the interrupt process described below before the process of S9. Incorporation processing (see FIG. 158 described later) is executed. By this interrupt processing, a non-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

  After the processing of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S10).

  In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (YES in S10), the main CPU 101 performs the process of S15 described below. On the other hand, when the main CPU 101 determines in S10 that the setting key type switch 54 is not in the on state (NO in S10), the main CPU 101 determines the sum check determination based on the result of the sum check process in S9. It is determined whether or not the result is normal (S11).

  In S11, when the main CPU 101 determines that the sum check determination result is not normal (when S11 is NO determination), the main CPU 101 performs the process of S13 described below. On the other hand, in S11, when the main CPU 101 determines that the sum check determination result is normal (YES in S11), the main CPU 101 performs game return processing (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the detection of the power failure. The details of the game return processing will be described later with reference to FIG. 66 described later.

  When S6 or S11 is NO, the main CPU 101 displays the character string "rr" meaning an error occurrence on the information display 6 (7-segment LED display) (S13). After that, the main CPU 101 repeats the WDT clearing process (S14).

  Here, returning to the process of S10 again, when the determination of S10 is YES, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a process of generating and storing a setting change command at the start of setting change. The details of the setting change confirmation process will be described later with reference to FIG. 68 described later.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address of "at the time of RAM abnormality or setting change start" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game from the start address. The information up to the final address in the RAM area for use is erased (cleared). Then, after the processing of S16, the main CPU 101 starts the main processing described later (see FIG. 82 described later).

  In this embodiment, the processing at power-on (reset interrupt) is performed as described above. Then, the processing of S2 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65A.

  In the source program of FIG. 65A, 10 MHz (the supply clock is 20 MHz) is set as the CPU clock, 228 is set as the prescaler register setting value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt processing.

  Further, the processing of S7 and S8 during the above-described power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65B. Specifically, the process of obtaining the state of the timer control register in S7 is executed by the "LD" command in FIG. 65B, and the determination process of S8 is executed by the "JBIT" command in FIG. 65B. The “LD” instruction in FIG. 65B and the “JBIT” instruction in FIG. 65B are repeatedly performed until 1.1172 ms after the timer circuit 113 starts counting, and when 1.1172 ms after the timer circuit 113 starts counting. An interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101 starts the interrupt process of the first 1.1172 ms period after the power is restored, triggered by the input of the interrupt request signal.

  In the interrupt process of the first 1.1172 ms cycle immediately after the power is restored (after initialization when the power is turned on), no command relating to the game operation is set, so that the main control circuit 90 transfers to the sub control circuit 200. No operation command is sent. In this way, by permitting the interrupt process immediately after the power is restored, a non-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  Further, the communication parameters 1 to 5 constituting the no-operation command transmitted by this communication operation are set to the data stored in the L register, the H register, the E register, the D register, and the C register, respectively, when the power is restored. To be done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the no-operation command transmitted in the first interrupt process after the power is restored is made different (undefined) every time the power is restored. You can That is, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power is restored (after initialization when the power is turned on) can be made different every time the power is restored. In this case, fraudulent acts such as goto can be suppressed.

  Further, the processing of S13 (interrupt prohibition processing) during the above-described processing at power-on (reset interrupt) is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65C. .. Then, the control for displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 is executed by one source code "LDW HL, 100H * cZCHRAR + cBX_PAYSEG" as shown in FIG. 65C. Then, the output operation of the 7-segment common output data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are simultaneously performed.

  That is, in the pachi-slot 1 of the present embodiment, 7-segment common output data and 7-segment cathode output data are simultaneously output when performing dynamic lighting control of the 2-digit 7-segment LED. In this case, the number of instruction codes required for dynamic lighting control of the 7-segment LED on the source program can be reduced, and the capacity of the source program (capacity used by the main ROM 102) can be reduced. Therefore, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  The "7-segment common output data" here is LED drive data output to the common (common) terminal of the 7-segment LED when dynamically controlling the 7-segment LED, and the "7-segment cathode output data" is , LED drive data output to each cathode terminal of the 7-segment LED when dynamically controlling the 7-segment LED.

[Game return processing]
Next, with reference to FIG. 66 and FIG. 67, the game return processing performed in S12 during the power-on (reset interrupt) processing (see FIG. 64) will be described. 66 is a flowchart showing the procedure of the game return processing, and FIG. 67 is a diagram showing an example of a source program for executing the processing of S25 to S32 in the flowchart.

  First, the main CPU 101 sets the stack pointer at the time of power failure in the stack pointer (SP) (S21). Next, the main CPU 101 clears (turns off) the on-edge data before the interrupt processing of the input port and the on-edge data currently set (S22). Next, the main CPU 101 sets the backup data of the output port in the output port (S23). Next, the main CPU 101 reads the data of the input port, and saves the data in the data storage area of the current input port and before the interrupt processing (S24).

  Next, the main CPU 101 sets the address of the drum control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

  Next, the main CPU 101 acquires reel control management information (data relating to fluctuation control of the display row at the time of power interruption) of a predetermined reel based on the address of the set spinning drum control data storage area (S27). The reel control management information (variation control management information on the display row) is information regarding the control state (rotational state) of each reel, and is backed up and saved when the power is cut off.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation status during reel acceleration, constant speed waiting, or constant speed (S28).

  In S28, when the main CPU 101 determines that the condition of S28 is not satisfied (NO in S28), the main CPU 101 performs the process of S31 described below. On the other hand, when the main CPU 101 determines in S28 that the condition of S28 is satisfied (YES in S28), the main CPU 101 clears the spinning cylinder control data (reel control management information) (S29). By this processing, after the game is returned, the reel rotation control is started from the acceleration processing. Next, the main CPU 101 sets a reel operation timing value (execution start timing “1” of the spinning drum control data) (S30). When the reel operation timing is set to "1", the excitation change timing comes within the reel control processing (see S903 in FIG. 158 described later), so the main CPU 101 accelerates the reel rotation control. Start from.

  After the processing of S30 or when the determination of S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S32).

  When the main CPU 101 determines in S32 that the value of the number of reels after the subtraction is not “0” (NO in S32), the main CPU 101 changes the reel to be checked and shifts the processing to the processing of S27. The processing is returned and the processing from S27 is repeated.

  On the other hand, when the main CPU 101 determines in S32 that the value of the number of reels after subtraction is "0" (YES in S32), the main CPU 101 performs the RAM initialization process (S33). In this process, the main CPU 101 sets the address of "at power recovery" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and from the start address to the end of the game RAM area. Erase (clear) the information up to the address.

  Next, the main CPU 101 restores the data of all the registers saved at the time of the power failure detection to all the registers (S34). Then, after the processing of S34, the main CPU 101 ends the game return processing, and returns the processing to the processing at the time of power failure detection.

  In the present embodiment, the game return processing is performed as described above. In the game return processing of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management at power recovery The processing required to acquire the information and start the re-rotation of the reel is also performed (see the processing of S25 to S32). Therefore, in this embodiment, the reel re-rotation control can be stably performed even when the power is restored from the power interruption during the rotation of the spinning drum, and the player does not feel uncomfortable.

  Further, the processing of S25 to S32 during the game return processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As described above, in the microprocessor 91 with a security function for gaming machines used in the pachi-slot 1 of this embodiment, various instruction codes dedicated to the main CPU 101 are provided. For example, the “LDQ” command (predetermined read command) in FIG. 67 is one of the main CPU 101 dedicated command codes.

  When, for example, the source code "LDQ HL, k" is executed on the source program, the address designated by the contents (stored data) of the Q register and the 1-byte integer k (direct value) causes the HL register Loaded in. At this time, the contents of the Q register become the higher-order address value of the designated address, and the integer k (direct value) becomes the lower-order address value of the designated address. Therefore, when the source code “LDQ HL, .LOW.wR1_CTRL” in FIG. 67 is executed, the contents of the Q register (the address value on the upper side of the address of the drum control data storage area) and the integer value “. LOW.wR1_CTRL "(address value on the lower side of the address of the drum control data storage area) (address of the drum control data storage area) is loaded into the HL register. Note that ".LOW." Is not an actual instruction but a pseudo instruction. With the function of this pseudo instruction, only the lower address of the address of the storage area defined after ".LOW." Is validated. Further, the pseudo instruction is not an instruction stored in the actual ROM, but an instruction referred to by a conversion program (assembler) when converting a source file into a format for storing in the ROM.

  As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 for addressing by using the Q register (extended register), the main ROM 102, the main RAM 103, and the memory map I / O can be directly read. Can be accessed. In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Setting change confirmation processing]
68 and 69, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 64) will be described. 68 is a flowchart showing the procedure of the setting change confirmation process, FIG. 69A is a diagram showing an example of a source program for executing the processes of S44 to S47 in the flowchart, and FIG. 69B is It is a figure which shows an example of the source program for performing the process of S57 in this flowchart.

  First, the main CPU 101 initializes the non-specified RAM area in the main RAM 103 (S41). Next, the main CPU 101 executes one interrupt waiting process (S42). In this process, the main CPU 101 waits until the process of transmitting the no-operation command to the sub control circuit 200 by the interrupt process is completed.

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address of "at the time of RAM abnormality or setting change start" in the game RAM area of the main RAM 103 shown in FIG. The information up to the final address in the RAM area for use is erased (cleared).

  Next, the main CPU 101 determines whether the setting key type switch 54 is in the on state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (settings 1 to 6) of the pachi-slot 1, and when the setting key is turned on, the setting key is set. The key switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (NO in S44), the main CPU 101 terminates the setting change confirmation process and powers on the process (reset interrupt). ) Step S16 of the hour processing (see FIG. 64) is performed. On the other hand, when the main CPU 101 determines in S44 that the setting key type switch 54 is in the ON state (YES in S44), the main CPU 101 performs the medal acceptance prohibition process (S45). By this processing, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medal is ejected from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets the setting change start or setting confirmation start information (005H: first value) in the L register, and performs the setting storage command (setting change / setting confirmation start) generation / storage processing (S46). .. In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and outputs the command data. It is saved in the communication data storage area provided in the main RAM 103. Details of the setting change command generation / storing process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation start) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Sent to.

  Next, the main CPU 101 sets the error count relay to the on state (S47). Next, the main CPU 101 determines which of the setting change and the setting confirmation is performed (S48).

  In S48, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (NO in S48), the main CPU 101 performs the process of S55 described below.

  On the other hand, in S48, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (YES in S48), the main CPU 101 updates the setting value (S49). ). Next, the main CPU 101 performs a 7-segment display setting process of the set value (S50). By this processing, the updated set value can be displayed by the 7-segment LED in the information display device 6.

  Next, the main CPU 101 determines whether or not the reset switch 76 is in the on state (S51).

  In S51, when the main CPU 101 determines that the reset switch 76 is in the ON state (YES in S51), the main CPU 101 returns the process to S49 and repeats the processes of S49 and thereafter. On the other hand, when the main CPU 101 determines in S51 that the reset switch 76 is not in the on state (NO in S51), the main CPU 101 determines whether the start switch 79 is in the on state (S52). ..

  In S52, when the main CPU 101 determines that the start switch 79 is not in the ON state (NO in S52), the main CPU 101 returns the process to S51 and repeats the processes of S51 and subsequent steps. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is in the ON state (YES in S52), the main CPU 101 sets the setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the off state (S54).

  In S54, when the main CPU 101 determines that the setting key type switch 54 is not in the OFF state (NO in S54), the main CPU 101 repeats the process of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (YES in S54), the main CPU 101 performs the process of S55 described below.

  When S48 is NO, or when S54 is YES, the main CPU 101 determines whether the setting change or the setting check is performed (S55).

  When the main CPU 101 determines in S55 that the setting has not been changed (the setting has been confirmed) (NO in S55), the main CPU 101 performs the process of S57 described below. On the other hand, when the main CPU 101 determines in S55 that the setting has been changed (the setting has not been confirmed) (YES in S55), the main CPU 101 performs the RAM initialization process (S56). .. In this processing, the main CPU 101 sets the address (at the end of setting change) (not shown) in the game RAM area of the main RAM 103 shown in FIG. 12C (the address next to the setting value storage area) as the start address for initialization. The information from the top address to the last address of the game RAM area is erased (cleared).

  After the processing of S56 or when the determination of S55 is NO, the main CPU 101 sets information (004H: second value) of the setting change end or the setting confirmation end in the L register, and the setting change command (setting change / setting confirmation end). ) Is generated and stored (S57). In this processing, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change processing or the setting confirmation processing, and outputs the command data. It is saved in the communication data storage area provided in the main RAM 103. Details of the setting change command generation / storing process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation end) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Sent to. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 of the power-on (reset interrupt) processing (see FIG. 64).

  In the present embodiment, the setting change confirmation process is performed as described above. The processes of S44 to S47 in the setting change confirmation process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 69A. Among them, for example, the setting key state determination processing of S44 is executed by the source code "BITQ 7, (.LOW. (WIBUF + 4))" in FIG. 69A, and the error count relay of S47 is set to the ON state. The process is executed by the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 69A.

  Both the "BITQ" instruction and the "SETQ" instruction are instruction codes dedicated to the main CPU 101 that address using the Q register (extension register).

  When, for example, the source code "BITQ b, (k)" is executed on the source program, the data stored in the Q register (upper address value) and a 1-byte integer value k (direct value: lower address value) ) And bit b of the memory of the address specified by and are checked, and if "1" is stored in the bit b, "0" is set to the zero flag (bit 6: see FIG. 11) of the flag register F. If "0" is stored in the bit b, "1" is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code “BITQ 7, (.LOW. (WIBUF + 4)” in FIG. 69A is executed, the data stored in the Q register and the address specified by the integer value “.LOW. (WIBUF + 4)” 7 is checked, and if "1" is stored in the bit 7, if the zero flag of the flag register F is set to "0", and if "0" is stored in the bit 7 , The zero flag of the flag register F is set to "1".

  When the source code “SETQ b, (k)” is executed on the source program, the data stored in the Q register (upper side address value) and the 1-byte integer value k (direct value: lower side) "1" is set to bit b of the memory at the address specified by (address value). Therefore, when the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 69A is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wECRREQ” are stored. Bit 1 is set to "1".

  That is, in the setting change confirmation processing of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extended register) as described above are used. Thus, it is possible to access the main ROM 102, the main RAM 103 and the memory map I / O. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to speed up the process.

  Further, the setting change command (initialization command) generation / storing process performed at the time of starting the setting change / setting check in S46 during the above-described setting change check process is performed by the main CPU 101 executing the “CALLF” command in FIG. 69A. The processing for generating and storing the setting change command (initialization command) performed at the end of the setting change / setting confirmation in S57 described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 69B. The "CALLF" instruction is also an instruction code dedicated to the main CPU 101.

  When, for example, the source code "CALLF mn" is executed on the source program, the current value of the PC register (program counter PC: see FIG. 11) (stored data) is designated by the stack pointer (SP). The value is stored in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALLF" instruction is a 2-byte instruction, and the address range that can be jumped is in the range of 0000H to 11FFH. Therefore, for example, when the source code "CALLF SB_PCINIT_00" in FIG. 69A is executed, the current value of the PC register is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by -2. , "SB_PCINIT_00" is stored in the PC register, and the process jumps to the address specified by "SB_PCINIT_00".

  In the present embodiment, an instruction code called a "CALL" instruction is also prepared as an instruction code of the same type as the "CALLF" instruction. Then, for example, when the source code "CALL mn" is executed on the source program, the current value of the PC register (program counter PC: see FIG. 11) (stored data) is the same as the "CALLF" instruction. It is stored in the memory designated by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address designated by "mn". However, the "CALL" instruction is a 3-byte instruction, and the jumpable address range is different from that of the "CALLF" instruction, and the jumpable address range is 0000H to FFFFH. Since the "CALLF" instruction is an instruction code having a smaller number of bytes than the "CALL" instruction, the capacity of the source program (the capacity used by the main ROM 102) can be reduced and the efficiency of the processing can be improved. be able to.

  Further, in the setting change confirmation processing of the present embodiment, as shown in FIGS. 69A and 69B, the jump destination address “SB_PCINIT_00” specified by the “CALLF” instruction of S46 is the jump destination specified by the “CALLF” instruction of S57. Is the same as the address of. That is, in the present embodiment, when the setting is changed (when the gaming machine is started), when the setting confirmation is started (during normal operation), and when the setting confirmation is finished, a setting change command (initialization command) generation / storing process is transmitted The source programs for executing the above are the same as each other, and the source programs for the setting change command generation and storage processing used in both the processing of S46 and S57 are shared (modularized).

  In this case, it is not necessary to separately provide a source program for the setting change command generation / storing process in both S46 and S57, so that the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Setting change command generation and storage processing]
Next, with reference to FIG. 70 and FIG. 71, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 68) will be described. Note that FIG. 70 is a flowchart showing the procedure of the setting change command generation / storage processing, and FIG. 71 is a diagram showing an example of a source program for executing the setting change command generation / storage processing.

  First, the main CPU 101 sets information of set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 executes communication data storage processing (S64). In this processing, the main CPU 101 sets the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 68) (setting change start / setting change end / setting change status / Setting confirmation start / setting confirmation end) is used to generate setting change command data, and the generated command data is stored in the communication data storage area. The details of the communication data storage processing will be described later with reference to FIG. 72 described later.

  After the processing of S64, the main CPU 101 ends the setting change command generation / storage processing. When ending the setting change command generation / storing process performed in S46 of the setting change confirmation process (see FIG. 68), the main CPU 101 executes the process of the setting change confirmation process (see FIG. 68) after the process of S64. The process moves to S47. Further, when ending the setting change command generation / storage processing performed in S57 during the setting change confirmation processing (see FIG. 68), the main CPU 101 ends the setting change command generation / storage processing after the processing of S64, and sets The change confirmation process (see FIG. 68) also ends.

  In this embodiment, the setting change command generation / storing process is performed as described above. The above-described setting change command generation / storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 71.

  As described above, in the setting change command generation / storing process, the setting status is stored in the D register as the communication parameter 4 immediately before the setting change command generation / storing process is executed, and the setting value is set during the execution of the setting change command generation / storing process. Is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 forming the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub control circuit 200 side, and these New information is set in the communication parameter. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the side of the sub-control circuit 200 and are different from the communication parameters 1 and 2. In this case, the values currently stored in the L register and the H register are set. Therefore, the values of the communication parameters 1 and 2 at the time of transmitting the setting change command (initialization command) are indefinite values. In this case, the sum value (BCC) of the setting change command can be set to an undefined value for each transmission, and fraudulent acts such as goto can be suppressed.

[Communication data storage processing]
Next, with reference to FIGS. 72 and 73, for example, the communication data storage processing performed in S64 of the setting change command generation storage processing (see FIG. 70) will be described. The communication data storage process is executed not only when the setting change command is generated, but also when another command is generated. FIG. 72 is a flowchart showing the procedure of communication data storage processing, and FIG. 73 is a diagram showing an example of a source program for executing the processing of S71 to S76 during the communication data storage processing.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72). ..

  Next, the main CPU 101 stores the data set in the D register and the E register in the communication data temporary storage area in the main RAM 103 as the parameters 3 and 4 of the communication command, respectively (S73). Next, the main CPU 101 stores the data set in the B register and the C register in the communication data temporary storage area in the main RAM 103 as the parameter 5 and the RT state data of the communication command, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

  After the processing of S76, the main CPU 101 determines whether or not there is a free space in the communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of 9 command data can be stored in the communication data storage area (see FIG. 75B described later).

  When the main CPU 101 determines in S77 that there is no free space in the communication data storage area (NO in S77), the main CPU 101 terminates the communication data storage processing, and, for example, the setting change command generation storage processing ( (See FIG. 70) also ends.

  On the other hand, when the main CPU 101 determines in S77 that there is a free space in the communication data storage area (when YES is determined in S77), the main CPU 101 stores the communication data in the temporary storage area for communication data by the processing of S71 to S76. The communication data is stored in the communication data storage area as communication command data (S78).

  Next, the main CPU 101 executes communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating the communication data pointer indicating the storage address of the communication data in the communication data storage area. The details of the communication data pointer update processing will be described later with reference to FIG.

  Then, after the processing of S79, the main CPU 101 terminates the communication data storage processing, and also terminates the setting change command generation storage processing (see FIG. 70), for example.

  In this embodiment, the communication data storage process is performed as described above. Note that the processing of S71 to S76 in the communication data storage processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In this series of processes, the storage process of the communication command type data, various communication parameters, game state flag data, and BCC data included in the command data is performed by the Q register on the source program as shown in FIG. It is executed by using the "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that uses the (extended register) for addressing.

  Specifically, when the source code “LDQ (.LOW. (WPDT_TMP + 0)), A” is executed, the type data of the communication command stored in the A register is equal to the data stored in the Q register (upper side address value) and 1 It is stored in the communication data temporary storage area of the address designated by the integer value “.LOW. (WPDT_TMP + 0)” (lower address value) of the byte. Also, by executing the source code “LDQ (.LOW. (WPDT_TMP + 1)), HL”, the communication parameter 1 stored in the L register becomes the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 1)”. The communication parameter 2 stored in the communication data temporary storage area of the address designated by "" and stored in the H register is stored in the communication data temporary storage area of the next address. In addition, by executing the source code “LDQ (.LOW. (WPDT_TMP + 3)), DE”, the communication parameter 3 stored in the E register becomes the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 3)”. The communication parameter 4 stored in the communication data temporary storage area of the address designated by "." Is stored in the communication data temporary storage area of the next address. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 5)), BC”, the communication parameter 5 stored in the C register becomes the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 5)”. "The game state flag data stored in the communication data temporary storage area of the address designated by and is stored in the B register is stored in the communication data temporary storage area of the next address.

  Further, the BCC data, which is the sum value of the command data set in the communication data storage process, is calculated by executing a series of source codes “ADD (addition instruction code) A, H” to “ADD A, B”. Stored in register. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 7)), A”, the BCC data stored in the A register becomes the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 7)”. It is stored in the communication data temporary storage area of the address specified by and.

  As described above, in the present embodiment, when one packet (8 bytes) of communication data (command data) is created, various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a method of creating command data, the data stored in each register at the time of command generation is directly stored in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. In this case, even if there is the same type of command data and the values of the used parameters are the same, the sum value (BCC data) of the command data can be changed each time a command is created. Further, in the present embodiment, the sum value, which is one of the error codes, is calculated by ADD (addition instruction code), but instead of the addition instruction code, SUB (subtraction instruction code), XOR (exclusive OR) The same effect can be obtained even if the error code is calculated by the instruction code). Further, the same effect can be obtained by calculating the error code using MUL (multiplication instruction code) or DIV (division instruction code), which are instructions dedicated to the main CPU 101.

  Therefore, in the present embodiment, by making the unused parameter an indefinite value, it is possible to make the analysis of communication data difficult and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the got countermeasure processing.

[Communication data pointer update processing]
Next, with reference to FIGS. 74 and 75, the communication data pointer updating process performed in S79 in the communication data storing process (see FIG. 72) will be described. 74 is a flowchart showing the procedure of the communication data pointer updating process, FIG. 75A is a diagram showing an example of a source program for executing the communication data pointer updating process, and FIG. 75B is a communication data pointer. It is a figure which shows the structure of the communication data storage area actually set on the source program of an update process.

  First, the main CPU 101 acquires the value of the communication data pointer currently set (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer for one packet (8 bytes) (S82). In this process, if the value of the updated communication data pointer is equal to or larger than the upper limit size of the communication data storage area (see FIG. 75B), the main CPU 101 sets the value of the updated communication data pointer to “0”. ", So that all command data stored in the communication data storage area is invalidated (the same state as the discarded state).

  In this embodiment, the amount of data (one packet) transmitted in one transmission operation is 8 bytes. That is, in this embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of 9 command data can be stored in the communication data storage area (see FIG. 75B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). .. Therefore, in the present embodiment, the range of the communication data pointer is set to "0" to "71", and the value of the communication data pointer after updating (when the communication data pointer is updated by +8) is "71 ( Upper limit value) ”, the value of the updated communication data pointer is set to“ 0 ”(return the communication data storage address to the start address) and store the communication data. Invalidates all command data stored in the area (sets the same state as the discarded state). When the value of the communication data pointer is set to "0", the next time command data is stored in the communication data storage area, the command data is stored from the start address of the communication data storage area, so the command data is stored before that. The new command data will be overwritten with the new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds "71 (upper limit value)".

  Then, after the processing of S82, the main CPU 101 finishes the communication data pointer updating processing and also finishes the communication data storing processing (see FIG. 72).

  In this embodiment, the communication data pointer updating process is performed as described above. The communication data pointer updating process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 75A. Among them, the communication data pointer update processing of S82 is executed by the "ADD" instruction and the "ICPLD" instruction (predetermined update instruction) in FIG. 75A. This "ICPLD" instruction is also dedicated to the main CPU 101. It is an instruction code.

  When, for example, the source code "ICPLD A, n" is executed on the source program, the content (stored data) of the A register is compared with the integer n. If the content of the A register is less than the integer n, , 1 is added to the contents of the A register, and if the contents of the A register is an integer n or more, "0" is set in the A register.

  Therefore, when the communication data pointer update process of S82 is executed, the source code "ADD A, 7" is first executed on the source program of FIG. 75A, and the contents of the A register (the communication data pointer before update is "7" is added to (value), and the addition result is stored in the A register. Next, the source code "ICPLD A, 71" is executed, the content of the A register (the value of the communication data pointer after adding 7) is compared with the integer "71", and the content of the A register is less than the integer "71". In some cases, "1" is added to the contents of the A register, and when the contents of the A register is an integer "71" or more, "0" is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7 and the value of the updated communication data pointer exceeds the upper limit value “71”, the process of clearing the communication data pointer to zero (communication A process of returning the data storage address to the start address of the communication data storage area) is performed. On the other hand, if the value of the updated communication data pointer does not exceed the upper limit value “71”, the value of the communication data pointer is totally increased by adding “1” to the communication data pointer with the “ICPLD” command. +8 update.

  As described above, in the present embodiment, in the communication data pointer updating process, the communication data is updated by one "ICPLD" instruction code (an instruction code in which the transmission buffer upper limit determination instruction and the determination branch instruction are integrated). It is possible to collectively execute the pointer update (1 addition) process, the communication data pointer determination check process after the update, and the communication data pointer clear process. In this case, it is not necessary to provide an instruction code for executing each processing separately. For example, the branch instruction code for determining whether the value of the updated communication data pointer exceeds the upper limit “71” can be omitted.

  Therefore, in the communication data pointer updating process and the like, by using the "ICPLD" instruction code dedicated to the main CPU 101, the capacity of the source program (used capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Disconnect (external) processing]
Next, the power-off (external) processing of the pachi-slot 1 performed by the control of the main CPU 101 will be described with reference to FIG. FIG. 76 is a flowchart showing the procedure of the process at the time of power failure (external). In the power interruption (external) process shown in FIG. 76, when the power management circuit 93 detects a decrease (power interruption) in the power supply voltage supplied to the microprocessor 91, the microprocessor 91 outputs a power interruption detection signal. Is output to the "XINT" terminal of the microprocessor 91, whereby the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101 is executed.

  First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads the data set in the power failure detection port (S92).

  Next, the main CPU 101 determines whether or not the power failure detection port is on (S93).

  In S93, when the main CPU 101 determines that the power failure detection port is not in the ON state (NO in S93), the main CPU 101 sets the interrupt process permission (S94). Then, after the processing of S94, the main CPU 101 ends the power-off (external) processing. It should be noted that these processes performed when S93 is NO determination correspond to the process of the countermeasure against the instantaneous power failure that occurs when the power management circuit 93 momentarily detects the power interruption.

  On the other hand, in S93, when the main CPU 101 determines that the power failure detection port is in the on state (YES in S93), the main CPU 101 sets medal insertion impossible and stops the hopper device 51. (S95).

  Next, the main CPU 101 stores the currently set stack pointer (SP) value in the stack area of the game RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 performs a checksum generation process for the main RAM 103 (S97). Note that this processing is performed in the non-regular work area (see FIG. 12C) in the main RAM 103. Further, the program used in this checksum generation processing is stored in the non-regulated area in the main ROM 102 (see FIG. 12B). The details of the checksum generation process will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 sets access prohibition to the main RAM 103 (S98). After the processing of S98, the infinite loop processing is performed until the power supply is stopped (the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation processing (non-standard)]
Next, with reference to FIGS. 77 and 78, the checksum generation process performed in S97 during the power interruption (external) process (see FIG. 76) will be described. 77 is a flowchart showing the procedure of the checksum generation process, FIG. 78A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 78B is a checksum generation process. FIG. 7 is a diagram showing a state of a stack pointer updating operation and a data reading operation from a main RAM 103 to a register which are executed.

  First, the main CPU 101 stores the current value of the stack pointer (SP) (address in use in the stack area of the game RAM area) in the non-specified stack area of the non-specified RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-specified stack area in the stack pointer (S102). Next, the main CPU 101 sets the upper address value (F0H) of the RAM address (address of the non-standard stack area) in the Q register (S103). Next, the main CPU 101 sets the power failure occurrence flag (S104).

  Next, the main CPU 101 sets the stack pointer to the calculation start address of the sum value in the game RAM area, and sets the sum calculation counter to the value obtained by dividing the number of bytes of the sum value calculation target storage area by “2”. Set (S105). The sum calculation counter is a counter for determining the trigger for ending the sum value calculation, and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation process of the game RAM area of the main RAM 103 ends.

  Next, the main CPU 101 clears the HL register to 0 (sets the value "0") (S106). By this processing, the initial value "0" of the sum value is set.

  Next, the main CPU 101 executes an instruction code (source code “POP DE” described in FIG. 78A) called “POP instruction” (specific instruction), and stores the main RAM 103 set in the stack pointer (SP). Data (stored value) of a 2-byte area is read from the address of the area to the DE register (S107).

  When the "POP" instruction is executed, the data (memory contents) saved in the 1-byte area of the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory content) stored in the 1-byte area of the address obtained by updating the created address by 1 is loaded into the register on the upper side of the pair register. Further, when the "POP" instruction is executed, an address updating process (a process of adding "2" to the address) of 2 bytes is performed on the address set in the stack pointer (SP).

  Therefore, in the process of S107, the data (memory content) saved at the address designated by the stack pointer is loaded into the E register and is saved at the address obtained by adding "1" to the address designated by the stack pointer. Data (memory contents) being loaded into the D register.

  FIG. 78B shows the operation of reading data into the DE register and the operation of updating the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is “F010h” at the start of the calculation of the sum value, the data (memory content) saved in the address “F010h” is loaded into the E register and The data (memory contents) saved in "F011h" is loaded into the D register. At this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from “F010h” to “F012h”. Then, when the "POP" instruction is executed again, the data (memory contents) saved at the address "F012h" is loaded into the E register, and the data (memory contents) saved at the address "F013h" is changed. It is loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from “F012h” to “F014h”. After that, every time the "POP" instruction is executed, the above-mentioned data read operation into the DE register and the address update operation set in the stack pointer are repeated.

  After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (NO in S110), the main CPU 101 returns the process to the process of S107 and repeats the processes of S107 and subsequent steps. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (YES in S110), the main CPU 101 sets the DE register in the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-prescribed sum count value is the number of bytes in the non-prescribed storage area. Therefore, when the sum calculation counter set in S111 becomes “0”, the sum value calculation process of the non-regulated RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 ends.

  Next, the main CPU 101 reads the data (saved value) of the 1-byte area from the address of the non-regular RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S115).

  When the main CPU 101 determines in S115 that the value of the sum calculation counter is not "0" (NO in S115), the main CPU 101 returns the process to the process of S112 and repeats the processes of S112 and thereafter. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the non-regulated RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

  On the other hand, in S115, when the main CPU 101 determines that the value of the sum calculation counter is “0” (YES in S115), the main CPU 101 determines the value stored in the HL register when the power failure occurs. The sum value is stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S101 to the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 at the time of power interruption (external) processing (see FIG. 76).

  In this embodiment, the checksum generation process is performed as described above. Then, the above-described checksum generation processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 78A. As described above, in the present embodiment, the checksum of the main RAM 103 at the time of power failure is calculated by the addition formula. At this time, in the sum value calculation of the game RAM area, addition processing is performed in units of 2 bytes (see the source code “ADD HL, DE” in FIG. 78A), and in the non-standard RAM area, addition processing is performed in units of 1 byte (See the source code “ADDWB HL, A” in FIG. 78A).

[Sum check processing (non-standard)]
Next, with reference to FIGS. 79 to 81, the sum check process performed in S9 of the power-on process (see FIG. 64) will be described. 79 and 80 are flowcharts showing the procedure of the sum check process, and FIG. 81 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the sum check process.

  First, the main CPU 101 saves the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the stack pointer to the address of the sum value storage area, and sets the sum calculation counter to a value obtained by dividing the number of bytes in the sum value calculation target storage area by “2” (S122). Note that the sum calculation counter set here is a counter for determining the end timing of the sum value calculation (sum value subtraction processing), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this processing, the checksum (initial value before subtraction) generated when the power failure occurs is stored in the HL register.

  Next, the main CPU 101 executes the “POP” instruction, and reads the data (saved value) of the 2-byte area from the address of the storage area of the main RAM 103 set in the stack pointer (SP) to the DE register (S124). .. At this time, by executing the "POP" instruction, the data (memory content) saved in the 1-byte area of the address designated by the stack pointer is loaded into the E register and the address designated by the stack pointer is loaded. The data (memory content) stored in the 1-byte area of the 1-updated address is loaded into the D register (see FIG. 78B). When the "POP" instruction is executed, an address update process (process of adding 2 to the address) for 2 bytes is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial sum value or the sum value after the previous subtraction processing), and the subtraction is performed. The value is stored in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (NO in S127), the main CPU 101 returns the process to S124 and repeats the processes of S124 and subsequent steps. That is, the processes of S124 to S127 are repeated until the sum value subtracting process is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is "0" (YES in S127), the main CPU 101 sets the DE register in the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard thumb count value is the number of bytes in the non-standard RAM area.

  Next, the main CPU 101 reads the data (stored value) of the 1-byte area from the address of the non-regular RAM area set in the DE register to the A register (S129).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S132).

  When the main CPU 101 determines in S132 that the value of the sum calculation counter is not "0" (NO in S132), the main CPU 101 returns the process to the process of S129 and repeats the processes of S129 and thereafter. That is, the processes of S129 to S132 are repeated until the sum value subtraction process is completed over the entire non-regulated RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is "0" (YES in S132), the main CPU 101 sets "sum abnormality" in the determination result of the sum check process. Yes (S133). Next, the main CPU 101 determines whether or not the calculated sum value is "0" (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is "0". In the present embodiment, the sum value is "0" when the sum calculation counter value set in S128 becomes "0", that is, when the sum value subtraction process is completed over the entire main RAM 103. , The zero flag of the flag register F is set to “1”, and when the sum value is not “0”, the zero flag of the flag register F is set to “0”. Therefore, at the time of the processing of S134, if "1 (ON state)" is set in the zero flag of the flag register F, the main CPU 101 determines that the sum value is "0".

  When the main CPU 101 determines in S134 that the calculated sum value is not “0” (NO in S134), the main CPU 101 performs the process of S139 described below. On the other hand, in S134, when the main CPU 101 determines that the calculated sum value is “0” (YES in S134), the main CPU 101 sets “abnormal power interruption” in the determination result (S135). ).

  Next, the main CPU 101 acquires the power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power failure occurrence flag is a status without power failure (off state) (S137).

  In S137, when the main CPU 101 determines that the power failure occurrence flag indicates that there is no power failure (YES in S137), the main CPU 101 performs the process of S139 described below. On the other hand, in S137, when the main CPU 101 determines that the power failure occurrence flag is not in the state of no power failure (NO in S137), the main CPU 101 sets “normal” in the determination result (S138).

  When the determination of S134 is NO or the determination of S137 is YES after the processing of S138, the main CPU 101 saves the determination result in the sum check determination result and clears (turns off) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S121 to the stack pointer (S140). Then, after the processing of S140, the main CPU 101 ends the sum check processing, and moves the processing to the processing of S10 of the power-on processing (see FIG. 64).

  In this embodiment, the sum check process is performed as described above. Then, the processing of S122 to S132 during the above-described sum check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  As described above, in the sum chok determination processing of the main RAM 103 in the present embodiment, first, the checksum value generated when the power failure occurs is sequentially subtracted by the data stored in the main RAM 103 when the power is restored. At this time, the subtraction process is performed in 2-byte units in the game RAM area (see the source code “SUB HL, DE” in FIG. 81), and the subtraction process is performed in 1-byte units in the non-regular RAM area (in FIG. 81). Source code “SUBWB HL, A”). Next, the presence or absence of an abnormality is determined based on whether or not the final subtraction result is "0" (whether or not the zero flag is in the on state). When the subtraction result is "0" (when the zero flag is in the on state), it is determined to be normal, and when the subtraction result is not "0" (when the zero flag is in the off state), it is determined to be abnormal. To be judged.

  That is, in the present embodiment, the checksum generation process at the time of power failure is performed by the addition method, and the checksum determination process at the power restoration is performed by the subtraction method. Then, the normality / abnormality is determined based on the final subtraction result of the checksum. When such checksum generation processing and determination processing are performed, it is not necessary to generate the checksum again when the power is restored and collate the checksum with the checksum when the power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, it is possible to secure a free space in the main ROM 102 corresponding to the omitted part of the collation command code, and it is possible to utilize the increased free space to enhance the game playability. The “POP” instruction executed in the checksum generation processing when power failure occurs and the checksum determination processing when power is restored is a stack pointer (SP) operation dedicated instruction, and the source code “ In addition to "POP DE", source codes "POP HL", "POP AF", etc. also exist.

[Main processing of pachi-slot by control of main CPU]
Next, the main processing (main operation processing) of the pachi-slot 1 executed under the control of the main CPU 101 will be described with reference to FIG. Note that FIG. 82 is a flowchart showing the procedure of main processing (hereinafter referred to as the main flow).

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address "at the end of one game" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and from the start address to the game RAM area. Erase (clear) the information up to the final address. The storage area in this range is, for example, a storage area such as an internal winning combination storage area or a display combination storage area in which data must be erased for each unit game (game).

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this processing, the main CPU 101 performs input check processing for the medal sensor (not shown), the start switch 79, and the like. The details of the medal acceptance / start check process will be described later with reference to FIG.

  Next, the main CPU 101 performs a random number acquisition process (S203). In this processing, the main CPU 101 causes the random number value for the internal winning combination lottery (0 to 65535: the value of the random number register 0 of the random number circuit 110 to be the hard latch random number) and the random number value for effect used in various lottery related to ART ( 0-65535: each value of the random number registers 1 to 3 of the random number circuit 110 that becomes the soft latch random number, 0-255: each value of the random number registers 4 to 7 of the random number circuit 110 that becomes the soft latch random number) The various random number values thus extracted are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 91 described later.

  Next, the main CPU 101 carries out an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 92 described later.

  Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, a process of generating an internal winning combination from the hit request flag status (flag status information), a process of expanding the hit request flag data, and a process of storing the hit request flag data in the hit request flag storage area. And so on. The details of the symbol setting process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 executes a start command generation / storage process (S206). In this processing, the main CPU 101 generates start command data to be transmitted to the sub control circuit 200, and stores the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The start command is configured to include a parameter (such as a sub flag) that specifies an internal winning combination or the like.

  Next, the main CPU 101 executes a second interface board control process (S207). The second interface board control process is executed in the non-specified work area of the main RAM 103. Details of the second interface board control processing will be described later with reference to FIG.

  Next, the main CPU 101 performs state-based control processing (S208). In this process, the main CPU 101 mainly performs a game start time process (start process) according to the game state. The details of the state-based control processing will be described later with reference to FIG. 104 described later.

  Next, the main CPU 101 executes reel stop initialization processing (S209). In this processing, the main CPU 101 refers to the reel stop initial setting table (see FIG. 26), and based on the internal winning combination and the game state, sets the pull-in priority table selection table number, the pull-in priority table number, and the stop table number. The process of acquiring and the process of storing “3” in the stop button non-operation counter are performed.

  Next, the main CPU 101 executes reel rotation start processing (S210). In this processing, the main CPU 101 requests rotation start of all reels. Then, when the rotation start of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 158, which will be described later), which will be described later, executed at a constant cycle (1.1172 msec). Is controlled, and rotation of the left reel 3L, the middle reel 3C, and the right reel 3R is started. Then, each reel is subjected to acceleration control until the rotation speed thereof reaches a constant speed, and then controlled so that the constant speed is maintained.

  Next, the main CPU 101 executes reel rotation start command generation and storage processing (S211). In this processing, the main CPU 101 generates the data of the reel rotation start command to be transmitted to the sub control circuit 200, and stores the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. 158. The reel rotation start command includes a parameter indicating that the reel rotation start operation has started.

  Next, the main CPU 101 executes a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the attraction-in priority data and stores it in the attraction-in priority data storage area. The details of the pull-in priority storage processing will be described later with reference to FIG. 126 described later.

  Next, the main CPU 101 executes reel stop control processing (S213). In this processing, the main CPU 101 controls the rotation stop of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG.

  Next, the main CPU 101 executes a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 35) in the winning operation flag storage area (see FIGS. 28 to 30). Further, in this processing, the main CPU 101 determines whether or not the display combination is displayed on the activated line, and sets the payout number of medals based on the determination result. The details of the prize search processing will be described later with reference to FIG. 145 described later.

  Next, the main CPU 101 executes illegal hit check processing (S215). In this process, the main CPU 101 combines the winning request flag (internal winning combination) and the winning operation flag (display combination), and determines whether or not there is an illegal hit error based on the combined result. The details of the illegal hit check processing will be described later with reference to FIG. 148 described later.

  Next, the main CPU 101 executes a prize check / medal payout process (S216). In this process, the main CPU 101 performs a winning operation command generation process. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the credit number based on the payout number of the display combination determined in S214, and performs the medal payout process. The details of the winning check / medal payout processing will be described later with reference to FIG. 150 described later.

  Next, the main CPU 101 performs BB check processing (S217). In this process, the main CPU 101 controls the operation and the end of the bonus state. The details of the BB check process will be described later with reference to FIG.

  Next, the main CPU 101 performs RT check processing (S218). In this processing, the main CPU 101 controls the transition of the RT state based on the symbol combination stopped and displayed on the activated line. The details of the RT check process will be described later with reference to FIGS. 155 and 156 described later.

  Next, the main CPU 101 executes a CZ / ART end time process (S219). In this process, the main CPU 101 mainly performs a CZ pullback lottery process. The details of the CZ / ART end processing will be described later with reference to FIG. 157 described later. After the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal reception / start check processing]
Next, with reference to FIGS. 83 and 84, the medal acceptance / start check processing performed in S202 in the main flow (see FIG. 82) will be described. 83 is a flowchart showing the procedure of medal acceptance / start check processing, and FIG. 84 is a diagram showing an example of a source program for executing the processing of S231 to S233 during the medal acceptance / start check processing. is there.

  First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is "1" or more, the main CPU 101 determines that there is an automatic insertion request. The automatic insertion medal counter is data for identifying whether or not the display combination relating to the replay (replay) has been established in the previous unit game. When the display combination relating to the replay is established, the number of medals inserted in the previous unit game is automatically inserted into the automatic insertion medal counter.

  When the main CPU 101 determines in S221 that the value of the automatic-insertion medal counter is “0” (YES in S221), the main CPU 101 performs the process of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not "0" (NO in S221), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, an LED lighting control process for the number of inserted medals, and the like. The details of the medal insertion process will be described later with reference to FIG. 85 described later.

  Next, the main CPU 101 subtracts 1 from the value of the automatic-insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is "0" (S224).

  In S224, when the main CPU 101 determines that the value of the automatic-insertion medal counter is not “0” (NO in S224), the main CPU 101 returns the process to S222 and repeats the processes from S222.

  On the other hand, when the main CPU 101 determines in S224 that the value of the automatic insertion medal counter is "0" (YES in S224) or in S221, the main CPU 101 determines that the medal auxiliary storage Warehouse switch check processing is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the ON / OFF state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 executes medal insertion state check processing (S226). Next, the main CPU 101 determines whether or not the medal can be inserted, based on the result of the medal insertion state check process (S227).

  In S227, when the main CPU 101 determines that it is not in a state where the medal can be inserted (NO in S227), the main CPU 101 performs the process of S231 described below.

  On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (YES in S227), the main CPU 101 performs the medal insertion check process (S228). In this process, the main CPU 101, for example, based on the medal sensor input state, a process of determining whether or not the medal has normally passed, and credits the medal when the specified number of medals has been inserted. Perform processing, etc. The details of the medal insertion check process will be described later with reference to FIG. 87 described later.

  Next, the main CPU 101 determines, based on the result of the medal insertion check process, whether or not it is in a medal insertion or creditable state (S229).

  When the main CPU 101 determines in S229 that a medal can be inserted or credits can be made (YES in S229), the main CPU 101 performs the process of S231 described below. On the other hand, in S229, when the main CPU 101 determines that it is not in a medal insertion or creditable state (NO in S229), the main CPU 101 performs a medal acceptance prohibition process (S230). By this processing, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is ejected from the medal payout opening 24.

  After the processing of S230, if the determination of S227 is NO, or if the determination of S229 is YES, the main CPU 101 determines whether or not the current inserted number of medals is the playable start number (S231). In the present embodiment, the number of games that can be started is three (see FIGS. 28 to 30).

  When the main CPU 101 determines in S231 that the current number of inserted medals is the playable start number (YES in S231), the main CPU 101 performs the process of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of inserted medals is not the playable start number (NO in S231), the main CPU 101 determines whether or not medals have been inserted (S232). ).

  In S232, when the main CPU 101 determines that a medal has been inserted (YES in S232), the main CPU 101 returns the processing to S226, and repeats the processing from S226. On the other hand, in S232, when the main CPU 101 determines that there is no medal insertion (NO in S232), the main CPU 101 performs the setting change confirmation process described in FIG. 68 (S233). In this process, the main CPU 101 performs a process of generating and storing a setting change command at the start of setting confirmation.

  After the processing of S233 or when the determination of S231 is YES, the main CPU 51 determines whether or not the start switch 79 is in the ON state (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the on state (NO in S234), the main CPU 101 returns the process to S226 and repeats the processes from S226.

  On the other hand, when the main CPU 101 determines in S234 that the start switch 79 is in the ON state (YES in S234), the main CPU 101 performs the medal acceptance prohibition process (S235). By this processing, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is ejected from the medal payout opening 24. Then, after the processing of S235, the main CPU 101 ends the medal acceptance / start check processing, and moves the processing to S203 of the main flow (see FIG. 82).

  In the present embodiment, the medal acceptance / start check process is performed as described above. Then, the processing of S231 to S233 during the medal acceptance / start check processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, in the process of S233, the process is jumped to the address “SB_WVSC_00” of the execution program of the setting change confirmation process by the “CALLF” instruction which is the instruction code for the main CPU 101, and the setting change confirmation described in FIGS. 68 and 69 is performed. Perform processing.

  Then, the process of S233 during the medal acceptance / start check process described above, that is, the setting change confirmation process is executed regardless of the gaming state. Therefore, in the present embodiment, regardless of the game state, that is, even if the game state is the bonus state (special prize operation state), set values and hole menus (various history data (errors, power interruption history, etc.)) are displayed. It can be confirmed, and fraudulent acts such as goto can be suppressed.

[Medal insertion process]
Next, with reference to FIGS. 85 and 86, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 83) will be described. It should be noted that FIG. 85 is a flowchart showing the procedure of the medal insertion process, and FIG. 86 is a diagram showing an example of a source program for executing the medal insertion process.

  First, the main CPU 101 adds "1" to the medal counter value (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 executes medal insertion command generation / storage processing (S242). In this process, the main CPU 101 generates data of the medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. 158. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command includes a parameter for specifying the number of inserted medals.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the number of inserted medals (lighting control data) based on the number of inserted medals (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and when the number of inserted medals is three, for example. For, LED lighting data for lighting all of the first to third LEDs for displaying the number of inserted medals is calculated. The method of calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 uses the calculated LED lighting data to light the corresponding LED for displaying the number of inserted medals (S245). Then, after the processing of S245, the main CPU 101 ends the medal insertion processing, and moves the processing to S223 of the medal acceptance / start check processing (see FIG. 83).

  In the present embodiment, the medal insertion process is performed as described above. The above-described medal insertion process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, in the processing of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop processing referring to the table but by the calculation processing. This arithmetic processing is performed by the main CPU 101 sequentially executing the source codes "LD A, L" to "OR L" in the source program shown in FIG.

  In this arithmetic processing, first, by executing the source code "LD A, L", the data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, "00000011B" (decimal number "3") is stored in the A register. In the present embodiment, 1-byte data is described as "*********", but the last character "B" is "0" or "1" shown before the character "B". Means that it is bit data.

  Next, by executing the source code “ADD A, A”, the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, when the data stored in the A register before the execution of this "ADD" instruction is "00000011B" (when the number of inserted medals is 3), the addition result is determined by this "ADD" instruction. “000000110B” is stored in the A register.

  Next, by executing the source code "DEC A", the data stored in the A register is subtracted by 1, and the subtraction result is stored in the A register. For example, when the data stored in the A register before the execution of this “DEC” instruction is “00000110B”, the subtraction result “00000101B” is stored in the A register by this “DEC” instruction. ..

  Next, by executing the source code “OR L”, the logical sum operation of the data (the number of inserted medals) stored in the L register and the data stored in the A register is performed, and the operation result is stored in the A register. Is stored. For example, when the data stored in the A register is “00000101B” and the data stored in the L register is “00000011B” before the execution of the “OR” instruction (the number of inserted medals is 3). In this case), this "OR" instruction stores "00000111B", which is the result of the logical sum operation of both data, in the A register. Then, the data stored in the A register by the execution of the “OR” command becomes the LED lighting data for displaying the number of inserted medals (data indicating the lighting state of the medal insertion LED).

  For example, when the number of inserted medals is 3, as described above, the final calculation result “00000111B” is displayed for displaying the number of inserted medals by the calculation processing of the LED lighting data for displaying the number of inserted medals in S244. It becomes the LED lighting data. Further, in the present embodiment, “1/0” of bit 0 of the finally calculated LED lighting data is “ON / OFF” of the output port to the LED (first LED) for displaying the number of inserted medals of the first coin. "1/0" of bit 1 corresponds to the "on / off" state of the output port to the LED (second LED) for displaying the number of inserted medals for the second coin, and bit 1 of "1" "/ 0" corresponds to the "on / off" state of the output port to the LED (third LED) for displaying the number of inserted medals for the third coin. Therefore, when the number of inserted medals is three, "00000111B" is generated as the LED lighting data as described above, and all the output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the ON state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

  When the LED lighting data for displaying the number of inserted medals is generated by the arithmetic processing as described above, the table data to be referred to when generating the LED lighting data for displaying the number of inserted medals is unnecessary, and therefore the table area of the main ROM 102 is not required. It is possible to increase the free space of the program and minimize the increase of the program capacity. That is, in the above-described medal shooting process of the present embodiment, the process of displaying the medal shooting LED can be made efficient, and the free space of the main ROM 102 can be secured (increased) and the increased free space can be utilized. It becomes possible to improve the playability.

[Medal insertion check processing]
Next, with reference to FIGS. 87 and 88, the medal insertion check process performed in S228 of the medal acceptance / start check process (see FIG. 83) will be described. Note that FIG. 87 is a flowchart showing the procedure of the medal insertion check process, and FIG. 88 is an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

  First, the main CPU 101 determines whether or not the game is being replayed (S251).

  When the main CPU 101 determines in S251 that the game is being replayed (YES in S251), the main CPU 101 ends the medal insertion check process, and the process proceeds to the medal acceptance / start check process (see FIG. 83). Move to S229.

  On the other hand, when the main CPU 101 determines in S251 that the game is not being played again (NO in S251), the main CPU 101 permits medal acceptance (S252). In this process, the solenoid of the selector 66 (see FIG. 4) is driven, and the medals inserted from the medal insertion slot 24 are accepted. The received medals are counted and then guided to the hopper device 51.

  Next, the main CPU 101 executes a bet button check process (S253). In this processing, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1 bet button 15b) is operated based on the ON / OFF state of the BET switch 77. Next, the main CPU 101 determines whether or not the bet operation is completed based on the result of the bet button check process of S253 (S254).

  In S254, when the main CPU 101 determines that the betting operation is completed (YES in S254), the main CPU 101 ends the medal insertion check process, and the medal acceptance / start check process (see FIG. 83). Move to S229.

  On the other hand, in S254, when the main CPU 101 determines that the betting operation is not completed (NO in S254), the main CPU 101 determines the medal sensor input state (game medium acceptance state) during the current process, The medal sensor input state at the time of the previous processing is acquired (S255). The medal sensor input state is information indicating the passing state of the medals received in the medal insertion slot 24 in the selector 66, and the detection result of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by.

  In the present embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the upstream first medal sensors (not shown) provided side by side in the medal passing direction at the outlet of the selector 66. The detection result corresponds to bit 0 information (“0” or “1”), and the detection result of the downstream second medal sensor (not shown) corresponds to bit 1 information (“0” or “1”) To do. If the passage of the medal is detected by the first medal sensor, the bit 0 is set to "1", and if the passage of the medal is detected by the second medal sensor, the bit 1 is set to "1". To be done. Therefore, the medal sensor input state “00000000B” indicates the state before or after the passage of the medal (at the time of passage), the medal sensor input state “00000001B” indicates the state at the start of passing the medal, and the medal sensor input state “ "00000011B" indicates a state during passage of a medal, and "000010B" input state by a medal sensor indicates a state immediately before the completion of passage of a medal.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256).

  When the main CPU 101 determines in S256 that the medal sensor input state during the current process has not changed from the medal sensor input state during the previous process (when S256 is NO determination), the main CPU 101 determines that the state of S261 will be described later. Perform processing.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state in the current process has changed from the medal sensor input state in the previous process (YES in S256), the main CPU 101 determines that Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained in the current process is generated by arithmetic processing (S257).

  In this process, when the medal sensor input state at the previous process is "00000000B" (when both the first and second medal sensors have not detected medals), the normal change value of the medal sensor input state is determined. “00000001B” (when the first medal sensor detects medals and when the second medal sensor does not detect medals) is generated, and when the medal sensor input state during the previous processing is “00000001B”, the medal sensor As a normal change value of the input state, "00000011B" (when both the first and second medal sensors are medal detection) is generated. In this process, when the medal sensor input state at the previous process is "00000011B", the normal change value of the medal sensor input state is "00000010B" (the first medal sensor has not detected the medal, (When the medal sensor is for medal detection) is generated and the medal sensor input state at the time of the previous processing is “00000010B”, the normal change value of the medal sensor input state is “00000000B” (first and second medals). (If both sensors have not detected medals). The method of generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal backward error has occurred. If the determination condition of S258 is not satisfied, the main CPU 101 determines that a medal backward error has occurred.

  In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S257 (when S258 is NO determination), the main CPU 101 executes the processing of S262 described below. To do.

  On the other hand, in S258, when the main CPU 101 determines that the medal sensor input state during the current process is the same as the normal change value generated in S257 (YES in S258), the main CPU 101 determines during the current process. It is determined whether or not the medal sensor input state of is the state after passing the medal (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is the state of passing medals (YES in S259), the main CPU 101 performs the process of S263 described below.

  In S259, when the main CPU 101 determines that the medal sensor input state in the current processing is not the state of passing medals (NO in S259), the main CPU 101 sets a medal passage check timer (S260). The time set in the medal passage check timer in this processing can be set to any time as long as it is possible to determine whether or not the medal has passed through the selector 66. Further, the timer value set in this process may be changed according to the medal sensor input state in the current process, for example.

  After the processing of S260 or when the determination of S256 is NO, the main CPU 101 determines whether the medal sensor input state at the time of the current processing is the medal passing state (“00000011B”) and the medal passing check timer is stopped. It is determined (S261). In this determination process, it is determined whether or not a medal passing error (inserted medal passing time error) has occurred. If the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passing error has occurred.

  In S261, when the main CPU 101 determines that the determination condition of S261 is not satisfied (NO in S261), the main CPU 101 returns the process to S253 and repeats the processes from S253.

  On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (YES in S261), or when S258 is NO, that is, a medal passing error or a medal backward error has occurred. If it is determined that the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process. The details of the error processing will be described later with reference to FIG. 89 described later. Then, after the processing of S262, the main CPU 101 returns the processing to the processing of S253, and repeats the processing of S253 and thereafter.

  Here, returning to the processing of S259 again, if the determination of S259 is YES, the main CPU 101 determines whether or not a prescribed number (three in the present embodiment) of medals have already been inserted (S263). ..

  In S263, when the main CPU 101 determines that the specified number of medals have not been inserted (NO in S263), the main CPU 101 performs the medal insertion process described in FIG. 85 (S264). Then, after the processing of S264, the main CPU 101 returns the processing to the processing of S253, and repeats the processing of S253 and thereafter.

  On the other hand, when the main CPU 101 determines in S263 that the prescribed number of medals have already been inserted (YES in S263), the main CPU 101 adds "1" to the value of the credit counter (S265). ). Next, the main CPU 101 executes medal insertion command generation / storage processing (S266). In this process, the main CPU 101 generates data of the medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. 158.

  Next, the main CPU 101 determines whether or not the number of credits of medals is the upper limit value (50 in this embodiment) based on the value of the credit counter (S267).

  In S267, when the main CPU 101 determines that the number of credits of medals is not the upper limit value (NO in S267), the main CPU 101 returns the processing to S253, and repeats the processing from S253. On the other hand, when the main CPU 101 determines in S267 that the number of credits of medals is the upper limit value (YES in S267), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check. The process moves to S229 of the process (see FIG. 83).

  In the present embodiment, the medal insertion check process is performed as described above. Then, the processes of S255 to S258 during the above-mentioned medal insertion check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, the process of generating the normal change value of the medal sensor input state in S257 is performed not by the process of referring to the table but by the calculation process. Specifically, the process of generating the normal change value is performed by the main CPU 101 executing the source codes “RLA” and “AND cBX_MDINSW” in the source program shown in FIG. 88 in this order.

  The “RLA” instruction is an instruction code that shifts the 1-byte data stored in the A register to the left (direction from bit 0 to bit 7) once (for 1 bit). In the example shown in FIG. 88, the 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LD A, B” executed before the “RLA” instruction is the “RLA” instruction. Will shift to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code “CP cBX_MDISW2” executed before the “RLA” instruction.

  The "CP" instruction is an instruction code that executes a comparison operation. Further, “cBX_MDISW2” is 1-byte data, and is “00000010B” in this embodiment. When the source code "CP cBX_MDISW2" is executed, the 1-byte data indicating the previous medal sensor input state stored in the A register is compared with "cBX_MDISW2 (00000010B)".

  Then, as a result of executing the source code “CP cBX_MDISW2”, if the result that the 1-byte data indicating the previous state of the medal sensor input is less than “cBX_MDISW2 (00000010B)”, the carry flag of the flag register F is obtained. "1" is set in (see FIG. 11), and when the "RLA" instruction is executed, "1" of the carry flag of the flag register F is stored in bit 0 of the A register. On the other hand, as a result of executing the source code “CP cBX_MDISW2”, if the result that the 1-byte data indicating the previous medal sensor input state is “cBX_MDISW2 (00000010B)” or more, the carry flag of the flag register F "0" is set in (see FIG. 11), and when the "RLA" instruction is executed, "0" of the carry flag of the flag register F is stored in bit 0 of the A register.

  Therefore, for example, if the 1-byte data indicating the previous state of the medal sensor input is “00000000B (state before passage of medal or after passage (at the time of passage))” (<“cBX_MDISW2”), the “RLA” command Execution generates "00000001B", and if the 1-byte data indicating the previous medal sensor input state is "00000001B (state at the start of passing medals)" (<"cBX_MDISW2"), execute the "RLA" command Thus, "00000011B" is generated. On the other hand, for example, if the 1-byte data indicating the previous state of the medal sensor input is "00000011B (state during passage of medals)" (> "cBX_MDISW2"), "0000110B" is generated by executing the "RLA" command. If the 1-byte data indicating the previous medal sensor input state is "00000010B (state immediately before completion of passing medals)" (= "cBX_MDISW2"), "0000100B" is generated by executing the "RLA" command. It

  Next, when the source code "AND cBX_MDINSW" is executed, the 1-byte data (data stored in the A register) generated by executing the "RLA" instruction is logically ANDed with the 1-byte data "cBX_MDINSW", and the medal sensor The normal change value of the input state is calculated. The 1-byte data “cBX_MDISW” is “00000011B” in this embodiment. Therefore, if the source code "AND cBX_MDINSW" is executed, only the data of bit 0 and bit 1 in the data stored in the A register is masked, and the other bit data becomes "0".

  As a result, for example, if the 1-byte data indicating the previous medal sensor input state is “00000000B (state before passing medals)”, the normal change value of the medal sensor input state is “00000001B (state at the start of passing medals). ) ”Is generated and the 1-byte data indicating the previous state of the medal sensor input is“ 00000001B (the state at the start of passing the medal) ”, the normal change value of the medal sensor input state is“ 00000011B (the state of passing the medal). State) "is generated. On the other hand, for example, if the 1-byte data indicating the previous state of the medal sensor input is “00000011B (state during passage of medal)”, the normal change value of the state of medal sensor input is “00000010B (state immediately before completion of passage of medal)”. Is generated and the 1-byte data indicating the previous medal sensor input state is “00000010B” (state immediately before the completion of passing the medal), the normal change value of the medal sensor input state is “00000000B (after passing the medal (passing State)) ”is generated.

  As described above, by changing the detection processing of the change state of the medal sensor input state from the table reference processing to the calculation processing, it is possible to increase the free capacity of the table storage area of the main ROM 102 and increase the capacity of the program. Can be kept to a minimum. Therefore, by adopting the above-described method, it is possible to improve the efficiency of the detection process of the medal insertion sensor state, and it is possible to utilize the increased free space in the main ROM 102 to improve the game playability.

[Error handling]
Next, with reference to FIGS. 89 and 90, for example, the error processing performed in S262 in the medal insertion check processing (see FIG. 87) will be described. FIG. 89 is a flow chart showing the procedure of error processing, and FIG. 90 is a diagram showing an example of the configuration of an error table that is actually referred to in the error processing source program.

  In the error table shown in FIG. 90, for each 1-byte data indicating the on / off state of the port indicating the type of error factor (for example, 1-byte data stored in the address “dERR_HE” in FIG. 90), Error display data (for example, 1-byte data stored in addresses “dERR_HE + 1” and “dERR_HE + 2” in FIG. 90) is defined. This error display data is output to a 2-digit 7-segment LED (for both payout number display and error display) included in the information display 6.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 performs a saving process of the payout amount display data of medals (S272).

  Next, the main CPU 101 executes error table setting processing (S273). By this processing, the start address of the error table shown in FIG. 90 is set on the source program.

  Next, the main CPU 101 acquires an error factor (S274). Note that the error factor acquired in this process changes according to the process in which the error process currently being processed is read. As shown in FIG. 90, the error factors targeted in this embodiment are “hopper empty error”, “hopper jam error”, “inserted medal passage count error”, “inserted medal passage check error”, The "inserted medal passing check error", the "inserted medal passing time error", the "inserted medal backward error", the "inserted medal auxiliary storage full error", and the "illegal hit error" are defined. For example, when the error process is read after the process of S258 during the medal insertion check process, the "insertion medal reverse error (Cr)" in FIG. 90 is acquired as the error factor in this process. Further, for example, when the error process is read after the process of S261 during the medal insertion check process, the "insertion medal passage time error (CE)" in FIG. 90 is acquired as the error factor in this process. ..

  Next, the main CPU 101 acquires error display data from the error table and the error factor (S275). For example, when the error factor is "inserted medal reverse error (Cr)", in this process, as error display data to be output to the upper digit 7-segment LED of the 2-digit 7-segment LED, the error shown in FIG. 90 is displayed. The 1-byte data “01001110B” stored in the address “dERR_CR + 1” in the table is acquired, and the 1-byte data “00001001B” stored in the address “dERR_CR + 2” is output as error display data to be output to the 7-segment LED of the lower digit. Is acquired. In this case, two characters "Cr" are displayed as error information on the 2-digit 7-segment LED.

  Next, the main CPU 101 performs an error command (occurrence) generation / storage process (S276). In this process, the main CPU 101 generates data of an error command to be transmitted to the sub control circuit 200 when an error occurs, and saves the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command stored in the communication data storage area when an error occurs is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The error command when an error occurs is configured to include a parameter indicating the error occurrence.

  Next, the main CPU 101 performs a waiting process for one interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been canceled (S278).

  In S278, when the main CPU 101 determines that the error has not been cleared (NO in S278), the main CPU 101 returns the process to S277 and repeats the processes from S277.

  On the other hand, when the main CPU 101 determines in S278 that the error has been canceled (YES in S278), the main CPU 101 performs the error factor clearing process (S279). It should be noted that this processing is performed in the non-specified work area of the main RAM 103. Next, the main CPU 101 carries out a restoration process of the payout amount display data of the medals saved in S272 (S280).

  Next, the main CPU 101 executes an error command (cancel) generation / storage process (S281). In this process, the main CPU 101 generates the data of the error command at the time of releasing the error, which is transmitted to the sub control circuit 200, and saves the command data in the communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command at the time of releasing the error, which is stored in the communication data storage area, is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. The error command at the time of error cancellation is configured to include a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and moves the processing to S253 in the medal insertion check processing (see FIG. 87), for example. In error cancellation, the error factor that has occurred is canceled and the reset switch 76 is pressed to cancel the error state.

[Random number acquisition process]
Next, the random number acquisition process performed in S203 in the main flow (see FIG. 82) will be described with reference to FIG. 91. Note that FIG. 91 is a flowchart showing the procedure of the random number acquisition process.

  First, the main CPU 101 acquires the hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for the internal winning combination lottery (random number storage area (not stored). (S291).

  Next, the main CPU 101 generates soft latch random numbers in the random number circuits 1 to 7 of the random number circuit (0 to 65535: random number value for effect used in lottery process related to ART, 0 to 255: 1-byte random number value in lottery process). The setting process of the soft latch random number acquisition register is performed (S292). Next, the main CPU 101 sets the number of soft latch random numbers to be acquired (for example, 7) (S293).

  Next, the main CPU 101 collectively acquires the acquired number of soft latch random numbers and stores the acquired number of soft latch random numbers in the random value storage area (S294). At this time, the soft latch random number (random number value for effect, 2-byte random number value) obtained from the random number register 1 of the random number circuit 110 is the hardware obtained from the random number register 0 of the random number circuit in the random number value storage area. The latch random number (random value for internal winning combination lottery) is stored in an area different from the area in which it is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing, and moves the processing to S204 of the main flow (see FIG. 82). In this embodiment, a 12-byte storage area is allocated as a random number storage area in the main RAM 103 to store four 2-byte random numbers and four 1-byte random numbers.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 82) will be described with reference to FIGS. 92 to 96. Note that FIG. 92 is a flowchart showing the procedure of the internal lottery process, and FIG. 93A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. 93B is It is a figure which shows an example of the source program for performing the process of S308-S309 during an internal lottery process.

  In addition, FIG. 94 is a diagram showing an example of the configuration of the internal lottery table (for general games) that is actually referred to on the source program of the internal lottery process, and FIG. 95 is the source program of the internal lottery process. It is a figure which shows an example of a structure of the lottery value selection table classified by RT state actually referred. Further, FIG. 96 is an internal lottery value table selection table, a 1-byte internal lottery value table, a 2-byte internal lottery value table, and a 1-byte setting internal lottery value table that are actually referred to on the source program of the internal lottery process. It is a figure which shows an example of a structure of the internal lottery value table classified by 2 and 2 bytes. In addition, in the present embodiment, an internal lottery table for RB (BB) is also provided, but here, the configuration of the internal lottery table for RB referred to on the source program of the internal lottery process is not shown. Omit it.

  First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this processing, the main CPU 101 checks the set value of the current game (one of 1 to 6) and the number of inserted medals (three in the present embodiment).

  Next, the main CPU 101 sets an internal lottery table for general games and a lottery number (53 times in this embodiment) (S302). In this process, the value (winning request flag status) of "special winning number + small winning number" in the internal lottery table (for general games) shown in FIG. 94 is set in the C register, and the "lottery value selection table or The value of the “lottery coefficient table” (determination data: data relating to address) is set in the A register. In addition, as shown in FIG. 94, the winning request flag status is set to the special winning number (“00H (out)”, “01H (BB1)”, “02H (BB2)”: decimal numbers 0, 1 and 2). "25H (hexadecimal number: 37 (special prize number to be described later in decimal number)) multiplied by a small winning combination number (" 00H "to" 24H ": 0 to 36 in decimal number) ..

  Next, the main CPU 101 determines whether or not the RB is operating (S303). In S303, when the main CPU 101 determines that the RB is not operating (NO in S303), the main CPU 101 performs the process of S305 described below.

  On the other hand, when the main CPU 101 determines in S303 that the RB is operating (when YES is determined in S303), the main CPU 101 sets the internal lottery table for RB and the lottery count (five in this embodiment). Set (S304). In this process, the internal lottery table for general game and the lottery number set in S302 are overwritten with the internal lottery table and lottery number for RB.

  After the processing of S304 or when the determination of S303 is NO, the main CPU 101 acquires the determination data (data regarding the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether or not the determination data is RT state-specific data (S306). In this processing, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination in which the lottery value changes according to the RT state. Specifically, the main CPU 101 determines whether or not the address specified in the determination data of the currently obtained lottery target combination is the address in the lottery value selection table for each RT state shown in FIG. 95. ..

  For example, in the determination data “(dRPPTR01-dRTRB_SEL) * 2 + 001H” associated with the internal winning combination “F_Chillilip” in the internal lottery table of FIG. 94, the internal lottery in the RT state-based lottery value selection table shown in FIG. Since the address "dRPPTR01" of the winning combination "F_Chillirip" is defined, the determination data associated with the internal winning combination "F_Chillirip" corresponds to the RT state-specific data. Therefore, when the currently-winning lottery target combination is the internal winning combination “F_Cililip”, the main CPU 101 determines in the processing of S306 that the determination data is RT state-specific data.

  In S306, when the main CPU 101 determines that the determination data is not RT state-specific data (NO in S306), the main CPU 101 performs the process of S308 described below. On the other hand, when the main CPU 101 determines in S306 that the determination data is the RT state-specific data (YES in S306), the main CPU 101 selects the RT state random determination value shown in FIG. 95 based on the determination data. The selection data is acquired from the table, and the acquired selection data is set as the determination data (S307).

  After the processing of S307 or when the determination of S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is the data for each setting (S308). In this processing, the main CPU 101 determines whether or not the currently-winning lottery target winning combination is an internal winning combination in which the lottery value changes according to the set value. Specifically, in the main CPU 101, the address defined in the determination data of the currently obtained lottery target combination is within the 1-byte setting-based internal lottery value table or the 2-byte-setting-based internal lottery value table shown in FIG. 96. It is determined whether the address is

  For example, in the determination data “((dNMLB00F289-dPRB_DB_WV) / 06H) * 2 + 080H” associated with the internal winning combination “F_strong Chile 1” in the internal lottery table of FIG. Since the address "dNMLB00F289" of the internal winning combination "F_strong Chile 1" in the lottery value table is defined, the determination data associated with the internal winning combination "F_strong Chile 1" corresponds to the data by setting. To do. Therefore, when the currently-winning lottery target combination is the internal winning combination “F_strong Chile 1”, the main CPU 101 determines in the processing of S308 that the determination data is the data for each setting.

  In S308, when the main CPU 101 determines that the determination data is not the data for each setting (NO in S308), the main CPU 101 performs the process of S310 described below. On the other hand, in S308, when the main CPU 101 determines that the determination data is the setting-specific data (YES in S308), the main CPU 101 adds the setting value data (one of 0 to 5) to the determination data. Then, the added value is set as the determination data (S309). The setting value data added to the determination data in this process is data associated with the setting value, but the setting value data “0” to “5” are not the values of the setting value itself, This is data corresponding to "setting 1" to "setting 6".

  After the processing of S309 or in the case of NO determination in S308, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target winning combination is stored, based on the set determination data (address data), and sets it to the address. The stored lottery value is acquired (S310).

  In the process of S310, for example, when the lottery target combination is the internal winning combination “F_Sabo 2” whose lottery value does not depend on both the RT state and the set value, the 1-byte internal lottery value table shown in FIG. 96. The lottery value "128" stored in the address "dNM_B00F26" is acquired from the. Further, for example, when the lottery target combination is an internal winning combination “F_RT3 Lip_1st” whose lottery value changes depending on the RT state and the RT state is the RT2 state, the 2-byte internal lottery value table shown in FIG. 96. The lottery value "1800" stored in the address "dRT2B00F13456" is acquired from the.

  Further, in the process of S310, for example, when the lottery target combination is the internal winning combination “F_strong Chile 1” whose lottery value changes according to the set value, the 1-byte internal lottery value table by setting shown in FIG. 96. From the 6 types of lottery values “150 (Setting 1), 150 (Setting 2), 150 (Setting 3), 150 (Setting 4), 160 (Setting 5), 170 (Setting 6)” The lottery value corresponding to the set value is acquired. At this time, the lottery value corresponding to the setting value is acquired by adding the setting value data to the determination data (processing of S309) and designating the address obtained. Therefore, for example, when the lottery target combination is “F_strong Chile 1” and the set value is “6” (set value data is “5”), the lottery value “dNMLB00F289 + 5” stored in the address “dNMLB00F289 + 5” is stored. 170 ”is acquired.

  In the present embodiment, in the case of a combination whose lottery value depends on both the RT state and the set value, such as an internal winning combination “F_maintenance rep A”, the internal lottery value table and the internal lottery by setting. The lottery value is obtained by referring to both of the value tables.

  Next, the main CPU 101 obtains the random number value (any of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 executes lottery execution processing (S312). In this processing, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as a lottery result (winning / non-winning of the lottery target combination). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (when it overflows), it is determined that the lottery target winning combination has been won (the lottery target winning combination has been determined as an internal winning combination). It

  Next, the main CPU 101 stores the value obtained by adding the random determination value to the random number value (the random number value after the random determination is executed) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not the lottery execution process has been won (whether or not an overflow has occurred) (S314).

  In S314, when the main CPU 101 determines that the lottery execution process has been won (YES in S314), the main CPU 101 refers to the internal lottery table and outputs the winning request flag status corresponding to the winning internal winning combination ( The value of “special winning number + small winning number” is acquired (S315). For example, in the normal game, when the lottery target combination is “F_Sure Chile Lip”, if the lottery execution process is successful, in the process of S315, the winning request flag status “(00H * 25H) + 02H” (special prize number = 0, small winning number = 2) is acquired. Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and moves the processing to S205 of the main flow (see FIG. 82).

  On the other hand, in S314, when the main CPU 101 determines that the lottery execution process is not successful (NO in S314), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table, and draws the lottery. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the lottery count after subtraction is not “0” (NO in S317), the main CPU 101 returns the process to the process of S305, and repeats the processes from S305.

  On the other hand, in S317, when the main CPU 101 determines that the number of lotteries after subtraction is “0” (YES in S317), that is, when the internal winning combination is “out”, the main CPU 101 determines that The lost status is set (S318). The "miss status" corresponds to a hit request flag status in which both the special winning number and the small winning number are "0". Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and moves the processing to S205 of the main flow (see FIG. 82).

  In the present embodiment, the internal lottery process is performed as described above. The processing of S302 to S305 during the above-mentioned internal lottery processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 93A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A.

  For example, when the source code "LDIN ss, (HL)" is executed on the source program, the memory specified by the address set in the HL register (pair register) and the address obtained by adding "1" to the address. Is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code "LDIN AC, (HL)" in FIG. 93A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( (Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the determination data acquisition process of S305, the determination data (the value of the “lottery value selection table or lottery coefficient table”) is stored in the A register by the “LDIN” instruction (predetermined read instruction), as described above. The winning request flag status (the value of “special winning number + small winning number”) is stored in the C register.

  As described above, in the determination data acquisition processing of S305 during the internal lottery processing, both the data loading processing and the address updating processing can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  Further, the processing of S308 and S309 during the above-mentioned internal lottery processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 93B. Among them, in the addition processing of the setting value data (any one of 0 to 5) in S309, the main CPU 101 outputs the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM)” in FIG. 93B. This is done by executing in this order. Both the “MUL” instruction and the “ADDQ” instruction are instruction codes dedicated to the main CPU 101, and the “ADDQ” instruction is an instruction code dedicated to the main CPU 101 that uses the Q register (extension register) to perform addressing.

  For example, when the source code "MUL A, n" is executed on the source program, the data stored in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code “MUL A, 6” in FIG. 93B, the content (stored data) of the A register is multiplied by the 1-byte integer 6, and the multiplication result is stored in the A register. The multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachi-slot 1 of the present embodiment, since the dedicated arithmetic circuit (arithmetic circuit 107) for executing the multiplication processing and the division processing on the source program is provided, the efficiency of the multiplication processing and the division processing should be improved. You can

  When the source code “ADDQ r, (k)” is executed on the source program, the data stored in the Q register (upper side address value) and a 1-byte integer k (direct value: lower side address value) ), The storage data of the r register (A, B, C, D, E, H, or L register) is added to the content (stored data) of the memory of the address specified by) and the addition result is stored in the r register. It Therefore, when the source code “ADDQ A, (.LOW.wWAVENUM)” in FIG. 93B is executed, the data stored in the Q register and the memory of the address specified by the integer value “.LOW.wWAVENUM” of 1 byte. Is added to the contents (set value data) of the A register (stored data), and the addition result is stored in the A register.

  That is, in the example shown in FIG. 93B, in the addition processing of the set value in S309, the lottery table selection relative value is multiplied by the coefficient “6”, and the set value data is added to the multiplication value to obtain the lottery target combination. The address of the lottery table storing the lottery value of is calculated.

  As described above, in the present embodiment, in the internal lottery process, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extended register) is used. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. Therefore, in the source program of the internal lottery process, the instruction related to the address setting can be omitted, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Design setting process]
Next, the symbol setting process performed in S205 in the main flow (see FIG. 82) will be described with reference to FIGS. 97 to 100.

  FIG. 97 is a flowchart showing the procedure of the symbol setting process. FIG. 98 is a correspondence table of special winning (bonus) winning numbers and small winning combinations, and internal winning combinations. It should be noted that, in FIG. 98, the illustration of the special winning number and the small winning number corresponding to the “miss (00)” is omitted. In addition, FIG. 99 is a diagram showing an example of a source program for executing the processing of S324 to S330 during the symbol setting processing, and FIG. 100 is a reference that is actually referred to on the source program of the symbol setting processing. It is a figure which shows an example of a structure of a request flag table (flag data table, winning flag table data).

  First, the main CPU 101 extracts the prize winning number and the small winning combination number based on the hit request flag status acquired in the internal lottery process, and stores the extracted special winning number and the small winning combination number in the main RAM 103. It is saved in the winning number storage area (not shown) (S321).

  In the present embodiment, as shown in FIG. 98, the internal winning combinations "F_BB1" and "F_BB2" are associated with the special prize (bonus) winning numbers "1" and "2", respectively. Further, the internal winning combinations “F_Chillip” to “F_RB winning combination 4” are associated with the small winning combinations “1” to “36”, respectively. As described with reference to FIG. 94, the value of the winning request flag status is obtained by multiplying the prize winning number by the prize number (“37 (25H in hexadecimal notation)” in this embodiment) by the small winning number. It is the added value. Therefore, in the process of S321, the prize winning number and the small winning combination number are extracted from the value of the hit request flag status. Therefore, in the present embodiment, the main CPU 101 sets the value of the hit request flag status to the prize number (“37”). ). As a result, the value of the quotient, which is generated by the division process, becomes the prize winning number (any of 0 to 2 in decimal), and the remainder value is the minor winning number (any of 0 to 36 in decimal). Become.

  Next, the main CPU 101 determines whether or not the small winning combination is won based on the extracted small winning combination winning number (S322). In this process, if the small winning combination number is any of 1 to 36, the main CPU 101 determines that the small winning combination has been won, and if the small winning combination number is 0, the main CPU 101 determines that It is determined that the small role has not been won.

  In S322, when the main CPU 101 determines that the small winning combination is not won (NO in S322), the main CPU 101 performs the process of S331 described below. On the other hand, in S322, when the main CPU 101 determines that the small winning combination is won (YES in S322), the main CPU 101 sets the small winning combination winning number as the initial value of the subtraction result (S323).

  Next, the main CPU 101 sets the hit request flag table (see FIG. 100) (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether the subtraction result is less than “0” (S326).

  When the main CPU 101 determines in S <b> 326 that the subtraction result is not less than “0” (NO in S <b> 326), the main CPU 101 performs the bit number calculation process (S <b> 327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the winning combination winning number defined in the hit request flag table is acquired.

  In the present embodiment, in the hit request flag storage area (internal winning combination storage area), blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11 are provided. Therefore, the maximum value of the number of blocks in the hit request flag data storage area acquired in the bit number calculation process of S327 is “2”. For example, when the internal winning combination is “F_probable change”, as shown in the hit request flag table (see FIG. 100), the storage area 7 included in the blocks of the hit request storage areas 0 to 7 and the hit request Since the hit request flag data is defined in each of the storage areas 9 included in the blocks of the storage areas 8 to 11, the number of blocks in the hit request flag data storage area acquired in the bit number calculation processing of S327 is “2”. Becomes

  Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in block units defined in the hit request flag table (see FIG. 100) is calculated. For example, when the internal winning combination is “F_probable change”, 1-byte hit request flag data is stored in both the storage area 7 and the storage area 9 as shown in the hit request flag table (see FIG. 100). Therefore, the number of bytes of the hit request flag data in block units acquired in the bit number calculation process of S328 is 1 byte. In the table shown in FIG. 100, the hit request flag data stored in the storage area 7 is described as “10000000B | 01000000B”, which means that the hit request flag data stored in the storage area 7 is It means “10000000B” or (“|” is a symbol of logical sum) “01000000B”.

  Note that the above-described processing of S325 to S328 is repeated for the number of small winning combinations. For example, when the internal winning combination is "F_probable chiririp" (small winning combination number is "2"), the above-described processing of S325 to S328 is repeated twice. Further, when the processes of S325 to S328 are repeated a plurality of times, the number of blocks and the number of bytes of the hit request flag data in block units, which are respectively acquired in the bit number calculation process of S327 and S328, are saved in another storage area. To be done. Further, the number of blocks and the number of bytes of the hit request flag data in block units obtained by the above-described processing of S325 to S328 serve as information (on-bit information) that specifies the storage destination of the hit request flag data.

  Here, returning again to the processing of S326, when the main CPU 101 determines in S326 that the subtraction result is less than “0” (YES in S326), the main CPU 101 determines that the hit request flag storage area ( The internal winning combination storing area) is set (S329). At this time, the main CPU 101 determines the hit request flag to be checked (updated) based on the number of blocks and the number of bytes (on-bit information) of the hit request flag data in block units obtained by the processing of S325 to S328 described above. Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register (see FIG. 99).

  Next, the main CPU 101 performs a compressed data storage process (S330). In this process, the main CPU 101 mainly performs a process of transferring (developing) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). Details of the compressed data storage processing will be described later with reference to FIG.

  After the processing of S330 or when the determination of S322 is NO, the main CPU 101 refers to the carryover combination storing area (see FIG. 31) and determines whether or not there is a carryover combination (S331). When the main CPU 101 determines in S331 that there is a carryover combination (when YES is determined in S331), the main CPU 101 performs the process of S334 described below.

  On the other hand, when the main CPU 101 determines in S331 that there is no carryover combination (NO in S331), the main CPU 101 determines a bonus combination (BB1 or BB2) based on the special winning number extracted in the process of S321. ) Is determined whether or not it is won (S332).

  In S332, when the main CPU 101 determines that the bonus combination is not won (NO in S332), the main CPU 101 ends the symbol determination process, and the process proceeds to S206 of the main flow (see FIG. 82). Transfer.

  On the other hand, when the main CPU 101 determines in S332 that the bonus combination has been won (YES in S332), the main CPU 101 stores the winning special prize number in the carryover combination storing area (S333).

  After the processing of S333 or when the determination of S331 is NO, the main CPU 101 sets the prize winning number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and sets the RT state to RT5. The number of RT games (the number of RT1 state digest games) is cleared (“0”) (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing, and moves the processing to S206 of the main flow (see FIG. 82).

  In this embodiment, the symbol setting process is performed as described above. The processing of S324 to S330 in the above-mentioned symbol setting processing (compression / decompression processing of data related to winning) is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 99. .. Among them, the compressed data storage processing of S330 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG.

  The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 99 is executed, processing is performed at the address specified by "SB_BTEP_00". A jump is made and the compressed data storage process is started. In the compressed data storage process of S330, as described above, the hit request flag data (compressed data) stored in the hit request flag table is expanded (copied) to the corresponding hit request flag storage area.

  Further, the setting process of the address of the hit request flag storage area in S329 during the above-mentioned symbol setting process is performed by the main CPU 101 executing the source code "LDQ DE, .LOW.wWAVEBIT" in FIG. That is, the process of S329 during the symbol setting process is performed by the "LDQ" instruction dedicated to the main CPU 101 which uses the Q register (extended register) to specify the address. In this case, the instruction code relating to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  Further, in the present embodiment, the compression / decompression processing of the winning data is performed by the processing procedure described in S324 to S330 during the above-mentioned symbol setting processing, and the main CPU 101 dedicated instruction code described above is included in the processing. By using it, it is possible to improve the efficiency of the compression / decompression process of winning data, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Compressed data storage processing]
Next, with reference to FIG. 101, for example, the compressed data processing performed in S330 in the symbol determination processing (see FIG. 97) will be described. FIG. 101 is a flowchart showing the procedure of compressed data storage processing.

  The compressed data storage processing shown in FIG. 101 is executed not only in S330 in the symbol determination processing (see FIG. 97) but also in S649 in the later-described symbol code acquisition processing (see later-described FIG. 128). In the compressed data storage process executed in S330 of the symbol determination process (see FIG. 97), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later. In the compressed data storage processing executed in S649 in (see FIG. 128 described later), the flag data to be processed is winning operation flag data (flag data relating to winning combinations). Then, both processes are the same except that the types of flag data to be processed are different.

  Therefore, in the flowchart of FIG. 101, the flag data to be processed is referred to as “processing target flag data”, and the flag table to be processed is referred to as “processing target flag table”. Further, in accordance with this description, in the following description of the compressed data storage processing, the hit request flag data or the winning operation flag data is referred to as “processing target flag data”, and the hit request flag table (see FIG. 100) or the later-described The symbol corresponding winning operation table (see, for example, FIG. 130A described later) is referred to as a “processing target flag table”.

  First, the main CPU 101 sets the storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

  The storage destination check bit is 1-byte data for designating a block as a storage destination (transfer destination) of the processing target flag data. In the present embodiment, both the hit request flag storage area and the winning operation flag storage area are composed of two blocks (a storage area 0 to 7 block and a storage area 8 to 11 block). Then, for example, when the internal winning combination “F_Sure Chile Lip” is determined, the hit request flag data is stored in each of the storage area 7 and the storage area 9 as shown in the hit request flag table of FIG. (Because the number of blocks at the storage destination is "2"), "00000011B" is set as the storage destination check bit in the processing of S341. The value of bit 0 (1/0) of this 1-byte data corresponds to the presence or absence of the storage destination in the blocks of storage areas 0 to 7, and the value of bit 1 (1/0) is the storage areas 8 to 11. It corresponds to the presence / absence of the storage destination in the block.

  Next, the main CPU 101 sets the value of the byte-by-byte transfer counter to "8" (S342). In the present embodiment, since the number of bytes in each block is "8", "8" is set as the initial value of the transfer counter.

  Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is right-shifted once (one bit). As a result, the transfer instruction bit is extracted. Specifically, when a 1-byte register (a register other than the A register) in which the storage destination check bit is stored is right-shifted once, the data stored in bits 7 to 1 is changed to bits 6 to 0, respectively. While moving, the data of bit 0 before the shift is output. Then, the data output by this shift processing becomes the value of the transfer instruction bit.

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this processing, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000011B" is set as the storage destination check bit, in the determination processing of S344 of the first time (corresponding to the first block of the storage area) and the second time (corresponding to the second block of the storage area), transfer is performed. Although it is determined that there is an instruction, in the determination processing of S344 from the third time onward, it is determined that there is no transfer instruction.

  In S344, when the main CPU 101 determines that there is no transfer instruction (NO in S344), the main CPU 101 performs the process of S354 described below.

  On the other hand, when the main CPU 101 determines in S344 that there is a transfer instruction (YES in S344), the main CPU 101 acquires the byte unit storage destination designation information from the processing target flag table (S345). In this process, as the byte-unit storage destination designation information, 1 indicating the transfer destination is stored in the head address of the area in which the flag data of the processing target winning combination (winning combination or winning combination) in the processing target flag table is stored. Bytes of data are retrieved. For example, when the internal winning combination is “F_probable chiririp”, it is stored in the head address of the area in which the flag data of “F_probable chiririp” in the hit request flag table shown in FIG. 100 is stored. 1-byte data “10000000B” that designates the area 7 as the transfer destination is acquired as the byte-unit storage destination designation information.

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S346). Further, in this processing, the main CPU 101 sets, as an initial address, an address designating the top storage area of the block that is the storage (transfer) destination of the processing target flag data. For example, in the processing of the first block, the address of the storage area 0 is set as the initial address in the processing of S346, and in the processing of the second block, the address of the storage area 8 is set as the initial address in the processing of S346. ..

  Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte-unit storage destination designation information (S347). Note that the transfer instruction bit here corresponds to bit 0 of the byte unit storage destination designation information, and in the process of S347, the byte unit storage destination designation information stored in the 1-byte register is shifted to the right once. Thus, the value of the transfer instruction bit is extracted (the data of bit 0 is output).

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when “00000010B” is set as the byte-unit storage destination designation information, the bit 1 data “1” is processed in the second time (Storing area 1 of the first block or storage area 9 of the second block) S347. Is output as the value of the transfer instruction bit and it is determined that there is a transfer instruction, but in the processing of S347 of the first time and the third to eighth times, it is determined that there is no transfer instruction.

  In S348, when the main CPU 101 determines that there is no transfer instruction (NO in S348), the main CPU 101 performs the process of S351 described below.

  On the other hand, when the main CPU 101 determines in S348 that there is a transfer instruction (YES in S348), the main CPU 101 determines that the processing target flag stored in the address in the currently set processing target flag table is set. The data (winning request flag data or winning action flag data) is transferred (copied) to the designated storage area (S349).

  For example, when the internal winning combination is "F_probable relipping" and the current processing is performed on the storage area of the first block (storage areas 0 to 7), the byte unit storage destination designation information is " 10000000B ”(data specifying the storage area 7 as a storage destination), it is determined that there is a transfer instruction in the process of S347 of the eighth time, and in subsequent processes of S349, the hit request flag data“ 10000000B ”,“ 01000000B ”. , "0010000B", or "00010000B" is transferred (copied) to the storage area 7 of the hit request flag storage area.

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S350).

  After the process of S350 or when the determination of S348 is NO, the main CPU 101 performs an update process (a process of adding 1 to the address) that specifies the storage area that is the storage destination of the process target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

  Next, the main CPU 101 determines whether or not the value of the transfer counter is "0" (S353). When the main CPU 101 determines in S353 that the value of the transfer counter is not "0" (NO in S353), the main CPU 101 returns the process to the process of S347 and repeats the processes of S347 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S353 that the value of the transfer counter is "0" (YES in S353), the main CPU 101 determines whether the transfer instruction target remains in the current storage destination check bit. It is determined whether or not (S354). In this process, the main CPU 101 determines whether or not there is a bit storing "1" in the storage destination check bits at the time of the current process. Then, the main CPU 101 issues a transfer instruction to the current storage-destination check bit when there is still a bit storing “1” in the storage-destination check bits, that is, when there is a block to be processed. It is determined that the target remains.

  When the main CPU 101 determines in S354 that the transfer instruction target remains in the current storage destination check bit (YES in S354), the main CPU 101 returns the process to the process of S342, and the processes of S342 and subsequent processes. repeat. On the other hand, when the main CPU 101 determines in S354 that the transfer instruction target does not remain in the current storage destination check bit (in the case of NO determination in S354), the main CPU 101 terminates the compressed data storage process and executes the process. For example, the process proceeds to S331 in the symbol determination process (see FIG. 97).

[Second interface board control processing (non-standard)]
Next, with reference to FIG. 102, the second interface board control processing performed in S207 in the main flow (see FIG. 82) will be described. FIG. 102 is a flowchart showing the procedure of the second interface board control processing. Note that this processing is performed in the non-regular work area (see FIG. 12C) in the main RAM 103. The program used in this second interface board control processing is stored in the non-regulated area in the main ROM 102 (see FIG. 12B).

  First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 in the stack pointer (SP) (S362).

  Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in the non-regular work area in the main RAM 103 (S364).

  Next, the main CPU 101 refers to the navigation conversion table to acquire the second interface pressing order number (S365). Next, the main CPU 101 stores the acquired second interface pressing order number in an unspecified pressing order number storage area (not shown) provided in the unspecified working area (S366). Next, the main CPU 101 sets “0” to the value of the pressed position table selection counter provided in the non-regular work area (S367).

  Next, the main CPU 101 determines whether or not the acquired navigation data is push-order navigation (navigation data for push-order small winning combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is push-order navigation (YES in S368), the main CPU 101 performs the process of S372 described below.

  On the other hand, when the main CPU 101 determines in S368 that the acquired navigation data is not the push-order navigation (NO in S368), the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (10). It is determined whether or not (S369).

  In S369, when the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (YES in S369), the main CPU 101 performs the process of S371 described below. On the other hand, when the main CPU 101 determines in S369 that the acquired navigation data is not the navigation data for the BB1 stop operation (NO in S369), the main CPU 101 sets the value of the pressed position table selection counter to "1". Is added (S370). The process of adding "1" to the value of the pressed position table selection counter in S370 is a process performed to acquire the pressed position of BB2 from the pressed position table (not shown).

  After the processing of S370 or when the determination of S369 is YES, the main CPU 101 adds "1" to the value of the pressed position table selection counter (S371). The process of adding "1" to the value of the pressed position table selection counter in S371 is a process performed to acquire the pressed position of BB1 or BB2 from the pressed position table (not shown).

  After the processing of S371 or when YES is determined in S368, the main CPU 101 selects a pressed position table (not shown) based on the value of the pressed position table selection counter (S372). Next, the main CPU 101 refers to the selected pressed position table and acquires the pressed position data for three reels (the left reel 3L, the middle reel 3C, and the right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressed position data in an unspecified pressed position storage area (not shown) provided in the unspecified work area (S374). By the processing of S367 to S371, if the navigation data is the push-order navigation, the value of the pressed position table selection counter becomes "0", and if the navigation data is the navigation data for BB1 stop operation, the pressed position table selection counter of the pressed position table selection counter is displayed. The value is "1", and if the navigation data is navigation data for BB2 stop operation, the value of the pressed position table selection counter is "2". That is, the pressed position data is acquired based on the navigation data.

  Next, the main CPU 101 performs a second interface board output process (S375). The details of the second interface board output processing will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 carries out a restoration process for all the registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 in the stack pointer (SP) (S377). Then, after the processing of S377, the main CPU 101 ends the second interface board control processing, and moves the processing to S208 of the main flow (see FIG. 82).

[Second interface board output processing]
Next, with reference to FIG. 103, the second interface board output process performed in S375 in the second interface board control process (see FIG. 102) will be described. FIG. 103 is a flowchart showing the procedure of the second interface board output processing. The second interface board output process is performed in the non-regular work area of the main RAM 103.

  First, the main CPU 101 determines whether or not a transmission operation is being performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). In S381, when the main CPU 101 determines that the transmission operation is performed via the second interface serial line (YES in S381), the main CPU 101 ends the second interface board output process, The process proceeds to S376 of the second interface board control process (see FIG. 102).

  On the other hand, in S381, when the main CPU 101 determines that the transmission operation is not being performed via the second interface serial line (NO in S381), the main CPU 101 is provided in the non-regular work area. The value of the loop counter is set to "3" (the number of reels), and the initial value "1" is set to the sum value for serial communication (S382). Next, the main CPU 101 transmits the transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

  Next, the main CPU 101 acquires the pressed position data of the predetermined reel by referring to the non-regular pressed position storage area of the predetermined reel (revolving cylinder) (S384). Next, the main CPU 101 updates the non-regular pressed position storage area to be referred to that of the next target reel (revolving barrel) (S385).

  Next, the main CPU 101 acquires pulse number data corresponding to the pressed position data (symbol position) based on the pulse conversion data (not shown) and the acquired pressed position data (S386). Although details of the correspondence between the pressed position data (symbol position) and the pulse number data are omitted, for example, the acquired pressed position data (symbol position) is "3" (the symbol "white 7" on the left reel 3L). ) Is obtained, “38” is acquired as the pulse number data, and when the pressed position data (symbol position) is “10” (the symbol “replay” on the left reel 3L), the pulse number data is “38”. 155 ”is acquired. Further, for example, when the obtained pressed position data (symbol position) is “12” (the symbol “blue 7” on the left reel 3L), “189” is acquired as the pulse number data, and the pressed position data (symbol When the position) is “15” (the symbol “replay” on the left reel 3L), “239” is acquired as the pulse number data.

  Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds the pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

  Next, the main CPU 101 determines whether or not the value of the loop counter is "0" (S390). When the main CPU 101 determines in S390 that the value of the loop counter is not "0" (NO in S390), the main CPU 101 changes the target reel to the next reel, and returns the process to S384. The processing from S384 is repeated.

  On the other hand, in S390, when the main CPU 101 determines that the value of the loop counter is “0” (YES in S390), the main CPU 101 determines the sum value for serial communication to the second interface serial line (second). 2 serial communication circuit 115: SCU2) (S391). Then, after the processing of S391, the main CPU 101 ends the second interface board output processing, and moves the processing to S376 of the second interface board control processing (see FIG. 102).

[Control processing by state]
Next, with reference to FIG. 104, the control processing for each state performed in S208 in the main flow (see FIG. 82) will be described. FIG. 104 is a flow chart showing the procedure of control processing for each state.

  First, the main CPU 101 performs a sub flag conversion process (S401). In this process, the main CPU 101 performs a process of converting an internal winning combination into a sub flag (see FIGS. 36 and 37). The details of the sub-flag conversion process will be described later with reference to FIG. 105 described later.

  Next, the main CPU 101 performs a navigation set process (S402). In this processing, the main CPU 101 acquires navigation data based on the RT state, the gaming state, and the small winning number. The details of the navigation set process will be described later with reference to FIG.

  Then, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (NO in S403), the main CPU 101 performs the process of S406 described below.

  On the other hand, when the main CPU 101 determines in S403 that the current RT state is the RT4 state (YES in S403), the main CPU 101 performs flag conversion processing (S404). In this process, the main CPU 101 performs a flag conversion lottery process (compression process of sub flag data) for converting the sub flag into the sub flag EX (see FIG. 36). By this flag conversion processing, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flags EX. The details of the flag conversion process will be described later with reference to FIG.

  Next, the main CPU 101 performs a sub flag compression process (S405). In this processing, the main CPU 101 converts the sub flag EX into the sub flag D (see FIG. 36), and further compresses the sub flag data. By this sub-flag compression processing, nine types (including loss) of sub-flags EX are converted (compressed) into seven types (including loss) of sub-flags D.

  After the processing of S405 or when the determination of S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

  In S406, when the main CPU 101 determines that the current game state is the normal game state (YES in S406), the main CPU 101 performs normal start processing (S407). The details of the normal start processing will be described later with reference to FIG. 112 described later. Then, after the processing of S407, the main CPU 101 ends the control processing for each state, and shifts the processing to S209 of the main flow (see FIG. 82).

  On the other hand, in S406, when the main CPU 101 determines that the current game state is not the normal game state (NO in S406), the main CPU 101 determines whether the current game state is CZ (or not). S408).

  In S408, when the main CPU 101 determines that the current game state is CZ (YES in S408), the main CPU 101 performs processing during CZ start (S409). Details of the CZ start processing will be described later with reference to FIG. 113 described later. Then, after the processing of S409, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S408 that the current gaming state is not CZ (NO in S408), the main CPU 101 determines whether the current gaming state is normal ART (S410). ).

  In S410, when the main CPU 101 determines that the current game state is the normal ART (when YES is determined in S410), the main CPU 101 performs the normal ART start time process (S411). It should be noted that the details of the processing at the start during the normal ART will be described later with reference to FIG. 117 described later. Then, after the processing of S411, the main CPU 101 ends the state-based control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

  On the other hand, in S410, when the main CPU 101 determines that the current game state is not the normal ART (when S410 is NO determination), the main CPU 101 determines whether the current game state is CT (S412). ).

  In S412, when the main CPU 101 determines that the current game state is CT (when YES is determined in S412), the main CPU 101 performs the CT start process (S413). It should be noted that the details of the processing during start during CT will be described later with reference to FIG. 118 described later. Then, after the processing of S413, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S412 that the current game state is not CT (when S412 is NO), the main CPU 101 determines whether or not the current game state is the bonus state (S414). ).

  In S414, when the main CPU 101 determines that the current gaming state is the bonus state (YES in S414), the main CPU 101 performs the BB start time process (S415). The details of the BB start processing will be described later with reference to FIG. 125 described later. Then, after the processing of S415, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, in S414, when the main CPU 101 determines that the current game state is not the bonus state (NO in S414), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a game state other than the game state targeted by the various determination processes. For example, when the current game state is the ART preparation state, processing corresponding to the ART preparation state is performed. Then, after the processing of S416, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 82).

[Sub-flag conversion process]
Next, referring to FIGS. 105 to 107, the sub-flag conversion process performed in S401 in the state-based control process (see FIG. 104) will be described. FIG. 105 is a flowchart showing the procedure of the sub flag changing process. FIG. 106 is a diagram showing an example of a source program for executing the sub-flag changing process, and FIG. 107 shows a sub-flag converting table (conversion table) actually referred to on the source program of the sub-flag converting process. It is a figure which shows an example of a structure.

  First, the main CPU 101 acquires a small winning combination winning number (0 to 36) (S421). Next, the main CPU 101 determines whether or not the bonus operation is currently being performed (S422).

  In S422, when the main CPU 101 determines that the bonus operation is currently in progress (when YES is determined in S422), the main CPU 101 converts the small winning combination number into a bonus operation sub flag and saves it (S423). .. The processing for converting the small winning number into the sub-flag during the bonus operation is performed by the main CPU 101 executing the source code "SUB (subtraction instruction) cNHT_RBST-c7HT1_FLA" in FIG. Then, in the present embodiment, by executing this "SUB" instruction, the small winning combination number is uniformly converted into the sub flag "cactus (14)". Then, after the processing of S423, the main CPU 101 ends the sub flag conversion processing, and moves the processing to S402 of the state-based control processing (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S422 that the bonus operation is not currently performed (NO in S422), the main CPU 101 sets the sub flag conversion table shown in FIG. 107 (S424). In this process, the initial value of the sub-flag to be determined is set to "miss (00)", and the sub-flag "miss (00)" is set as the initial address of the block in the sub-flag conversion table shown in FIG. The address ("dSBCVTB + 1") in which is stored is set.

  Next, the main CPU 101 determines whether the data of the small winning combination number defined in the block in the sub-flag conversion table currently being referred to is the data corresponding to the small winning combination number obtained in the current game. It is determined whether or not (S425).

  In S425, the main CPU 101 determines that the data of the small winning combination number defined in the block in the sub-flag conversion table that is the reference target is not the data corresponding to the small winning combination number acquired in the current game. At this time (NO in S425), the main CPU 101 updates the block in the sub-flag conversion table to be referred to with the block at the next address (S426). Next, the main CPU 101 adds "1" to the value of the sub flag (S427). Then, after the processing of S427, the main CPU 101 returns the processing to the processing of S425, and repeats the processing of S425 and thereafter.

  On the other hand, in S425, the main CPU 101 causes the data of the small winning combination number defined in the block in the sub-flag conversion table to be referred to to be the data corresponding to the small winning combination number obtained in the current game. When it is determined (YES in S425), the main CPU 101 refers to the sub-flag conversion table shown in FIG. 107 to refer to the sub-flag conversion control data (the address of the small-win winning number) associated with the small-win winning number. The 1-byte data stored at the next address) is acquired, and the sub-flag conversion control data is stored in the sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this process, for example, when the small winning combination number obtained in the current game is "03" (internal winning combination "F_3 consecutive chiririp"), the sub flag conversion table shown in FIG. The control data “00000011B” is acquired. Then, after the processing of S428, the main CPU 101 ends the sub flag conversion processing, and moves the processing to S402 of the state-based control processing (see FIG. 104).

  In this embodiment, the sub flag conversion process is performed as described above. The sub-flag conversion process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Further, in the sub-flag conversion table shown in FIG. 107, which is actually referred to on the source program of the sub-flag conversion process, sub-flag conversion control data (control status) is associated with each sub-flag. At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

  For example, sub-flag conversion control data (control status) “00000011B” is commonly assigned to the sub-flags “three consecutive chili-rips A” and “three consecutive chili-rips B”. Further, for example, sub-flag conversion control data (control status) “00000001B” is commonly assigned to the sub-flags “reach-eye lip 1” to “reach-eye lip 4”. Then, in the flag conversion lottery process when converting the internal winning combination (sub flag) to the sub flag EX, the lottery is performed based on the sub flag conversion control data (control status) stored in the sub flag conversion control data storage area. ..

  In the sub-flag conversion table for converting the flag managed on the main side (internal winning combination) into the flag manageable on the sub side, common sub-flag conversion control data is provided for the same internal winning combination (sub-flag). Since the versatility of the conversion table is improved and the change of the conversion program due to the model change can be dealt with by a slight change, an increase in development cost can be suppressed.

[Naviset processing]
Next, with reference to FIGS. 108 to 110, the navigation set process performed in S402 in the state-based control process (see FIG. 104) will be described. FIG. 108 is a flowchart showing the procedure of the navigation set process. FIG. 109 is a diagram showing an example of a source program for executing the processing of S434 to S436 described later during the navigation set processing, and FIG. 110 is actually referred to on the source program of the navigation set processing. It is a figure which shows an example of a structure of the navigation data table.

  First, the main CPU 101 determines whether or not the navigation set flag is set in the sub flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small winning combination number (10 to 23) that causes the push-order navigation. It is determined whether or not. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub flag conversion control data storage area (NO in S431), the main CPU 101 terminates the navigation setting process and changes the process according to the state. The process moves to S403 of the control process (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S431 that the navigation set flag is set in the sub flag conversion control data storage area (YES in S431), the main CPU 101 is in the RT0 or RT1 state. It is determined whether or not (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (NO in S432), the main CPU 101 ends the navigation set process and controls the process by state (see FIG. 104). Move to S403.

  On the other hand, when the main CPU 101 determines in S432 that the RT state is the RT0 or RT1 state (YES in S432), the main CPU 101 determines whether or not the gaming state is the general gaming state ( S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (YES in S433), the main CPU 101 terminates the navigation set process and controls the process by state (see FIG. 104). Move to S403.

  On the other hand, in S433, when the main CPU 101 determines that the game state is not the general game state (NO in S433), the main CPU 101 acquires the small winning combination number (S434). Next, the main CPU 101 refers to the navigation data table shown in FIG. 110, and acquires the navigation data (any one of 1 to 9) based on the small winning number (S435).

  Next, the main CPU 101 stores the acquired navigation data (information related to the stop operation of the variable display of a plurality of display columns) in a navigation data storage area (stop operation instruction information storage area) (not shown) in the main RAM 103 (S436). Then, after the processing of S436, the main CPU 101 ends the navigation set processing, and moves the processing to S403 of the state-based control processing (see FIG. 104).

  In the present embodiment, the navigation set processing is performed as described above. Note that the processing of S434 to S436 during the above-described navigation set processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In this series of processing, as shown in FIG. 109, the "LDQ" instruction dedicated to the main CPU 101 that uses the Q register (extended register) to specify the address is used on the source program.

  For example, when the source code "LDQ A, (k)" is executed on the source program, the data stored in the Q register (upper side address value) and a 1-byte integer k (direct value: lower side address value) The contents of the memory (stored data) at the address specified by and are loaded into the A register. Therefore, for example, when the source code "LDQ A, (wHITFRT)" in FIG. 109 is executed, the contents of the memory at the address specified by the stored data in the Q register and the integer value "wHITFRT" are registered in the A register. Loaded in.

  Further, for example, when the source code “LDQ (k), A” is executed on the source program, the data stored in the A register is the data stored in the Q register (upper side address value) and a 1-byte integer k. (Direct value: Lower address value) is loaded into the memory at the address specified by. Therefore, for example, when the source code “LDQ (wNAVIPTN), A” in FIG. 109 is executed, the data (navi data) stored in the A register is 1 byte and the data stored in the Q register (upper side address value). Is stored in the navigation data storage area at the address designated by the integer value “wNAVIPTN” (lower address value).

  As described above, in the present embodiment, in the navigation set processing, the main CPU 101 dedicated instruction code using the Q register (extended register) is used, and the main ROM 102, the main RAM 103, and the memory map I / O are directly accessed. can do. In this case, an instruction related to address setting can be omitted on the source program of the navigation set process, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Flag conversion process]
Next, with reference to FIG. 111, the flag conversion process performed in S404 in the state-based control process (see FIG. 104) will be described. Note that FIG. 111 is a flowchart showing the procedure of the flag conversion process.

  First, the main CPU 101 determines whether it is the time to start CT (S441).

  In S441, when the main CPU 101 determines that it is not CT start time (NO in S441), the main CPU 101 performs the process of S443 described below. On the other hand, in S441, when the main CPU 101 determines that it is the time to start CT (when YES is determined in S441), the main CPU 101 randomly determines the table number of the flag conversion random determination table used for the flag conversion random determination during CT. And set (S442).

  After the processing of S442 or when the determination of S441 is NO, the main CPU 101 sets the flag conversion lottery table according to the current state (S443). For example, when the current state is the RT4 state during non-ART, the non-ART during flag conversion lottery table (see FIG. 62) is set, and when the current state is the RT4 state during normal ART, The ART flag conversion lottery table (see FIGS. 47A and 47B) is set, and when the current state is the RT4 state during CT, the CT flag conversion lottery table (see FIG. 54) is set.

  Next, the main CPU 101 refers to the set flag conversion lottery table and performs the flag conversion lottery process based on the internal winning combination (S444). In this process, the main CPU 101 actually performs the flag conversion lottery process based on the sub-flag corresponding to the internal winning combination, using the sub-flag conversion control data acquired from the sub-flag conversion table shown in FIG.

  Next, the main CPU 101 determines whether or not the flag conversion lottery in S444 has been won (S445).

  When the main CPU 101 determines in S445 that the flag conversion lottery is won (YES in S445), the main CPU 101 performs a sub flag conversion process (S446). In this process, for example, when the internal winning combination is “F_1 definite Chilelip”, that is, when the subflag is “3 consecutive Chilelip B (03)”, if the flag conversion lottery process is won, the subflag conversion process of S446 is performed. , The sub-flag “3 consecutive chili lip B (03)” is converted to the sub flag EX “determining hand (06)” or the sub flag EX “3 consecutive chili lip (07)” (see FIG. 36).

  After the processing of S446, the main CPU 101 determines whether or not the current gaming state is the non-ART state (S447). In S447, when the main CPU 101 determines that the current game state is not the non-ART state (NO in S447), the main CPU 101 ends the flag conversion process, and the process is controlled by state (see FIG. 104). ) Move to S405.

  On the other hand, when the main CPU 101 determines in S447 that the current gaming state is the non-ART state (YES in S447), the main CPU 101 adds "1" to the number of ART sets (S448). Next, the main CPU 101 sets the ART ready state to the game state of the next game (S449). Then, after the processing of S449, the main CPU 101 ends the flag conversion processing, and moves the processing to S405 of the state-based control processing (see FIG. 104).

  Here, returning again to the processing of S445, when the main CPU 101 determines in S445 that the flag conversion lottery has not been won (in the case of NO determination in S445), the main CPU 101 performs the sub flag maintaining processing (S450). .. In this process, for example, when the internal winning combination is “F_1 definite Chilelip”, that is, when the subflag is “3 consecutive Chilelip B (03)”, if the flag conversion lottery is non-win, the subflag of S450 is maintained. By the processing, the sub-flag “3 consecutive Chile Lips B (03)” is converted (maintained) into the sub-flag EX “Replay (01)”. Then, after the processing of S450, the main CPU 101 ends the flag conversion processing, and moves the processing to S405 of the state-based control processing (see FIG. 104).

[Normal start processing]
Next, with reference to FIG. 112, the normal start processing performed in S407 in the state-based control processing (see FIG. 104) will be described. It should be noted that FIG. 112 is a flowchart showing the procedure of the normal start processing.

  First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A), and performs the CZ lottery process based on the current CZ lottery state and the internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery in S461 has been won (S462).

  In S462, when the main CPU 101 determines that the CZ lottery has not been won (when S462 is NO determination), the main CPU 101 performs the process of S465 described below.

  On the other hand, in S462, when the main CPU 101 determines that the CZ lottery has been won (in the case of YES determination in S462), the main CPU 101 sets the winning type of CZ in the game state of the next game (S463). Next, the main CPU 101 sets the CZ game number of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter for counting the duration of CZ and is provided in the main RAM 103. In the process of S464, for example, when CZ1 is won, the first predetermined number of games (for example, “12”) is set in the CZ game number counter (first half), and when CZ2 is won. Is set to a second predetermined game number (for example, “15”) in the CZ game number counter (first half), and when CZ3 is won, the CZ game number counter is set to the fourth predetermined game number. (For example, “17”) is set.

  After the processing of S464 or in the case of NO determination in S462, the main CPU 101 refers to the normal medium / high probability random determination table (see FIG. 40A) and performs the transfer lottery of the CZ random determination state based on the internal winning combination (sub-flag) (S465). ). Next, the main CPU 101 updates the lottery state of CZ based on the result of the transfer lottery (S466). Then, after the processing of S466, the main CPU 101 terminates the normal start processing and also the state-based control processing (see FIG. 104).

[Processing during CZ start]
Next, with reference to FIG. 113, the CZ start-time processing performed in S409 in the state-based control processing (see FIG. 104) will be described. Note that FIG. 113 is a flowchart showing the procedure of the CZ start processing.

  First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

  In S471, when the main CPU 101 determines that the current gaming state is CZ1 (YES in S471), the main CPU 101 performs the CZ1 (CZ2) intermediate process (S472). The details of the CZ1 (CZ2) intermediate processing will be described later with reference to FIGS. 114 and 115 described later. After the processing of S472, the main CPU 101 finishes the CZ start-time processing and also the state-based control processing (see FIG. 104).

  On the other hand, in S471, when the main CPU 101 determines that the current game state is not CZ1 (NO in S471), the main CPU 101 determines whether the current game state is CZ2 (S473). ..

  In S473, when the main CPU 101 determines that the current game state is CZ2 (YES in S473), the main CPU 101 performs the CZ1 (CZ2) intermediate process (S474). Details of the CZ1 (CZ2) processing will be described later with reference to FIGS. 114 and 115 described later. After the processing of S474, the main CPU 101 terminates the CZ start-time processing and also the state-based control processing (see FIG. 104). In addition, in this embodiment, only the rank (mode or point) indicating the degree of expectation of winning the ART lottery is different between the CZ1 middle processing and the CZ2 middle processing, and the basic processing contents are the same. Therefore, in this embodiment, the CZ1 middle processing and the CZ2 middle processing will be described as one CZ1 (CZ2) middle processing by one processing.

  On the other hand, in S473, when the main CPU 101 determines that the current gaming state is not CZ2 (NO in S473), the main CPU 101 performs the CZ3 intermediate process (S475). The details of the CZ3 middle processing will be described later with reference to FIG. Then, after the processing of S475, the main CPU 101 finishes the CZ start-time processing and also the state-based control processing (see FIG. 104).

[Processing during CZ1 (CZ2)]
Next, with reference to FIGS. 114 and 115, the CZ1 (CZ2) in-process performed in S472 or S474 during the CZ-in-start process (see FIG. 113) will be described. 114 and 115 are flowcharts showing the procedure of the CZ1 (CZ2) intermediate processing.

  First, the main CPU 101 determines whether or not the current game is a game of the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not the game of the first half of CZ1 (or CZ2) (when S481 is NO determination), the main CPU 101 performs the process of S490 described later.

  On the other hand, in S481, when the main CPU 101 determines that the current game is the first half of CZ1 (YES in S481), the main CPU 101 refers to the CZ1 mode up lottery table (see FIG. 42). Then, the mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). Further, in S481, when the main CPU 101 determines that the current game is the first half of CZ2 (YES in S481), the main CPU 101 refers to the CZ2 middle point lottery table (see FIG. 43). The point-up lottery is performed based on the internal winning combination (sub flag) (S482).

  Next, the main CPU 101 updates the rank (mode or points) based on the lottery result of S482 (S483). Next, the main CPU 101 determines whether or not a freeze is won in the lottery in S482 (S484).

  In S484, when the main CPU 101 determines that a freeze has been won (YES in S484), the main CPU 101 performs freeze processing for temporarily stopping the progress of the game, and the number of ART sets and the number of CT sets. Is incremented by "1" (S485). Further, in this processing, the main CPU 101 determines and sets the ART level by referring to the ART level determination table (see FIG. 48A). When the freeze occurs, "ART level 2" is determined as the ART level.

  Next, the main CPU 101 sets the ART ready state to the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 finishes the processing during CZ1 (CZ2), and also finishes the processing during CZ start (see FIG. 113).

  Here, returning again to the processing of S484, when the main CPU 101 determines in S484 that the freeze has not been won (NO in S484), the main CPU 101 determines the value of the CZ game number counter (first half). Is decremented by 1 (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half part) is “0” (S488).

  When the main CPU 101 determines in S488 that the value of the CZ game number counter (first half) is not "0" (NO in S488), the main CPU 101 terminates the CZ1 (CZ2) mid-process, and The processing at the start during CZ (see FIG. 113) also ends.

  On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is “0” (YES in S488), the main CPU 101 sets the game state of the next game to CZ1 or The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 finishes the processing during CZ1 (CZ2) and also finishes the processing during CZ start (see FIG. 113).

  Here, again returning to the processing of S481, when the determination of S481 is NO, the main CPU 101 determines whether or not the current game is the first game of the latter half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game of the second half of CZ1 or CZ2 (NO in S490), the main CPU 101 performs the process of S495 described later.

  On the other hand, when the main CPU 101 determines in S490 that the current game is the first game of the second half of CZ1 or CZ2 (YES in S490), the main CPU 101 determines that the CZ mid ART lottery table (FIG. 44A and FIG. 44B), the ART lottery process is performed based on the rank (mode or point) of the first half (S491).

  Next, the main CPU 101 determines whether or not the ART lottery is won (S492). When the main CPU 101 determines in S492 that the ART lottery has not been won (NO in S492), the main CPU 101 performs the process of S494 described later.

  On the other hand, when the main CPU 101 determines in S492 that the ART lottery has been won (YES in S492), the main CPU 101 adds “1” to the ART set number, and the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S493).

  After the processing of S493 or when the determination of S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the process of S494, for example, when the ART lottery is won, the CZ game number counter (second half) is set to "4", and when the ART lottery is not won, the CZ game number is determined. “3” is set in the counter (second half).

  After the process of S494 or when the determination of S490 is NO, the main CPU 101 refers to the CZ ART lottery table (see FIG. 44C) and performs the ART lottery process based on the internal winning combination (sub-flag) (S495).

  Next, the main CPU 101 determines whether or not the ART lottery is won (S496). When the main CPU 101 determines in S496 that the ART lottery has not been won (NO in S496), the main CPU 101 performs the process of S498 described below.

  On the other hand, in S496, when the main CPU 101 determines that the ART lottery is won (YES in S496), the main CPU 101 adds “1” to the ART set number, and the ART level determination table (see FIG. 48A). ), The ART-level lottery is performed, and the lottery result is set (S497).

  After the processing of S497 or when the determination of S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is “0” (S499).

  When the main CPU 101 determines in S499 that the value of the CZ game number counter (latter half) is not "0" (NO in S499), the main CPU 101 terminates the CZ1 (CZ2) process and The processing at the start during CZ (see FIG. 113) also ends.

  On the other hand, when the main CPU 101 determines in S499 that the value of the CZ game number counter (second half) is "0" (YES in S499), the main CPU 101 determines that the ART set number is "1" or more. It is determined whether or not (S500).

  In S500, when the main CPU 101 determines that the number of ART sets is “1” or more (YES in S500), the main CPU 101 sets the ART ready state to the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 finishes the processing during CZ1 (CZ2), and also finishes the processing during CZ start (see FIG. 113).

  On the other hand, in S500, when the main CPU 101 determines that the number of ART sets is not “1” or more (NO in S500), the main CPU 101 sets the game state of the next game to the state at the time of CZ failure ( S502). Then, after the processing of S502, the main CPU 101 terminates the processing during CZ1 (CZ2) and also terminates the processing during CZ start (see FIG. 113).

[Processing during CZ3]
Next, with reference to FIG. 116, the CZ3 mid-process performed in S475 during the CZ mid-start process (see FIG. 113) will be described. Note that FIG. 116 is a flowchart showing the procedure of the process during CZ3.

  First, the main CPU 101 refers to the in-CZ ART lottery table (see FIG. 45) and performs the ART lottery process based on the internal winning combination (sub flag) (S511).

  Next, the main CPU 101 determines whether or not the ART lottery is won (S512). In S512, when the main CPU 101 determines that the ART lottery has not been won (NO in S512), the main CPU 101 performs the process of S518 described below.

  On the other hand, when the main CPU 101 determines in S512 that the ART lottery has been won (in the case of YES determination in S512), the main CPU 101 adds “1” to the ART set number and “1” to the CT set number. Add (S513). Next, the main CPU 101 determines whether or not the freeze is won in the ART lottery in S512 (S514).

  When the main CPU 101 determines in S514 that the freeze has not been won (NO in S514), the main CPU 101 performs the process of S516 described below. On the other hand, in S514, when the main CPU 101 determines that the freeze is won (YES in S514), the main CPU 101 performs the freeze process for temporarily stopping the progress of the game (S515).

  After the processing of S515 or when the determination of S514 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48A), performs the ART level lottery processing, and sets the lottery result (ART level) (S516). .. Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 terminates the CZ3 in-progress processing and the CZ in-start processing (see FIG. 113).

  Here, returning to the processing of S512 again, when the determination of S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is “0” (S519).

  In S519, when the main CPU 101 determines that the value of the CZ game number counter is not “0” (NO in S519), the main CPU 101 terminates the CZ3 middle processing and the CZ middle start processing (FIG. (See 113) also ends.

  On the other hand, when the main CPU 101 determines in S519 that the value of the CZ game number counter is "0" (YES in S519), the main CPU 101 adds "1" to the ART set number, and the ART The ART level lottery is performed with reference to the level determination table (see FIG. 48A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 terminates the CZ3 in-progress processing as well as the CZ in-start processing (see FIG. 113).

[Normal start processing during ART]
Next, with reference to FIG. 117, description will be given of the start-time process during normal ART performed in S411 in the control process for each state (see FIG. 104). It should be noted that FIG. 117 is a flowchart showing a procedure of processing at the start during normal ART.

  First, the main CPU 101 adds "1" to the value of the ART continuous game number counter (S531). The ART continuous game number counter is a counter that counts the number of games (digested game number) in which the normal ART has continued. Further, in the present embodiment, in addition to the ART continuing game number counter, an ART ending game number counter for counting the number of games in which the normal ART can be continued is provided. Then, in the pachi-slot 1 of the present embodiment, the value of the ART continuing game number counter is compared with the value of the ART ending game number counter, and when the value of the ART continuing game number counter reaches the value of the ART ending game number counter, the ART is finished. The gaming state ends.

  Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50) and performs the CT lottery process based on the current CT lottery state and the internal winning combination (sub flag) (S532). Next, the main CPU 101 determines whether or not the CT lottery is won (S533). When the main CPU 101 determines in S533 that the CT lottery has not been won (NO in S533), the main CPU 101 performs the process of S536 described below.

  On the other hand, when the main CPU 101 determines in S533 that the CT lottery has been won (in the case of YES determination in S533), the main CPU 101 adds “1” to the CT set number, and adds “1” to the value of the CT game number counter. 8 "is set (S534). Next, the main CPU 101 sets the type of winning CT in the gaming state of the next game (S535).

  After the processing of S535 or when the determination of S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), and randomly draws the ART level based on the value of the ART continuous game number counter, and sets the lottery result. Yes (S536). Next, the main CPU 101 refers to the normal ART medium / high probability random determination table (see FIG. 49), and based on the current CT random determination state and the internal winning combination (sub-flag), randomly selects the CT random determination state of the transfer destination, and the random determination result. Is set (S537).

  Next, the main CPU 101 refers to the additional lottery table during normal ART (see FIG. 51) and performs the additional lottery process of the number of ART games based on the internal winning combination (sub flag) (S538). Next, the main CPU 101 determines whether or not the additional lottery has been won (S539).

  In S539, when the main CPU 101 determines that the additional lottery has not been won (NO in S539), the main CPU 101 performs the process of S541 described below. On the other hand, when the main CPU 101 determines in S539 that the additional lottery has been won (in the case where S539 is YES), the main CPU 101 adds the winning result to the ART game for ending ART (S540).

  After the processing of S540 or when the determination of S539 is NO, the main CPU 101 determines whether or not the value of the ART continuing game number counter has reached the value of the ART ending game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continued game number counter does not reach the value of the ART finished game number counter (NO in S541), the main CPU 101 performs the normal ART start time process. And the control processing for each state (see FIG. 104) are also ended.

  On the other hand, when the main CPU 101 determines in S541 that the value of the ART continuous game number counter has reached the value of the ART end game number counter (YES in S541), the main CPU 101 sets the ART set number to 1 Subtract (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 finishes the normal start processing during ART and the control processing for each state (see FIG. 104).

[Processing at start during CT]
Next, with reference to FIG. 118, the start-time processing during CT performed in S413 in the control processing for each state (see FIG. 104) will be described. Note that FIG. 118 is a flowchart showing the procedure of the processing at the start during CT.

  First, the main CPU 101 refers to the additional lottery table during CT (see FIG. 55) and performs additional lottery on the number of ART games based on the internal winning combination (sub-flag) (S551). Next, the main CPU 101 determines whether or not the additional lottery has been won (S552).

  When the main CPU 101 determines in S552 that the additional lottery has not been won (when S552 is NO), the main CPU 101 performs the process of S556 described below. On the other hand, when the main CPU 101 determines in S552 that the additional lottery has been won (YES in S552), the main CPU 101 adds the winning result to the ART game number counter for ending ART (S553). As described above, in the pachi-slot 1 of the present embodiment, as the number of times the sub-flag “three consecutive chillips (three consecutive chillips A or three consecutive chillips B)” is won during the same CT is increased, one lottery is won. The amount to be added increases.

  After the processing of S553, the main CPU 101 determines whether or not the internal winning combination is a winning combination corresponding to the sub-flag EX “3 consecutive chilirip” (or “determined winning combination”), that is, the internal winning combination “F_probable chirilip” or “F_1”. It is determined whether or not it is “probable change”, and whether the flag conversion lottery process of S444 in FIG. 111 has been won (S554).

  When the main CPU 101 determines in S554 that the internal winning combination is not a combination corresponding to the sub-flag EX "3 consecutive chilirip" (NO in S554), the main CPU 101 terminates the CT start process, and The state-based control processing (see FIG. 104) also ends.

  On the other hand, in S554, when the main CPU 101 determines that the internal winning combination is a combination corresponding to the sub flag EX “three consecutive chiririp” (YES in S554), the main CPU 101 determines the value of the CT game number counter. "1" is added (S555). Then, after the processing of S555, the main CPU 101 terminates the CT start processing and the state-based control processing (see FIG. 104).

  Here, returning to the process of S552 again, when the determination of S552 is NO, the main CPU 101 performs the CT lottery process during CT (S556). In this process, the main CPU 101 mainly performs the lottery with the number of CT sets added. The details of the CT lottery process during CT will be described later with reference to FIG.

  Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is “0” (S558).

  In S558, when the main CPU 101 determines that the value of the CT game number counter is not “0” (NO in S558), the main CPU 101 terminates the CT start process and controls the state-based control process ( (See FIG. 104) is also ended. On the other hand, when the main CPU 101 determines in S558 that the value of the CT game number counter is "0" (YES in S558), the main CPU 101 determines whether or not the CT set number is "1" or more. It is determined whether or not (S559).

  When the main CPU 101 determines in S559 that the CT set number is equal to or larger than “1” (YES in S559), the main CPU 101 subtracts 1 from the CT set number (S560). Next, the main CPU 101 sets the value of the CT game number counter to "8" (S561). Then, after the processing of S561, the main CPU 101 terminates the CT start processing and also the state-based control processing (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S559 that the CT set number is not equal to or larger than "1" (NO in S559), the main CPU 101 sets the normal ART to the game state of the next game (S562). Then, after the processing of S562, the main CPU 101 terminates the CT start processing and also the state-based control processing (see FIG. 104).

[CT lottery process during CT]
Next, with reference to FIG. 119, the CT in-CT lottery processing performed in S556 during the CT start processing (see FIG. 118) will be described. Note that FIG. 119 is a flowchart showing the procedure of CT lottery processing during CT.

  First, the main CPU 101 sets the CT lottery table during CT (S571). Note that the CT random number table during CT set here is a lottery table with the number of CT sets described in FIG. 56 added, but the CT random number table during CT (set during CT) actually set on the source program. The configuration of the additional lottery table) will be described later with reference to FIG. 122 described later.

  Next, the main CPU 101 executes table data acquisition processing (S572). In this process, the main CPU 101 acquires the address of the lottery table referred to in the CT lottery process during CT. The details of the table data acquisition process will be described later with reference to FIG. 120 described later.

  Next, the main CPU 101 carries out a 1-byte lottery process (S573). In this processing, the main CPU 101 carries out a lottery on the CT set. The details of the 1-byte lottery process will be described later with reference to FIG. 123 described later.

  Next, the main CPU 101 determines whether or not the 1-byte lottery process has been won (S574). In S574, when the main CPU 101 determines that the 1-byte lottery process has not been won (when S574 is NO determination), the main CPU 101 ends the CT lottery process in CT and starts the process in CT (Fig. (Refer to 118) (S118).

  On the other hand, when the main CPU 101 determines in S574 that the 1-byte lottery process is won (YES in S574), the main CPU 101 adds “1” to the CT set number (S575). Then, after the processing of S575, the main CPU 101 ends the CT lottery processing during CT, and shifts the processing to S557 during CT start processing (see FIG. 118).

[Table data acquisition process]
Next, with reference to FIGS. 120 to 122, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 119) will be described. FIG. 120 is a flowchart showing the procedure of table data acquisition processing. FIG. 121 is a diagram showing an example of a source program for executing the table data acquisition process, and FIG. 122 is actually referred to on the source programs for the CT random determination process during CT and the table data acquisition process. It is a figure which shows an example of a structure of the CT lottery table in CT (corresponding to the lottery table with the number of sets in CT explained in FIG. 56 added). Note that the specific lottery values stored in the CT lottery table during CT shown in FIG. 122 are examples.

  In the present embodiment, when the lottery value referred to in the CT lottery process during CT is acquired, the lottery value is stored through a two-stage address calculation process (first-stage and second-stage table data acquisition process). Calculate the address. First, in the first-stage table data acquisition process (processes of S582 and S583 described below), a “selection value (1 byte)” associated with an internal winning combination (actually, the sub-flag D) is acquired. In addition, the selected value is provided for each type of internal winning combination, it is possible to determine whether the internal winning combination is a lottery target, and the arrangement destination of the lottery table associated with the internal winning combination can be specified. Values (relative values) are specified. Further, in the present embodiment, the selection value “0” is defined in advance for the internal winning combination (actually, the sub-flag D) in which the lottery result of the CT random determination process during CT is non-winning, and those internal winning combinations are set to 1 At the time of the table data acquisition process of the stage, it is treated as “miss”. Then, in the table data acquisition process of the second stage (processes of S585 to S587 described later), an address storing the lottery value of the internal winning combination for which the selection value other than “0” is defined is calculated (the lottery table. The address obtained by adding the relative value (selection value) from the reference address (2 bytes) of is calculated.

  First, the main CPU 101 refers to a CT lottery selection table in CT (not shown), and calculates the addresses of the CT lottery table in CT at the first stage and the address of the addition selection data in the second stage, and the CT. The lottery number of times of lottery (two times in this embodiment) is acquired (S581). Next, the main CPU 101 adds the address of the addition selection data of the first stage to the address of the CT random determination table during CT to calculate the selection address of the first stage (S582).

  Next, the main CPU 101 acquires the selection value stored in the calculated first-step selection address (S583). Next, the main CPU 101 determines whether or not the selected value is "0" (S584).

  In S584, when the main CPU 101 determines that the selected value is “0” (YES in S584), the main CPU 101 ends the table data acquisition process, and the process is the CT random determination process in CT (FIG. 119). (Refer) to S573.

  On the other hand, when the main CPU 101 determines in S584 that the selection value is not “0” (NO in S584), the main CPU 101 adds the selection value to the selection address and sets the second-stage selection address. Calculate (S585). Next, the main CPU 101 adds the address of the second-stage addition selection data to the second-stage selection address to calculate the selection address (S586).

  Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates an address to be referred to in the CT random determination table during CT (S587). .. After the processing of S587, the main CPU 101 ends the table data acquisition processing, and moves the processing to S573 of the CT random determination processing during CT (see FIG. 119).

  In the present embodiment, the table data acquisition process is performed as described above. The above-described table data acquisition processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 121.

  Among them, in the table data acquisition processing of the first stage (processing of S581 to S584), the data is stored in the area from the address “dCTCTSTTB” to “dCTCTS_RER-1” in the CT lottery table during CT shown in FIG. A table (table selection relative table for each winning combination) is referred to. Further, in the table combination relative table for each winning combination (lottery table selection table), each winning combination of the CT winning combinations (sub-flag D “missing”, “cactus”, “weak cherry”, “strong cherry”, “determined winning combination”) "," "Three consecutive Chilelips"), "0" is stored as the above-mentioned selection value (relative value) in the address of the selection table. In the table data acquisition process (address calculation process) of the first stage, if the selection value is “0”, the lottery result is set to “miss” (see the determination process of S584 above).

  In the CT lottery table in CT having the above-described configuration, in the table combination relative table for each winning combination referred to in the table data acquisition process of the first stage, "Loss" can be set only by the type of winning combination, so that the lottery table It is no longer necessary to specify the lottery value for the “miss” role. Therefore, in the present embodiment, it is not necessary to store the lottery value data (“0”) of the “miss” combination in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

  Further, in the process of S587 in the table data acquisition process (the processes of S585 to S587) of the second stage (during the acquisition of the sub flag D “reach eye lip”), the CT shown in FIG. 122 is calculated based on the calculated lottery table address. From the medium CT win lottery table (corresponding to the lottery table with the number of sets in CT in FIG. 56 added), the lottery table used at the normal CT state (starting address “dNMTCTS_RER”) or the lottery table in the high-probability CT state (starting address “dSPCTCTS_RR”) ) Is selected.

  In the lottery table used in the high-probability CT state, as shown in FIG. 122, a “decision bit” (judgment data) consisting of 1-byte data is stored in the address area next to the start address “dSPCTCTS_RER”. The determination bit stores data indicating the range of the address in which the lottery value of the lottery target is stored. As in the example shown in FIG. 122, when the lottery value of the lottery target (high-accuracy CT) is stored only in the address next to the storage area of the “determination bit” of the lottery table in the high probability CT state, the determination is made. In the bit storage area, 1-byte data “00000001B” in which “1” is stored only in bit 0 is stored as a determination bit. On the other hand, like the lottery table used in the normal CT state, when the lottery value of the lottery target (high-accuracy CT and normal CT) is stored at the next address and the next address of the determination bit storage area, FIG. As shown in (1), 1-byte data "00000011B" in which "1" is stored only in bits 0 and 1 is stored as a determination bit in the determination bit storage area. When such a determination bit is provided, it is not necessary to store the lottery value data not subject to the lottery in the area of the address where the bit data in the determination bit is “0” in the lottery table.

  Further, in the lottery table used in the high-probability CT state, as shown in FIG. 122, the lottery value of the high-probability CT winning is stored in the address “dSPCTCTS_RER + 2” next to the “decision bit”, and the lottery value of the high-probability CT winning is stored. Data defined in the address "cABS_HIT" is stored. In the present embodiment, the data defined in the address “cABS_HIT” is data indicating the winning confirmation (100% winning) (hereinafter, “confirmation data”). Further, in the present embodiment, since it is not necessary to provide random determination lottery data (“0”) for CT in the CT random determination random determination table during CT, as shown in FIG. 122, the fixed data defined in the address “cABS_HIT” is set. Can be defined as "0". That is, in the CT winning lottery table during CT having the above configuration, the lottery value “0” can be used as the finalized data.

  In addition, as described in the lot number table for additional CT sets in FIG. 56, in the present embodiment, in the lottery for additional number of sets in CT in the high probability CT state, “high probability CT winning” is always determined. Therefore, in the present embodiment, on the source program, the confirmed data can be stored as the lottery value of the high-probability CT winning lot in the CT lottery table during CT shown in FIG.

  Like the lottery table of the second stage (when the sub-flag D “reach eye lip” is acquired), the lottery target combination of the CT lottery and the non-lottery combination (sub-flag D) are determined by the value of each bit data forming the determination bit. ) Is determined, it is not necessary to store the lottery value data (miss data) of the winning combination that is not a lottery target in the table. The lottery value “0” can be used as the finalized data in which the winning probability of the lottery target combination is 100%. From these things, in this embodiment, the capacity of the CT winning lottery table in CT (the lottery table with the number of sets in CT added) can be compressed, and the free capacity in the main ROM 102 can be secured (increased). , It is possible to improve the game playability by utilizing the increased free space. Further, in the present embodiment, an example in which this technique is used in the CT winning process during CT has been described, but the present invention is not limited to this, and the ART lottery (see FIG. 115) and the ART game number added lottery (see FIG. 117). ), CT lottery (see FIG. 154, which will be described later), and CZ pull-back lottery (see FIG. 157, which will be described later) described later, and the like.

[1-byte lottery processing]
Next, with reference to FIGS. 123 and 124, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 119) will be described. FIG. 123 is a flowchart showing the procedure of the 1-byte lottery process. Further, FIG. 124 is a diagram showing an example of a source program for executing the 1-byte lottery process.

  First, the main CPU 101 uses a 1-byte random number value for CT random determination in CT stored in a random number storage area (not shown) in the main RAM 103 (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110). Set (S591). Next, the main CPU 101 extracts the lottery determination data (the determination bit in the lottery table defined in the second stage of FIG. 122) from the CT random determination table in CT based on the address calculated in S587 during the table data acquisition process. It is acquired (S592). In addition, in this processing, the main CPU 101 sets the number of determination bits “8” as the initial value of the lottery number.

  Next, the main CPU 101 determines whether or not the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to the bit data in the determination bit associated with the current lottery count, and if the bit data is "1", determines that the lottery target is selected. In the present embodiment, bits 0 to 7 in the determination bit are associated with the lottery numbers “8” to “1”, respectively.

  In S593, when the main CPU 101 determines that the lottery determination data is not the lottery target (NO in S593), the main CPU 101 performs the process of S599 described below. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is the lottery target (YES in S593), the main CPU 101 acquires the lottery value from the CT lottery table during CT (S594).

  Next, the main CPU 101 determines whether or not the lottery value is “0” (winning confirmation data) (S595).

  In S595, when the main CPU 101 determines that the lottery value is “0” (YES in S595), the main CPU 101 ends the 1-byte lottery process, and the process is the CT random determination process in CT (FIG. 119). (See) S574. On the other hand, in S595, when the main CPU 101 determines that the lottery value is not “0” (NO in S595), the main CPU 101 performs CT lottery (CT lottery additional lottery) processing (S596). Specifically, the main CPU 101 subtracts the lottery value from the random number value (1-byte random number value) and sets the subtraction result as the random number value.

  Next, the main CPU 101 determines whether or not the CT lottery in S596 has been won (S597). In the CT lottery in S596, the main CPU 101 determines that the winning is won when the subtraction result in S596 is “0” or less (so-called “carrying” occurs).

  In S597, when the main CPU 101 determines that the CT lottery is won (in the case of YES determination in S597), the main CPU 101 ends the 1-byte lottery process and the CT lottery process during CT (see FIG. 119). Move to S574. On the other hand, when the main CPU 101 determines in S597 that the CT lottery has not been won (NO in S597), the main CPU 101 stores the lottery value storage address (lottery address) to be referred to in the CT lottery table during CT. Is updated to the next lottery address (S598).

  After the processing of S598 or when the determination of S593 is NO, the main CPU 101 subtracts 1 from the lottery number (S599). Next, the main CPU 101 determines whether or not the number of lotteries is “0” (S600).

  In S600, when the main CPU 101 determines that the number of lotteries is not “0” (NO in S600), the main CPU 101 returns the process to S593 and repeats the processes from S593. On the other hand, in S600, when the main CPU 101 determines that the number of lotteries is “0” (YES in S600), the main CPU 101 ends the 1-byte lottery process, and the process is the CT random determination process in CT ( (See FIG. 119) (S574).

  In the present embodiment, the 1-byte lottery process is performed as described above. The 1-byte lottery process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  In the random number acquisition process of S591 during the 1-byte lottery process, as shown in FIG. 124, the “LDQ” instruction, which is the instruction code for the main CPU 101 dedicated to addressing using the Q register (extended register), is executed on the source program. Used. Therefore, in the present embodiment, the instruction code using the Q register (extended register) is used even in the 1-byte lottery process to directly access the main ROM 102, the main RAM 103, and the memory map I / O. Therefore, the instruction code related to the address setting can be omitted, and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Processing during BB start]
Next, with reference to FIG. 125, the during-BB start processing performed in S415 in the state-based control processing (see FIG. 104) will be described. It should be noted that FIG. 125 is a flowchart showing the procedure of the BB start processing.

  First, the main CPU 101 executes the lottery processing for adding the number of ART games based on the internal winning combination by referring to the lottery table for adding bonus ART games (see FIG. 59) (S611). Next, the main CPU 101 determines whether or not the additional lottery has been won (S612).

  In S612, when the main CPU 101 determines that the additional lottery has not been won (NO in S612), the main CPU 101 terminates the BB start process and also controls by state (see FIG. 104). finish. On the other hand, when the main CPU 101 determines in S612 that the additional lottery is won (in the case of YES determination in S612), the main CPU 101 adds the winning result (the number of additional games) to the ART game number for ending ART (S613). ..

  Next, the main CPU 101 determines whether or not the number of ART sets is “0” (S614). In S614, when the main CPU 101 determines that the number of ART sets is not “0” (NO in S614), the main CPU 101 terminates the BB start process and controls by state (see FIG. 104). ) Also ends.

  On the other hand, when the main CPU 101 determines in S614 that the number of ART sets is "0" (YES in S614), the main CPU 101 adds "1" to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 finishes the BB start processing, and also finishes the state-based control processing (see FIG. 104).

[Loading priority storage processing]
Next, with reference to FIGS. 126 and 127, the attraction-in priority storage processing performed in S212 in the main flow (see FIG. 82) will be described. FIG. 126 is a flow chart showing the procedure of the attraction-in priority storage process. Further, FIG. 127 is a diagram showing an example of a source program for executing the processes of S625 and S626 described later during the pull-in priority storing process.

  First, the main CPU 101 sets the number of search reels to "3" (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this processing, the attraction priority table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 executes a pull-in priority storage area selection process (S623). In this processing, the pull-in priority data storage area of the reel to be searched is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs a symbol code acquisition process (S625). In this processing, the symbol code is acquired by referring to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 128 described later.

  Next, the main CPU 101 performs a logical product calculation process (S626). In this process, the main CPU 101 performs a winning operation flag data generation process. Details of the logical product operation processing will be described later with reference to FIG. 133 described later.

  Next, the main CPU 101 performs a pull-in priority order acquisition process (S627). In this process, the main CPU 101 sets the bit to "1" in the winning operation flag (winning combination) storage area (see FIGS. 28 to 30), and sets the bit to "1" in the hit request flag storage area. With regard to the winning combination set to ", the attraction priority data is acquired by referring to the attraction priority table (see FIG. 27). The details of the attraction-in priority acquisition process will be described later with reference to FIGS. 134 and 135 described later.

  Next, the main CPU 101 stores the acquired attraction priority data in the attraction priority data storage area (not shown) in the main RAM 103 (S628). At this time, the pull-in priority data is stored in the pull-in priority data storage area so that the value of each priority and the bit of the storage area correspond.

  The pull-in priority data storage area is provided with a storage area for priority data for each type of main reel. In each attraction priority data storage area, attraction priority data determined according to each symbol position "0" to "19" of the corresponding main reel is stored. In the present embodiment, by referring to this pull-in priority data storage area, it is searched whether or not there is a more appropriate number of sliding pieces in addition to the number of sliding pieces determined based on the stop table.

  The content of the priority attraction-in data stored in the attraction-in priority data storage area differs depending on the type of attraction-in priority table number in the attraction-in priority table referred to when determining the attraction-in priority data. Further, the larger the value of the attraction-in priority data, the higher the priority. By referring to the attraction-in priority data, it is possible to make a relative evaluation of the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol for which the largest value is determined as the attraction-in priority data is the symbol with the highest priority. Therefore, it can be said that the attraction-in priority data indicates the order between the symbols arranged on the peripheral surface of the main reel. In addition, when there are a plurality of symbols having the same value of the attraction-in priority data, one symbol is determined according to the priority order defined by the priority order table.

  Next, the main CPU 101 updates the attraction-in priority storage area (S629). In this process, the main CPU 101 sets the attraction-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is "0" (S631).

  In S631, when the main CPU 101 determines that the number of symbol checks is not “0” (NO in S631), the main CPU 101 returns the processing to S625 and repeats the processing of S625 and thereafter. On the other hand, in S631, when the main CPU 101 determines that the number of symbol checks is "0" (YES in S631), the main CPU 101 executes the process of changing the reel to be searched (S632).

  Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the series of processes described above has been performed for all the main reels (S634).

  When the main CPU 101 determines in S634 that the number of search reels is not “0” (NO in S634), the main CPU 101 returns the process to the process of S622 and repeats the processes of S622 and subsequent steps. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (YES in S634), the main CPU 101 ends the attraction-in priority storage process and executes the process in the main flow (FIG. 82)) to S213.

  In this embodiment, the attraction-in priority storage process is performed as described above. The processing of S625 and S626 during the above-mentioned pull-in priority storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 127.

  Among them, the logical product operation processing of S626 is performed by the main CPU 101 executing the source code "CALLF SB_DAND_00" in FIG. 127. The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code “CALLF SB_DAND_00” in FIG. 127 is executed, the process is performed on the address specified by “SB_DAND_00”. A jump is made and the logical product arithmetic processing is started.

[Design code acquisition process]
Next, with reference to FIG. 128 to FIG. 132, the symbol code acquisition process performed in S625 in the attraction-in priority storage process (see FIG. 126) will be described. FIG. 128 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 129 is a diagram showing an example of a source program for executing the symbol code acquisition process. 130A is a diagram showing an example of the configuration of the first reel (left reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition processing, and FIG. 130B is the first reel symbol arrangement table set. It is a figure which shows an example of a structure of the symbol corresponding winning operation table referred at time. 131A is a diagram showing an example of the configuration of the second reel (middle reel) symbol arrangement table that is actually referred to on the source program of the symbol code acquisition processing, and FIG. 131B is the second reel symbol arrangement table set. It is a figure which shows an example of a structure of the symbol corresponding winning operation table referred at time. Further, FIG. 132A is a diagram showing an example of the configuration of the third reel (right reel) symbol arrangement table that is actually referred to on the source program of the symbol code acquisition processing, and FIG. 132B is the third reel symbol arrangement. It is a figure which shows an example of a structure of the symbol corresponding winning operation table referred at the time of table setting.

  First, the main CPU 101 performs a clearing process of the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning operation flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 130A) (S642).

  Next, the main CPU 101 determines whether or not the first reel (the left reel 3L) is stopped (S643).

  In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (YES in S643), the main CPU 101 performs the process of S647 described below. On the other hand, in S643, when the main CPU 101 determines that the first reel (left reel 3L) is not stopped (NO in S643), the main CPU 101 refers to the second reel symbol arrangement table (see FIG. 131A). Set (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether or not the second reel (middle reel 3C) is stopped (S645).

  In S645, when the main CPU 101 determines that the second reel (the middle reel 3C) is stopped (YES in S645), the main CPU 101 performs the process of S647 described below. On the other hand, in S645, when the main CPU 101 determines that the second reel (middle reel 3C) is not stopped (NO in S645), the main CPU 101 reads the third reel symbol arrangement table (see FIG. 132A). Set (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten with the third reel symbol arrangement table.

  After the processing of S646, or when S643 or S645 is YES, the main CPU 101 performs the symbol check process at the time of executing the stop operation for the reel to be stopped, and the symbol corresponding to the symbol acquired by the symbol check process. The winning operation table is acquired (S647). For example, when the first reel (the left reel 3L) is stopped and the symbol located on the activated line at the time of the stop operation is “white 7”, the main CPU 101 causes the main CPU 101 to start from the address “dR1_SVN1” to the address “dR1_SVN2” in FIG. 130B. The start address of the symbol corresponding winning operation table defined in the block of "-1" is acquired.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 81 conducts the compressed data storage process described in FIG. 101 (S649). In this process, the main CPU 101 mainly performs a process of transferring (developing) the winning operation flag data which can be won stored in the symbol corresponding winning operation table to the corresponding storage area in the winning operation flag storage area.

  For example, when the first reel (the left reel 3L) is stopped and the symbol located on the activated line at the time of the stop operation is “white 7”, the winning symbol combination (combination) is as shown in FIGS. As shown in FIG. 30, combination names “C_2nd_A_01”, “C_2nd_A_01” and “C_SP1_01” defined in the second storage area, and combination names “C_9 sheets C_01” to “C_9 sheets C_03” defined in the third storage area, "C_9 sheets C_07" to "C_9 sheets C_09" and "C_9 sheets E_01", combination names "C_RB combination A_01", "C_RB combination A_02", "C_RB combination B_01" to "C_RB combination B_04" defined in the fourth storage area , “C_RB role C_01” and “C_RB role C_02”, defined in the sixth storage area. Combination names “C_reach eye lip C_01” to “C_reach eye lip C_03”, “C_reach eye lip D_01”, “C_reach eye lip D_02” and “C_reach eye lip E_01”, and the tenth storage area It is the combination name “C_BB1” defined in.

  In this case, the storage destination of the first block (0th to 7th storage areas) of the prize-winning winning operation flag data stored in the symbol corresponding winning operation table is stored at the address “dR1_SVN1 + 1” in the table shown in FIG. 130B. It is designated by the designated 1-byte designated data "01011100B" (see the comment "storage area +2, +3, +4, +6" column in FIG. 130B). The storage destination of the second block (8th to 11th storage areas) of the winning operation flag data which can be won stored in the symbol corresponding winning operation table is stored at the address “dR1_SVN1 + 6” in the table shown in FIG. 130B. It is designated by the 1-byte designated data “10000000B” (see the comment “storage area +10” column in FIG. 130B).

  Note that in the present embodiment, bits 0 to 7 of the designated data of the first block are bits that respectively designate the 0th to 7th storage areas of the first block as the storage destination, and the designated data of the second block Bits 0 to 3 are bits for specifying the eighth to eleventh storage areas of the second block, respectively, as the storage destination. Then, in the 1-byte designated data of each block, "1" is stored in the bit corresponding to the storage area in the winning operation flag storage area that is the storage destination of the winning operation flag data.

  Therefore, for example, when the first reel (the left reel 3L) is stopped and the symbol located on the activated line at the time of the stop operation is “white 7”, in the process of S649, the address in the table shown in FIG. 130B is set. The winning operation flag data “00010000B” or “00000100B” stored in “dR1_SVN1 + 2” is transferred from the symbol corresponding winning operation table to the second storage area in the winning operation flag storage area and stored in the address “dR1_SVN1 + 3”. The winning operation flag data “0010000B” or “00000100B” is transferred from the symbol corresponding winning operation table to the third storage area in the winning operation flag storage area. In this case, in the process of S649, the winning operation flag data “10000000B”, “01000000B” or “001000000B” stored in the address “dR1_SVN1 + 4” in the table shown in FIG. 130B is won from the symbol corresponding winning operation table. The winning operation flag data “0010000B”, “00010000B” or “00001000B” transferred to the fourth storage area in the operation flag storage area and stored at the address “dR1_SVN1 + 5” is stored from the symbol corresponding winning operation table. It is transferred to the sixth storage area in the area. Further, in this case, in the processing of S649, the winning operation flag data “10000000B” stored in the address “dR1_SVN1 + 8” in the table shown in FIG. 130B is the tenth in the winning operation flag storage area from the symbol corresponding winning operation table. It is transferred to the storage area.

  After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and moves the processing to S626 of the attraction-in priority storage processing (see FIG. 126).

  In the present embodiment, the symbol code acquisition process is performed as described above. The above-described symbol code acquisition processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 129. Among them, the compressed data storage processing of S649 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 129.

  The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 129 is executed, processing is performed at the address specified by "SB_BTEP_00". A jump is made and the compressed data storage process is started. Then, in this compressed data storage processing, as described above, the winning operation flag data (compressed data) stored in the symbol corresponding winning operation flag table of each reel is expanded (copied) in the winning operation flag storage area.

  In the present embodiment, the winning / compressing data compression / decompression process is performed by the processing procedure described in S647 to S649 in the above-described symbol code acquisition process, and the main CPU 101 dedicated instruction code described above is included in the process. By using, it is possible to improve the efficiency of the compression / decompression processing of the winning data, and it is possible to effectively utilize the limited capacity of the main RAM 103.

  Further, in the present embodiment, in the compressed data storage processing of S649 during the symbol code acquisition processing, the jump destination address "SB_BTEP_00" specified by the "CALLF" command is the compression of S330 during the symbol setting processing described in FIG. In the data storage process, it is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process, and S649 and S330. In both processes, the source program of the compressed data storage process is shared (modularized). In this case, since it is not necessary to separately provide a source program for the compressed data storage process in both S649 and S330, the capacity of the source program (capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[AND operation processing]
Next, with reference to FIG. 133, for example, the logical product operation process performed in S626 in the pull-in priority storage process (see FIG. 126) will be described. FIG. 133 is a flowchart showing the procedure of the AND operation processing. Note that the logical product operation processing shown in FIG. 133 is performed not only in S626 in the attraction priority order storage processing (see FIG. 126) but also in S687 in the attraction priority order acquisition processing (see FIGS. 134 and 135 below). Is also executed.

  In the logical product calculation process executed in S626 of the attraction-in priority storage process (see FIG. 126), the two pieces of data that are logical product calculated are the winning operation flag storage set in S650 in the above-mentioned symbol code acquisition process. The data of the area and the data of the symbol code storage area. The former data corresponds to "logical product destination data" described later, and the latter data corresponds to "logical product source data" described later. Further, in this case, the number of bytes “12” of the data length (12 bytes) set in S650 during the above-mentioned symbol code acquisition processing corresponds to the “number of logical product” described later.

  On the other hand, in the logical product operation process executed in S687 in the later-described pull-in priority order acquisition process (see FIGS. 134 and 135, which will be described later), the two data items to be subjected to the logical product are hit (pull-in) request flag storage areas. And the data of the winning operation flag storage area. The former data corresponds to "logical product destination data" described later, and the latter data corresponds to "logical product source data" described later. Further, in this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described in FIG. 136B described later corresponds to the “number of times of logical product” described later.

  First, the main CPU 101 acquires logical product original data (for example, data in the symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, the data of the winning operation flag storage area), and stores the calculation result as the logical product destination data (S662).

  Next, the main CPU 101 adds 1 to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 increments the address of the logical product destination data to be referenced by 1 (S664).

  Next, the main CPU 101 subtracts 1 from the logical product number (S665). Next, the main CPU 101 determines whether or not the number of logical products is “0” (S666).

  In S666, when the main CPU 101 determines that the number of ANDs is not “0” (NO in S666), the main CPU 101 returns the process to S661 and repeats the processes from S661. On the other hand, when the main CPU 101 determines in S666 that the number of AND operations is “0” (YES in S666), the main CPU 101 terminates the AND operation processing and stores the processing, for example, in the attraction priority order storage. The processing moves to S627 of the processing (see FIG. 126).

[Acquisition priority acquisition processing]
Next, with reference to FIGS. 134 to 137, the attraction priority order acquisition processing performed in S627 in the attraction priority order storage processing (see FIG. 126) will be described. Note that FIG. 134 and FIG. 135 are flowcharts showing the procedure of the attraction-in priority order acquisition process. FIG. 136A is a diagram showing an example of a source program for executing the processing of S680 to S683, which will be described later, during the attraction priority acquisition processing, and FIG. 136B shows the processing of S686, which will be described later, during the attraction priority acquisition processing. FIG. 136C is a diagram showing an example of a source program for executing, and FIG. 136C is a diagram showing an example of a source program for executing the process of S687, which will be described later, during the pull-in priority obtaining process. In addition, FIG. 137 is a diagram showing an example of the configuration of the attraction-in priority table that is actually referred to in the source program of the attraction-in priority acquisition processing.

  First, the main CPU 101 determines whether or not it is time to check the right reel 3R (specific display row) (S671).

  In S671, when the main CPU 101 determines that it is not time to check the right reel 3R (NO in S671), the main CPU 101 performs the process of S674 described below. On the other hand, in S671, when the main CPU 101 determines that it is time to check the right reel 3R (YES in S671), the main CPU 101 sets “ANY combination” as the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (predetermined symbol combination) is included (S672). The “ANY winning combination” here means a winning combination in which the winning is fixed regardless of at least the stop symbol of the right reel 3R (at least a winning symbol in which the stopping symbol of the right reel 3R is an arbitrary symbol).

  In S672, when the main CPU 101 determines that the “ANY combination” is not included in the symbol combination related to the internal winning combination (when the determination of S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes “ANY winning combination” (YES in S672), the main CPU 101 determines that “ANY” in the winning operation flag storage area. The storage area corresponding to the "role" is masked (S673). Specifically, the main CPU 101 sets "1" to the bit corresponding to the "ANY combination" in the winning operation flag storage area.

  After the processing of S673 or when the determination of S671 or S672 is NO, the main CPU 101 sets "1" to the address of the rearmost storage area as the address of the winning operation flag storage area (see FIGS. 28 to 30). The added address is set, the stop prohibition data is set, and the winning operation flag data length (the data length of the winning operation flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons whose stop operation has been detected. The operation state of the stop button is acquired by referring to the operation stop button storage area (see FIG. 33).

  Next, the main CPU 101 subtracts 1 from the address of the winning operation flag storage area that has been set (-1 update) (S676). Next, the main CPU 101 generates hit request flag data from the set winning operation flag storage area and the hit request flag storage area corresponding thereto (see FIGS. 28 to 30), and the created hit request flag data. The prohibited winning operation position is generated based on (S677).

  Next, the main CPU 101 determines whether or not the stop operation position is the prohibited winning operation position (S678).

  In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning operation position (NO in S678), the main CPU 101 performs the process of S684 described below. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (YES in S678), the main CPU 101 determines that the value of the stop button operation counter is the third stop value. It is determined whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button actuation counter is the third stop value (YES in S679), the main CPU 101 performs the process of S705 described below. On the other hand, in S679, when the main CPU 101 determines that the value of the stop button actuation counter is not the value of the third stop (when NO in S679), the main CPU 101 determines that the value of the stop button actuation counter is the second stop. It is determined whether the value is a value (S680).

  When the main CPU 101 determines in S680 that the value of the stop button actuation counter is not the second stop value (NO in S680), the main CPU 101 performs the process of S684 described below. On the other hand, when the main CPU 101 determines in S680 that the value of the stop button actuation counter is the second stop value (YES in S680), the main CPU 101 determines whether the right reel 3R has been stopped. It is determined (S681).

  In S681, when the main CPU 101 determines that the right reel 3R is stopped (YES in S681), the main CPU 101 performs the process of S684 described below. On the other hand, when the main CPU 101 determines in S681 that the right reel 3R is not stopped (NO in S681), the main CPU 101 determines that the hit request flag may interfere with the "ANY winning combination". It is determined whether or not (whether or not “ANY combination” is included in the symbol combination (winning combination) related to the internal winning combination) (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may interfere with the “ANY winning combination” (YES in S682), the main CPU 101 performs the process of S684 described below. On the other hand, when the main CPU 101 determines in S682 that the hit request flag is a flag that may be interfered with by the "ANY winning combination" (when NO is determined in S682), the main CPU 101 determines that the current check is "ANY." It is determined whether or not it is time to check the hit request flag including “win” (S683).

  In S683, when the main CPU 101 determines that the current check is at the time of checking the hit request flag including the “ANY winning combination” (YES in S683), the main CPU 101 performs the process of S705 described below.

  On the other hand, in S683, when the main CPU 101 determines that the current check is not the time of checking the hit request flag including the "ANY combination" (NO in S683), NO in S678 or S680, or S681. Alternatively, if the determination in S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning operation flag data length is “0” (S685).

  In S685, when the main CPU 101 determines that the winning operation flag data length is not “0” (NO in S685), the main CPU 101 returns the process to S676 and repeats the processes from S676.

  On the other hand, when the main CPU 101 determines in S685 that the winning operation flag data length is "0" (YES in S685), the main CPU 101 performs stop control pull-in request flag setting processing (S686). .. This processing is performed by the main CPU 101 sequentially executing each processing defined by the source program of FIG. 136B. Therefore, in this processing, the logical product operation processing described in FIG. 133 is performed. In the logical product calculation process executed in the process of S686, as described above, the data in the hit (pull-in) request flag storage area is set to the "logical product destination data", and the data in the winning operation flag storage area is set. The "logical product original data" is set, and the "logical product number" is set to the byte number "1" of the data length (1 byte) of the RT operation combination display flag. The RT operation combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 11 is shown as shown in FIGS. 28 to 30. Become.

  Next, the main CPU 101 refers to the attraction-in priority table address storage area to obtain the attraction-in priority table (S687). This processing is performed by the main CPU 101 sequentially executing each processing defined by the source program of FIG. 136C. Therefore, in this process, the initial value “1 (001H)” of the pull-in priority data is set to the address that is currently set, and the start addresses shown in FIG. 137 are “dPLVLTB00” to “dPLVLTB05”. The attraction priority table stored in any of the blocks is acquired. Note that the attraction priority table stored in the blocks whose start addresses are “dPLVLTB00” to “dPLVLTB05” shown in FIG. 137 are respectively the attraction priority table numbers “00” to “05” described in FIG. 27. Corresponds to the pull-in priority table.

  Next, the main CPU 101 determines whether or not the data of the attraction priority table stored at the currently set address is the end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data of the attraction priority table stored at the currently set address is the end code (YES in S688), the main CPU 101 proceeds to S705 described later. Process. On the other hand, in S688, when the main CPU 101 determines that the data of the attraction-in priority table stored at the currently set address is not the end code (NO in S688), the main CPU 101 determines the winning operation. The flag storage area is set (S689).

  Next, the main CPU 101 obtains the attraction-in priority data from the attraction-in priority table based on the currently set address (S690). Next, the main CPU 101 sets the block counter of the attraction priority table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter of the attraction priority table.

  Next, the main CPU 101 sets the number of checks in the attraction priority table and increments (+1 updates) the address of the attraction priority table to be referenced (S692). In this embodiment, in this process, the main CPU 101 sets “8” (the number of bits of check data defined in the attraction priority table shown in FIG. 137) in the number of checks in the attraction priority table.

  Next, the main CPU 101 acquires the check data (see FIG. 137) based on the updated address of the attraction-in priority table, and extracts the check bit from the check data (S693). In this embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the processing of S690, when the attraction-in priority data “03EH” is acquired from the attraction-in priority table defined in the block whose start address is “dPLVLTB00”, in the processing of S693, “10001000B” is set as the check data. It is acquired and “0” is extracted as the value of the check bit.

  Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

  In S694, when the main CPU 101 determines that the value of the extracted check bit is not “1” (NO in S694), the main CPU 101 performs the process of S699 described below. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is "1" (YES in S694), the main CPU 101 increments the address of the attraction-in priority table to be referenced by one. (+1 update), and the determination data (“flag determination data” in FIG. 137) is acquired from the pull-in priority table based on the updated address (S695).

  Next, the main CPU 101 determines whether or not the currently obtained winning operation flag data is a determination target based on the determination data acquired in S695 (S696). In this process, the main CPU 101 compares the currently obtained winning operation flag data with the determination data, determines whether the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently-acquired winning operation flag data is the determination target.

  In S <b> 696, when the main CPU 101 determines that the winning operation flag data is not the determination target (NO in S <b> 696), the main CPU 101 performs the process of S <b> 699 described below. On the other hand, when the main CPU 101 determines in S696 that the winning operation flag data is the determination target (YES in S696), the main CPU 101 updates the attraction-in priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set attraction-in priority data with the attraction-in priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 executes check data update processing (S698). In this process, the main CPU 101 shifts the check data rightward by 1 bit (direction from bit 7 to bit 0). In this process, "0" is set in bit 7 of the check data after the shift.

  After the processing of S698 or when the determination of S694 or S696 is NO, the main CPU 101 determines whether or not there is a check target bit (a bit for which "1" is set) in the check data (S699).

  In S699, when the main CPU 101 determines that there is no check target bit in the check data (NO in S699), the main CPU 101 performs the process of S702 described below. On the other hand, in S699, when the main CPU 101 determines that the check data has a bit to be checked (YES in S699), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update). ), And 1 is subtracted from the number of checks (S700).

  Next, the main CPU 101 determines whether the number of checks is "0" (S701). When the main CPU 101 determines in S701 that the number of checks is not "0" (NO in S701), the main CPU 101 returns the process to S698, and repeats the processes from S698.

  On the other hand, in S701, when the main CPU 101 determines that the number of checks is “0” (YES in S701), the main CPU 101 indicates the number of checks in the address of the prize operation flag storage area currently referred to. The address of the winning operation flag storage area is updated by adding the initial value "8", and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is "0" (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (NO in S703), the main CPU 101 returns the process to S692 and repeats the processes from S692.

  On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is “0” (YES in S703), the main CPU 101 adds 1 to the address of the attraction priority table to be referred to (+1 update). ) (S704). For example, if the currently-referred attraction-in priority table is the attraction-in priority table defined in the block whose start address is "dPLVLTB00", this process causes the attraction-in priority table to be referenced to have the start address " It is changed to the attraction-in priority table defined in the block which is “dPLVLTB01”. After the processing of S704, the main CPU 101 returns the processing to the processing of S688 and repeats the processing of S688 and thereafter.

  Here, the process returns to the processing of S679, S683 or S688 again, and in the case of YES determination in S679, S683 or S688, the main CPU 101 uses the attraction-in priority data set at this time as the final attraction-in priority data. Set (S705). When S679 or S683 is YES, the main CPU 101 sets "0 (00H)" as the final attraction priority data. In this case, since the end code is assigned to the pull-in priority data "0 (00H)", no pull-in data (stop prohibited) is set. Then, after the processing of S705, the main CPU 101 terminates the attraction-in priority order acquisition processing, and moves the processing to S628 of the attraction-in priority storage processing (see FIG. 126).

  In the present embodiment, the attraction-in priority order acquisition process is performed as described above. Note that the attraction priority handling processing of “ANY combination” of S680 to S683 during the attraction priority order acquisition processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 136A. Be seen. Among them, for example, the determination process of S683 is executed by the "JCP" instruction (predetermined determination instruction) on the source program. The “JCP” instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

  For example, when the source code "JCP cc, A, n, e" is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. If so, the process jumps to the address designated by e. In the "cc condition" of the "JCP" instruction, one of the carry flag state and the zero flag state in the flag register F is designated (see FIG. 11). For example, if "C" is specified in cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified in cc, the condition of cc is satisfied. Means that the carry flag is "0" (off state). Further, for example, if "Z" is specified in cc, the condition of cc means that the zero flag is "1" (on state), and if "NZ" is specified in cc, the cc of The condition means that the zero flag is "0" (off state).

  When the "JCP" command is used on the source program for the pull-in priority handling process of "ANY role", the command related to the address setting can be omitted (the command related to the address setting is separately provided. Since it is not necessary to provide), it is possible to improve the processing efficiency of the pull-in priority handling processing of the “ANY role” and reduce the capacity of the source program (used capacity of the main ROM 102).

  Further, the stop control attraction request flag setting processing of S686 during the attraction priority acquisition processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 136B. In the stop control pull-in request flag setting processing of S686, as shown in FIG. 136B, the "LDQ" instruction and the "CALLF" instruction for performing address designation using the Q register (extension register) which is the instruction code dedicated to the main CPU 101. Command is used.

  Therefore, in the stop control pull-in request flag setting processing of S686, by using the "LDQ" instruction using the Q register (extended register), the main ROM 102, the main RAM 103, and the memory map I / O are directly accessed. can do. In this case, the address setting instruction can be omitted in the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced. The "CALLF" instruction is a 2-byte instruction code as described above. Therefore, in the stop control pull-in request flag setting process, by using these main CPU 101-dedicated instruction codes, the efficiency of the process can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

  Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the address "SB_DAND_00" of the logical AND operation process of the jump destination specified by the "CALLF" instruction is the same as that in FIG. This is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 during the pull-in priority storage processing described in (1) (see FIG. 127). That is, in the present embodiment, the source program for executing the logical product operation process performed in the stop control pull-in request flag setting process of S686 during the priority pull-in priority acquisition process is performed by the source program executed in S626 during the pull-in priority store process. This is the same as the source program for executing the product arithmetic processing, and the source program for the logical product arithmetic processing is shared (modularized) in both the processing of S686 and S626. In this case, since it is not necessary to separately provide a source program for the AND operation in both S686 and S626, the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  Further, in the acquisition processing of the attraction priority table (see FIG. 137) in S687 during the attraction priority acquisition processing described above, the main CPU 101 sequentially executes each source code defined by the source program of FIG. 136C. Done. Then, in the pull-in priority table acquisition processing of S687, as shown in FIG. 136C, the “LDQ” instruction for performing address designation using the Q register (extended register), which is the instruction code dedicated to the main CPU 101, is used.

  Therefore, also in the acquisition processing of the pull-in priority table in S687, the instruction related to the address setting can be omitted in the source program by using the "LDQ" instruction. As a result, it is possible to improve the efficiency of the acquisition processing of the attraction-in priority table and reduce the capacity of the source program (used capacity of the main ROM 102).

  As described above, in the various processes during the priority attraction-in order acquisition process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used, and the efficiency of the corresponding process and the reduction of the capacity of the source program are realized. is doing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and to reduce the capacity, and it is possible to improve the playability by utilizing the empty area corresponding to the reduced capacity. Becomes

[Reel stop control processing]
Next, with reference to FIGS. 138 to 140, the reel stop control processing performed in S213 in the main flow (see FIG. 82) will be described. Note that FIG. 138 is a flowchart showing the procedure of reel stop control processing. FIG. 139 is a diagram showing an example of a source program for executing the processing of S711 to S716 described later during the reel stop control processing, and FIG. 140 executes the processing of S726 described later during the reel stop control processing. It is a figure which shows an example of the source program for.

  First, the main CPU 101 executes reel stop enable signal OFF processing (S711). In this process, the main CPU 101 mainly performs a port output process of reel stop enable signal OFF data. Further, this processing is performed using the non-regular work area of the main RAM 103. The details of the reel stoppable signal OFF processing will be described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not they have become “constant speed”) (S712). In S712, when the main CPU 101 determines that the rotation speeds of all reels are not “constant speed” (NO in S712), the main CPU 101 repeats the processing of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotation speeds of all reels have reached the "constant speed" (YES in S712), the main CPU 101 performs a reel stoppable signal ON process (S713). In this process, the main CPU 101 mainly performs a port output process of reel stop enable signal ON data. Further, this processing is performed using the non-regular work area of the main RAM 103. The details of the reel stoppable signal ON processing will be described later with reference to FIG. 142 described later.

  Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

  In S714, when the main CPU 101 determines that the valid stop button is not pressed (NO in S714), the main CPU 101 returns the process to S713 and repeats the processes from S713. On the other hand, when the main CPU 101 determines in S714 that the valid stop button has been pressed (YES in S714), the main CPU 101 updates the operation stop button storage area (see FIG. 33) and indicates that the stop button has not been pressed. The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines the reel to be searched from the operation stop button (S716). Further, in this process, an address (start address) setting process of the spinning control data storage area in which the reel control management information of the reel to be searched is stored is also performed (source code “LDQ IX, wR1_CTRL− (wR2_CTRL) in FIG. 139. -WR1_CTRL) ").

  Next, the main CPU 101 executes reel stop enable signal OFF processing (S717). This process is performed using the non-regular work area of the main RAM 103, as in S711. The details of the reel stoppable signal OFF processing will be described later with reference to FIG. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 executes reel stop selection processing (S719). Although detailed description is omitted, in this process, the main CPU 101 performs a sliding frame number selection process.

  Next, the main CPU 101 determines a scheduled stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined scheduled stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding pieces to the stop start position and sets the addition result as the planned stop position.

  Next, the main CPU 101 executes a symbol code storage process (S721). In this process, the symbol code corresponding to the planned stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether the reel to be controlled is the last stopped reel (third stopped reel) (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button non-operation counter, and the value of the stop button non-operation counter is When it is "0", it is determined that the reel to be controlled is the reel that is finally stopped.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stopped reel (NO in S722), the main CPU 101 performs control change processing (S723). In this process, the stop information group used to stop the reels is updated when the reel is at the specific stop position. Next, the main CPU 101 executes the attraction-in priority storage process described in FIG. 126 (S724).

  Next, the main CPU 101 carries out a standby processing for the remaining stop interval time (S725). In this process, the main CPU 101 performs a standby process until a preset predetermined reel stop interval time elapses. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing of S711 and thereafter.

  Here, returning to the processing of S722 again, in S722, when the main CPU 101 determines that the reel to be controlled is the reel of the final stop (in the case of YES determination in S722), the main CPU 101 causes the excitation of all reels. It is determined whether or not is in the stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all reels is not stopped (NO in S726), the main CPU 101 repeats the process of S726.

  On the other hand, in S726, when the main CPU 101 determines that the excitation of all the reels is in the stopped state (when the determination in S726 is YES), the main CPU 101 keeps the stop button that has been subjected to the third stop operation in the ON state. It is determined whether or not (the stop button is not released) (S727). In S727, when the main CPU 101 determines that the third stop-operated stop button is still in the ON state (YES in S727), the main CPU 101 repeats the process of S727. On the other hand, in S727, when the main CPU 101 determines that the third stop-operated stop button is not still in the ON state (NO in S727), the main CPU 101 ends the reel stop control process and executes the process. The process moves to S214 in the main flow (see FIG. 82).

  In the present embodiment, the reel stop control process is performed as described above. Note that the processing of S711 to S716 during the above reel stop control processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 139. As shown in FIG. 139, in the reel stop control processing source program of the present embodiment, for example, an “LDQ” instruction for performing address designation using the Q register (extended register), which is an instruction code dedicated to the main CPU 101, or “ The "CALLF" instruction is used.

  Therefore, in the reel stop control process, by using such an instruction code dedicated to the main CPU 101, the capacity of the source program of the reel control process can be reduced and the processing efficiency of the reel stop control process can be improved. it can. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 that has increased in accordance with the reduced capacity, thereby improving the game playability. It becomes possible to raise.

  The determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 140, this processing is executed using “LDQ” instruction and “ORQ” instruction (predetermined OR operation instruction) on the source code.

  The "ORQ" instruction is an instruction code for performing an OR operation, and is an instruction code for the main CPU 101 dedicated to addressing using the Q register (extension register). Then, for example, when the source code "ORQ (k)" is executed on the source program, the data stored in the Q register (upper address value) and the 1-byte integer k (direct value: lower address value) are used. The contents of the memory at the designated address (stored data) and the contents of the A register (stored data) are ORed, and the result of the operation is stored in the A register.

  Therefore, in the determination process of S726 during the reel stop control process, first, when the source code "LDQ A, (.LOW.wR1_TIM)" in FIG. 140 is executed, the data stored in the Q register and the integer value " .LOW.wR1_TIM ", the contents of the memory at the address (excitation timer value of the first reel) are loaded into the A register. In the present embodiment, the address of the area in the main RAM 103 in which the excitation timer value of the first reel is stored is “F032h”. In the determination processing of S726 described above, the upper side address value “F0h” of the address “wR1_TIM (F032h)” is set in the Q register in advance when the LDQ instruction is executed, and the value of k (direct value) is set to the lower side. The address value (“.LOW.wR2_TIM” = 32h) is substituted.

  Next, when the source code "ORQ (.LOW.wR2_TIM)" in FIG. 140 is executed, the storage data (F0h) of the Q register and the address "wR2_TIM (of the area storing the excitation timer value of the second reel are stored. F03Dh) "lower side address value (3Dh) of the address specified by the memory content (second reel excitation timer value) and A register content (first reel excitation timer value) The calculation result (composite result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code "ORQ (.LOW.wR3_TIM)" in FIG. 140 is executed, the storage data (F0h) of the Q register and the address "wR3_TIM (of the region where the excitation timer value of the third reel is stored are stored. F048h) "lower address value (48h) specified by the memory contents (3rd reel excitation timer value) and A register contents (1st reel excitation timer value and 2nd reel excitation timer) Value is combined with the value), and the operation result (composition result of the excitation timer values of the first to third reels) is stored in the A register.

  As described above, in the present embodiment, various main CPU 101-dedicated instruction codes using the Q register (extended register) are used in the process of checking the reel (turning drum) stop state. Therefore, by using these instruction codes dedicated to the main CPU 101, it is possible to directly access the main ROM 102, the main RAM 103 and the memory map I / O, and to omit the address setting instruction on the source program. Therefore, the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  As described above, in the various processes during the reel stop control process of the present embodiment, the various command codes dedicated to the main CPU 101 described above are appropriately used to realize the corresponding process efficiency and the reduction of the source program capacity. ing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and to reduce the capacity, and it is possible to improve the playability by utilizing the empty area corresponding to the reduced capacity. Becomes

[Reel stop enable signal OFF processing]
Next, with reference to FIG. 141, the reel stoppable signal OFF processing performed in S711 or S717 in the reel stop control processing (see FIG. 138) will be described. Note that FIG. 141 is a flowchart showing the procedure of the reel stoppable signal OFF processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

  Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 carries out a reel stop enable signal OFF data setting process (S734).

  Next, the main CPU 101 performs non-regular port output processing (S735). In this processing, the main CPU 101 performs generation and output processing of OFF output data (output off mode data) described later based on the reel stop enable signal OFF data. It should be noted that this process is performed using the non-regular work area of the main RAM 103. Details of the non-regular port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores the data of all the registers saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

  After the processing of S737, the main CPU 101 ends the reel stoppable signal OFF processing. At this time, if the executed reel stop enable signal OFF processing is the processing of S711 in the reel stop control processing (see FIG. 138), the main CPU 101 shifts the processing to the processing of S712 in the reel stop control processing. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 in the reel stop control process (see FIG. 138), the main CPU 101 shifts the process to the process of S718 in the reel stop control process.

[Reel stop enable signal ON processing]
Next, with reference to FIG. 142, the reel stoppable signal ON processing performed in S713 during the reel stop control processing (see FIG. 138) will be described. Note that FIG. 142 is a flowchart showing the procedure of the reel stop enable signal ON processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

  Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 acquires the stop button state by referring to the operation stop button storage area (see FIG. 33) (S744). Next, the main CPU 101 performs a reel stop enable signal ON data setting process (S745).

  Next, the main CPU 101 performs non-regular port output processing (S746). In this processing, the main CPU 101 performs generation and output processing of ON output data (output ON mode data) described later based on the reel stop enable signal ON data. It should be noted that this process is performed using the non-regular work area of the main RAM 103. Details of the non-regular port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores the data of all the registers saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 in the stack pointer (SP) (S748). After the processing of S748, the main CPU 101 ends the reel stop enable signal ON processing, and shifts the processing to the processing of S714 in the reel stop control processing (see FIG. 138).

[Out-of-specification port output processing]
Next, with reference to FIGS. 143 and 144, regarding the non-regular port output process performed in S735 during the reel stoppable signal OFF process (see FIG. 141) and S746 during the reel stoppable signal ON process (see FIG. 142) explain. Note that FIG. 143 is a flowchart showing the procedure of the non-regulated port output processing. Further, FIG. 144 is a diagram showing an example of a source program for executing the non-specified port output processing.

  First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and determines that the reel stop enable signal OFF data is set when the reel output enable signal ON data is set. , It is determined that the port output setting is not the ON output mode.

  In S751, when the main CPU 101 determines that the port output setting is the ON output mode (YES in S751), the main CPU 101 performs the process of S753 described below. On the other hand, when the main CPU 101 determines in S751 that the port output setting is not the ON output mode (NO in S751), the main CPU 101 performs processing for generating OFF output data (output OFF mode data) (S752). ). In this process, of the ports (bits) that are currently in the output on state, turn off the port (bit) that you want to turn off and turn off the port (bit) that is currently in the output off state. OFF output data for maintaining the state is generated.

  After the processing of S752 or when the determination of S751 is NO, the main CPU 101 performs processing for generating ON output data (output ON mode data) (S753). In this process, of the ports (bits) that are currently in the output off state, turn on the port (bit) that you want to turn on and turn on the port (bit) that is currently in the output on state. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

  Then, after the processing of S754, the main CPU 101 ends the non-specified port output processing. At this time, if the non-regular port output process executed is the process of S735 during the reel stoppable signal OFF process (see FIG. 141), the main CPU 101 performs the process of S736 during the reel stoppable signal OFF process. Move to. On the other hand, if the executed non-regular port output process is the process of S746 during the reel stoppable signal ON process (see FIG. 142), the main CPU 101 shifts the process to the process of S747 during the reel stoppable signal ON process. Transfer.

  In this embodiment, the non-specified port output processing is performed as described above. The above-described non-specified port output processing is performed by the main CPU 101 sequentially executing the respective source codes specified by the source program of FIG. 144.

  Among them, in the OFF output data generation process of S752 during the above-mentioned non-regular port output process, the source codes “XOR (HL)” and “AND (HL)” in FIG. 144 are executed in this order. Done. Further, the ON output data generation processing of S753 during the above-described non-regular port output processing is performed by executing the source code “OR (HL)” in FIG. 144.

  By performing such generation processing of each output data on the source program, even if the ON output data generation processing of S753 is performed after the OFF output data generation processing of S752, the OFF output data generated in S752 Does not change.

  For example, the port output setting is the OFF output mode, the output data indicating the non-regulated port to be turned off in this process is “000101011” (“1” is the bit to be turned off), and the non-regulated port is currently set. When the output data (backup data) output to is “01010011” (“1” is a bit that is currently on), the data of bits 0, 1 and 5 of the backup data are changed from “1” to “1”. The OFF output data for setting to "0" is generated. In this case, first, when the source code “XOR (HL)” in FIG. 144 is executed, the exclusive OR operation of the output data “000101011” and the backup data “01010111” is performed, and the operation result is “ 01000100 "is obtained. Next, when the source code “AND (HL)” in FIG. 144 is executed, the logical product operation of the operation result “01000100” and the backup data “01010011” is performed, and the operation result “01000000” is set as the OFF output data. Is generated.

  After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 144) is executed, the calculation result “01000000” (OFF output data) and the current process are turned on. An OR operation is performed with the output data “00000000” (the port output setting is the OFF output mode, so “0” is set in each bit of the output data) indicating the non-regulated port to be processed, and the result of the operation is "01000000" is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, in the ON output data generation processing of S753, the output for maintaining the port (bit) whose output is in the ON state in the OFF output data is in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation process in S753 is performed after the OFF output data generation process in S752.

[Prize search processing]
Next, with reference to FIG. 145 to FIG. 147, the winning prize search processing performed in S214 in the main flow (see FIG. 82) will be described. It should be noted that FIG. 145 is a flowchart showing the procedure of the prize search processing. FIG. 146 is a diagram showing an example of a source program for executing the prize search processing. In addition, FIG. 147 is a diagram showing an example of the configuration of the payout amount data table that is actually referred to on the source program of the prize search processing.

  First, the main CPU 101 transfers and stores the data in each storage area stored in the symbol code storage area (see FIG. 35) to the corresponding storage area in the winning operation flag storage area (see FIGS. 28 to 30). (S761). At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the payout amount data table (the head address “dPAYNUMTB” of the payout amount data table shown in FIG. 147) in the HL register (S762). Next, the main CPU 101 sets the payout number table number (“5” in the present embodiment) as an initial value of the winning prize search counter, and sets the initial value in the B register (S763).

  Next, the main CPU 101 sets the data of the payout number of medals (any one, two, three, and nine in this embodiment) in the C register based on the address set in the HL register. The data to be judged is set in the A register, and "2" is added to the address set in the HL register (+2 is updated) (S764). In the payout amount data table shown in FIG. 147, the data of the payout amount of medals is “payout amount (1, 2, 3, or 9) * 2 + 0”, and the determination target data is the data following the payout amount data. It is 1-byte data (for example, "11111000B" or the like) stored in the address. Further, hereinafter, the data “0” in the data “Payout number (1, 2, 3, or 9) * 2 + 0” of the payout number of medals set in the C register is referred to as “determination bit”. This determination bit is information indicating whether or not the block is a determination target block for the winning search.

  Next, the main CPU 101 extracts the value of the determination bit from the data of the number of paid-out medals set in the C register (S765). Next, the main CPU 101 determines whether or not it is a determination target block based on the value of the extracted determination bit (S766). In this processing, the main CPU 101 determines that the block is the determination target block when the value of the extracted determination bit is “1”. In the present embodiment, as shown in FIG. 147, the value of the determination bit is always "0" regardless of the number of paid-out medals, so the process of S766 is always NO determination.

  In S766, when the main CPU 101 determines that the block is not the determination target block (NO in S766), the main CPU 101 performs the process of S768 described below. On the other hand, when the main CPU 101 determines in S766 that the block is the determination target block (YES in S766), the main CPU 101 subtracts 1 from the address of the winning operation flag storage area set in the DE register (- 1 update) (S767).

  After the processing of S767 or when the determination of S766 is NO, the main CPU 101 extracts the data in the storage area designated by the address of the winning operation flag storage area set in the DE register as the determination data (S768).

  Next, the main CPU 101 determines whether or not the result of the determination is a win based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a winning.

  When the main CPU 101 determines in S769 that the result of the determination is not a win (in the case of NO determination in S769), the main CPU 101 performs the process of S776 described later. On the other hand, in S769, when the main CPU 101 determines that the result of the determination is a win (in the case of YES determination in S769), the main CPU 101 determines that the current game is a three-card game (a game in which the number of medals is three). ) Is determined (S770).

  In S770, when the main CPU 101 determines that the current game is a three-card game (YES in S770), the main CPU 101 performs the process of S772 described later. On the other hand, in S770, when the main CPU 101 determines that the current game is not the 3-card game (NO in S770), the main CPU 101 pays out the 2-card game (the game in which the number of medals is 2). The number of sheets (two sheets) is set in the C register (S771).

  After the processing of S771 or when the determination of S770 is YES, the main CPU 101 performs update processing of the payout number (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current prize number counter value, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether or not the value of the payout number is less than the maximum payout number "10" (S773).

  When the main CPU 101 determines in S773 that the value of the payout number is less than the maximum payout number "10" (YES in S773), the main CPU 101 performs the process of S775 described below. On the other hand, when the main CPU 101 determines in S773 that the value of the payout number is not less than the maximum payout number "10" (NO in S773), the main CPU 101 sets the payout number to "10". Yes (S774).

  After the processing of S774 or when the determination in S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

  After the processing of S775 or if NO in S769, the main CPU 101 determines whether or not there is another winning (S776). In S776, when the main CPU 101 determines that there is another winning (in the case of YES determination in S776), the main CPU 101 returns the process to the process of S769, and repeats the processes of S769 and thereafter.

  On the other hand, in S776, when the main CPU 101 determines that there is no other winning (NO in S776), the main CPU 101 decrements (-1 updates) the value of the winning retrieval counter (S777). In addition, as in the present embodiment, when the number of the activated lines is one, a plurality of small wins do not overlap, and therefore the determination process of S776 is always a NO determination.

  Next, the main CPU 101 determines whether or not the value of the prize search counter is "0" (S778).

  In S778, when the main CPU 101 determines that the value of the prize search counter is not “0” (NO in S778), the main CPU 101 returns the process to S764 and repeats the processes from S764. On the other hand, in S778, when the main CPU 101 determines that the value of the prize search counter is “0” (YES in S778), the main CPU 101 ends the prize search process and executes the process in the main flow (FIG. 82)).

  In the present embodiment, the winning search processing is performed as described above. Then, the above-described prize search processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 146. Among them, the setting process of the payout number and the determination target data in S764 is performed by the main CPU 101 executing the source code “LDIN AC, (HL)”.

  When the source code "LDIN ss, (HL)" is executed on the source program, for example, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( (Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (addition of 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 146 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The payout number and determination target data) are loaded into the AC register, and the address set in the HL register is updated by +2 (addition of 2). In the process of S764, the "LDIN" instruction stores the payout amount data in the A register, the determination target data in the C register, and the address set in the HL register is updated by +2.

  As described above, in the winning retrieval process of this embodiment, both the data loading process and the address updating process can be performed by one "LDIN" command. In this case, an instruction related to address setting can be omitted in the source program, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  In addition, the medal counter value acquisition process referred to in the determination process of S770 during the above-described prize retrieval process, the prize number counter value acquisition process referred to in the process of S772, and the prize number counter performed in the process of S775. As shown in FIG. 146, each save (update) process is executed by an “LDQ” instruction (main CPU 101-dedicated instruction code) that uses the Q register (extended register) to specify the address. Therefore, in the prize search processing of the present embodiment, it is possible to directly access the main ROM 102, the main RAM 103, and the memory map I / O by using the "LDQ" command, so that the address on the source program The instruction related to the setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

  In addition, the determination process of S769 during the above-described prize search process is executed by a "JSLAA" command (predetermined determination command) on the source program, as shown in FIG. 146. The “JSLAA” instruction is an instruction that executes an operation equivalent to a left shift (SLA) instruction.

  For example, when the source code "JSLAA cc, e" is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address designated by e. The "cc condition" defined by the "JSLAA" instruction specifies the state of the carry flag in the flag register F. For example, if "C" is specified in cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified in cc, the condition of cc is satisfied. Means that the carry flag is "0" (off state). Therefore, in the source code “JSLAA NC, MN_CKLN_06” in FIG. 146, if the carry flag is “0” (off state), the process jumps to the address specified by “MN_CKLN_06”.

  In addition, the determination processing of S770 and S773 during the above-described winning prize search processing is executed by the “JCP” command on the source program, as shown in FIG. 146. It should be noted that the "JCP" instruction is an instruction that executes an operation equivalent to the comparison instruction, and is an instruction code dedicated to the main CPU 101 as described above.

  Therefore, when the above-mentioned “JSLAA” command and “JCP” command are used on the source program of the prize search processing, the command related to the address setting can be omitted (it is necessary to separately provide the command related to the address setting). Therefore, the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[Illegal hit check processing]
Next, with reference to FIGS. 148 and 149, the illegal hit check processing performed in S215 in the main flow (see FIG. 82) will be described. Note that FIG. 148 is a flowchart showing the procedure of illegal hit check processing. FIG. 149 is a diagram showing an example of a source program for executing illegal hit check processing. It should be noted that the illegal hit is a BB winning number and a small winning combination number (internal winning combination) that is randomly selected in the internal drawing process (see FIG. 92) and stored in the winning number storing area in the symbol setting process (see FIG. 97). Based on this, the left reel 3L, the middle reel 3C, and the right reel 3R are terms indicating that they are stopped on the activated line with a symbol combination that cannot be established (symbol combination is not established).

  First, the main CPU 101 sets the address of the winning operation flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size (the number of bytes, “12” in this embodiment) of the winning operation flag storage area to the value of the check counter (S782).

  Next, the main CPU 101, based on the address of the winning action flag storage area that is currently set, the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storage area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 combines the data of the winning combination (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the data of the internal winning combination (winning request flag data) ( S784).

  In this synthesizing process, the main CPU 101 first obtains the exclusive OR of the data of the winning combination (winning operation flag data) and the data of the internal winning combination (winning request flag data) (source program shown in FIG. 149). Source code inside "XOR (HL)"). Next, the main CPU 101 obtains a logical product of the calculated exclusive OR result and the winning combination data (prize operation flag data) (source code “AND (HL)” in the source program shown in FIG. 149). ), And the calculation result of the logical product is used as the synthesis result. When the illegal hit error does not occur, the value of this combined result is "0".

  Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the combining process of S784 (S785).

  In S785, when the main CPU 101 determines that an illegal hit error has not occurred (NO in S785), the main CPU 101 updates the address of the winning operation flag storage area to be referenced by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is "0" (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (NO in S788), the main CPU 101 returns the process to S783 and repeats the processes from S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is “0” (YES in S788), the main CPU 101 ends the illegal hit check process and executes the process in the main flow (FIG. 82)).

  Here, again returning to the processing of S785, when the main CPU 101 determines in S785 that an illegal hit error has occurred (YES in S785), the main CPU 101 performs the error processing described in FIG. Is performed (S789). By this processing, a 2-digit 7-segment LED (for both display of payout number and error display) included in the information display 6 is used to display two characters “EE” indicating occurrence of illegal hit error as error information. Error display data is output. The occurrence state of the illegal hit error (error state) is released by pressing the reset switch 76 (see FIG. 7).

  Next, the main CPU 101 clears the value of the winning number counter and the data in the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 82).

  In this embodiment, the illegal hit check process is performed as described above. Then, the above-mentioned illegal hit check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 149.

  In the present embodiment, as shown in FIGS. 28 to 30, the structure of the winning operation flag storage area (display combination storing area) is the same as that of the hit request flag storage area (internal winning combination storing area). The winning request flag storage area and the winning operation flag storage area, which are arranged in the main RAM 103 during the process of combining the winning combination of the winning operation flag storage area and the internal winning combination, can have the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of combining the data of the winning combination and the data of the internal winning combination) is, as described above, the data of the winning combination and the internal data of the winning combination. It is obtained by simply performing a logical product (executed by the "AND" instruction) with the data of the winning combination. As a result, in the present embodiment, the illegal hit check processing can be made efficient and simplified, the free space of the main control program can be secured (increased), and the increased free space is used to improve the game playability. It becomes possible to raise.

[Prize check / medal payout processing]
Next, with reference to FIG. 150 and FIG. 151, the winning check / medal payout processing performed in S216 in the main flow (see FIG. 82) will be described. Note that FIG. 150 is a flow chart showing the procedure of the winning check / medal payout processing. Further, FIG. 151 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the prize check / medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this processing, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub control circuit 200. It should be noted that the winning operation command includes parameters for specifying a winning operation flag (display combination) and the like.

  Next, the main CPU 101 executes the communication data storage processing described in FIG. 72 (S802). By this processing, the winning operation command data is saved in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is "0" (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (YES in S803), the main CPU 101 ends the winning check / medal payout process, and executes the process in the main flow ( The process proceeds to S217 in (see FIG. 82).

  On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not “0” (NO in S803), the main CPU 101 determines that the number of credits (the number of stored coins) of the medal is the upper limit number (the present number). In the embodiment, it is determined whether the number is 50 or more (S804).

  In S804, when the main CPU 101 determines that the number of credits of medals is not equal to or more than the upper limit (NO in S804), the main CPU 101 adds “1” to the value of the credit counter (+1 update) ( S805). The added credit counter value is displayed by a two-digit 7-segment LED (not shown) for displaying the number of stored sheets, which is included in the information display 6. Next, the main CPU 101 executes a medal payout number check process (S806). The details of the medal payout number check processing will be described later with reference to FIG. 152 described later.

  Next, the main CPU 101 determines whether or not the payout of medals has been completed (S807). When the main CPU 101 determines in S807 that the payout of medals has been completed (YES in S807), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 82). Then, the process proceeds to S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not been completed (NO in S807), the main CPU 101 performs payout interval standby processing (S808). In this processing, the main CPU 101 waits until a preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt processing (1.1172 msec cycle) described later in FIG. 158) elapses. Wait. After the processing of S808, the main CPU 101 returns the processing to the processing of S803 and repeats the processing of S803 and thereafter.

  Here, again returning to the processing of S804, in S804, when the main CPU 101 determines that the number of credits of medals is the upper limit number (50) or more (when YES is determined in S804), the main CPU 101 determines A medal payout process is performed (S809). By this process, one medal is paid out. After the processing of S809, the main CPU 101 terminates the winning check / medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 82).

  In the present embodiment, the winning check / medal payout process is performed as described above. The processing of S804 to S808 during the winning check / medal payout processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 151.

  In the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval wait) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 is realized by executing the source codes “LD BC, cTM_PAYC” and “RST SB_W1BC_00” in this order. As described above, in the prize check / medal payout process, if a wait of 60.33 ms (waiting for payout interval) is performed when the payout operation is continued after the credit counter is updated (+1), unnecessary waiting time is reduced. It is possible to reduce the mental burden on the player.

[Medal payout number check process]
Next, with reference to FIG. 152 and FIG. 153, the medal payout number check process performed in S806 of the prize check / medal payout process (see FIG. 150) will be described. Note that FIG. 152 is a flowchart showing the procedure of the medal payout number check processing. Further, FIG. 153A is a diagram showing an example of a source program for executing the processing of S811 to S814 described later during the medal payout number check processing, and FIG. 153B shows S816 and later described during the medal payout number check processing. It is a figure which shows an example of the source program for performing the process of S817.

  First, the main CPU 101 adds “1” to the value of the medal OUT counter (+1 update) (S811). The medal OUT counter is a counter for counting the number of payouts of medals. Next, the main CPU 101 adds "1" to the value of the payout number counter (+1 update) (S812). The payout number counter is a counter for counting the payout number of medals.

  Next, the main CPU 101 executes a payout number 7SEG display process (S813). In this process, the main CPU 101 performs a control process for displaying the value of the payout amount counter by a 2-digit 7-segment LED (not shown) for displaying the payout amount included in the information display 6.

  Next, the main CPU 101 updates the combination end number counter (S814). The winning combination ending number counter is a counter for counting the remaining number of paid-out medals corresponding to the winning combination. In this process, the main CPU 101 compares the value of the combination end number counter with its lower limit value "0", and when the value of the combination end number counter is larger than the lower limit value "0", the combination end number. The value of the counter is decremented by 1 (updated by -1), and when the value of the combination end number counter is less than or equal to the lower limit value "0", the value of the combination end number counter is held at "0".

  Next, the main CPU 101 subtracts 1 from the value of the winning number counter (-1 update) (S815).

  Next, the main CPU 101 executes credit information command generation processing (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub control circuit 200. The credit information command includes a parameter that specifies the number of credits of a medal.

  Next, the main CPU 101 executes the communication data storage process described in FIG. 72 (S817). By this processing, the credit information command data is saved in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Then, after the processing of S817, the main CPU 101 ends the medal payout number check processing, and shifts the processing to the processing of S807 in the prize check / medal payout processing (see FIG. 150).

  In the present embodiment, the medal payout number check process is performed as described above. Note that the processing of S811 to S814 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 153A. Among them, the update processing of the combination end number counter of S814 is executed by the "DCPLD" command (predetermined update command) in FIG. 153A. The "DCPLD" instruction is an instruction code dedicated to the main CPU 101.

  When the source code "DCPLD (HL), n" is executed on the source program, the memory content (stored data) at the address specified by the HL register is compared with the integer n, and the memory content is If it is larger than the integer n, 1 is subtracted from the content of the memory, and if the content of the memory is not larger than the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code “DCPLD (HL), 0” in FIG. 153A is executed, the contents of the memory at the address specified by the HL register (the value of the combination end number counter) and the integer 0 (lower limit value) Are compared with each other, and when the content of the memory (the value of the combination end number counter) is larger than the integer 0, the content of the memory is subtracted by 1. When the content of the memory is less than or equal to the integer 0, the content of the memory is compared. "0" is set in (the value of the combination end number counter). That is, when the value of the combination end number counter at the present time is larger than “0”, the combination end number counter is updated, and when the value of the combination end number counter at the present time is “0” or less. A process of holding the value of the combination end number counter at "0" is performed.

  As described above, in the process of S814 during the medal payout number check process, one "DCPLD" command (a command in which the lower limit judgment command of the number management counter and the judgment branch command are integrated) is used to finish the winning combination number. Both the counter updating (subtracting) process and the process of holding the value of the continuous end number counter at “0” can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. For example, the judgment branch instruction code for judging whether or not the value of the continuous end number counter is "0" can be omitted. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), which increases. It becomes possible to improve the game playability by utilizing the free space.

  Further, the processing of S816 and S817 during the above-mentioned medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 153B.

  Among them, in the processing of S816, as shown in FIG. 153B, the value of the payout number counter is set to the communication parameter 1 of the credit information command via the L register, and the communication parameter 5 is credited via the C register. The counter value is set. However, the other communication parameters 2 to 4 constituting the credit information command are set to the values (undefined values) currently stored in the H register, the E register, and the D register, respectively. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[BB check process]
Next, with reference to FIG. 154, the BB check processing performed in S217 in the main flow (see FIG. 82) will be described. Note that FIG. 154 is a flowchart showing the procedure of the BB check process.

  First, the main CPU 101 determines whether or not the current gaming state is the bonus state (S821). In S821, when the main CPU 101 determines that the current game state is not the bonus state (NO in S821), the main CPU 101 performs the process of S832 described below.

  On the other hand, when the main CPU 101 determines in S821 that the current game state is the bonus state (YES in S821), the main CPU 101 counts the number of medals that can be paid out during the bonus state. From the value of the BB middle payout number counter, the payout number of medals paid out in the prize check / medal payout process is subtracted (S822).

  Next, the main CPU 101 determines whether or not the value of the BB medium payout number counter is less than “0” (S823). In S823, when the main CPU 101 determines that the value of the BB medium payout number counter is not less than “0” (NO in S823), the main CPU 101 ends the BB check process and executes the process in the main flow (FIG. 82)).

  On the other hand, when the main CPU 101 determines in S823 that the value of the BB medium payout number counter is less than “0” (YES in S823), the main CPU 101 performs the bonus end process (S824). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the ON state.

  Next, the main CPU 101 refers to the bonus lottery CT random determination table (see FIG. 60) to perform the bonus lottery CT random determination (S825). Next, the main CP 91 determines whether or not the CT lottery at the end of the bonus is won (S826).

  When the main CPU 101 determines in S826 that the CT lottery has not been won (NO in S826), the main CPU 101 performs the process of S828 described below. On the other hand, in S826, when the main CPU 101 determines that the CT lottery is won (YES in S826), the main CPU 101 adds “1” to the CT set number (S827). When the CT lottery is won when the number of ART sets is “0”, in the process of S827, “1” is added to the number of CT sets and “1” is also added to the number of ART sets. ..

  After the process of S827 or when the determination of S826 is NO, the main CPU 101 determines whether the number of ART sets or the number of CT sets is “1” or more (S828).

  In S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is “1” or more (YES in S828), the main CPU 101 sets the ART ready state to the game state of the next game. Yes (S829). Then, after the processing of S829, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

  On the other hand, in S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is not "1" or more (NO in S828), the main CPU 101 sets the normal game state to the game state of the next game. Yes (S830). Next, the main CPU 101 refers to the normal medium-high probability random determination table (see FIG. 40B) to randomly determine the random determination state of CZ, and sets the random determination result (S831). Then, after the processing of S831, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

  Here, again, returning to the processing of S821, when the determination of S821 is NO, the main CPU 101 determines whether or not the symbol combination (the symbol combination of the combination “C_BB1” or “C_BB2”) related to the BB combination is displayed. (S832). In S832, when the main CPU 101 determines that the symbol combination relating to the BB combination has not been displayed (NO in S832), the main CPU 101 ends the BB check process and executes the process in the main flow (see FIG. 82). The process moves to S218 in the process.

  On the other hand, in S832, when the main CPU 101 determines that the symbol combination related to the BB combination is displayed (YES in S832), the main CPU 101 refers to the bonus type random determination table (see FIG. 58), and determines the bonus. The type is randomly selected and the result of the lottery is set (S833). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers a bonus end: “216” in the present embodiment) to the value of the BB medium payout number counter (S834).

  Next, the main CPU 101 executes a bonus start time process (S835). In this process, the main CPU 101 performs various processes necessary for starting the operation of the bonus, such as setting a bonus state in the game state of the next game. Then, after the processing of S835, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

[RT check processing]
Next, the RT check processing performed in S218 in the main flow (see FIG. 82) will be described with reference to FIGS. 155 and 156. 155 and 156 are flowcharts showing the procedure of the RT check process.

  First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). When the main CPU 101 determines in S841 that the RT state is the RT5 state (YES in S841), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 82). Move to processing.

  On the other hand, when the main CPU 101 determines in S841 that the RT state is not the RT5 state (NO in S841), the main CPU 101 determines whether the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (NO in S842), the main CPU 101 performs the process of S845 described below.

  On the other hand, in S842, when the main CPU 101 determines that the RT state is the RT0 state (YES in S842), the main CPU 101 displays the symbol combination of the abbreviation “bell spilled eyes” (see FIG. 28). It is determined whether or not (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviated name “bell sloping eyes” is not displayed (NO in S843), the main CPU 101 ends the RT check process and executes the process in the main flow (FIG. 82)).

  On the other hand, in S843, when the main CPU 101 determines that the symbol combination of the abbreviated name “bell sloping eyes” is displayed (YES in S843), the main CPU 101 sets the RT2 state flag to the ON state (S844). .. By this processing, the RT state shifts from the RT0 state to the RT2 state. Then, after the processing of S844, the main CPU 101 terminates the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  Here, returning to the processing of S842 again, when the determination of S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (NO in S845), the main CPU 101 performs the process of S850 described below.

  On the other hand, in S845, when the main CPU 101 determines that the RT state is the RT1 state (YES in S845), the main CPU 101 determines whether or not the symbol combination of the abbreviation “bell spilled eyes” is displayed. Yes (S846).

  In S846, when the main CPU 101 determines that the symbol combination of the abbreviated name “bell sloping eyes” is displayed (YES in S846), the main CPU 101 sets the RT1 state flag to the off state and the RT2 state flag. Is turned on (S847). By this processing, the RT state shifts from the RT1 state to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  On the other hand, in S846, when the main CPU 101 determines that the symbol combination of the abbreviated name "bell sloping eyes" is not displayed (NO in S846), the main CPU 101 determines whether 20 games in the RT1 state have passed. It is determined (S848).

  In S848, when the main CPU 101 determines that the game in the RT1 state has not passed 20 games (NO in S848), the main CPU 101 ends the RT check process and executes the process in the main flow (see FIG. 82). ) To the processing of S219. On the other hand, when the main CPU 101 determines in S848 that 20 games in the RT1 state have passed (YES in S848), the main CPU 101 sets the RT1 state flag to the off state (S849). By this processing, the RT state shifts from the RT1 state to the RT0 state. After the processing of S849, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  Here, returning again to the processing of S845, when the determination of S845 is NO, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (NO in S850), the main CPU 101 performs the process of S853 described below.

  On the other hand, in S850, when the main CPU 101 determines that the RT state is the RT2 state (YES in S850), the main CPU 101 displays the symbol combination of the abbreviation “RT3 transition rep” (see FIG. 28). It is determined whether or not (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation “RT3 shift rep” has not been displayed (NO in S851), the main CPU 101 ends the RT check process and executes the process in the main flow (FIG. 82)).

  On the other hand, in S851, when the main CPU 101 determines that the symbol combination of the abbreviation “RT3 shift rep” is displayed (YES in S851), the main CPU 101 sets the RT2 state flag to the off state and RT3. The state flag is set to the on state (S852). By this processing, the RT state shifts from the RT2 state to the RT3 state. Then, after the processing of S852, the main CPU 101 ends the RT check processing, and moves the processing to the processing of S219 in the main flow (see FIG. 82).

  Here, returning to the processing of S850 again, when the determination of S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when S853 is NO determination), the main CPU 101 performs the process of S862 described below.

  On the other hand, in S853, when the main CPU 101 determines that the RT state is the RT3 state (YES in S853), the main CPU 101 displays the symbol combination of the abbreviations “bell spilled eyes” or “RT2 transition lip”. It is determined whether or not it has been performed (S854).

  In S854, when the main CPU 101 determines that the symbol combination of the abbreviations “bell spilled eyes” or “RT2 shift lip” is displayed (YES in S854), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the ON state (S855). By this processing, the RT state shifts from the RT3 state to the RT2 state. Then, after the processing of S855, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  On the other hand, in S854, when the main CPU 101 determines that the symbol combination of the abbreviations “bell spilled eyes” or “RT2 shift lip” is not displayed (NO in S854), the main CPU 101 determines the abbreviation “RT4 shift”. It is determined whether or not the symbol combination of "rip" (see FIG. 28) is displayed (S856).

  In S856, when the main CPU 101 determines that the symbol combination of the abbreviation “RT4 transition rep” is not displayed (NO in S856), the main CPU 101 ends the RT check process and executes the process in the main flow ( The processing proceeds to S219 in (see FIG. 82). On the other hand, in S856, when the main CPU 101 determines that the symbol combination of the abbreviation “RT4 shift lip” is displayed (YES in S856), the main CPU 101 sets the RT3 state flag to the OFF state and RT4. The state flag is set to the on state (S857). By this processing, the RT state shifts from the RT3 state to the RT4 state.

  After the processing of S857, the main CPU 101 determines whether or not the game state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the game state is not the ART preparation state (NO in S858), the main CPU 101 ends the RT check process and the process proceeds to S219 in the main flow (see FIG. 82). Move to processing.

  On the other hand, in S858, when the main CPU 101 determines that the game state is the ART preparation state (YES in S858), the main CPU 101 determines whether or not the CT set number is “1” or more. (S859).

  In S859, when the main CPU 101 determines that the number of CT sets is “1” or more (YES in S859), the main CPU 101 sets CT in the game state of the next game and sets it in the CT game number counter. "8" is set (S860). Then, after the processing of S860, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  On the other hand, in S859, when the main CPU 101 determines that the CT set number is not equal to or more than “1” (NO in S859), the main CPU 101 sets the normal game ART state in the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the processing of S861, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

  Here, returning to the process of S853 again, when the determination of S853 is NO, the main CPU 101 determines whether or not the symbol combination of the abbreviations "bell spilled eyes" or "RT2 shift lip" is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviations “bell-eye drop” or “RT2 shift lip” is not displayed (NO in S862), the main CPU 101 ends the RT check process. , And moves the processing to the processing of S219 in the main flow (see FIG. 82).

  On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviations “bell spilled eyes” or “RT2 shift lip” is displayed (YES in S862), the main CPU 101 turns off the RT4 state flag. And the RT2 state flag is set to the on state (S863). By this processing, the RT state shifts from the RT4 state to the RT2 state. Then, after the processing of S863, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

[Processing at the end of CZ / ART]
Next, with reference to FIG. 157, the CZ / ART end processing performed in S219 in the main flow (see FIG. 82) will be described. Note that FIG. 157 is a flow chart showing the procedure of the CZ / ART end processing.

  First, the main CPU 101 determines whether the current gaming state is one of CZ failure and the end of ART (S871). When the main CPU 101 determines in S871 that the current game state is neither CZ failure nor ART end (when S871 is NO determination), the main CPU 101 ends the CZ / ART end process, The process moves to the process of S201 in the main flow (see FIG. 82).

  On the other hand, in S871, when the main CPU 101 determines that the current game state is either CZ failure or ART end (YES in S871), the main CPU 101 determines the CZ lottery table (see FIG. 41B). ), The CZ pullback lottery is performed (S872). Next, the main CPU 101 determines whether or not the CZ pull-back lottery has been won (S873).

  When the main CPU 101 determines in S873 that the CZ pull-back lottery has been won (in the case of YES determination in S873), the main CPU 101 sets the winning type of CZ in the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 terminates the CZ / ART termination processing, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

  On the other hand, in S873, when the main CPU 101 determines that the CZ pull-back lottery has not been won (S873 is NO determination), the main CPU 101 sets the normal game state to the game state of the next game (S876). Next, the main CPU 101 refers to the normal medium / high probability random determination table (see FIG. 40B) to randomly determine the random determination state of CZ, and sets the determination result (S877). Then, after the processing of S877, the main CPU 101 terminates the CZ / ART termination processing, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

[Interrupt processing under the control of the main CPU (1.1172 msec)]
Next, with reference to FIG. 158, an interrupt process performed by the main CPU 101 in a 1.1172 msec cycle will be described. Note that FIG. 158 is a flowchart showing the procedure of the interrupt processing. The interrupt process that is repeatedly executed in the 1.1172 msec cycle occurs based on the output timing of the timeout signal of the timer circuit 113 set in the initialization process of the timer circuit 113 (PTC) (see S2 in FIG. 64). This is a process executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs a register save process (S901). Next, the main CPU 101 executes an input port check process (S902). In this process, signals input from various switches such as a stop switch are checked.

  Next, the main CPU 101 executes reel control processing (S903). In this process, the main CPU 101 starts the rotation of the left reel 3L, the middle reel 3C, and the right reel 3R when the rotation start of all reels is requested, and thereafter, the respective reels rotate at a constant speed. Drives and controls three stepping motors. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits until the updated symbol counter coincides with the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and then the corresponding reel. The corresponding stepping motor is drive-controlled so that the rotation is decelerated and stopped.

  Next, the main CPU 101 executes communication data transmission processing (S904). In this process, mainly, various commands stored in the communication data storage area are transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting the command to the sub control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown) to clear the transmitted command data in the communication data storage area. When a plurality of command data are stored in the communication data storage area, the command data are transmitted to the sub-control circuit 200 in the order in which they are stored. When no command data is stored in the communication data storage area, that is, when the value of the communication data pointer is “0”, a no-operation command is generated and transmitted to the sub control circuit 200. Next, the main CPU 101 executes the inserted medal passage check process (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed through the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 executes WDT restart processing (S906).

  Next, the main CPU 101 performs 7-segment LED drive processing (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display device 6 to display, for example, the number of medals paid out, the number of credits, stop button press order data, and the like. The details of the 7-segment LED drive processing will be described later with reference to FIG. 159 described later.

  Next, the main CPU 101 executes a timer update process (S908). In this processing, the main CPU 101 counts (subtracts) the various set timers. The details of the timer update process will be described later with reference to FIG.

  Next, the main CPU 101 performs error detection processing (S909). Next, the main CPU 101 executes door open / close check processing (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitor switch 67.

  Next, the main CPU 101 executes a test-shooting test signal control process (S911). In this process, a control process for outputting various test signals to the tester via the second interface boat or the like is performed. Further, this processing is executed using the non-regular work area of the main RAM 103 (see FIG. 12C). In addition, in this embodiment, this process is performed also at the time other than the test firing test (after the pachi-slot 1 is installed in the game shop), but at this time, the main control board 71 passes through the second interface boat or the like. Since various test signals are generated, they are not output because they are not connected to the tester. Details of the trial shooting test signal control processing will be described later with reference to FIG. 166 described later.

  Next, the main CPU 101 executes register restoration processing (S912). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[7-segment LED drive processing]
Next, the 7-segment LED drive process performed in S907 during the interrupt process (see FIG. 158) will be described with reference to FIGS. 159 and 160. Note that FIG. 159 is a flowchart showing the procedure of the 7-segment LED drive processing. Further, FIG. 160A is a diagram showing an example of a source program for executing the processing of S923 to S925 described later during the 7-segment LED driving processing, and FIG. 160B is S931 to be described later during the 7-segment LED driving processing. It is a figure which shows an example of the source program for performing the process of S936.

  First, the main CPU 101 adds "1" to the value of the interrupt counter (+1 update) (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (NO in S922), the main CPU 101 ends the 7-segment LED driving process and interrupts the process (see FIG. 158). ) To S908. That is, in the present embodiment, the 7-segment LED driving process is performed every two interrupt cycles. In the present embodiment, an example in which the 7-segment LED drive processing is executed when the value of the interrupt counter is an even number has been described, but the present invention is not limited to this, and 7-segment LED drive processing is performed when the value of the interrupt counter is an odd number. The LED drive processing may be executed, or the execution timing of the 7-segment LED drive processing may be determined using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in S922 that the value of the interrupt counter is an odd number (YES in S922), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets the address of the credit display data storage area for storing the credit display data output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs 7-segment display data generation processing (S928). In this processing, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG.

  Next, the main CPU 101 sets the address of the 7-segment common counter storage area for storing the value of the 7-segment common counter described later (S929). Next, the main CPU 101 adds "1" to the value of the 7-segment common counter (+1 update) (S930). In this process, when the updated 7-segment common counter value becomes "8", the main CPU 101 sets the 7-segment common counter value to "0". In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every eight cycles.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and outputs the address of the target cathode data storage area (the push order display data storage area or the target storage area in the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This processing is performed in order to turn off the 7-segment LED to eliminate the influence of the afterimage.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED driving processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 158).

  In the present embodiment, the 7-segment LED drive processing is performed as described above. The processing of S923 to S925 during the above-described 7-segment LED drive processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 160A. Further, the processing of S931 to S936 during the above-described 7-segment LED driving processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 160B.

  Among them, the output processing of each 7-segment output data in S936 is executed by one source code “LD (cPA_SEGCOM), BC” as shown in FIG. 160B. Therefore, in the 7-segment LED drive processing according to the present embodiment, 7-segment common output (selection) data and 7-segment cathode output data are simultaneously output when performing dynamic lighting control of the 2-digit 7-segment LED. In other words, in the 7-segment common output (7-segment common output (7-segment LED dynamic lighting control of the 7-segment LED when displaying the credit information by the 2-digit 7-segment LED) (Selection) data and 7-segment cathode output data are simultaneously output.

  In this case, the number of instruction codes required for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), and the increased free space can be utilized. Therefore, it becomes possible to improve the game playability. Further, in the present embodiment, an example in which a 7-segment driving circuit (not shown) that performs a 7-segment LED driving process is configured by a cathode common circuit and is controlled by the cathode has been described, but the present invention is not limited to this. The segment driving circuit may be configured with an anode common circuit, and the anode may control the 7 segment LED.

  Further, both the navigation data acquisition processing of S923 and the address setting processing of the push display data storage area of S924 during the 7-segment LED driving processing described above are performed by using the Q register (extended register) as shown in FIG. 160A. It is executed by an "LDQ" instruction (main CPU 101 dedicated instruction code) for addressing. Therefore, in the 7-segment LED drive processing of the present embodiment, by using the “LDQ” instruction, it is possible to directly access the main ROM 102, the main RAM 103 and the memory map I / O. The instruction related to the address setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to utilize the increased free space to improve the game playability.

[7-segment display data generation process]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 159) will be described with reference to FIGS. Note that FIG. 161 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 162 is a diagram showing an example of a source program for executing the 7-segment display data generation process. FIG. 163 is a diagram showing an example of the configuration of the 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

  The "display data" described below, which is generated in the 7-segment display data generation process performed in S925 of the 7-segment LED drive process (see FIG. 159), corresponds to the push-order display data, and the 7-segment LED drive process (see FIG. “Display data”, which will be described later, generated in the 7-segment display data generation process performed in S928 of (see 159) corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, obtains the quotient value of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and performs the division. The residual value of the result is acquired as the display data of the lower digit (S941). Next, the main CPU 101 determines whether to display upper digits based on the acquired upper digit display data (S942).

  When the main CPU 101 determines in S942 that the high-order digit display is to be performed (YES in S942), the main CPU 101 performs the process of S944 described below. On the other hand, when the main CPU 101 determines in S942 that the upper digit is not displayed (NO in S942), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when the determination of S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the higher digit (S944). Next, the main CPU 101 saves the acquired upper digit display data in the upper digit display data storage area (not shown) (S945).

  Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the lower digit (S946). Next, the main CPU 101 saves the acquired lower-order digit display data in the lower-order digit display data storage area (not shown) (S947).

  Then, after the processing of S947, the main CPU 101 ends the 7-segment display data generation processing. At this time, if the executed 7-segment display data generation process is the process of S925 in the 7-segment LED drive process (see FIG. 158), the main CPU 101 shifts the process to the process of S926 in the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 158), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. ..

  In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 162.

[Timer update processing]
Next, with reference to FIG. 164 and FIG. 165, the timer update process performed in S908 during the interrupt process (see FIG. 158) will be described. Note that FIG. 164 is a flowchart showing the procedure of the timer updating process. Further, FIG. 165 is a diagram showing an example of a source program for executing the processing of S951 to S954 described later during the timer updating processing.

  First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the 2-byte timer number in the B register (S951).

  Next, the main CPU 101 compares the 2-byte timer number with the lower limit value "0", and if the 2-byte timer number is larger than the lower limit value "0", subtracts 1 from the 2-byte timer number (-1 update). If the 2-byte timer number is less than or equal to the lower limit value "0", the 2-byte timer number is held at "0" (S952). Further, in the processing of S952, the main CPU 101 subtracts 2 (-2 updates) from the update start address of the 2-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 from the 2-byte timer number set in the B register (updates -1) (S953). Next, the main CPU 101 determines whether or not the 2-byte timer number set in the B register is "0" (S954).

  In S954, when the main CPU 101 determines that the 2-byte timer number set in the B register is not “0” (NO in S954), the main CPU 101 returns the process to the process of S952, and after S952. Repeat the process.

  On the other hand, when the main CPU 101 determines in S954 that the 2-byte timer number set in the B register is “0” (YES in S954), the main CPU 101 sets the 1-byte timer storage area in the HL register. The update start address is set, and the 1-byte timer number is set in the B register (S955).

  Next, the main CPU 101 compares the 1-byte timer number with the lower limit value “0”, and if the 1-byte timer number is larger than the lower limit value “0”, subtracts 1 from the 1-byte timer number (-1 update). If the 1-byte timer number is less than or equal to the lower limit value "0", the 1-byte timer number is held at "0" (S956). Further, in the processing of S956, the main CPU 101 subtracts 1 (-1 update) from the update start address of the 1-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 from the 1-byte timer number set in the B register (-1 update) (S957). Next, the main CPU 101 determines whether or not the 1-byte timer number set in the B register is "0" (S958).

  When the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is not "0" (NO in S958), the main CPU 101 returns the process to S956, Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is "0" (YES in S958), the main CPU 101 performs electromagnetic counter control processing (S959). ). In this process, an output control process for outputting a signal indicating IN / OUT of the medal to the external centralized terminal board 47 is performed. Then, after the processing of S959, the main CPU 101 ends the timer updating processing, and shifts the processing to the processing of S909 in the interrupt processing (see FIG. 158).

  In this embodiment, the timer updating process is performed as described above. Note that the processing of S951 to S954 during the above-described timer update processing (2-byte timer update processing) is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 165.

  Among them, the processing of S952 (update processing of the 2-byte timer) is executed by the "DCPWLD" instruction (predetermined update instruction) in FIG. 165. The “DCPWLD” instruction is an instruction code dedicated to the main CPU 101.

  For example, when the source code "DCPWLD (HL), n" is executed on the source program, the contents (stored data) of the memory of 2 bytes from the address specified by the HL register are compared with the integer n, When the content of the memory for 2 bytes is larger than the integer n, 1 is subtracted from the content of the memory for 2 bytes, and when the content of the memory for 2 bytes is less than or equal to the integer n, it is specified by the HL register. The integer n is stored in the memory for 2 bytes from the address.

  Therefore, in the source code “DCPWLD (HL), 0” in FIG. 165, the contents of the memory for 2 bytes (2-byte timer number) and the integer “0” (lower limit value) are read from the address specified by the HL register. When the contents of the memory for 2 bytes are larger than the integer “0”, the contents of the memory for 2 bytes are subtracted by 1, and the contents of the memory for 2 bytes are less than or equal to the integer “0”. Is set to "0" in the memory contents of 2 bytes. That is, if the current 2-byte timer count is greater than “0”, the 2-byte timer update process is performed. If the current 2-byte timer count is “0” or less, the 2-byte timer count is “0”. Held in.

  As described above, in the timer updating process of the present embodiment, the “DCPWLD” instruction, which is the instruction code dedicated to the main CPU 101, executes both the updating (subtracting) process of the number of timers and the process of holding the number of timers at “0”. can do. In this case, it is not necessary to provide an instruction code for executing both processes separately. Further, the judgment branch instruction code for judging whether or not the number of timers is “0” can be omitted. Therefore, in the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), and the increased free space can be utilized. Therefore, it becomes possible to improve the game playability. In the present embodiment, the example in which the "DCPWLD" instruction is used only in the update processing of the 2-byte timer has been described, but the present invention is not limited to this, and the "DCPWLD" instruction is also used in the update processing of the 1-byte timer. May be used.

[Test firing test signal control processing (out of regulation)]
Next, with reference to FIG. 166, the test shot test signal control process performed in S911 during the interrupt process (see FIG. 158) will be described. It should be noted that FIG. 166 is a flowchart showing the procedure of the test-shooting test signal control processing.

  First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves the data in all the registers (S963).

  Next, the main CPU 101 executes a cylinder braking signal generation process (S964). In this process, the main CPU 101 performs a process of generating and outputting a rotation control signal (drive signal) for each reel, which is output to the tester via the second interface boat or the like. The details of the turning cylinder braking signal generation process will be described later with reference to FIG. 167 described later.

  Next, the main CPU 101 performs a prize signal control process (S965). In this process, the main CPU 101 performs a process of outputting a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. The details of the prize signal control processing will be described later with reference to FIG. 168 described later.

  Next, the main CPU 101 executes a condition device signal control process (S966). In this process, the main CPU 101 performs a process of outputting a control signal corresponding to the state of the condition device signal control flag. The details of the condition device signal control processing will be described later with reference to FIGS. 169 and 170 described later.

  Next, the main CPU 101 performs a process of restoring the data of all the registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the processing of S968, the main CPU 101 ends the trial shooting test signal control processing, and shifts the processing to the processing of S912 in the interrupt processing (see FIG. 158).

[Turning cylinder braking signal generation processing]
Next, with reference to FIG. 167, the turning cylinder braking signal generation process performed in S964 in the test-firing test signal control process (see FIG. 166) will be described. It should be noted that FIG. 167 is a flow chart showing the procedure of the cylinder rotation braking signal generation process.

  First, the main CPU 101 sets a rotation control data storage area (not shown) in the non-regular work area (S971). Next, the main CPU 101 sets the number of reels to "3", and clears the spinning cylinder control signal and its generation state (1 byte data) (S972).

  Next, the main CPU 101 determines whether or not the turning cylinder control data is "less than stopped" data (S973). It should be noted that the term "under stop" of the spinning drum control data means spinning drum control data other than the spinning drum control data for stopping the reel, that is, the spinning drum control data for driving the reel to rotate (acceleration). Preparation, accelerating, waiting at constant speed, either during constant speed or waiting for stop start position).

  In S973, when the main CPU 101 determines that the turning cylinder control data is “less than stopped” data (YES in S973), the main CPU 101 performs the process of S975 described below. On the other hand, when the main CPU 101 determines in step S973 that the turning cylinder control data is not "less than stopped" data (NO in step S973), the main CPU 101 determines that the turning cylinder control data is "quiet steady hold control end". It is determined whether or not it is the data of "(S974). It should be noted that the spinning cylinder control data of “end of static control hold control” here is spinning cylinder control data indicating a state in which all reels are stopped in all phases.

  In S974, when the main CPU 101 determines that the turning cylinder control data is the data of “end of static control hold control” (YES in S974), the main CPU 101 performs the process of S976 described below. On the other hand, in S974, when the main CPU 101 determines that the turning cylinder control data is not the data of “end of static control hold control” (when S974 is NO determination) or when S973 is YES determination, the main CPU 101 determines that Bit 3 of the generation state (1 byte data) of the cylinder control signal is turned on ("1") (S975).

  After the processing of S975 or when the determination of S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by 1 bit to the right (direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the spinning drum control data storage area to the address of the next reel to be controlled (S977).

  Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is "0" (S979).

  In S979, when the main CPU 101 determines that the number of reels is not “0” (NO in S979), the main CPU 101 returns the process to S973 and repeats the processes from S973.

  On the other hand, in S979, when the main CPU 101 determines that the number of reels is “0” (YES in S979), the main CPU 101 sends the data of the generation state to the test machine through the spinning cylinder braking signal output port. Output to the first interface board 301 for use (see FIG. 7) (S980). Then, after the processing of S980, the main CPU 101 terminates the turning cylinder braking signal generation processing, and shifts the processing to the processing of S965 in the test shot test signal control processing (see FIG. 166).

[Special signal control processing]
Next, with reference to FIG. 168, the prize signal control processing performed in S965 in the test-shooting test signal control processing (see FIG. 166) will be described. Note that FIG. 168 is a flowchart showing the procedure of the prize signal control processing.

  First, the main CPU 101 refers to the game state flag storage area (see FIG. 32) to acquire the game state flag (S991). Next, the main CPU 101 determines whether the gaming state is the RB gaming state (S992).

  In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (YES in S992), the main CPU 101 sends the ON signal from the RB middle signal port for the test signal to the first interface for test machine. The data is output to the board 301 (see FIG. 7) (S993). On the other hand, in S992, when the main CPU 101 determines that the gaming state is not the RB gaming state (NO in S992), the main CPU 101 sends an OFF signal from the RB mid signal port for the test signal to the first testing machine. The data is output to the interface board 301 (see FIG. 7) (S994).

  After the processing of S993 or S994, the main CPU 101 refers to the game state flag storage area (see FIG. 32) and determines whether the game state is the BB game state (S995).

  In S995, when the main CPU 101 determines that the game state is the BB game state (YES in S995), the main CPU 101 sends the ON signal from the BB medium signal port for the test signal to the first interface for test machine. The data is output to the board 301 (see FIG. 7) (S996). On the other hand, in S995, when the main CPU 101 determines that the gaming state is not the BB gaming state (NO in S995), the main CPU 101 sends the OFF signal from the BB medium signal port for the test signal to the first testing machine. The data is output to the interface board 301 (see FIG. 7) (S997).

  Then, after the processing of S996 or S997, the main CPU 101 ends the prize signal control processing, and shifts the processing to the processing of S966 in the test firing test signal control processing (see FIG. 166).

[Condition device signal control processing]
Next, with reference to FIG. 169 and FIG. 170, the condition device signal control processing performed in S966 in the test shot test signal control processing (see FIG. 166) will be described. 169 and 170 are flowcharts showing the procedure of the condition device signal control processing.

  First, the main CPU 101 determines whether or not the conditional device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the conditional device signal control flag is in the initial state (YES in S1001), the main CPU 101 ends the conditional device signal control process, and the process is the test firing test signal control process. (See FIG. 166) The process proceeds to S967.

  On the other hand, in S1001, when the main CPU 101 determines that the condition device signal control flag is not in the initial state (when S1001 is NO determination), the main CPU 101 sets the condition device signal control flag to the ON state of the re-gaming state identification signal. It is determined whether or not it is shown (S1002).

  In S1002, when the main CPU 101 determines that the condition device signal control flag indicates the on-state of the re-game state identification signal (YES in S1002), the main CPU 101 plays a role in the condition device signal control state. The ON state of the object condition device signal is set (S1003). Next, the main CPU 101 outputs information on the RT state from the condition devices 1 to 6 signal ports to the first tester interface board 301 (see FIG. 7) (S1004). Then, after the processing of S1004, the main CPU 101 ends the condition device signal control processing, and moves the processing to the processing of S967 in the test shot test signal control processing (see FIG. 166).

  On the other hand, in S1002, when the main CPU 101 determines that the condition device signal control flag does not indicate the on-state of the re-game state identification signal (when S1002 is NO determination), the main CPU 101 determines that the condition device signal control flag is It is determined whether or not the re-game state identification signal indicates the off state (S1005).

  In S1005, when the main CPU 101 determines that the condition device signal control flag indicates the off state of the re-gaming state identification signal (when S1005 is YES), the main CPU 101 determines that the condition device 1 to 8 signal ports. Outputs an OFF signal to the first interface board 301 for a tester (see FIG. 7) (S1006). After the processing of S1006, the main CPU 101 terminates the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

  On the other hand, in S1005, when the main CPU 101 determines that the condition device signal control flag does not indicate the off-state of the re-game state identification signal (when S1005 is NO), the main CPU 101 determines that the condition device signal control state is It is determined whether or not the accessory condition device signal is in the on state (S1007).

  In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (YES in S1007), the main CPU 101 selects the prize from the condition device 1 to 8 signal ports. The number information is output to the tester first interface board 301 (see FIG. 7), and at this time, the ON signal is output from the conditioner 8 signal port to the tester first interface board 301 (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) in the condition device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal output control state to the condition device signal output waiting state (S1010). After the processing of S1010, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

  On the other hand, in S1007, when the main CPU 101 determines that the condition device signal control state is not the ON state of the accessory condition device signal (NO in S1007), the main CPU 101 determines that the condition device signal control state is the condition device signal. It is determined whether or not the output is waiting (S1011).

  When the main CPU 101 determines in step S1011 that the condition device signal control state is the condition device signal output waiting state (YES in step S1011), the main CPU 101 determines that the condition device signal output waiting timer value is "0". It is determined whether or not it is "(S1012).

  In S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is not “0” (NO in S1012), the main CPU 101 terminates the condition device signal control process, and executes the test test test. The processing moves to S967 in the signal control processing (see FIG. 166). On the other hand, when the main CPU 101 determines in S1012 that the value of the condition device signal output waiting timer is "0" (YES in S1012), the main CPU 101 sets the condition device signal control state to the small winning condition device. The ON state of the signal or the OFF state of the condition device signal is set (S1013). After the processing of S1013, the main CPU 101 terminates the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

  Here, returning to the processing of S1011 again, in S1011, when the main CPU 101 determines that the condition device signal control state is not in the condition device signal output waiting state (when S1011 is NO determination), the main CPU 101 determines the condition. It is determined whether or not the device signal control state is the small winning condition device signal ON state (S1014).

  In S1014, when the main CPU 101 determines that the condition device signal control state is the small role condition device signal ON state (in the case of YES determination in S1014), the main CPU 101 determines from the condition device 1 to 8 signal ports to the small role. The winning number information is output to the first tester interface board 301 (see FIG. 7), and the ON signal is output from the conditioner 7 signal port to the first tester interface board 301 (see FIG. 7). (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set in the conditioner signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal control state to the condition device signal output waiting state (S1017). Then, after the processing of S1017, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1014 that the condition device signal control state is not the ON state of the small winning combination condition device signal (NO in S1014), the main CPU 101 turns OFF from the condition device 1 to 8 signal ports. The signal is output to the first tester interface board 301 (see FIG. 7) (S1018). Then, after the processing of S1018, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test shot test signal control processing (see FIG. 166).

<Explanation of operation of sub-control circuit>
Next, the contents of various processes executed by the sub CPU 201 of the sub control circuit 200 using a program will be described with reference to FIGS.

[Sub-side navigation control processing]
First, the sub-side navigation control processing will be described with reference to FIG. Note that FIG. 171 is a flowchart showing the procedure of the sub-side navigation control processing.

  First, the sub CPU 201 determines whether or not navigation data has been acquired (S1101). The sub CPU 201 acquires the navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1101, the sub CPU 201 determines whether or not the received start command data includes navigation data.

  When the sub CPU 201 determines in S1101 that the navigation data has been acquired (YES in S1101), the sub CPU 201 sets the sub navigation data corresponding to the navigation data (S1102). For example, when the sub CPU 201 acquires the navigation data “4”, as shown in FIG. 63, the navigation data for notifying the pressing order “left, middle, right” is set as the sub-side navigation data in this process. It As a result, the contents of the stop operation can be notified on both the main side and the sub side. Then, after the processing of S1102, the sub CPU 201 ends the sub-side navigation control processing.

  On the other hand, when the sub CPU 201 determines in S1101 that navigation data has not been acquired (NO in S1101), the sub CPU 201 determines whether navigation (notification of stop operation) is necessary. (S1103). In the present embodiment, the sub CPU 201 needs to perform navigation when, for example, a flag conversion lottery is performed on the main control board 71, or when a predetermined winning combination is determined as an internal winning combination on the main control board 71. To determine. The result of the flag conversion lottery and the type of the internal winning combination are included in the start command data. Therefore, in the processing of S1103, the sub CPU 201 determines whether or not navigation is necessary based on these various types of information included in the start command data.

  When the sub CPU 201 determines in S1103 that navigation is not required (NO in S1103), the sub CPU 201 ends the sub navigation control process.

  On the other hand, when the sub CPU 201 determines in S1103 that navigation is required (YES in S1103), the sub CPU 201 sets sub side navigation data according to various lottery results (S1104). For example, when the internal winning combination “F_probable chiriripu” is determined and the winning of the flag conversion lottery is successful, the sub CPU 201 is a navigation for displaying the symbol combination related to the abbreviation “3 consecutive chiriripu” in this processing. Set the data (for example, navigation data that allows you to aim for the Chile pattern by pressing the button normally). In addition, for example, when the internal winning combination “F_Sure Chile Lip” is determined and the flag conversion lottery is non-win, the sub CPU 201 displays the symbol combination related to the abbreviation “Replay” in this process. Set navigation data (for example, navigation data indicating a pressing order other than normal pressing). By these processes, even if the main side does not notify the content of the stop operation, the sub side can notify the content of the stop operation by itself. After the processing of S1104, the sub CPU 201 ends the sub navigation control processing.

[Player registration process]
Next, the player registration processing will be described with reference to FIG. 172. Note that FIG. 172 is a flowchart showing the procedure of the player registration processing.

  First, the sub CPU 201 determines whether or not a registration operation has been accepted (S1111). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18 and the predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 causes the sub CPU 201 to perform the registration operation. Is determined to have been accepted.

  When the sub CPU 201 determines in S1111 that the registration operation is accepted (YES in S1111), the sub CPU 201 sets the player registration state (S1112). In the situation where the player registration state is set, the sub CPU 201 of the sub display device 18 displays the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen. Then, after the processing of S1112, the sub CPU 201 ends the player registration processing.

  On the other hand, when the sub CPU 201 determines in S1111 that the registration operation has not been accepted (NO in S1111), the sub CPU 201 determines whether the registration deletion operation has been accepted (S1113). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that a registration deletion operation has been accepted.

  In S1113, when the sub CPU 201 determines that the registration deletion operation has not been accepted (NO in S1113), the sub CPU 201 ends the player registration process.

  On the other hand, when the sub CPU 201 determines in S1113 that the registration deletion operation is accepted (YES in S1113), the sub CPU 201 clears the player registration state (S1114). In the situation where the player registration state has been cleared, the sub CPU 201 causes the sub display device 18 to be unable to display the game information screens 223, 224, 225 (see FIGS. 5C to 5E). Control the display screen of. Then, after the processing of S1114, the sub CPU 201 ends the player registration processing.

[History management processing]
Next, the history management process will be described with reference to FIG. Note that FIG. 173 is a flowchart showing the procedure of the history management process.

  First, the sub CPU 201 acquires a game result from various command data received from the main control board 71 (S1121). For example, in this process, the sub CPU 201 can grasp the type of winning combination determined as the internal winning combination from the start command data. In addition, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning operation command data (that is, the presence or absence of the winning of the winning combination determined as the internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current game state and the transition state of the game state from the start command data and the like.

  Next, the sub CPU 201 performs game history update processing based on the acquired game result (S1122). By this processing, the sub CPU 201, for example, based on the game results obtained from various command data, for example, the number of bonuses, the number of ARTs, the number of games (number of games), the number of CZs, the number of CZ successes, the number of winnings of each combination, and the number of winnings. It is possible to manage various game histories such as probability. Then, after the processing of S1122, the sub CPU 201 ends the history management processing.

<Various effects>
In the pachi-slot 1 of the present embodiment, the following various effects can be obtained in terms of playability.

[Management of duration during CT]
In the pachi-slot 1 of the present embodiment, a CT is provided as an additional chance zone that can extend the duration of the normal ART, and the number of ART games is added based on the internal winning combination (sub-flag) in this CT. In CT, a set of 8 games is played, but if the number of ART games can be added during CT, the number of games is not subtracted without adding the number of games Subtract. Therefore, the player does not know how long the CT will last, and since the CT will not end as long as the addition is performed, the interest of the game during the CT can be enhanced.

  Further, in the present embodiment, when the sub-flag EX “three consecutive chilirip” is won during the CT (the sub-flag conversion lottery is won) and the addition is performed, one set of 8 times the CT game is also reset (stock). To be done. In this case, for example, even immediately before the CT game period is over, when the sub-flag EX "3 consecutive chilirip" is won, an addition is made and the CT is restarted from the beginning. Therefore, it is possible to continue the game without getting bored and to increase the interest of the game during CT.

  In addition, the sub-flag EX "3 consecutive chilirip" is added only when the internal winning combination "F_certain chililip" or "F_1 certain chililip" is determined as the internal winning combination and the flag conversion lottery is won. .. Therefore, it is possible to prevent an excessive profit from being given to the player, and it is possible to balance the profit between the player and the game store. In the above embodiment, an example (see FIG. 54) is explained in which the internal winning combination “F_probable chiririp” or “F_1 probable chiririp” is surely won in the flag conversion lottery during the CT. The present invention is not limited to this, and the winning probability of the flag conversion lottery can be appropriately set according to the profit balance between the player and the game shop.

[Number of additional games when winning "3 consecutive chilirip" in CT]
In the pachi-slot 1 of the above-described embodiment, if the sub-flag “three consecutive chili-rips” is won during CT and the number of additions based on the sub-flag “three consecutive chili-reps” exceeds a predetermined number, one extra lottery is performed. The number of additional ART games won is increased (see FIG. 55). Further, as described above, as long as the number of ART games is added, CT does not end, and if the sub-flag EX “3 consecutive chilirip” is won, CT is reset. Therefore, the player can expect that the amount of additional money per one time (one game) will increase as the CT continues, and the interest during the CT will improve. Furthermore, since the number of times that triggers an increase in the amount to be added per one time (one game) is more than the number of basic games (8 times) for one set of CT (9 times or more), It is possible to prevent an excessive profit from being given to the player, and it is possible to balance (maintain good) the profit between the player and the game store.

[Bonus notification performed on the main side]
In the pachi-slot 1 of the above-described embodiment, the numerical value “10” uniquely associated with the stop operation information for displaying the symbol combination related to the bonus combination (BB combination) on the instruction monitor (not shown) of the information display device 6. (Or "11") is displayed, the bonus is notified on the main side (see FIG. 63). However, normally, in pachislot, the priority of symbols drawn on the activated line (displayed as a stop) is set, and when the bonus combination and the other combination are overlapped and determined as the internal winning combination, the priority order is set. As a result, the symbol combination related to the bonus combination may or may not be drawn in.

  For example, in the pachi-slot 1 of the present embodiment, the bonus combination and any one of the internal winning combinations “off”, “F_special combination 1”, “F_special combination 2”, and “F_special combination 3” are determined overlappingly. If it is, the symbol combination related to the bonus combination can be drawn in, but the bonus combination and the internal winning combination “out”, “F_special combination 1”, “F_special combination 2” and “F_special combination 3” When a combination other than the above is determined in duplicate, the symbol combination related to the bonus combination cannot be drawn. Therefore, in the present embodiment, the bonus winning combination and any of the internal winning combinations “off”, “F_special winning combination 1”, “F_special winning combination 2”, and “F_special winning combination 3” are determined redundantly. Only in this case, the numerical value “10” (or “11”) is displayed on the instruction monitor. In this case, the navigation (bonus notification) on the main side can be performed at an appropriate timing when the bonus combination can be won.

  Further, in the pachi-slot 1 of the present embodiment, the bonus combination and any one of the internal winning combinations “off”, “F_special combination 1”, “F_special combination 2” and “F_special combination 3” are determined in an overlapping manner. Even if the bonus combination is won first, the instruction monitor does not display the numerical value "10" (or "11") until the predetermined number of games have elapsed (without navigating), and the predetermined number of times The value "10" (or "11") is displayed on the instruction monitor on condition that the game has passed.

  Note that, for example, when an effect (so-called continuous effect) that is performed over a plurality of games triggered by winning the bonus combination (so-called continuous effect) is performed, a numerical value “10” (or “on the instruction monitor is displayed during this continuous effect. 11)) is displayed, the meaning of the continuous production may be diminished and the interest may be spoiled. Therefore, in the pachi-slot 1 of the present embodiment, the display by the instruction monitor is not performed until the predetermined number of games have passed, and the display by the instruction monitor is performed after the predetermined number of games have passed. As a result, it is possible to perform bonus notification on the main side without impairing the effect of production.

[Notification performed by both the main side and sub side and notification performed by the sub side alone]
In the pachi-slot 1 of the present embodiment, a plurality of types of winning combinations having different symbol combinations displayed according to the mode of stop operation (pushing order) are provided (see FIG. 24), and the symbols displayed in these multiple types of winning combinations. A combination in which different privileges are awarded depending on the combination and a combination in which the same privilege is awarded even if the displayed symbol combination is different are included.

  For example, the number of medals to be paid out differs depending on whether the symbol combination relating to the abbreviation "bell" is displayed or the symbol combination relating to the abbreviation "bell" is displayed, and these symbols are displayed. It is a role that gives different benefits depending on the combination. Further, in the case where the symbol combination relating to the abbreviation "Replay" is displayed and the symbol combination relating to the abbreviation "RT2 shift rep" is displayed, whether or not the RT state shift is performed in addition to the re-game operation. Since different, the internal winning combination "F_3 choice bell_1st" and "F_maintenance lip_1st" are also different winning combinations depending on the symbol combination displayed.

  On the other hand, in the case where the symbol combination relating to the abbreviation "3 consecutive chili lip" is displayed and the symbol combination relating to the abbreviation "Replay" is displayed, both of them only perform the re-game operation. Therefore, the internal winning combination “F_certain Chilelip” or “F_1 sure Chilelip” is a role to which the same privilege is given even if the displayed symbol combinations are different. As described above, the internal winning combination “F_Sure Chiririp” or “F_1 Sure Chiririp” has different benefits to be given according to the result of the flag conversion lottery, but the benefit to be given to the symbol combination to be displayed. It does not play a role in affecting.

  In the pachi-slot 1 of the present embodiment, both main side and sub side notify the winning combination to which different benefits are given depending on the displayed symbol combination, but the same symbol combination is displayed even if the displayed symbol combination is different. With respect to the winning combination to which the privilege is granted, the sub-display device 11 is used for the notification, not the main-side instruction monitor. By providing such a notification function, the notification that affects the benefit is appropriately performed on the instruction monitor on the main side that manages the benefit, while the notification that does not affect the benefit is diverse on the sub-side display device 11. You can do it with navigation.

[Game history display function]
In the pachi-slot 1 of the present embodiment, a sub-display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and the sub-display device 18 displays various information useful for the player. For example, as shown in FIGS. 5A to 5E, a sub-display device includes a top screen 221, which represents an outline game history, a menu screen 222 which allows various operations for the pachi-slot 1, and game information screens 223, 224, and 225 which represent detailed game history. 18 can be displayed.

  Further, the pachi-slot 1 of the present embodiment has a function of allowing a player who plays a game to be registered through the sub-display device 18, and a function of providing a unique service to the registered player. For example, in the present embodiment, when the registration of the player is not accepted, the game information screens 223, 224, and 225 showing the detailed game history cannot be displayed on the sub display device 18, but the registration of the player is not performed. When accepted, the game information screens 223, 224, and 225 showing the detailed game history can be displayed on the sub display device 201. Since it is possible to improve the convenience of the player by making it possible to confirm the more detailed game history, in the present embodiment, the convenience can be improved when the registration of the player is accepted.

  In addition, in the pachi-slot 1 of the present embodiment, the sub display device 18 is provided separately from the display device 11 that produces an effect. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Further, the display unit 212 constituting the display device 11 is controlled by the sub control board 72 (sub CPU 201) via the accessory relay board (not shown). Therefore, in this embodiment, the sub display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub display device 18 can be switched even during a game (that is, during execution of the effect by the display device 11). Therefore, even during the game, the player can obtain various information by switching the display of the sub display device 18 without disturbing the effect performed by the display device 11.

  Further, in the display device 11 of the pachi-slot 1 of the present embodiment, a planar image display is used by switching a plurality of screen mechanisms (display units 212) that cause an image to appear by the irradiation of the irradiation light from the projector mechanism 211. When performing the effect, the effect using the image display having a sense of depth (stereoscopic effect), and the effect using the curved image display, the effect effect can be remarkably enhanced. However, such a display form of information is not suitable for displaying information such as a game history that is not related to production during production. Therefore, in the pachi-slot 1 of the present embodiment, it is possible to display information unrelated to the performance on the sub-display device 18 provided separately from the display device 11, so that the performance effect is not impaired and the game is played. Various information such as history can be displayed appropriately.

  By the way, in a general pachi-slot, the medal insertion slot 14 is provided on the right side of the pedestal portion 13 and the bet buttons 15a and 15b and the start lever 16 are provided on the left side of the pedestal portion 13 as viewed from the player side. Therefore, normally, when proceeding with the game, the player operates the operation part on the right side or the left side (side) of the pedestal part 13.

  On the other hand, in the pachi-slot 1 of the present embodiment, the sub display device 18 is provided on the side (left side) of the surface that stands substantially vertically from the pedestal portion 13, and the sub display device 18 is provided on the screen of the sub display device 18. A touch sensor 19 for switching the display screen of is provided. Therefore, in the present embodiment, the sub-display device 18 and the input device (touch sensor 19) for controlling the display thereof are provided at the place where the player's hand is located during the game, so that the operability of the player is improved. Can be improved. In particular, when the sub-display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 standing upright from the horizontal plane as in the present embodiment, the player places his or her hand on the pedestal portion 13. Meanwhile, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player due to the operation can be reduced, and as a result, the operating rate can be expected to be improved.

[Non-specified ROM area and non-specified RAM area]
In the pachi-slot 1 of the present embodiment, as shown in FIG. 12B, various programs and various programs used for various processes (various processes that do not affect the game property) not directly related to the game property of the game executed by the player. The data (table) is stored in the main ROM 102 in an unspecified ROM area arranged at an address different from the game ROM area.

  With such a configuration of the main ROM 102, according to the conventional rule, a program and data unnecessary for the actual game played by the player are arranged in the ROM area (non-regular ROM area) where the program and the like cannot be arranged. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the game ROM area in the main ROM 102 of the main control board 71, and enhance the expandability of the programs and tables in the main ROM 102.

[Effects obtained by processing at power-on (reset interrupt)]
In the power-on (reset interrupt) process of the pachi-slot 1 of the present embodiment, as shown in FIG. 64, the first 1.1172 ms cycle interrupt process is performed immediately after the power is restored (before the sum check) (S7 and S8). ), A non-operation command is transmitted from the main control circuit 90 to the sub control circuit 200. In this way, by permitting the interrupt process immediately after the power is restored, a non-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  Further, in the communication parameters 1 to 5 which form the no-operation command transmitted immediately after the power is restored, the data stored in the L register, the H register, the E register, the D register, and the C register are set when the power is restored. To be done. Therefore, in the present embodiment, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power is restored can be made different each time the power is restored, and fraudulent acts such as goto can be suppressed. it can.

  Further, the control for displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 performed in the process of S13 during the power-on (reset interrupt) process is performed by one "LDW". Command (a predetermined read command), the 7-segment common output (selection) data output operation to the 2-digit 7-segment LED and the 7-segment cathode output data output operation are simultaneously performed (see FIG. 65C). That is, in the pachi-slot 1 of the present embodiment, in the process at power-on (reset interrupt), 7-segment common output (selection) data and 7-segment cathode output data are generated when the 2-digit 7-segment LED is dynamically lighting-controlled. It is output at the same time.

  In this case, the number of instruction codes required for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), and the increased free space can be utilized. Therefore, the playability can be improved.

[Effects obtained by game return processing]
In the game return processing of the pachi-slot 1 of the present embodiment, as shown in FIG. 66, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the rotating body is rotating at the time of power failure, When the power is restored, the reel control management information is acquired and the processing required to start the reel re-rotation is also performed (see S25 to S32). Therefore, in the present embodiment, even when the electric power is restored during the rotation of the reel, it is possible to stably perform the re-rotation control of the reel, and the player does not feel uncomfortable.

  In addition, the pachi-slot 1 of the present embodiment includes the microprocessor 91 with a security function for gaming machines as described above. The microprocessor 91 is provided with various instruction codes (main CPU 101 dedicated instruction code) peculiar to the microprocessor 91 that can be defined on the source program, and the main CPU 101 dedicated instruction code is used in various processes. As a result, processing efficiency and program capacity can be reduced.

  For example, in the game return processing, as shown in FIG. 67, the "LDQ" instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The “LDQ” instruction is an instruction code for addressing using the Q register (extended register), and can directly access the main ROM 102, the main RAM 103 and the memory map I / O as described above. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program of the game return processing (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects of setting change confirmation processing]
In the setting change confirmation processing of the pachi-slot 1 of the present embodiment, as shown in FIG. 69A, the "BITQ" instruction and the "SETQ" instruction (predetermined instruction) which are instruction codes dedicated to the main CPU 101 are used on the source program. . Both the "BITQ" instruction and the "SETQ" instruction are instruction codes for addressing using the Q register (extended register). When these instruction codes are used, as described above, the main RAM 103 is a direct value. And memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and also to speed up the processing.

  69A and 69B show the generation / storing process of the setting change command (initialization command) performed at the time of setting change / setting confirmation start in S46 and the setting change / setting confirmation end in S57 during the setting change confirmation process. In addition, it is executed by the "CALLF" instruction which is the instruction code dedicated to the main CPU 101 on the source program. The jump destination address specified by the "CALLF" instruction of S46 is the same as the jump destination address specified by the "CALLF" instruction of S57. That is, in the present embodiment, when the setting is changed (when the gaming machine is started), when the setting confirmation is started (during normal operation), and when the setting confirmation is finished, a setting change command (initialization command) generation / storing process is transmitted The source programs for executing the above are the same as each other, and the source programs are shared (modularized) in both the processes of S46 and S57.

  In this case, it is not necessary to separately provide a source program for the setting change command generation / storing process in both S46 and S57, so that the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. it can. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects of setting change command generation and storage]
In the setting change command generation / storing process of the pachi-slot 1 of the present embodiment, the setting value is stored in the E register as the communication parameter 3 and the RT information is stored in the C register as the communication parameter 5, as shown in FIG. That is, among the communication parameters 1 to 5 that make up the setting change command (initialization command), the communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1, 2, and 4 that make up the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and communication parameters 1, 2 and For 4 and 4, the values currently stored in the L register, H register, and D register are set. Therefore, the values of the communication parameters 1, 2, and 4 at the time of transmitting the setting change command (initialization command) are indefinite values. In this case, the sum value (BCC) of the setting change command can be set to an undefined value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects of communication data storage processing]
In the communication data storage process of the pachi-slot 1 of the present embodiment, as shown in FIG. 72, the data stored in the A register is set as the communication command type data, and the L register, the H register, the E register, the D register and the C register are set. The data stored in the register is set as the communication parameters 1 to 5 of the communication command, and the data stored in the B register is set as the game state flag data of the communication command. That is, in the present embodiment, when one packet (8 bytes) of communication data (command data) is created, various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer).

  In this case, when the command data including the unused parameter is created, the value of the unused parameter becomes an undefined value every time it is created. That is, in the command data including the unused parameter, the sum value (BCC data) of the command data can be changed every time the command is created even if the command data of the same type has the same value of the used parameter. .. Therefore, in the present embodiment, by making the unused parameter an indefinite value, it is possible to make the analysis of communication data difficult and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the got countermeasure processing.

[Effects of updating communication data pointer]
In the communication data pointer update processing of the pachi-slot 1 of the present embodiment, as shown in FIG. 75A, the "ICPLD" instruction, which is the instruction code dedicated to the main CPU 101, is used on the source program.

  In the communication data pointer update process, the "ICPLD" instruction is an instruction code in which the transmission buffer upper limit determination instruction and the determination branch instruction are integrated, so the instruction code for executing each instruction processing separately There is no need to provide it. Therefore, by using the "ICPLD" instruction, it is possible to reduce the capacity of the source program of the communication data pointer update processing (the capacity used by the main ROM 102). As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects Obtained by Checksum Generation Process and Sum Check Process]
In the pachi-slot 1 of the present embodiment, in the checksum generation process (out of regulation) performed at the time of power interruption, as shown in FIG. 77, the checksum is calculated by sequentially adding the data in the main RAM 103. On the other hand, in the sum check process (out of regulation) performed when the power is turned on (when the power is restored), the value of the checksum generated when the power is interrupted is stored in the main RAM 103 when the power is restored, as shown in FIG. Subsequent subtraction is performed on the obtained data, and whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is "0". That is, in the present embodiment, the checksum generation process at the time of power failure is performed by the addition method, and the checksum determination process at the power recovery is performed by the subtraction method.

  When such checksum generation processing and determination processing are adopted, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omitted part of the collation command code, and it is possible to utilize the increased free space to enhance the game playability. Become.

[Effects of medal acceptance / start check processing]
In the medal acceptance / start check process of the pachi-slot 1 of the present embodiment, as shown in FIG. 83, the setting change confirmation process (the process of S233) is performed, but this process is executed regardless of the gaming state. Therefore, in the present embodiment, even if the game state is the bonus state (special prize operation state), the set value and the hall menu (various history data (errors, power interruption history, etc.)) can be confirmed, and the like. Can be suppressed.

[Effects obtained by the medal insertion process]
In the medal insertion process of the pachi-slot 1 of the present embodiment, as shown in FIG. 85, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the calculation process. .. Specifically, the LED lighting data for displaying the number of inserted medals is generated by sequentially executing a series of source codes “LD A, L” to “OR L” in the source program shown in FIG. 86.

  When the LED lighting data for displaying the number of inserted medals is generated by the arithmetic processing, the free space in the table area of the main ROM 102 can be increased and the increase in the capacity of the program can be minimized. That is, in the medal insertion process of the present embodiment, it is possible to streamline the process of displaying the medal insertion LED, secure (increase) the free space of the main ROM 102, and utilize the increased free space to improve the game playability. Can be increased.

[Effects obtained by the medal insertion check process]
In the medal insertion check process of the pachi-slot 1 of the present embodiment (see FIG. 87), the process of generating the normal change value of the medal sensor input state in S257 is performed not by the process of referring to the table but by the calculation process. Specifically, the source code "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 88 are sequentially executed to calculate the medal sensor input state normal change value.

  By changing the detection processing of the change state of the medal sensor input state from the table reference processing to the calculation processing, it is possible to increase the free space of the table storage area of the main ROM 102 and to minimize the increase in the capacity of the program. it can. Therefore, by adopting the above-mentioned processing method, it is possible to improve the efficiency of the detection processing of the change state of the medal shooting sensor state, and to improve the game playability by utilizing the free space increased in the main ROM 102. it can.

[Effects of internal lottery processing]
In the internal lottery process (see FIG. 92) of the pachi-slot 1 of the present embodiment, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A. By executing this "LDIN" instruction, in the process of S305, the determination data (the value of the "lottery value selection table or the lottery count table") is stored in the A register, and the winning request flag status ("prize winning number" is stored in the C register. + (Small winning combination number) value) is stored. In addition, the execution of the "LDIN" instruction updates the address set in the HL register by +2 (adds 2).

  That is, in the determination data acquisition process of S305 during the internal lottery process, both the data loading process and the address updating process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  In addition, in the addition processing of the set value data (any one of 0 to 5) of S309 of the internal lottery processing, the main CPU 101 uses the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM as shown in FIG. 93B. ) ”In this order.

  The “MUL” instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachi-slot 1 of the present embodiment, since the dedicated arithmetic circuit (arithmetic circuit 107) for executing the multiplication processing and the division processing on the source program is provided, the efficiency of the multiplication processing and the division processing should be improved. You can

  The "ADDQ" instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for addressing using the Q register (extension register). Then, if this "ADDQ" instruction is used, it is possible to access the main ROM 102, the main RAM 103 and the memory map I / O by a direct value. Therefore, by using the "ADDQ" instruction, the instruction related to the address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. You can As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects obtained by the symbol setting process]
In the symbol setting process of the pachi-slot 1 of the present embodiment (see FIG. 97), the compressed data storage process of S330 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG. 99. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 99 is executed, the process is performed on the address specified by "SB_BTEP_00". A jump is made and the compressed data storage processing is started.

  Further, the setting process of the address of the hit request flag storage area in S329 during the symbol setting process is performed by the main CPU 101 executing the source code "LDQ DE, .LOW.wWAVEBIT" in FIG. That is, the process of S329 is performed by the "LDQ" instruction dedicated to the main CPU 101 using the Q register (extended register). In this case, the instruction code relating to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  Further, in the present embodiment, the compression / decompression process of the winning data is performed by the processing procedure described in S324 to S330 during the above-described symbol setting process, and the main CPU 101 dedicated instruction code described above is included in the process. By using it, it is possible to improve the efficiency of the compression / decompression process of winning data, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Effects obtained by sub-flag conversion processing]
In the pachi-slot 1 of the present embodiment, the sub-flag conversion control data (control status) is associated with each sub-flag in the sub-flag conversion table shown in FIG. . At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

  For example, sub-flag conversion control data (control status) “00000011B” is commonly assigned to the sub-flags “three consecutive chili-rips A” and “three consecutive chili-rips B”. Then, in the flag conversion lottery process when the internal winning combination (sub flag) is converted into the sub flag EX, the lottery is performed based on the sub flag conversion control data (control status) associated with the sub flag.

  Thus, in the sub-flag conversion table managed on the main side, by providing common sub-flag conversion control data for internal winning combinations (sub-flags) of the same type, the versatility of the conversion table is increased and the model change is accompanied. Changes in the conversion program can also be handled by making minor changes, so an increase in development costs can be suppressed.

[Effects obtained by naviset processing]
In the naviset process of the pachi-slot 1 of the present embodiment, as shown in FIG. 109, the "LDQ" instruction (main CPU 101-dedicated instruction code) for addressing using the Q register (extended register) is used on the source program. Be done.

  Therefore, in the naviset process of the present embodiment, the instruction related to the address setting can be omitted in the source program, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects of table data acquisition process]
In the table data acquisition process of the pachi-slot 1 of the present embodiment (see FIG. 120), in the table data acquisition process of the first stage of S581 to S584, a table for each winning combination in the CT winning lottery table during CT (see FIG. 122) is selected. A relative table is referenced. Then, in the table combination relative table for each winning symbol combination referred to in the table data acquisition process of the first stage, the “Loss” of the CT lottery is set by the selection value provided for each type of the internal symbol combination (sub flag D). Therefore, it is not necessary to specify the lottery value of the “miss” role in the lottery table. Therefore, in the present embodiment, it is not necessary to store the lottery value data of the “miss” combination in the CT lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

  In addition, in the lottery table of the second stage (when the sub-flag D “reach eye lip” is acquired) in the CT lottery table during CT, the lottery target combination or the non-lottery target combination is determined by the value of each bit forming the determination bit. Therefore, it is not necessary to store the lottery value data (miss data) in the table for the winning combinations not subject to the lottery. Further, in the CT lottery table during CT, the lottery value “0” can be used as the finalized data in which the winning probability of the lottery target combination is 100%. From these things, in this embodiment, the capacity of the CT winning lottery table in CT (the lottery table with the number of sets in CT added) can be compressed, and the free capacity in the main ROM 102 can be secured (increased). , It is possible to improve the game playability by utilizing the increased free space.

[Effects obtained by the symbol code acquisition process]
In the symbol code acquisition process (see FIG. 128) of the pachi-slot 1 of the present embodiment, the data related to winning is compressed / decompressed by the processing procedure described in S647 to S649, and the main CPU 101 dedicated instruction in the process is executed. By using the code (“CALLF” instruction or the like), it is possible to improve the efficiency of the compression / decompression process of the winning data, and it is possible to effectively utilize the limited capacity of the main RAM 103.

  Further, in the present embodiment, in the compressed data storage processing of S649 during the symbol code acquisition processing, the jump destination address specified by the "CALLF" command is the compressed data storage processing of S330 during the symbol setting processing (see FIG. 97). In, the address is the same as the jump destination address specified by the "CALLF" instruction. That is, in this embodiment, in both the symbol code acquisition process and the symbol setting process, the source program for executing the compressed data storage process is shared (modularized). In this case, since it is not necessary to separately provide a source program for the compressed data storage process in each process, the capacity of the source program (capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects of the pull-in priority acquisition process]
In the attraction priority acquisition processing (see FIGS. 134 and 135) of the pachi-slot 1 of the present embodiment, the determination processing of S683 during the attraction priority handling processing of the “ANY hand” is a main CPU 101 dedicated instruction code on the source program. It is executed by a certain "JCP" instruction (comparison instruction) (see FIG. 136A).

  When the "JCP" command is used on the source program for the "ANY winning combination" pull-in priority handling processing, the instruction relating to the address setting can be omitted as described above, so the "ANY winning combination" pull-in priority handling The processing efficiency of the processing can be improved, and the capacity of the source program (used capacity of the main ROM 102) can be reduced.

  Further, in the stop control pull-in request flag setting process of S686 during the pull-in priority obtaining process, as shown in FIG. 136B, the Q register (extended register), which is a main CPU 101 dedicated instruction code, is used on the source program. An "LDQ" instruction and an "CALLF" instruction for addressing are used.

  Therefore, in the stop control pull-in request flag setting process of S686, by using the "LDQ" instruction, the instruction related to the address setting can be omitted in the source program, and the capacity of the source program (use of the main ROM 102). Capacity) can be reduced. The "CALLF" instruction is a 2-byte instruction code as described above. Therefore, in the stop control pull-in request flag setting process, by using these main CPU 101-dedicated instruction codes, the efficiency of the process can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

  Further, in the present embodiment, in the stop control pull-in request flag setting processing of S686 during the priority pull-in order acquisition processing, the address of the jump-destination AND operation processing designated by the "CALLF" instruction is the pull-in priority storage processing ( This is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 in (see FIG. 126) (see FIG. 127). That is, in this embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority attraction-in priority acquisition processing and the attraction-in priority priority storage processing.

  In this case, it is not necessary to separately provide a source program for the AND operation processing in both the priority attraction-in priority order acquisition processing and the attraction-in priority order storage processing, and accordingly, the capacity of the source program (used capacity of the main ROM 102) Can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  Further, in the acquisition processing of the attraction priority table (see FIG. 137) in S687 during the attraction priority acquisition processing, as shown in FIG. 136C, the “LDQ” instruction (main CPU 101 dedicated instruction code) is used. Therefore, even in the acquisition processing of the pull-in priority table in S687, the instruction related to the address setting can be omitted in the source program. As a result, it is possible to improve the efficiency of the acquisition processing of the attraction-in priority table and reduce the capacity of the source program (used capacity of the main ROM 102).

[Effects of reel stop control processing]
In the reel stop control process (see FIG. 138) of the pachi-slot 1 of the present embodiment, in the processes of S711 to S715, as shown in FIG. 139, addressing is performed using the Q register (extended register) on the source program. The "LDQ" command and the "CALLF" command are used.

  Therefore, in the present embodiment, by using the instruction code dedicated to the main CPU 101, the capacity of the source program of the reel control processing can be reduced and the processing efficiency of the reel stop control processing can be improved. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 that has increased according to the reduced capacity to improve the game playability. Can be increased.

  Further, in the determination processing of S726 during the reel stop control processing (reel (turning drum) stop state check processing), as shown in FIG. 140, the “LDQ” instruction and the “ORQ” instruction (Q A main CPU 101-dedicated instruction code for addressing using a register (extended register) is used.

  Therefore, in the present embodiment, an instruction related to address setting can be omitted in the source program of the reel stop control process, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects obtained by winning search processing]
In the prize search process of the pachi-slot 1 of the present embodiment (see FIG. 145), in the process of setting the payout amount and the determination target data in S764, as shown in FIG. 146, the “LDIN” command is used on the source program.

  Therefore, in the winning search process of this embodiment, both the data loading process and the address updating process can be performed by one "LDIN" command. In this case, an instruction relating to address setting can be omitted in the source program of the winning search process, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  Further, the process of acquiring the value of the medal counter referenced in the determination process of S770 during the prize search process, the process of acquiring the value of the prize number counter referenced in the process of S772, and the saving of the prize number counter performed in the process of S775 ( In each of the (update) processing, as shown in FIG. 146, an “LDQ” instruction that uses the Q register (extension register) for addressing is used. Therefore, in the winning prize search process of the present embodiment, the instruction related to the address setting can be omitted in the source program, and the capacity of the source program (used capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

  Furthermore, in the determination processing of S769 during the winning search processing, as shown in FIG. 146, the "JSLAA" instruction is used on the source program, and in the determination processing of S770 and S773, the "JCP" instruction is used. When the "JSLAA" command and the "JCP" command are used on the source program of the prize search processing, as described above, the address setting command can be omitted, and the capacity of the source program (the main ROM 102) can be omitted. Used capacity) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and the increased free space can be utilized to improve the game playability.

[Effects obtained by illegal hit check processing]
In this embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storing area) is the same as that of the winning request flag storage area (internal winning combination storing area). Therefore, in the calculation process of S784 in the illegal hit check process of the present embodiment, the data of the winning combination and the data of the internal winning combination are simply ANDed (“AND” command) on the source program (see FIG. 149). Only by executing), it is possible to obtain the combined result of the data of the winning combination and the data of the internal winning combination.

  Therefore, in the present embodiment, the illegal hit check processing can be made efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space is used to enhance the game playability. be able to.

[Effects of winning check / medal payout processing]
In the prize check / medal payout process (see FIG. 150) of the pachi-slot 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), in the process of S808, the wait (payout interval) of 60.33 ms is performed. (Wait) processing is performed. In this case, useless waiting time can be reduced, and the mental burden on the player can be reduced.

[Effects of the medal payout number check process]
In the update processing of the combination end number counter of S814 during the medal payout number check processing (see FIG. 152) of the pachi-slot 1 of the present embodiment, as shown in FIG. The "DCPLD" instruction is used.

  In the process of S814, the "DCPLD" command is an instruction code in which the lower limit judgment command of the number management counter and the judgment branch command are integrated, so the combination end number counter update (subtraction) process and the consecutive end number Both the process of holding the value of the counter at “0” can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), which increases. You can improve the game play by utilizing the free space.

  In the process of S816 during the medal payout number check process, as shown in FIG. 153B, the value of the payout number counter is set in the communication parameter 1 of the credit information command, and the value of the credit counter is set in the communication parameter 5. To be done. However, the other communication parameters 2 to 4 (unused parameters) forming the credit information command are set to the values currently stored in the H register, the E register, and the D register, respectively. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects obtained by 7-segment LED drive processing]
The output process of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 of the 7-segment LED drive process (see FIG. 159) of the pachi-slot 1 of the present embodiment is performed by one source as shown in FIG. 160B. It is executed by the code “LD (cPA_SEGCOM), BC”. That is, in the present embodiment, in the 7-segment LED drive processing, the 7-segment common output data and the 7-segment cathode output data are simultaneously output when performing dynamic lighting control of the 2-digit 7-segment LED. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

  In this case, it is possible to reduce the number of instruction codes necessary for the dynamic lighting control of the 7-segment LED on the source program of the 7-segment LED drive processing. Therefore, in the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), and the increased free space can be utilized. Therefore, the playability can be improved.

[Effects of timer update processing]
In the process of S952 (the update process of the 2-byte timer) in the timer update process of the pachi-slot 1 (see FIG. 164) of the present embodiment, as shown in FIG. The "DCPWLD" instruction is used.

  When the "DCPWLD" command is executed in the timer update process, both the update (subtraction) process of the number of timers (2-byte timer number) and the process of holding the number of timers at "0" are executed as described above. You can In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the present embodiment, the capacity of the source program (the used capacity of the main ROM 102) can be reduced, and the free space in the main ROM 102 can be secured (increased), and the increased free space can be utilized. Therefore, the playability can be improved.

<Variations>
Heretofore, the configuration and operation of the gaming machine according to the present invention have been described, including the operational effects thereof. However, the present invention is not limited to the above-described embodiments, and various other embodiments and modifications are included without departing from the gist of the present invention described in the claims.

[Modification 1: CT precursor game and notification lottery during normal ART]
In the pachi-slot 1 of the above-described embodiment, in order to facilitate understanding, when the player wins a state advantageous to the player (for example, CT), the game state is shifted from the next game (next game) to the advantageous state. However, the present invention is not limited to this. For example, when performing game control in an advantageous state for a player, the game control in the advantageous state may be performed after performing a predetermined number of games, which is a so-called "predatory game". .

  Here, with reference to FIGS. 174A and 174B, as an example thereof, an example in which the game state shifts from the normal ART to the CT through the predetermined number of precursor games will be described. In addition, FIG. 174A is a diagram showing a game flow at the time of winning the CT lottery in the modified example 1, and FIG. 174B is a block diagram of a flag conversion lottery table used in the flag conversion lottery performed during the omen game.

  In the game during the normal ART in this example, first, as shown in FIG. 174A, as in the above embodiment, the CT lottery table during ART (see FIG. 50) is used, and the CT lottery is performed based on the internal winning combination (sub-flag). I do. If this CT lottery is won, it is determined that the game state shifts to a state called CT (additional opportunity zone), which is advantageous for the player. Therefore, during the period until the lottery for CT, various lottery for CT lottery is performed. Is performed on the main side (main control board 71). For example, the main control board 71 (main CPU 101) performs an internal lottery for determining an internal winning combination, and as the internal winning combination, an internal winning combination “F_ sure chiririp”, “F_1 sure chiririp” and “F_reach eye lip A”. If any of "-F_reach-eye lip D" is determined, the flag conversion lottery is performed using the ART flag conversion lottery table (see FIGS. 47A and 47B).

  Next, if the CT lottery is won in the game during the normal ART, in this example, the precursor game for a predetermined period (CT precursor game) is performed before the CT transition. In this example, in the CT precursor game, for example, a lottery for a player such as a CT lottery based on a sub-flag EX (eg, “3 consecutive chili lip”, “reach eye lip”, “replay”) determined by a flag conversion lottery The lottery that gives However, in this example, in the CT precursor game, for example, the flag conversion lottery using the flag conversion lottery table shown in FIG. 174B is performed on the sub side (sub control board 72 side), and the flag conversion lottery performed on this sub side is performed. Based on the result, the content of the notification performed on the sub side is controlled (determined). For example, in the case of winning the flag conversion lottery performed on the sub side, the display device 11 (projector mechanism 211 and display unit 212) notifies the information for displaying the symbol combination related to the abbreviation "reach eye lip", When the flag conversion lottery is non-win, the display device 11 notifies the display device 11 of information for displaying the symbol combination related to the abbreviation “Replay”.

  As described above, in the recent pachi-slot, it is required that the lottery that influences the profit (ball payout) of the player be performed on the main side, but in the pachi-slot 1 of this example, the lottery result of the flag conversion lottery is the game. A period that does not have any effect on the profit of the person (a period of CT precursor game) is provided, and the flag conversion lottery is performed on the sub side only for this period. Therefore, in this example, for example, in a situation in which the privilege of being a sign of CT has been decided, it is possible to increase the opportunity to display a special symbol combination such as the symbol combination relating to the abbreviation “reach eye lip”. At the same time, it is possible to increase variations in how the symbol combinations are shown. As a result, according to the configuration of this example, it becomes possible to further improve the playability.

  The lottery table shown in FIG. 174B is a flag conversion lottery table in the CT sign used for the flag conversion lottery performed on the sub side, and is stored in the ROM cartridge board 86. The flag conversion lottery table in the sign of CT is an internal winning combination “F_reach eye lip A” to “F_reach eye lip D”, the lottery result (non-win / win) of the flag conversion lottery performed on the sub side, and each lottery. The correspondence with the lottery value information associated with the result is defined.

  As is clear from the flag conversion lottery table shown in FIG. 174B, in this example, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” have a very high probability of being the sub-flag EX “in the CT predictive game. It is converted to "Reach eye Lip" (wins the lottery for flag conversion). That is, in the CT predictive game, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, the symbol combination of the abbreviation “reach eye lip” is stopped and displayed with high probability. As a result, it is possible to suggest to the player that the current game is the CT precursor game. At this time, as described above, if the player wins the flag conversion lottery performed on the sub side in the CT amenity game, the notification for displaying the symbol combination related to the abbreviation "reach eye lip" is given, but a privilege is given. There is no.

  In this example, the flag conversion lottery during the CT precursor game may be performed on the main side. However, as in the example described with reference to FIGS. 174A and 174B, by performing the lottery on the sub side during the period that does not affect the profit of the player at all, the data capacity and the processing load on the main side can be reduced.

[Modification 2: Another example of the pressing order for displaying the triple chili lip]
In the pachi-slot 1 of the above embodiment, when the internal winning combination “F_probable chillip” or “F_1 probable chillip” is determined, if the stop button is pressed in the correct order, the symbol combination relating to the abbreviation “3 consecutive chillips” is The example in which the symbol combination related to the abbreviation “Replay” is displayed when the displayed order is incorrect and the pressing order is incorrect has been described (see FIG. 24). Further, in the above-described embodiment, an example in which the correct answer pressing order associated with the internal winning combination “F_probable chiririp” and “F_1 probable chilirip” is “forward press” has been described. However, the present invention is not limited to this.

  For example, when the internal winning combination “F_Sure Chilelip” or “F_1 Sure Chilelip” is determined, the number of symbol combinations displayed when the pressing order is incorrect is increased, and the internal winning combination “F_Sure Chilelip” The pressing order of the correct answers when “” is determined may be different from that when the internal winning combination “F_1 definite Chilelip” is determined. One example (Modification 2) will be described with reference to FIGS. 175A and 175B. 175A is a diagram showing a correspondence relationship between the internal winning combination and the symbol combination (stop symbol (abbreviation)) that is stopped and displayed in the modified example 2, and FIG. 175B is during normal ART in the modified example 2. It is a diagram showing a correspondence relationship between the result of the flag conversion lottery and the navigation type performed on the sub side.

  In this example, as shown in FIG. 175A, when the internal winning combination “F_Sure Chile Lip” is determined, the correct answer pressing order is “forward pressing (left reel 3L first stop)”, and incorrect pressing The order is "first stop of middle reel 3C (hereinafter referred to as" middle push ") or first stop of right reel 3R (hereinafter referred to as" reverse push ")," that is, "irregular push". In this example, when the internal winning combination “F_Sure Chiririp” is determined, the symbol combination related to the abbreviation “3 consecutive chiririp” is displayed when the button is pressed forward, and the abbreviation “Replay” when the center is pressed. The symbol combination relating to is displayed, and when it is pressed backward, the symbol combination relating to the abbreviation "2 consecutive chili lip" is displayed.

  In addition, in this example, when the internal winning combination “F_1 definite chiririp” is determined, the correct pressing order is reverse pressing, and the incorrect pressing order is normal pressing and middle pressing. In this example, when the internal winning combination “F_1 definite chiririp” is determined, when the back push is performed, the symbol combination related to the abbreviation “3 consecutive chiririp” is displayed, and when the middle press is performed, the abbreviation “replay” is displayed. The symbol combination relating to is displayed, and when the button is pressed forward, the symbol combination relating to the abbreviation "2 consecutive chili lip" is displayed.

  In the pachi-slot 1 of this example, if either the internal winning combination “F_probable chililip” or “F_1 probable chililip” is determined, when pressed forward, the abbreviation “three consecutive chililip” or The symbol combination related to “two consecutive chirip” is displayed. In addition, if either the internal winning combination “F_Sure Chillirip” or “F_1 Sure Chillirip” is determined, pressing the reverse key will abbreviate “3 consecutive Chillirip” or “2 consecutive Chillirip” depending on the type of the internal winning combination. The symbol combination relating to “” is displayed. Furthermore, in this example, when either the internal winning combination “F_Sure Chiririp” or “F_1 Sure Chiririp” has been determined, pressing the middle key will result in a symbol combination relating to the abbreviation “Replay” regardless of the type of the internal winning combination. Is displayed.

  When the corresponding relationship between the internal winning combination and the symbol combination (stop symbol (abbreviation)) that is stopped and displayed is set to the relationship shown in FIG. 175A, for example, the internal winning combination “F_certain Chilelip” or “F_1 certain Chilelip” is determined. In such a case, it becomes possible to carry out various navigations (notifications) for causing the player to aim for the Chile pattern.

  For example, it is possible to perform both "navigation to push Chile pattern by pushing forward" and "navigation to push Chile pattern by pressing backward". In addition, when the internal winning combination “F_Sure Chiriripu” is determined, “Navigating the Chile design by pushing forward” is the navigation for displaying the symbol combination related to the abbreviation “3 consecutive chiriripu”, and “ The "navi that allows you to aim at the Chile symbol by pressing backward" is a navigation for not displaying the symbol combination related to the abbreviation "3 consecutive Chile lip" (the navigation displaying the symbol combination related to the abbreviated "2 consecutive Chile lip"). On the other hand, when the internal winning combination "F_1 probable Chilelip" is determined, "navigation to aim for Chilean design by pressing forward" is a navigation for not displaying the symbol combination related to the abbreviation "3 consecutive Chilelip" (abbreviated " The "navigation for displaying a symbol combination related to" two consecutive chilirips "becomes", and the "navi for aiming at a chili symbol by reverse pressing" is a navigation for displaying the symbol combination related to the abbreviation "three consecutive chilirips".

  In this example, the determination as to whether or not to perform the navigation described above is managed by the flag conversion lottery performed on the main side, and the navigation is executed by the control on the sub side based on the result of the flag conversion lottery on the main side. .. At this time, the correspondence between the lottery result of the flag conversion lottery performed on the main side during the normal ART and the navigation type controlled on the sub side is the correspondence shown in FIG. 175B.

  Also in this example, when the internal winning combination “F_probable chillip” or “F_1 probable chillip” is determined in the game during the normal ART, the main control board 71 (main CPU 101) performs the two-stage flag conversion lottery ( See FIG. 47). On the other hand, on the sub side, the result of the two-step flag conversion lottery is acquired from the start command data, and based on the result of the two-step flag conversion lottery, the navigation performed on the display device 11 is determined.

  Therefore, in this example, if the lottery result is non-win at the time of the flag conversion lottery in the first stage, the sub control board 72 (sub CPU 201) indicates “Replay Navi” as shown in FIG. 175B. Carry out a navigation called. In the "replay navigation", information for instructing the player to press the middle button is notified. In this example, as shown in FIG. 174A, regardless of whether the internal winning combination is "F_probable chilirip" or "F_1 probable chililip", the symbol combination related to the abbreviation "replay" is displayed when the player presses the middle key. ..

  In addition, in this example, when the first-stage flag conversion lottery is won and the second-stage flag conversion lottery result is non-win, the sub-control board 72 (sub-CPU 201) is shown in FIG. 175B. As shown in, a navigation referred to as "chillilip fan navigation" is performed. Note that in the “Chililip fanning navigation”, when the internal winning combination “F_Sure Chilirip” has been determined, the player is informed of instruction information that allows the player to aim the Chile symbol by pressing the button backwards. On the other hand, in the “Chililip fanning navigation”, when the internal winning combination “F_1 definite Chilelip” is determined, the player is informed of the instruction information that allows the player to press the Chile symbol by pushing forward. Then, in such a “chillilip fan navigation”, as shown in FIG. 174A, when the internal winning is “F_probable chilirip”, the symbol combination related to the abbreviation “two consecutive chilirips” is displayed at the time of reverse pressing, When the internal winning combination is "F_1 probable chili lip", the symbol combination related to the abbreviation "2 consecutive chili lip" will be displayed when the user presses the forward combination.

  In addition, in this example, when both the first-stage and the second-stage flag conversion lottery are won, the sub-control board 72 (sub-CPU 201) calls "Chirilip complete navigation" as shown in FIG. 175B. Navi. In the “Chililip complete navigation”, when the internal winning combination “F_probable chilirip” is determined, the player is informed of the instruction information that allows the player to press the Chile symbol by pushing forward. On the other hand, in the “Chililip complete navigation”, when the internal winning combination “F_1 probable Chilelip” is determined, the player is informed of the instruction information that allows the player to aim the Chile symbol by pressing the button backwards. Then, in such a “chilly lip complete navigation”, as shown in FIG. 174A, when the internal winning is “F_Sure Chilelip”, the symbol combination related to the abbreviation “3 consecutive chililip” is displayed at the time of forward pressing, When the internal winning combination is "F_1 probable chili lip", the symbol combination related to the abbreviation "3 consecutive chili lip" is displayed at the time of reverse pressing.

  In this example, the notification based on the lottery result of the flag conversion lottery described above does not affect the profit (although the flag conversion lottery itself affects the profit, the symbol combination displayed as a result affects the profit. Therefore, the notification operation in this example is not performed on the main side (instruction monitor), but is performed only on the sub side (display device 11). Further, in this example, as described above, not only the “navigation complete navigation” but also the “native lip incline navigation” are performed, so that the sub side can control the navigation that does not affect the profit in various ways. .. As a result, the enjoyment of the game can be improved.

[Modification 3: Another example of Bernavi mode between flags and between non-flags]
In the pachi-slot 1 of the above-described embodiment, as described above, a numerical value uniquely corresponding to the reel stop operation information is displayed on the instruction monitor (not shown) to notify the main side. At this time, the correspondence relationship of the navigation data described in FIGS. 63A to 63D is referred to. Further, in the above-described embodiment, an example in which "white 7 navigation" and "blue 7 navigation" are performed during the BB flag state (RT5 state), but "bell navigation" is not performed has been described. Not limited. During the state between BB flags (RT5), "bell navigation" or the like may be performed in addition to "white 7 navigation" and "blue 7 navigation".

  In this case, the numerical value displayed on the instruction monitor may be different between the BB flag state and the non-BB flag state. Here, FIGS. 176A and 176B show the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the BB flag state in the third modification. Note that FIG. 176A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the RT5 state (between BB1 flags), and FIG. 176B shows the RT5 state in the RT5 state. It is a figure which shows the correspondence of the notification (navi) performed by the main side and the notification (navi) performed by the sub side in (between BB2 flags).

  Further, in this example, the correspondence relationship between the notification (navi) performed on the main side and the notification (navi) performed on the sub side during the non-BB flag state is the same as in the above-described embodiment (see FIGS. 63A and 63B). .. Therefore, when the "bell navigation" is performed in the non-BB flag state, a numerical value of "1" to "3" (push order combination second instruction information) is displayed on the instruction monitor.

  In this example, as shown in FIGS. 176A and 176B, when "bell navigation" is performed in the BB flag state, a numerical value of "12" to "14" (first push-order combination instruction information) is displayed on the instruction monitor. It Note that the present invention is not limited to this, and the numerical value displayed on the instruction monitor can be appropriately changed when the "bell navigation" is performed in the BB flag state. In this example, the sub-side navigation performed using the display device 11 may be provided in common in both the inter-BB flag state and the non-BB flag state.

[Modification 4: Another example of awarding]
In the pachi-slot 1 of the above-described embodiment, the content of the notification is controlled based on the result of the flag conversion lottery performed on the main side. Therefore, when the stop operation is performed according to the notification, the symbol combination displayed is different. That is, in the above embodiment, an example in which it is determined whether or not to grant the privilege based on the result of the flag conversion lottery performed on the main side has been described, but the present invention is not limited to this. For example, the main side (main control board 71) may be configured to give a privilege based on the symbol combination actually displayed.

  In this case, the main control board 71 (main CPU 101) gives a privilege when the predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, and when not following the notification. Even if a predetermined symbol combination is displayed, the privilege may not be given. In the pachi-slot 1 of the above-mentioned embodiment, the symbol combination displayed differs depending on the pressing order, but even when the player ignores the notification and performs the stop operation, the symbol combination relating to the abbreviation “3 consecutive chili lip” There is a possibility that a special symbol combination such as "" will be displayed. Therefore, in this example, even if the special symbol combination is displayed ignoring the notification, the privilege is not given, and the privilege is given only when the special symbol combination is displayed according to the notification. May be.

[Modification 5: Another example of notification control that does not affect profit (privilege)]
In the pachi-slot 1 of Modification 1 (see FIGS. 174A and 174B), whether or not to notify the profit-affecting one is determined by the notification lottery (flag conversion lottery) on the main side and does not affect the profit. The example has been described in which whether or not to notify is determined by the notification lottery on the sub side. And, as an example of the notification that does not affect the profit, an example of performing the notification for displaying the symbol combination related to the abbreviation "reach eye lip" during the aura game was described, but the notification that does not affect the profit is However, the present invention is not limited to this example.

  In recent years, the pachi-slot may make a transition to a state in which it is easy (difficult) to perform game lock depending on the order of stop operations. For example, transition to a state where it is easy to lock the game when the pressing order is "left, middle, right", and transition to a state where it is difficult to lock the game when the pressing order is "right, middle, left". There is. In such a pachi-slot, by notifying the pressing order, it is possible to make a transition to a state in which game locking is easy (difficult). However, if whether or not to lock the game affects the profit, it is necessary to control this notification on the main side. It should be noted that this notification may be controlled on the sub side when the game lock does not affect the profit.

  Further, as a case in which whether or not to perform the game lock affects the profit, for example, a case where the game lock is performed and the ART lottery is won. On the other hand, in the case where whether to lock the game does not affect the profit, it is a case where the game lock is performed as an effect. For example, by frequently performing a game lock during a precursory game in which a profit (privilege) is determined to be given, it is possible to show in the effect that a profit is given in the subsequent game. ..

  Here, with reference to FIGS. 177A and 117B, a configuration example in which the pressing order and the locked state are associated with each other in the modified example 5 will be described. Note that FIG. 177A is a diagram showing a correspondence relationship between the pushing order and the locked state, and FIG. 177B is a diagram showing a relationship between the presence or absence of the effect of the game lock on the profit and the notification mode.

  In the example shown in FIG. 177A, when the internal winning combination “F_maintenance lip A” is determined and the stop operation is performed in the pushing order of “left, middle, right”, the lock state is “0” (the state that is difficult to lock). ) To “1” (easy to lock), and when the stop operation is performed in the pushing order of “left, right, middle”, “middle, left, right” or “middle, right, left”, When the lock state is maintained and the stop operation is performed in the pushing order of “right, left, center” or “right, center, left”, the lock state transitions from “1” to “0”. Further, when the internal winning combination “F_maintenance lip B” is determined, when the stop operation is performed in the pushing order of “middle, left, right”, the lock state changes from “0” (the state that is difficult to lock) to “1”. When the stop operation is performed in the other pushing order, the current locked state is maintained.

  Note that, in the example shown in FIG. 117A, in order to simplify the description, an example will be described in which the lock state is set to two stages of “0 (state that is difficult to lock)” and “1 (state that is easy to lock)”. The present invention is not limited to this. For example, a lock state of three stages or more may be provided. Further, in this case, the lock state may not be changed step by step but may be changed in multiple steps at once.

  In this example, as shown in FIG. 117B, when the game lock affects the profit, the notification lottery as to whether or not to notify is performed on the main (main control board 71) side and the lottery result. Based on the above, the predetermined pushing order is notified on both the main side and the sub side. On the other hand, when the game lock does not affect the profit, the sub lot (sub-control board 72) performs the notification lottery of whether or not to give the notice, and the sub-side has a predetermined push order based on the lottery result. To inform.

  As the pachi-slot, there are pachi-slots in which the game lock influences the profit over the entire period of the game, and there are pachi-slots in which the game lock does not influence the profit over the entire period of the game. Further, as a pachi-slot, there is a pachi-slot in which a game lock affects profits during a predetermined period of a game, but a game lock does not affect profits during a specific period of a game. Therefore, during the period when the game lock affects the profit, the notification lottery whether or not to notify is performed on the main side, and based on the lottery result, both the main side and the sub side notify the predetermined pushing order. On the other hand, in the period when the game lock does not affect the profit, the notification side lottery whether or not to notify is performed on the sub side, and even if the sub side notifies the predetermined pushing order based on the lottery result. Good.

  Since the game lock control is normally performed on the main side (main control board 71), the main control board 71 is provided with the function of transitioning the lock state according to the pressing order shown in FIG. 117A. That is, the main control board 71 randomly determines whether or not to lock the game with a probability according to the lock state setting unit that sets the lock state based on the detected stop operation sequence and the lock state set by the lock state setting unit. When the game lock determining means and the game lock determining means determine to lock the game, it also functions as lock executing means for temporarily stopping the progress of the game. In addition, the main control board 71 and / or the sub-control board 72, when the lock state setting means sets a lock state in which the game is easily locked (difficult to lock), a notification of whether or not to notify the push order is performed. It also functions as a lottery means and as an informing means for informing a predetermined pushing order based on the lottery result of the informing lottery means.

[Modification 6: Another example of ending condition of normal ART or CT]
The termination condition for normal ART or CT is not limited to the example described in the above embodiment, and any termination condition can be adopted. For example, the number of medals given during the normal ART or CT, the number of times the unit game is exhausted during the normal ART or CT, the number of times of notification of information advantageous to the player performed during the normal ART or CT, An end condition such as the number of sets when the predetermined number of games (for example, 50 games) is one set, a continuation rate at the end of one set, or the like can be adopted.

  Further, as a method of counting the number of medals given during normal ART or CT, for example, a method of counting the number of medals paid out in a unit game may be adopted, or paid out in a unit game. A method of counting the difference number (net increase number) by subtracting the bet (multiplied) number of medals used in the unit game from the number of medals that have been played may be adopted. Further, as a method of counting the number of medals given during normal ART or CT, a method of calculating based on the actually increased medals (calculation by actual value) may be adopted, or is it actually increased? Regardless of whether or not the notification is made, a method (calculation based on an ideal value) based on the number of medals expected to increase when the notification is followed may be adopted.

  Depending on the type of internal winning combination, a configuration may be adopted in which the number of awarded medals is not increased, that is, a configuration is not counted in the number of medals or the difference, which is the condition for ending the number of awarded medals. .. For example, even if some winning combination (rare winning combination) with a low probability of being determined as an internal winning combination, or a winning combination in which the display / non-display of the symbol combination is switched according to the timing of the stop operation is determined as an internal winning combination. It is also possible not to increase or decrease (count) the number of awarded medals.

[Modification 7: Others]
The content of the notification normally performed during ART or CT is not limited to the example described above, and is arbitrary. For example, the order of stop operations (pushing order) in which a special symbol combination that is advantageous for the player is displayed may be notified, or the timing of the stop operation necessary for displaying the symbol combination ( The pattern to be aimed at) may be notified.

  As an advantageous state for the player, the winning probability of the internal winning combination relating to the re-play does not change (or changes within a range that does not affect the playability), but a mode of the stop operation advantageous for the player is set. The function of notifying, that is, the gaming state in which the AT function operates may be used. Further, as an advantageous state for the player, a re-game high probability state (replay time) in which the winning probability of the internal winning combination relating to the re-play becomes high is activated, and a mode of the stop operation advantageous for the player is notified. It may be a gaming state in which a function operates, that is, an ART function operates.

  Further, in the pachi-slot 1 of the above embodiment, an example in which various display screens are displayed on the sub display device 18 provided on the left side of the reel display window 4 when viewed from the player side has been described, but the present invention is not limited to this. .. For example, another sub display device may be provided on the right side of the reel display window 4 as viewed from the player side, and various display screens may be displayed on this sub display device. In this case, a touch sensor is provided on the display surface of the sub display device provided on the right side of the reel display window 4, and the display screen of the sub display device is switched based on the touch input information output from the touch sensor. You can

  Further, in the above-described embodiment and various modifications, a pachi-slot has been described as an example of a game machine, but the present invention is not limited to this. The characteristics other than the characteristics peculiar to the pachi-slot 1 such as the characteristics related to the reel control and the characteristics related to the setting change and confirmation of the present invention can be applied to the gaming machine called "pachinko", and the same effect can be obtained. For example, checksum generation and determination processing, various processing using the main CPU 101 dedicated instruction code (address designation processing using Q register, soft timer update processing, 7-segment LED drive processing, communication data generation / storage processing, etc.) ), Features such as various processes using the non-specified ROM area and the non-specified RAM area are also applicable to "pachinko".

<Various functions of the main control board and the sub-control board>
The embodiments and various modifications of the pachi-slot 1 according to the present invention have been described above. Here, various functions of the main control board 71 (main control circuit 90, main CPU 101) and the sub control board 72 (sub control circuit 200, sub CPU 201) of the pachi-slot 1 according to the present invention will be collectively described.

  The main control board 71 is connected to the start switch 79 and the stop switch board 80 and controls the progress of the game shown in FIG. Therefore, the main control board 72 functions as a start operation detecting means, a symbol varying means, an internal winning combination determining means, a stop operation detecting means, a reel stop controlling means (stop controlling means) and a winning determination means.

  Further, when the internal winning combination “F_probable chiririp” or “F_1 probable chiririp” is determined during the normal ART, the main control board 71 performs the flag conversion lottery, and the result of the flag conversion lottery and other internal winning combinations. When the lottery based on CT is won, the CT for extending the duration of the normal ART is started. Therefore, the main control board 71 also functions as a conversion lottery means and an addition game starting means.

  Further, the main control board 71 adds (extends) the number of ART games showing the duration period of the normal ART according to the internal winning combination during CT. Specifically, when the internal winning combination corresponding to the sub-flags “cactus”, “weak cherry” or “strong cherry” is determined, the main control board 71 adds the ART game number of the normal ART by a predetermined amount, When the internal winning combination corresponding to the sub-flag “three consecutive chillips (three consecutive chillips A or three consecutive chillips B)” is determined, the specific ART number of ART games is added. Further, the main control board 71 adds 1 when the number of additions of the ART game based on the sub-flag “three consecutive chili-rips” exceeds 9 which is the basic game number of one set of CT. Increase the amount added per time. Therefore, the main control board 71 also functions as additional control means.

  Further, the main control board 71 counts the number of games in which the number of ART games is not added during CT by using the CT game number counter, and when the CT game number counter counts “8”, the CT is ended. At this time, if the sub-flag EX “3 consecutive chiririp” is won (that is, the flag conversion lottery is won), the main control board 71 resets the CT game of 8 times (8 games) per set (of the CT game number counter). Return the value to the initial value). Therefore, the main control board 71 also functions as counting means and additional game ending means.

  Further, when the bonus combination (internal winning combination “F_BB1”, “F_BB2”) is determined as the internal winning combination, the main control board 71 shifts the gaming state to the BB flag state (RT5 state) and also the BB flag. In the interim state, the bonus combination is carried over as an internal winning combination until the bonus is activated (until the bonus combination is won). Therefore, the main control board 71 also functions as a bonus carryover means. When the bonus combination is won in the BB flag state, the main control board 71 activates the bonus and shifts the game state to the bonus state. Therefore, the main control board 71 also functions as a bonus starting means and an advantageous game means.

  Further, as shown in FIG. 25, in the main control board 71, the bonus combination and the predetermined internal winning combination (“off”, “F_special 1” to “F_special 3”) overlap in the BB flag state. If the winning combination is determined, the stop control is performed so that the symbol combination (“C_BB1”, “C_BB2”) related to the bonus combination can be displayed, and the internal winning combination other than the bonus combination and the predetermined internal winning combination is performed. When and are determined to overlap, stop control is performed so that the symbol combination related to the bonus combination cannot be displayed. When the symbol combination relating to the bonus combination can be displayed during the BB flag state, the main control board 71 controls the instruction monitor (not shown) of the information display 6 to win the bonus combination. Numerical value "10" or "11" that uniquely indicates the mode of the stop operation of is displayed to inform the bonus instruction information. On the other hand, when the symbol combination related to the bonus combination cannot be displayed during the BB flag state, the main control board 71 does not display (notify) the numerical values “10” and “11” on the instruction monitor. Therefore, the instruction monitor of the main control board 71 and the information display 6 functions as instruction information notifying means.

  Further, at this time, the main control board 71 informs the numerical value “10” or “11” via the instruction monitor only after the bonus notification. Specifically, the main control board 71, when determining the bonus combination as an internal winning combination in a state where the bonus combination is not carried over, counts the number of subsequent games, and after the count result reaches a predetermined number, the bonus When the winning combination and the predetermined internal winning combination (“out”, “F_special 1” to “F_special 3”) are determined in an overlapping manner, the numerical value “10” or “11” is notified via the instruction monitor. .. Therefore, the main control board 71 also functions as a counting unit that counts the number of unit games after the bonus combination is determined as the internal winning combination.

  The sub-control board 72 manages the game history based on various command data received from the main control board 71, and when the registration operation from the player is accepted, the sub-control board 72 accepts the registration of the player who plays the game. Therefore, the sub control board 72 functions as history management means and registration acceptance means.

  Further, the pachi-slot 1 according to the present invention is provided separately from the display device 11 that produces an effect according to the progress of the game, and includes a top screen 221, game information screens 223, 224, 225, and the like. And a touch sensor 19 provided on the display unit of the sub display device 18. The sub control board 72 controls the operations of the display device 11 and the sub display device 18. To do. Specifically, when the registration of the player is accepted, the sub control board 72 controls the sub display device 18 so that the game information screens 223, 224, 225 can be displayed on the sub display device 18. If the registration of the player is not accepted, the sub display device 18 is controlled so that the game information screens 223, 224, and 225 cannot be displayed. Therefore, the sub control board 72 also functions as control means.

  The main control board 71 also functions as a privilege granting means, as it grants various benefits depending on the result of the game. Specifically, the main control board 71 gives a privilege according to the symbol combination displayed along the activated line.

  For example, in the game in which the internal winning combination “F_3 choice bell_1st” is determined, when the symbol combination related to the abbreviation “bell” is displayed on the activated line, the main control board 71 gives 9 medals, When the symbol combination related to the abbreviation "bell crevice" is displayed on the activated line, the main control board 71 gives 0 medals. Further, for example, in the game in which the internal winning combination “F_Sure Chiririp” is determined, when the symbol combination related to the abbreviation “3 consecutive chiririp” or the abbreviation “Replay” is displayed on the activated line, the main control board 71, The same privilege of re-playing is given. Further, the main control board 71 gives a privilege based on the result of the flag conversion lottery instead of the symbol combination displayed along the activated line. For example, the main control board 71 performs a flag conversion lottery when the internal winning combination “F_Sure Chile Lip” is determined, and when the flag conversion lottery is won, a benefit such as winning the CT lottery is given.

  In addition, the sub-control board 72 executes an effect according to the mode of the stop operation via the display device 11. Therefore, the sub-control board 72 and the display device 11 also function as an effect execution means. At this time, when the privilege to be given is different depending on the symbol combination displayed along the activated line, the main control board 71 provides the information uniquely indicating the mode of the stop operation advantageous to the player via the instruction monitor. If the benefit given by the symbol combination displayed along the activated line is the same, the mode of the stop operation advantageous to the player is not notified. On the other hand, the sub-control board 72 executes an effect indicating the order of the stop operation regardless of whether the privilege given by the displayed symbol combination is the same or different.

  Further, the main control board 71 performs CT lottery as to whether or not to start CT, and when winning the CT lottery, starts CT after winning a predetermined number of predictive games after winning the CT lottery. Therefore, the main control board 71 also functions as an advantageous state lottery means and an advantageous state start means. Further, at this time, when the internal winning combination “F_probable chililip” or “F_1 probable chililip” is determined during the CT precursor game, the sub control board 72 carries out a flag conversion lottery on the sub side. Therefore, the sub control board 72 also functions as a notification lottery means.

  Further, in the pachi-slot 1 according to the present invention, based on the result of the flag conversion lottery, the main control board 71 gives a privilege, and the main control board 71 and the sub-control board 72 pass through the instruction monitor and the display device 11. Notify the pressing order. Therefore, the main control board 71 also functions as a privilege granting means. Further, the main control board 71, the sub control board 72, the instruction monitor and the display device 11 also function as an informing means.

  Further, in the pachi-slot 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) performs various control processes throughout the game operation. Therefore, the main control board 71 also functions as an arithmetic control unit. Further, in the pachi-slot 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) also functions as a means for executing various processes described below.

  The main control board 71 (main control circuit 90, main CPU 101) performs a checksum generation process when power failure occurs (see FIG. 77) and a sum check process when power is restored (see FIGS. 79 and 80). Therefore, the main control board 71 also functions as a sum value calculating means, a sum value subtracting means, and a sum value determining means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a winning search process (see FIG. 145). Therefore, the main control board 71 also functions as a privilege giving determination means and a winning combination determination means.

  The main control board 71 (main control circuit 90, main CPU 101) performs communication data transmission processing (S904 during interrupt processing in FIG. 158). Therefore, the main control board 71 also functions as a data transmission unit.

  The main control board 71 (main control circuit 90, main CPU 101) performs setting change confirmation processing (see FIG. 68). Therefore, the main control board 71 also functions as setting change confirmation means, start command generation means, and end command generation means.

  The main control board 71 (main control circuit 90, main CPU 101) performs communication data storage processing (see FIG. 72) and communication data pointer update processing (see FIG. 74). Therefore, the main control board 71 also functions as communication data generation means and communication data generation / storage means.

  The main control board 71 (main control circuit 90, main CPU 101) performs 7-segment LED drive processing (see FIG. 159). Therefore, the main control board 71 also functions as a 7-segment LED drive unit and an LED drive control unit.

  The main control board 71 (main control circuit 90, main CPU 101) performs game return processing (see FIG. 68). Therefore, the main control board 71 also functions as a game return means.

  The main control board 71 (main control circuit 90, main CPU 101) performs medal acceptance / start check processing (see FIG. 83). Therefore, the main control board 71 also functions as a game start determination means and a setting confirmation means (S233).

  The main control board 71 (main control circuit 90, main CPU 101) performs a medal insertion check process (see FIG. 87). Therefore, the main control board 71 also functions as a game medium acceptance state determination means (S255 to S258).

  The main control board 71 (main control circuit 90, main CPU 101) repeatedly executes the interrupt processing (see FIG. 158) at a cycle of 1.1172 msec. Therefore, the main control board 71 also functions as interrupt processing execution means and fixed cycle processing means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a power-on process (see FIG. 64). Therefore, the main control board 71 also functions as a power restoration process execution means.

  The main control board 71 (main control circuit 90, main CPU 101) performs an internal lottery process (see FIG. 92). Therefore, the main control board 71 also functions as an internal lottery means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a symbol setting process (see FIG. 97). Therefore, the main control board 71 has an internal winning combination generating means (S321), a flag table expanding means, a winning flag table expanding means (S324), a flag storage area designating means, a winning flag storage area designating means (S329) and flag data. It also functions as a storage unit and a winning flag data storage unit (S330).

  The main control board 71 (main control circuit 90, main CPU 101) performs a symbol code acquisition process (see FIG. 28). Therefore, the main control board 71 also functions as a winning flag storage area designating means (S648) and a symbol code storage area setting means (S650).

  The main control board 71 (main control circuit 90, main CPU 101) performs reel stop control processing (see FIG. 139). Therefore, the main control board 71 also functions as a stop operation detection result acquisition unit (S714) and a stop control data storage area setting unit (source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139). ..

  The main control board 71 (main control circuit 90, main CPU 101) performs a pull-in priority order acquisition process (see FIGS. 134 and 135). Therefore, the main control board 71, priority stop symbol determination means, arbitrary winning combination processing means (S680-S683), winning flag storage area designating means (S686), winning flag storage area designating means (S686), AND operation means. It also functions as (S686) and priority order data table acquisition means (S687).

  The main control board 71 (main control circuit 90, main CPU 101) performs illegal hit check processing (see FIG. 148). Therefore, the main control board 71 also functions as an error detecting unit, an error processing unit, a winning flag storage area designating unit (S781), a logical product calculating unit (S784), and an error determining unit (S785).

  The main control board 71 (main control circuit 90, main CPU 101) performs a prize check / medal payout process (see FIG. 150). Therefore, the main control board 71 also functions as a game medium payout unit, a game medium addition unit (S805), a payout end determination unit (S807), and a weight generation unit (S808).

  The main control board 71 (main control circuit 90, main CPU 101) performs CT lottery processing during CT (see FIG. 119). Therefore, the main control board 71 also functions as a privilege giving determination means.

  The main control board 71 (main control circuit 90, main CPU 101) performs sub-flag conversion processing (see FIG. 105). Therefore, the main control board 71 also functions as a first sub flag conversion means.

  Further, the main control board 71 (main control circuit 90, main CPU 101) performs flag conversion processing (see FIG. 111). Therefore, the main control board 71 also functions as the second sub flag conversion means.

<Appendix (Summary of the present invention)>
[First gaming machine]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that obtains a checksum of data stored in the RAM at the time of power failure and performs a checksum determination process obtained at the time of power failure at the time of power restoration ( See, for example, Japanese Patent Laid-Open No. 2009-011375). In the gaming machine disclosed in Japanese Patent Laid-Open No. 2009-011375, in the checksum determination process when the power is restored, an error is notified when the checksum obtained when the power is restored does not match the checksum obtained when the power is cut off.

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of playability, and it is required to reduce the capacity of processing programs and tables other than the playability managed by the main control circuit.

  The present invention has been made in order to solve the above first problem, and a first object of the present invention is to reduce the capacity of processing programs and tables other than the game play managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM of the main control circuit and utilizing the free space of the ROM for the increased capacity to improve the game playability.

  In order to solve the first problem, the present invention provides a first gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Power supply means for supplying a power supply voltage (for example, the power supply substrate 53b and the switching regulator 94),
Start-up means (for example, reset signal output processing of the power management circuit 93) that outputs a start-up signal to the arithmetic processing means when the power supply voltage exceeds a predetermined start-up voltage value (for example, 10 V);
A power failure means for outputting a power failure signal to the arithmetic processing means when the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V) (for example, output of a power failure detection signal of the power management circuit 93). Processing) and
The arithmetic processing means,
A flag register (for example, flag register F) for storing data corresponding to the result of the arithmetic processing,
When the power failure means outputs the power failure signal, all the information stored in a predetermined storage area (for example, a game RAM area) in the second storage means is cumulatively added to calculate a sum value. Sum value calculation means (for example, checksum generation processing),
A sum value that sequentially subtracts the information stored in the predetermined storage area from the sum value generated by the sum value calculation means at the time of the latest power failure when the starting means outputs the start signal. Subtraction means (for example, S122 to S131 during sum check processing),
For all the information stored in the predetermined storage area, when the subtraction processing by the sum value subtraction means is completed, the subtraction result set in a predetermined bit area (for example, a zero flag) in the flag register is obtained. A game machine characterized by having a sum value judging means (for example, S134 during a sum check process) for judging whether or not an abnormality has occurred based on the corresponding data.

Further, in the first gaming machine of the present invention, the sum value calculation means executes a specific command (for example, a POP command) when adding the information stored in the predetermined storage area, Acquiring and adding 2 bytes of information stored continuously, and updating the information of the read start address of the information by 2 bytes,
The sum value subtracting means executes the specific instruction when subtracting the information stored in the predetermined storage area from the sum value generated when the power failure occurs, so that the two consecutively stored values are stored. Information of the read start address of the information may be updated by 2 bytes while the information of bytes is acquired and subtracted.

Further, in the first gaming machine of the present invention, the arithmetic processing means has a stack pointer capable of setting an address of the predetermined storage area of the second storage means,
The specific instruction executed when the sum value calculation means adds the information stored in the predetermined storage area may be a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

  According to the first gaming machine of the present invention having the above-mentioned configuration, the capacity of the processing program other than the game property, the table, etc. is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and this is increased. It is possible to improve the game playability by utilizing the free area of the ROM for the capacity.

[Second to fifth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there has been proposed a gaming machine equipped with a main control device that processes numerical data by using a stack pointer in an operation command (see, for example, JP-A-2005-237737). ).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above-mentioned second problem, and a second object of the present invention is to reduce the capacity of the processing programs and tables managed by the main control circuit to reduce the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the second problem, the present invention provides a second gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
A dedicated register for storing data when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) that can specify a part of an address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means executes a predetermined instruction (for example, a "BITQ" instruction, a "SETQ" instruction, an "LDQ" instruction, etc.) capable of specifying an address in the second storage means using the extension register. A game machine characterized by being possible.

  Further, in the second gaming machine of the present invention, a part of the address that can be designated by the extension register may be an upper-order side address value forming the address.

  In order to solve the second problem, the present invention provides a third gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
A dedicated register for storing data when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) that can specify a part of an address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means,
In the process of checking the stopped state of the display column,
The predetermined register stored in the second storage means is executed by executing a predetermined read instruction (for example, "LDQ" instruction) capable of addressing in the second storage means using the extension register. Reads out the information indicating the variable display status in the display column,
Next, a predetermined logical sum operation instruction (for example, “ORQ” instruction) capable of addressing in the second storage means is executed by using the extension register and stored in the second storage means. While reading the information indicating the variable display state of the other one of the display columns, and performing an OR operation of the information and the information indicating the variable display state of the predetermined display column,
After that, the execution of the predetermined OR operation command is repeated, and the OR operation of the result of the OR operation and the information indicating the variable display state of each of the remaining display columns is repeated, and the OR operation is performed on all the display columns. A gaming machine characterized by determining whether or not all the display columns are in a stopped state, based on the result of the operation sum operation obtained when the operation is completed.

  Further, in the third gaming machine of the present invention, a part of the address that can be designated by the extension register may be a higher-order address value that constitutes the address.

  In order to solve the second problem, the present invention provides a fourth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation of the internal winning combination by the internal winning combination determination means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
A dedicated register for storing data when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) that can specify a part of an address in the first storage means or the second storage means by the stored data ) And
The internal winning combination determined by the internal winning combination determining means includes an internal winning combination for each setting, in which a winning probability is changed according to a set value for adjusting an expected value for determining an internal winning combination related to awarding. Is provided,
The arithmetic processing means,
In the process of determining the internal winning combination,
By setting a predetermined addition instruction (for example, "ADDQ" instruction) capable of addressing in the second storage means using the extension register, the setting of the internal winning combination for each setting to be a lottery target The current setting value is added to the top address of the area where the lottery value for each value is stored, and the address where the lottery value of the internal winning combination for each setting associated with the current setting value is stored is specified, A gaming machine characterized by acquiring the lottery value.

  Further, in the fourth gaming machine of the present invention, a part of the address that can be designated by the extension register may be an upper-order side address value forming the address.

  In order to solve the second problem, the present invention provides a fifth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When the variable display of the plurality of display columns is stopped by the stop control means, on the determination line set across the plurality of display columns, a symbol corresponding to the internal winning combination relating to the payout of the game medium. And a bonus grant determination means (for example, a prize search process) for determining whether or not the combination of
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the privilege granting determination means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means,
The arithmetic processing means,
In the process of determining whether or not a combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
By executing a predetermined read command (for example, “LDIN” command), the game that can be given when a combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line. The data of the number of payouts of the medium and the determination data indicating the type of the combination of the symbols corresponding to the internal winning combination relating to the payout of the game medium, which are associated with the data of the number of payouts, are simultaneously acquired. A gaming machine.

Further, in the fifth gaming machine of the present invention, the arithmetic processing means is
In the process of determining whether or not a combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
A determination command, a process jump destination address designation command, and a process jump operation command are executed by executing a predetermined determination command (for example, a "JSLAA" command), and the inside relating to the payout of the game medium is executed. It may be determined whether or not a combination of symbols corresponding to a winning combination is stopped and displayed.

  According to the second to fifth gaming machines of the present invention having the above-described configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced, and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by increasing the free space of the ROM for the increased capacity.

[Sixth and seventh gaming machines]
Conventionally, in the gaming machine having the above-mentioned configuration, when an abnormality occurs in the data stored in the RAM of the main control unit, it is controlled to the RAM abnormality error state, the progress of the game is disabled, and the setting change mode is set. When a set value is newly selected and set based on a setting change operation, a gaming machine is proposed in which the disabled state of the game progress is released and the game progress is made possible. See, for example, JP 2007-209810A.

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the third problem described above, and a third object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the third problem, the present invention provides a sixth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Data transmission means for transmitting command data relating to the game operation (for example, S904 during interrupt processing (communication data transmission processing)),
Setting change confirmation means (for example, setting change confirmation processing) capable of executing setting value change processing and setting value confirmation processing for adjusting the expected value for determining the internal winning combination related to award,
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the change operation or the confirmation operation of the set value by the setting change confirmation means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
Start-time command generating means for generating first command data at the start of the setting value changing process or the setting value confirming process (for example, S43 during setting change confirming process),
An end-time command generation unit (for example, S57 during setting change confirmation processing) that generates second command data at the end of the setting value change processing or the setting value confirmation processing,
The generation processing of the first command data executed by the start time command generation means and the generation processing of the second command data executed by the end time command generation means are shared. Characteristic gaming machine.

Further, in the sixth gaming machine of the present invention, the arithmetic processing means has a general-purpose register for storing data when the arithmetic processing is executed by the arithmetic processing means,
The arithmetic processing means,
When generating the first command data, a first value (for example, “005H”) is set in a predetermined register (for example, L register) of the general-purpose register, and the generation process is executed,
When generating the second command data, a second value (for example, “004H”) may be set in a predetermined register of the general-purpose register and the generation process may be executed.

  In order to solve the third problem, the present invention provides a seventh gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Data transmission means for transmitting command data relating to the game operation (for example, S904 during interrupt processing (communication data transmission processing)),
Communication data generation means for generating the command data (for example, setting change command generation / storage processing and communication data storage processing),
Setting change confirmation means (for example, setting change confirmation processing) capable of executing setting value change processing and setting value confirmation processing for adjusting the expected value for determining the internal winning combination related to award,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the command data generation operation by the communication data generation means and the setting value change operation or confirmation operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
Start-time command generation means for generating start-time command data at the start of the setting value change processing or the setting value confirmation processing (for example, S43 during setting change confirmation processing),
When the setting value changing process or the setting value confirming process is completed, an end time command generating unit (for example, S57 during the setting change confirming process) that generates end time command data is provided,
The generation processing of the start time command data executed by the start time command generation means and the generation processing of the end time command data executed by the end time command generation means are shared.
The arithmetic processing means has a plurality of general-purpose registers in which a plurality of types of data are respectively stored when the arithmetic processing is executed by the arithmetic processing means,
The arithmetic processing means,
In the process of generating the command data,
Of the plurality of types of communication parameters forming the command data, the communication parameters used are set in the corresponding general-purpose registers of the plurality of general-purpose registers,
The communication parameters used in the general-purpose register are stored in a predetermined storage area (for example, communication data temporary storage area) in the second storage means,
If there is an unused communication parameter among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the command data is generated is used as the communication parameter. Stored in the storage area of
A gaming machine, wherein a sum value of the command data is generated based on data stored in the general-purpose register associated with a communication parameter.

  Also, in the seventh gaming machine of the present invention, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. By doing so, a sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

  According to the sixth and seventh gaming machines of the present invention having the above structure, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity The playability can be improved by utilizing the empty area of the minute ROM.

[Eighth and ninth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that transmits a command from the gaming control board (main control circuit) to the effect control board (sub control circuit) (for example, see JP-A-2002-360766). ).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above-mentioned fourth problem, and a fourth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the fourth problem, the present invention provides an eighth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Data transmission means for transmitting communication data relating to the game operation (for example, S904 (communication data transmission processing) during interrupt processing),
Communication data generation and storage means (for example, communication data storage processing and communication) that creates the communication data and stores the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means. Data pointer update processing),
The communication data generating and storing means is
When sequentially storing the communication data in the communication data storage area from the storage area of the first address to the storage area of the last address in the predetermined address range, an update instruction, an upper limit determination instruction and a determination branch instruction are By executing a predetermined update command (eg, “ICPLD” command) that can be executed by one command, the current value of the communication data pointer, which is a parameter relating to addressing in the communication data storage area, and the last address. While comparing the upper limit value of the communication data pointer corresponding to, if the current communication data pointer is less than the upper limit value, the communication data pointer is added and updated, the current communication data pointer is the upper limit value. If the above is satisfied, the communication data pointer is located below the communication data pointer corresponding to the start address. Gaming machine and changing the value.

  Further, in the eighth gaming machine of the present invention, the communication data generation / storage means, when the communication data pointer is changed to a lower limit value of the communication data pointer corresponding to the start address, the communication data storage area You may make it invalidate the said communication data stored in.

  Further, in order to solve the fourth problem, the present invention provides a ninth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
In the counting process of the value of the predetermined data related to the progress of the game operation (for example, the medal payout number check process),
When updating the value of the predetermined data, by executing a predetermined update instruction (for example, “DCPLD” instruction) capable of executing the update instruction, the lower limit determination instruction, and the judgment branch instruction with one instruction, The value of the predetermined data is compared with the lower limit of the value of the predetermined data, and if the current value of the predetermined data is larger than the lower limit of the value of the predetermined data, the value of the predetermined data Is subtracted and updated, and if the current value of the predetermined data is less than or equal to the lower limit value of the value of the predetermined data, the value of the predetermined data is held at the lower limit value.

  Further, in the ninth gaming machine of the present invention, the predetermined data may be a payout number of the game medium.

  According to the eighth and ninth gaming machines of the present invention having the above configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by increasing the free space of the ROM for the increased capacity.

[Tenth game machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine controlled by a timer subtraction process by software is known (see, for example, Japanese Patent Laid-Open No. 2004-041261).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the fifth problem described above, and a fifth object of the present invention is to reduce the capacity of a processing program or a table managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the fifth problem, the present invention provides a tenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
In the counting process of the number of timers of the soft timer (for example, the timer updating process),
By executing a predetermined update command (for example, a "DCPWLD" command) capable of executing the update command, the lower limit determination command, and the determination branch command with one command, the current timer number of the soft timer and the lower limit of the timer number If the current number of timers of the soft timer is greater than the lower limit value, the number of soft timers is subtracted and updated, and if the current number of soft timers is less than or equal to the lower limit value. The gaming machine is characterized by holding the number of timers of the soft timer at the lower limit value.

  In the tenth gaming machine of the present invention, the soft timer may be a 2-byte soft timer.

Further, in the tenth gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt processing repeatedly executed at a 1.1172 msec cycle) for performing a processing at a constant cycle,
The counting process of the number of timers by the soft timer is implemented by the fixed cycle processing means,
The elapsed time of the soft timer may be determined based on the cycle in which the fixed cycle processing means performs processing and the number of timers.

  Further, in the tenth gaming machine of the present invention, the processing by the fixed cycle processing means is executed based on an interrupt signal generated by a timer function (for example, timer circuit 113) built in the arithmetic processing means. You may do it.

  According to the tenth gaming machine of the present invention having the above structure, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, It is possible to provide a game machine capable of enhancing the game playability by utilizing the free space of the ROM for the increased capacity.

[Eleventh and twelfth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that displays an internal lottery result with a 7-segment LED by the control of a main control circuit (see, for example, Japanese Patent Laid-Open No. 2008-237337).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the sixth problem described above, and a sixth object of the present invention is to reduce the capacity of a processing program or a table managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the sixth problem, the present invention provides an eleventh gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
Multiple 7-segment LEDs that notify specific information about the game,
7-segment LED driving means (for example, 7-segment LED driving processing) for driving the plurality of 7-segment LEDs,
LED drive control means for controlling drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The LED drive control means,
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, "LDW" command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by:

Further, in the eleventh gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt processing repeatedly executed at a 1.1172 msec cycle) for performing processing at a constant cycle,
The fixed cycle processing means counts the number of executions of processing by the fixed cycle processing means,
The control process by the LED drive control means may be executed when the counted value is an even number.

  In order to solve the sixth problem, the present invention provides a twelfth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
An instruction indicator (for example, an instruction monitor) including a plurality of 7-segment LEDs that informs information regarding the stop operation of the variable display of the plurality of display columns,
7-segment LED driving means (for example, 7-segment LED driving processing) for driving the plurality of 7-segment LEDs,
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, "LDW" command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by:

Further, in the twelfth gaming machine of the present invention, the arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) capable of designating a part of an address in the second storage means by the stored data,
In the second storage means, the arithmetic processing means executes a predetermined read instruction (for example, “LDQ” instruction) capable of addressing in the second storage means using the extension register. The address of the stop operation instruction information storage area (for example, the navigation data storage area) that is arranged in the storage area and stores the information regarding the stop operation of the variable display of the plurality of display columns is specified, and the variable display of the plurality of display columns is displayed. Information about the stop operation may be stored in the stop operation instruction information storage area.

  According to the eleventh and twelfth gaming machines of the present invention having the above-described configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced, and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by increasing the free space of the ROM for the increased capacity.

[Thirteenth gaming machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine in which a gaming control board (main control board) controls a reel unit is known (for example, see JP 2012-034914A).

  By the way, in the rotation control of the reel (revolving cylinder), lack of a sense of stability of the rotation operation of the reel causes discomfort to the player (especially skilled person), and there is a possibility that the interest of the game is reduced from the discomfort. There is. In this case, it is disadvantageous to the game shop and may affect the sales of the game machine itself.

  The present invention has been made to solve the above-mentioned seventh problem, and a seventh object of the present invention is to suppress a lack of sense of stability in the rotation operation of the reel and not to give a player uncomfortable feeling. It is to provide a gaming machine capable of doing so.

  In order to solve the seventh problem, the present invention provides a thirteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A setting switch (for example, a setting key type switch 54) for initializing a predetermined area of the second storage means,
The arithmetic processing means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When the power is restored, the input state of the input port and the output state of the output port at the time of power failure are set, and when the display row is fluctuating at the time of power failure, it is stored in the second storage means. Clear the fluctuation control management information (for example, reel control management information) of the display row at the time of power interruption, and set the information for instructing the fluctuation start of the display row to the fluctuation control management information of the display row. A means (for example, a game returning process), and a gaming machine.

Further, in the thirteenth gaming machine of the present invention, the arithmetic processing means is
When the setting switch is in the off state, the processing by the game returning means is executed,
When the setting switch is in the ON state, a predetermined area of the second storage means may be initialized without executing the processing by the game returning means.

  According to the thirteenth gaming machine of the present invention having the above-described configuration, it is possible to suppress lack of sense of stability in the reel rotation operation (variable display operation of the display row) and prevent the player from feeling uncomfortable. ..

[14th Gaming Machine]
Conventionally, in the gaming machine having the above-mentioned configuration, there is known a gaming machine capable of displaying a set value (1 to 6) by operating a setting change switch (for example, Japanese Patent Laid-Open No. 2008-245704 and Japanese Patent Laid-Open No. 2008-245704). (See JP 2013-042870 A).

  By the way, conventionally, a gaming machine in which a set value cannot be confirmed is mainly used while a game is being played in a gaming state advantageous to a player, for example, during a bonus game or an ART game. In such a gaming machine, if a bonus game or an ART game is started immediately after a fraudulent act called "goto", the fraudulent act cannot be confirmed, and there is a possibility that it may be disadvantageous to a game shop. is there.

  The present invention has been made to solve the above-mentioned eighth problem, and an eighth object of the present invention is to provide a game in a game state advantageous to a player, An object is to provide a gaming machine capable of confirming information such as set values and suppressing fraudulent acts such as goto.

  In order to solve the eighth problem, the present invention provides a fourteenth gaming machine having the following configuration.

A setting switch arranged at a predetermined position inside the gaming machine main body,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Based on the internal winning combination determined by the internal winning combination determining means, advantageous game means (for example, a bonus game described later) for executing a game state advantageous to the player,
A setting change confirming means (for example, S233 during medal acceptance / start check processing) capable of changing or confirming a set value relating to the probability that an internal winning combination is determined according to the operation of the setting switch;
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
A game start determining means (for example, medal acceptance / start check processing) for determining whether or not the game can be started,
The setting change confirmation means is capable of changing a set value relating to the probability that an internal winning combination is determined in response to the operation of the setting switch when the power is turned on,
When the game start determination means determines that the game can be started and the setting switch is operated, the setting change confirmation of the setting value related to the probability that the internal winning combination is determined is confirmed regardless of the game state. A gaming machine characterized in that it can be confirmed by processing by means.

  Further, in the fourteenth gaming machine of the present invention, the setting change confirmation means, when the gaming machine is powered on with the setting switch operated, a predetermined storage area of the second storage means. May be initialized, the setting value may be changed, and the changed setting value may be stored in the second storage unit.

  According to the fourteenth gaming machine of the present invention having the above-mentioned configuration, set values and the like are set even during the game being played in a game state advantageous to the player, such as during bonus game and ART game. The information can be confirmed and fraudulent acts such as goto can be suppressed.

[15th and 16th gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine provided with a display device for displaying the number of inserted medals (see, for example, Japanese Unexamined Patent Publication No. 1999-178983).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above-mentioned ninth problem, and a ninth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the ninth problem, the present invention provides a fifteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
A game medium detecting means (for example, a medal sensor) for detecting a reception state of the game medium (for example, a medal sensor input state);
Whether or not the current change state of the acceptance state of the game medium detected by the game medium detection means is normal is determined by arithmetic processing based on the acceptance state of the game medium detected in the previous process. A game machine including a game medium acceptance state determination means (for example, S255 to S258 during the medal insertion check process).

  In the fifteenth gaming machine of the present invention, the game medium acceptance state determination means is a normal value of the acceptance state of the game medium that can be detected in the current process based on the acceptance state of the game medium detected in the previous process. May be calculated by a logical operation, and the normal value may be compared with the current acceptance state of the game medium to determine whether or not the change state of the acceptance state of the game medium is normal. ..

  Further, in the fifteenth gaming machine of the present invention, the game medium acceptance state determination means determines whether or not the change state of the acceptance state of the game medium is normal, based on 2 bits in 1-byte information. You may do it.

  In order to solve the ninth problem, the present invention provides a sixteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) for determining an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
Stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Display means (for example, a first LED to a third LED) for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media,
Arithmetic processing means (for example, main CPU 101, medal insertion processing) for performing arithmetic processing for controlling the notification operation by the display means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing means,
Lighting control data for notifying information indicating the number of loaded game media in a display mode corresponding to the number of loaded game media is generated by a logical operation process based on the number of loaded game media. A gaming machine.

  Further, in the sixteenth gaming machine of the present invention, in the logical operation processing, the lighting control data of the gaming medium may be generated from 3-bit data of information within 1 byte.

  According to the fifteenth and sixteenth gaming machines of the present invention having the above-mentioned configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the increased capacity The playability can be improved by utilizing the empty area of the minute ROM.

[17th and 18th gaming machines]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine is known in which a main board (main control board) and a sub board (sub control board) are connected by communication, and a command is transmitted from the main board to the sub board. (See, for example, Japanese Patent No. 5725590).

  By the way, conventionally, the communication between the main control board that controls the game and the sub control board that controls the production is one-way communication from the main control board to the sub control board. There is a large gap between the start-up time of the main control board and that of the sub-control board. Therefore, the communication connection between the main control board and the sub control board may become unstable when the power is turned on.

  The present invention has been made to solve the above tenth problem, and a tenth object of the present invention is to provide a main control board (main control means) and a sub control board (sub control means) when the power is turned on. An object of the present invention is to provide a game machine capable of stably operating communication between them.

  In order to solve the tenth problem, the present invention provides a seventeenth gaming machine having the following configuration.

A main control means (for example, a main control circuit 90) for transmitting communication data relating to a game operation,
The main control means,
During the control processing by the main control means, the interrupt processing is executed at a predetermined cycle, and when there is no communication data regarding the game operation at the time of executing the interrupt processing, an interrupt processing execution means for transmitting a no-operation command (for example, , Interrupt processing),
And a power restoration process executing means (for example, power-on process) that executes a predetermined power restoration process when the power is restored.
The power restoration process executing means performs a process of waiting after the power restoration process starts until the interruption process can be executed by the interruption process executing means (for example, S7 and S8 during power-on process). Done,
The gaming machine, wherein the interrupt processing execution means executes the interrupt processing and transmits the no-operation command to the sub-control means at the end of the standby by the power recovery processing execution means.

Further, in the seventeenth gaming machine of the present invention, the main control means is
A timer circuit (for example, timer circuit 113) for measuring the predetermined period,
An interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for executing the interrupt process based on a time-out signal of the timer circuit,
The power recovery processing execution means,
After setting the initial setting for generating the timeout signal at the predetermined cycle in the timer circuit, a process of waiting until the interrupt process can be executed by the interrupt process execution means,
The end of the waiting may be determined based on whether or not the time-out signal of the timer circuit is generated.

  In order to solve the tenth problem, the present invention provides an eighteenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
Communication data generation means (for example, setting change command generation and storage processing and communication data storage processing) for generating command data relating to game operations,
During the control processing by the arithmetic processing means, interrupt processing is executed at a predetermined cycle, and when there is no command data related to the game operation at the time of executing the interrupt processing, an interrupt operation execution means (for example, a non-operation command is transmitted. , Interrupt processing),
Power restoration processing execution means for executing a predetermined power restoration processing when the power is restored (for example, power-on processing),
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The power restoration process executing means performs a process of waiting after the power restoration process starts until the interruption process can be executed by the interruption process executing means (for example, S7 and S8 during power-on process). Done,
The interrupt processing execution means executes the interrupt processing and transmits the no-operation command at the end of the standby by the power recovery processing execution means,
The arithmetic processing means,
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing is executed by the arithmetic processing means,
The command data includes a command type, a plurality of communication parameters, and a sum value,
A plurality of the communication parameters are respectively assigned to the plurality of general-purpose registers,
The communication data generating means,
After setting the communication parameter in the general-purpose register assigned to the communication parameter according to the command type of the command data, the communication parameter set in the general-purpose register is stored in a predetermined manner in the second storage means. Stored in an area (for example, communication data temporary storage area),
Even when there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is used as the communication parameter. Stored in the predetermined storage area as
A game machine characterized by generating a sum value of the command data based on the command type and the data stored in the general-purpose register assigned to the communication parameter.

In the eighteenth gaming machine of the present invention, a power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage is provided,
The arithmetic processing means,
If the state of the power supply voltage is not stable, wait until the state of the power supply voltage is stable,
The timer circuit, the serial communication circuit, and the random number circuit of the arithmetic processing means are initialized on condition that the state of the power supply voltage is stable, and then the predetermined area of the second storage means is used to 2 Check whether the storage means is normal,
The non-operation command may be transmitted on condition that the second storage unit is normal.

  According to the seventeenth and eighteenth gaming machines of the present invention having the above configuration, it is possible to stably operate the communication between the main control board and the sub control board when the power is turned on.

[19th and 20th gaming machines]
Conventionally, in the gaming machine having the above-mentioned configuration, based on the lottery result, for example, a gaming machine is known which executes a control called pull-in control of reel winning symbol and a control called kick-off control of reel winning symbol. (See, for example, JP-A-2002-219213).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Furthermore, in recent years, as the playability has become more complicated and the number of symbol combination patterns of winning combinations (winning combinations) has increased, the RAM capacity of the main control circuit has been squeezed, and the efficiency of the processing executed by the main control circuit is improved. Therefore, it is required to develop a technology capable of effectively utilizing the limited RAM capacity of the main control circuit.

  The present invention has been made to solve the eleventh problem described above, and an eleventh object of the present invention is to improve the efficiency of the processing executed by the main control circuit and make the RAM capacity of the main control circuit effective. It is to provide a game machine that can be utilized.

  In order to solve the eleventh problem, the present invention provides a nineteenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing means,
An internal lottery means (for example, an internal lottery process) for determining flag status information (for example, a hit request flag status) regarding an internal winning combination with a predetermined probability,
An internal winning combination generating means for generating an internal winning combination from the flag status information acquired by the internal lottery means (for example, S321 in the symbol setting process),
A flag that defines a correspondence relationship between the internal winning combination, flag data corresponding to the internal winning combination, and storage destination data that specifies a storage destination of the flag data in the second storage unit, and is stored in the first storage unit. A flag table expanding unit (for example, S324 during the symbol setting process) for expanding a data table (for example, a hit request flag table) in the second storage unit,
Flag storage area designating means (for example, S329 in the symbol setting process) for designating an address of a flag data storage area (for example, hit request flag storage area) arranged in the second storage means and storing the flag data. ,
Flag data for transferring and storing the flag data corresponding to the internal winning combination generated by the internal winning combination generating means from the flag table into the flag data storage area based on the corresponding storage destination data. A storage device (for example, S330 during the symbol setting process), and a gaming machine.

  Further, in the nineteenth gaming machine of the present invention, the arithmetic processing means calculates on-bit information indicating the storage destination data of the flag data table, and is set to the on-bit information to be transferred. The flag data stored may be transferred to the flag data storage area.

  In order to solve the eleventh problem, the present invention provides a twentieth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data )When,
An internal lottery means (for example, an internal lottery process) for determining flag status information (for example, a hit request flag status) regarding an internal winning combination with a predetermined probability,
An internal winning combination generating means for generating an internal winning combination from the flag status information acquired by the internal lottery means (for example, S321 in the symbol setting process),
A winning flag data table (for example, a winning request) that defines a correspondence relationship between the internal winning combination, the corresponding winning flag data, and the storage destination data that specifies the storage destination of the winning flag data in the second storage means. A winning flag table expanding means (for example, S324 during the symbol setting process) for expanding the flag table) into the second storage means,
By executing a predetermined read instruction (eg, "LDQ" instruction) capable of addressing in the second storage means by using the extension register, the read instruction is placed in the second storage means and the winning is performed. A winning flag storage area designating unit (eg, S329 in the symbol setting process) for designating an address of a winning flag data storage area (for example, a hit request flag storage area) for storing flag data,
Based on the corresponding storage location data, the winning flag data corresponding to the internal winning combination generated by the internal winning combination generating means is transferred from the winning flag table to the winning flag data storage area and stored therein. With a winning flag data storage means (for example, S330 during the symbol setting process),
Based on the determination result of the internal lottery means and the detection of the stop operation by the stop operation detection means, stop control means (for example, reel stop control processing) for stopping the variable display of the symbols,
When the variable display of the plurality of display columns is stopped by the stop control means, a combination of symbols corresponding to the internal winning combination is stopped and displayed on the determination line set across the plurality of display columns. A winning combination determining means (for example, a winning search process) for determining whether or not
A prize flag data storage area (eg, a prize flag data storage area for storing prize flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined read command) A prize flag storage area designating means for designating an address of the winning operation flag storage area (for example, S648 during the symbol code acquisition processing),
By executing the predetermined read command, the address of the symbol code storage area for storing the symbol code data corresponding to the symbol combination arranged in the second storage means and stopped and displayed on the determination line is designated. And a symbol code storage area setting means (for example, S650 during the symbol code acquisition process), and a gaming machine.

  Further, in the twentieth gaming machine of the present invention, a part of the addresses that can be designated by the extension register may be an upper-order side address value forming the address.

  According to the nineteenth and twentieth gaming machines of the present invention having the above structure, it is possible to improve the efficiency of the processing executed by the main control circuit and effectively utilize the RAM (second storage means) capacity of the main control circuit. ..

[Twenty-first and twenty-second gaming machines]
Conventionally, in the gaming machine having the above-mentioned configuration, the stop control of the variable display of the reel symbol is performed based on the internal winning combination and the stop operation of the player, the winning combination is determined by the combination of the symbols, and the hopper is based on the result of the winning determination. There is known a gaming machine that controls a (medal payout device) to control the payout of medals (for example, see Japanese Patent Laid-Open No. 2008-19498).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above twelfth problem, and a twelfth object of the present invention is to reduce the capacity of a processing program, a table and the like managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the twelfth problem, the present invention provides a twenty-first gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
An extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and a part of the address in the second storage means can be designated by the stored data;
By executing a predetermined read command (for example, "LDQ" command) capable of addressing in the second storage means using the extension register, the detection result of the stop operation by the stop operation detection means is displayed. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired,
When the stop operation detecting means detects a stop operation of a player for a predetermined display row, the predetermined read command is executed to thereby arrange the second display means and the predetermined display row. Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139) for designating the address of the stop control data storage area for storing the variable display stop control data, A gaming machine characterized by having.

  Further, in the twenty-first gaming machine of the present invention, a part of the address that can be designated by the extension register may be a higher-order address value that constitutes the address.

  In order to solve the twelfth problem, the present invention provides a twenty-second gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) for determining an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
Stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if a combination of a plurality of types of symbols respectively corresponding to the plurality of types of internal winning combinations is set, the plurality of display columns are set. On the determined determination line, a priority stop symbol determination means (for example, attraction-in priority acquisition process) for determining a combination of symbols to be stopped and displayed with priority,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the stop operation of the display row by the stop control means, and the operation of determining the combination of symbols to be stopped and displayed by the priority stop symbol determining means.
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
An extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and a part of the address in the second storage means can be designated by the stored data;
By executing a predetermined read command (for example, "LDQ" command) capable of addressing in the second storage means using the extension register, the detection result of the stop operation by the stop operation detection means is displayed. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired,
When the stop operation detecting means detects a stop operation of the player with respect to a predetermined display row, the predetermined read command is executed to arrange the second display means in the second storage means and to display the predetermined display row. Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139) for designating the address of the stop control data storage area for storing the variable display stop control data,
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determination means, a comparison determination command, a jump destination address designation command of the process, and a jump operation command of the process By executing a predetermined determination command (for example, “JCP” command) that can be executed by a command, a combination of symbols corresponding to the internal winning combination to be determined is a specific display string currently being determined (for example, , The right reel 3R) determines whether or not a predetermined symbol combination (for example, "ANY" combination) in which the stop symbol on the determination line on the determination line is arbitrary is included in the internal winning combination to be determined. When it is determined that the predetermined symbol combination is included in the corresponding symbol combination, the stop display of the symbol combination corresponding to the internal winning combination to be determined is displayed. Gaming machine, characterized in that it comprises any combination corresponding processing means for locking (e.g., S683 in attraction priority acquisition processing), the.

  Further, in the twenty-second game machine of the present invention, a part of the address that can be designated by the extension register may be an upper-order side address value forming the address.

  According to the twenty-first and twenty-second gaming machines of the present invention having the above-described configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the increased capacity The playability can be improved by utilizing the empty area of the minute ROM.

[23rd to 25th gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that performs the stop control of the symbols by using the pull-in priority table during the stop control of the symbols (see, for example, JP-A-2007-175450).

  By the way, conventionally, as a restriction peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game play, and it is required to reduce the capacity of processing programs and tables managed by the main control circuit.

  The present invention has been made to solve the above thirteenth problem, and a thirteenth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM and utilizing the free area of the ROM for the increased capacity to improve the game playability.

  In order to solve the thirteenth problem, the present invention provides a twenty-third gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if a combination of symbols of a plurality of types corresponding to each of the plurality of types of internal winning combinations, it is set across the plurality of display columns On the determined determination line, priority stop symbol determination means (for example, attraction-in priority acquisition process) for determining the combination of symbols to be stopped and displayed with priority,
An arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the operation of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) capable of designating a part of the address in the second storage means by the stored data is included. ,
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determination means,
The arithmetic processing means,
Is located in the second storage means and is internal to the second storage means by executing a predetermined read instruction (eg, an "LDQ" instruction) capable of addressing in the second storage means using the extension register. A winning flag storage area designating unit (eg, S686 during acquisition priority order acquisition processing) for designating an address of a winning flag data storage area (for example, a winning request flag storage area) for storing winning flag data corresponding to a winning combination;
A prize flag data storage area (eg, a prize flag data storage area for storing prize flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined read command) A winning flag storage area designating means for designating an address of a winning operation flag storage area (for example, S686 during attraction priority acquisition processing),
A gaming machine, comprising: a logical product calculating means (for example, S686 in the attraction priority acquisition process) that performs a logical product operation of the winning flag data and the corresponding winning flag data.

In the twenty-third gaming machine of the present invention, the priority stop symbol determination means determines a combination of symbols to be stopped and displayed with priority, in the process of determining a combination of symbols corresponding to the internal winning combination to be determined. In the case where a combination of predetermined symbols (for example, “ANY” combination) that makes the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined to be arbitrary is included in
The arithmetic processing means includes an addressing process for the winning flag data storage area by the winning flag storage area designating means, an addressing processing for the winning flag data storage area by the winning flag storage area designating means, and the AND operation. The logical product arithmetic processing by the means may not be executed.

  In order to solve the thirteenth problem, the present invention provides a twenty-fourth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if a combination of symbols of a plurality of types corresponding to each of the plurality of types of internal winning combinations, it is set across the plurality of display columns On the determined determination line, priority stop symbol determination means (for example, attraction-in priority acquisition process) for determining the combination of symbols to be stopped and displayed with priority,
An arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the operation of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) that can specify a part of an address in the first storage means or the second storage means by the stored data ) And
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determination means,
The arithmetic processing means,
Is located in the second storage means and is internal to the second storage means by executing a predetermined read instruction (eg, an "LDQ" instruction) capable of addressing in the second storage means using the extension register. A winning flag storage area designating unit (eg, S686 during acquisition priority order acquisition processing) for designating an address of a winning flag data storage area (for example, a winning request flag storage area) for storing winning flag data corresponding to a winning combination;
A prize flag data storage area (eg, a prize flag data storage area for storing prize flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined read command) A winning flag storage area designating means for designating an address of a winning operation flag storage area (for example, S686 during attraction priority acquisition processing),
A logical product calculation means for performing a logical product calculation of the winning flag data and the corresponding winning flag data (for example, S686 during the attraction priority acquisition process),
By executing the predetermined read command, priority order data table acquisition means (for example, attraction priority order) that acquires a data table that defines the priority order of the combination of symbols to be stopped and displayed among the combinations of the plurality of types of symbols. S687) during the acquisition process, and a gaming machine.

Further, in the twenty-fourth gaming machine of the present invention, in the process of determining the combination of symbols to be stopped and displayed by priority by the priority stop symbol determination means, a combination of symbols corresponding to the internal winning combination to be determined. In the case where a combination of predetermined symbols (for example, “ANY” combination) that makes the stop symbol on the determination line in a specific display column (for example, right reel 3R) currently being determined to be arbitrary is included in
The arithmetic processing means includes addressing processing of the winning flag data storage area by the winning flag storage area designating means, addressing processing of the winning flag data storage area by the winning flag storage area designating means, and the logical product operation. The logical product arithmetic processing by the means may not be executed.

  In order to solve the thirteenth problem, the present invention provides a twenty-fifth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) for determining an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
Stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
Error detection means for determining whether or not an illegal hit error has occurred (for example, illegal hit check processing),
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the error detecting means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing means,
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means;
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an extension register (for example, a Q register) capable of designating a part of the address in the second storage means by the stored data is included. ,
In the determination process of whether or not an illegal hit error has occurred by the error detection means,
The arithmetic processing means,
A plurality of the plurality of storage units arranged in the second storage unit by executing a predetermined read command (for example, “LDQ” command) capable of addressing in the second storage unit by using the extension register. The winning flag that specifies the address of the winning flag data storage area (for example, the winning operation flag storage area) that stores the winning flag data corresponding to the combination of symbols stopped and displayed on the determination line set across the display columns Storage area designation means (for example, S781 during illegal hit check processing),
Logical product calculation means for performing a logical product calculation of the winning flag data stored in the winning flag data storage area and the corresponding winning flag data indicating the internal winning combination (for example, S784 during illegal hit check processing). When,
An error determination unit (for example, S785 during illegal hit check processing) for determining whether or not an illegal hit error has occurred based on the calculation result by the logical product calculation unit,
The gaming machine is characterized in that a winning flag data storage area (for example, a hit request flag storing area) in which the winning flag data is stored is the same as the winning flag data storing area.

  Further, in the twenty-fifth gaming machine of the present invention, a part of the address that can be designated by the extension register may be an upper-side address value that constitutes the address.

Further, in the twenty-fifth gaming machine of the present invention, the arithmetic processing means has an error processing means for performing error processing when the error detection means determines that there is an illegal hit error,
The error processing means may visually notify the illegal hit error, and may stop the game until the illegal hit error is released.

  According to the twenty-third to twenty-fifth gaming machines of the present invention having the above configuration, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the increased capacity The playability can be improved by utilizing the empty area of the minute ROM.

[Twenty-sixth gaming machine]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that transmits command data from a gaming control board (main control board) to a production control board (sub control board) (for example, JP 2013-027655A). And Japanese Patent Laid-Open No. 2014-033751).

  By the way, in recent years, with the diversification of playability, there is a tendency that the processing relating to playability increases in the effect control by the sub control circuit. Therefore, a fraudulent act called "goto" that alters the communication data transmitted from the main control circuit to the sub control circuit has occurred, causing damage to the amusement arcade. On the other hand, conventionally, as proposed in, for example, Japanese Unexamined Patent Application Publication No. 2014-033751, the main control circuit also implements a measure for performing got prevention processing on transmission data. However, the addition of such a got prevention process causes a problem that the program capacity of the main control circuit is pressed.

  The present invention has been made to solve the fourteenth problem described above, and a fourteenth object of the present invention is to prevent fraudulent acts without performing fraudulent (goto) prevention processing on transmission data, and It is an object of the present invention to provide a gaming machine capable of eliminating pressure on the program capacity of the main control circuit due to fraud prevention processing.

  In order to solve the fourteenth problem, the present invention provides a twenty sixth gaming machine having the following configuration.

Data transmission means (for example, main control circuit 90) for transmitting communication data relating to the game operation,
Communication data generation means for creating the communication data (for example, communication data storage processing),
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the operation of generating communication data by the communication data generating means,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
A second storage unit (for example, a main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing unit is stored,
The arithmetic processing means,
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing is executed by the arithmetic processing means,
The arithmetic processing means,
In the communication data generation processing by the communication data generation means,
A plurality of types of communication parameters constituting the communication data are respectively assigned to the plurality of general-purpose registers,
Of the plurality of types of communication parameters that make up the communication data, set the communication parameters based on the type of the communication data in the corresponding general-purpose registers of the plurality of general-purpose registers,
Storing the communication parameters set in the general-purpose register in a predetermined storage area (communication data temporary storage area) in the second storage means;
Of the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the communication data is generated is stored in the predetermined storage area as the communication parameter,
A game machine characterized by generating a sum value of the communication data based on data set in the plurality of general-purpose registers according to the plurality of kinds of communication parameters.

  Further, in the twenty-sixth gaming machine of the present invention, the communication data generation means, if there is no free space in a predetermined storage area in the second storage means, the communication set in the plurality of general-purpose registers. The communication data generation process may be terminated without storing the parameter in a predetermined storage area in the second storage means.

  According to the twenty-sixth gaming machine of the present invention having the above-described configuration, it is possible to suppress fraudulent acts without performing fraud prevention processing on transmission data (communication data), and program capacity of the main control circuit by fraud prevention processing. The pressure of can be eliminated.

[The 27th gaming machine]
Conventionally, in the gaming machine having the above-mentioned configuration, there is known a gaming machine having a function of updating the number of credits according to the number of medals paid out by the control of the main control circuit (for example, Japanese Patent Laid-Open No. 2009- 077797).

  By the way, conventionally, in a game during ART or bonus, the payout frequency of medals is high, but at this time, the payout interval for each medal is often controlled uniformly (constantly). In this case, useless waiting time occurs during the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes uselessly long, which may impose a mental burden on the player.

  The present invention has been made to solve the fifteenth problem described above, and a fifteenth object of the present invention is to reduce wasteful waiting time and reduce the mental burden on the player during the medal payout period. It is to provide a game machine capable of playing.

  In order to solve the fifteenth problem, the present invention provides a twenty-seventh gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium,
Start operation detecting means (for example, start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and that variably displays the symbols provided in each display row based on the detection of the start operation by the start operation detection means,
A stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player,
Based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, stop control means for stopping the variable display of the symbol (for example, reel stop control processing),
When the variable display of the plurality of display columns is stopped by the stop control means, on the determination line set across the plurality of display columns, a symbol corresponding to the internal winning combination relating to the payout of the game medium. And a bonus grant determination means (for example, a prize search process) for determining whether or not the combination of
When it is determined that the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line, the bonus medium determination means pays out the game medium (for example, game medium payout means). , Prize check / medal payout processing),
A game medium storing means (for example, a credit function) for storing the game medium,
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the payout operation of the game medium by the game medium payout means,
The arithmetic processing means,
It is determined by the privilege giving determination means that the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line, and the game medium stored in the game medium storing means. When the stored number of is less than the upper limit value, a game medium adding means for adding 1 to the stored number of the game medium (for example, S805 during winning check / medal payout processing),
After the game medium is added to the storage number of the game medium by the game medium adding means, the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is provided when the symbol is stopped and displayed. A payout end determination means for determining whether or not the total payout amount of the game medium has been completed (for example, S807 during prize check / medal payout processing),
When it is determined by the payout end determination means that the payout of the total number of payouts of the game medium is not completed, a weight generation means (for example, a winning check / S808) during the medal payout process, and a gaming machine.

Further, in the twenty-seventh gaming machine of the present invention, the arithmetic processing means has an interrupt processing execution means for executing interrupt processing at a predetermined cycle,
In the weight in which the operation relating to the game by the weight generating means is invalid, the interrupt processing by the interrupt processing executing means may be executed a predetermined number of times.

  According to the twenty-seventh gaming machine of the present invention having the above configuration, it is possible to reduce a wasteful waiting time and a mental burden on a player during a medal (game medium) payout period.

[28th and 29th gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine in which a lottery table for determining an internal winning combination and an AT game is stored in a ROM (see, for example, Japanese Patent Laid-Open No. 2009-125459).

  By the way, in the gaming machine described in Japanese Patent Laid-Open No. 2009-125459, the lottery table and lottery processing program of the AT game are stored in the ROM provided in the sub-control board, which has a sufficient storage capacity. However, for a reason peculiar to the recent gaming machine industry, it is necessary to store the table and the program related to the lottery of the AT game in the ROM provided on the main control board. Therefore, the ROM capacity of the main control board, which is limited to a small capacity, is pressed.

  The present invention has been made to solve the sixteenth problem described above, and a sixteenth object of the present invention is to reduce the amount of data used in the processing of the main control circuit and to make the ROM of the main control circuit free. An object is to provide a game machine capable of increasing the capacity.

  In order to solve the 16th problem, the present invention provides a 28th gaming machine having the following configuration.

Start operation detection means (for example, start switch 79) for detecting a start operation by the player,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Based on the internal winning combination determined by the internal winning combination determining means, a privilege giving determination means (eg, CT lottery processing during CT) for randomly determining whether or not to give a game state advantageous to the player as a privilege. When,
A lottery table (for example, a CT lottery table during CT) that is referred to by the privilege grant determination means,
In the lottery table,
Determination data (for example, a determination bit) that specifies the type of the internal winning combination that is a lottery target, and a lottery value of the internal winning combination that is a lottery target that is specified by the determination data are defined,
The lottery value of the internal winning combination that is not subject to the lottery is not specified,
A value other than 0 is defined for the lottery value of the internal winning combination of the lottery target whose winning probability is less than 100%, and 0 is defined for the lottery value of the internal winning combination of the lottery target whose winning probability is 100%. A gaming machine characterized by being used.

Further, in the twenty-eighth gaming machine of the present invention, the privilege grant determining means is
Obtain a 1-byte random number from the soft latch random number,
A lottery may be performed using the obtained random number value and the lottery value to determine whether or not to give a game state advantageous to the player as a privilege.

  In order to solve the sixteenth problem, the present invention provides a twenty ninth gaming machine having the following configuration.

Start operation detecting means (for example, a start switch 79) for detecting a start operation by the player,
An internal winning combination determining means (for example, an internal lottery process) for determining an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
Based on the internal winning combination determined by the internal winning combination determining means, a privilege giving determination means (eg, CT lottery processing during CT) for randomly determining whether or not to give a game state advantageous to the player as a privilege. When,
A lottery table (for example, a CT lottery table during CT) that is referred to by the privilege grant determination means and is provided for each type of the internal winning combination.
A lottery table selection table for selecting the lottery table associated with the currently determined internal winning combination (for example, a table selection relative table for each winning combination),
In the lottery table selection table,
For each type of the internal winning combination, it is possible to determine whether or not the internal winning combination of the type is a lottery target, and it is possible to specify an arrangement destination of the lottery table associated with the internal winning combination of the type. Selection value is defined,
The selection value of the internal winning combination that is not subject to the lottery is defined as 0, which treats the result of the lottery by the privilege grant determination means as a loss.
A game machine characterized in that data other than 0 is defined in the selection value of the internal winning combination that is a lottery target.

  Further, in the twenty-ninth gaming machine of the present invention, the selection value of the lottery table selection table is a relative value up to the lottery table to be selected, and the relative value may be a 1-byte value. Good.

  According to the twenty-eighth and twenty-ninth gaming machines of the present invention having the above configuration, it is possible to reduce the capacity of data used in the processing of the main control circuit and increase the free capacity of the ROM of the main control circuit.

[30th gaming machine]
Conventionally, in the gaming machine having the above-described configuration, the program and the table are arranged in predetermined areas in the ROM mounted on the main control board (see, for example, Japanese Unexamined Patent Publication No. 2012-110635).

  By the way, the programs and tables that can be arranged in the ROM of the main control board are limited by the rules of the game machine industry, such as the game machine described in JP 2012-110635A, and the ROM of the main control board is limited. The extensibility of programs and tables inside is extremely poor.

  The present invention has been made to solve the seventeenth problem described above, and a seventeenth object of the present invention is to provide a gaming machine capable of enhancing the expandability of programs and tables in the ROM of the main control board. Is to provide.

  In order to solve the seventeenth problem, the present invention provides a thirtieth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operations,
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
In the first storage means, a game storage area (for example, a game ROM area) in which information necessary for executing processing relating to the game playability of a game performed by a player is stored, and the game storage. A non-regular storage area (for example, a non-regular ROM area) that is arranged in an area different from the area and stores information necessary for executing a process that is not related to the playability of the game performed by the player is provided. A gaming machine characterized by being present.

  Further, in the thirty-seventh gaming machine of the present invention, for the game in which the second storage means temporarily stores information necessary for executing a process relating to the game playability of the game executed by the player. A game temporary storage area (for example, a game RAM area) including a work area and a game stack area, and a game property of a game which is arranged in an area different from the game temporary storage area and which is executed by the player. A non-regular temporary storage area (for example, a non-standard RAM area) including a non-standard work area and a non-standard stack area in which information necessary for execution of processing not related to Good.

Further, in the thirty-seventh gaming machine of the present invention, the arithmetic processing means has a stack pointer as a dedicated register,
The arithmetic processing means,
When executing the program stored in the non-specified storage area of the first storage means, the address of the non-specified stack area of the second storage means is set in the stack pointer,
When terminating the program stored in the non-regular storage area of the first storage means, the game of the second storage means saved when the program stored in the non-regular storage area is executed The address of the stack area may be set in the stack pointer and returned to the program stored in the game storage area of the first storage area.

  According to the thirtieth gaming machine of the present invention having the above structure, the expandability of the programs and tables in the ROM of the main control board can be improved.

[The 31st gaming machine]
Conventionally, in the gaming machine having the above-mentioned configuration, in order to use the information of the internal winning combination determined by the main control circuit in the production control of the sub-control circuit, the internal winning combination is converted into a sub-flag whose type is grouped together. A gaming machine having a function is known (see, for example, JP 2010-051471 A).

  In the gaming machine described in Japanese Patent Laid-Open No. 2010-051471, the conversion table for converting the internal winning combination into the sub-flag and the conversion processing program are stored in the ROM provided in the sub-control board with a sufficient storage capacity. Has been done. However, for reasons peculiar to the recent gaming machine industry, the information of the internal winning combination determined by the main control circuit cannot be transmitted to the sub control circuit, and the conversion table and conversion processing program related to the sub flag are also provided on the main control board. Need to be stored in ROM. In this case, the ROM capacity of the main control board, which is limited to a small capacity, is pressed by these tables and programs. Therefore, it is necessary to suppress the pressure on the ROM capacity of the main control board due to the conversion table related to the sub-flag and the conversion processing program, and to develop a technology capable of efficiently responding to changes in the game machine model, planning, specifications, etc. ing.

  The present invention has been made to solve the above-mentioned eighteenth problem, and an eighteenth object of the present invention is to suppress the pressure on the ROM capacity of the main control board and to make a model, a plan, and a specification of the gaming machine. It is an object of the present invention to provide a gaming machine capable of efficiently responding to changes such as.

  In order to solve the above eighteenth problem, the present invention provides a thirty-first gaming machine having the following configuration.

Start operation detecting means (for example, a start switch 79) for detecting a start operation by the player,
An internal winning combination determining means (for example, an internal lottery process) for determining an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means,
First sub-flag conversion means (for example, sub-flag conversion processing) for converting the internal winning combination determined by the internal winning combination determination means into a first sub-flag (for example, sub-flag) with reference to a conversion table,
The first sub-flag obtained by the conversion process by the first sub-flag conversion means is converted into a second sub-flag (for example, sub-flag EX) by lottery with reference to a lottery table (for example, various flag conversion lottery table). Second sub-flag conversion means (for example, flag conversion processing)
In the conversion table, a correspondence relationship between the internal winning combination, control status data associated with the internal winning combination, and the first sub-flag is defined, and for the first sub-flag of the same type, The control status data of the same value is assigned,
The lottery by the second sub-flag conversion means is performed based on the control status data.

Further, in the gaming machine of the present invention, a data transmission unit for transmitting command data relating to the game operation is provided,
The data transmitting unit may transmit the first sub-flag as a communication parameter of command data when the start operation detecting unit detects the start operation.

  According to the thirty-first gaming machine of the present invention having the above-described configuration, it is possible to suppress pressure on the ROM capacity of the main control board and efficiently respond to changes in the gaming machine model, planning, specifications, and the like.

  1 ... Pachi-slot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information display, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit, 200 ... Sub control circuit, 201 ... Sub CPU 201, 301 ... First interface board, 302 ... Second interface board

Claims (2)

Arithmetic processing means for performing arithmetic processing for controlling the game operation,
First storage means in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored,
Second storage means for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means has an interrupt processing means for executing processing at a fixed time cycle,
The arithmetic processing means,
In the counting process of the timer value of the 2-byte soft timer,
By executing a predetermined update instruction capable of executing the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer value of the soft timer and the lower limit value of the timer value are compared, and If the timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is less than or equal to the lower limit value, the timer value of the soft timer is changed. Hold at the lower limit,
After that, the update start address of the soft timer in the second storage means is updated by 2 bytes,
The counting process of the timer value executed by the arithmetic processing unit is one of the processes executed by the interrupt processing unit,
The interrupt processing means first executes the saving process of the register, executes the counting process of the timer value after executing the saving process, and outputs the signal to the outside of the gaming machine after executing the counting process of the timer value. An external signal output control process for generating a register is executed, a register return process is executed after the external signal output control process is executed, and the process is terminated immediately after the register return process is executed. Amusement machine. The first storage means has a first game area in which data relating to the progress of the game is stored, and a first non-regular area in which data not related to the progress of the game is stored.
The second storage means has a second game area for storing data relating to the progress of the game and a second non-regular area for storing data not relating to the progress of the game.
The interrupt processing means is stored in the first game area and executes processing using the second game area, but the external signal output control processing is performed in the first non-regulated area. The gaming machine according to claim 1, wherein the gaming machine is stored and executed using the second non-specified area.

Images