JP2020068505A - Code generation device and spread spectrum signal reception system - Google Patents

Abstract

To provide a code generation device and spread spectrum signal reception system applied therewith, capable of alleviating various types of loads concerning generation of an M sequence code.SOLUTION: The code generation device generates a phase register value as a code in a desired phase state by changing a phase state by an amount of a predetermined cycle with a phase of an M sequence code of an input signal as a phase state, and includes phase register calculation means for calculating a phase register value corresponding to a linear change factor of the M sequence code and phase register adjustment means for adjusting the phase register value, being mapped with a nonlinear change factor of the M sequence code.SELECTED DRAWING: Figure 1

Description

  The present invention provides code generation for generating a code (0 or 1) in a desired phase state in order to receive an M-sequence spread signal broadcast by a "Global Positioning System" (GPS: Global Positioning System) or the like. The present invention relates to a device and a spread spectrum signal receiving system to which the code generating device is applied.

  The L2C signal of GPS is spectrum-spread by the M series by the Galois linear feedback shift register, and the L6 signal of the Michibiki "Quasi-Zenith Satellite System" (QZSS) is a combination of the M series by the Fibonacci linear feedback shift register. The spectrum is spread by the Kasami series. In order to receive the L2C and L6 signals, it is necessary to set the proper phase register value in the code generator in the receiver. The L2C signal and the L6 signal can be received by multiplying the output of the code generator in which an appropriate phase register value is set and the received baseband signal (spread spectrum signal).

Patent No. 4453338 Patent No. 4806341 Patent No. 4510219

  However, conventionally, in order to calculate the phase register value set in the code generator, all the phase register values are stored in a ROM (Read Only Memory) or calculated by software, but the GPS L2C signal is used. The following two technical problems arise in order to receive a signal spread by a long-period M sequence such as the L6 signal of QZSS or QZSS.

  First, there is a technical problem that a large amount of ROM capacity is required to store all the long-period phase register values in the ROM. Second, there is a technical problem that a high-performance CPU (Central Processing Unit) capable of high-speed operation is required to calculate a long-period phase register value.

  Therefore, the present invention has been made in view of the above problems, and a code generation device capable of reducing various loads related to the generation of M-sequence codes and a spread spectrum signal reception system to which the code generation device is applied. The purpose is to provide.

  In order to solve the above problems, the invention according to claim 1 is a code of a desired phase state by changing the phase state by a predetermined cycle by setting the phase of the M-sequence code of the received signal as the phase state. A code generation device for generating a phase register value, comprising phase register calculation means for calculating a phase register value corresponding to a linear change factor of the M-sequence code, and corresponding to a non-linear change factor of the M-sequence code. Phase register adjusting means for adjusting the phase register value.

  According to a second aspect of the present invention, in the phase register adjusting means, when the M-sequence code is generated by a Galois linear feedback shift register and the Doppler shift amount corresponding to the nonlinear change factor is positive, a forward Galois The linear feedback shift register adjusts the phase register value, and when the Doppler shift amount is negative, the reciprocal Galois linear feedback shift register adjusts the phase register value.

  According to a third aspect of the present invention, in the phase register adjusting means, when the M-sequence code is generated by a Fibonacci linear feedback shift register and the Doppler shift amount according to the nonlinear change factor is positive, a forward Fibonacci is used. A linear feedback shift register adjusts the phase register value, and when the Doppler shift amount is negative, the phase register value is adjusted by a reciprocal Fibonacci linear feedback shift register.

  The invention according to claim 4 comprises the code generation device according to any one of claims 1 to 3, wherein the phase register value generated and output by the code generation device captures and tracks a spread spectrum signal from a satellite. It is a spread spectrum signal reception system characterized by being set in a code generator for.

  According to the first aspect of the present invention, the phase register calculating means and the phase register adjusting means are selectively used depending on the linear change factor and the non-linear change factor, so that a small-scale circuit configuration can be obtained for a long-period M-sequence code. Even a low-performance CPU can optimally calculate the phase register value without storing all the phase register values in the ROM. As a result, it is possible to reduce the ROM capacity and the CPU processing capacity.

  According to the second aspect of the present invention, both forward type and reciprocal type Galois linear feedback shift registers are provided. In particular, by providing the forward Galois linear feedback shift register, the phase register value can be adjusted by the Doppler shift amount changing in the positive direction. On the other hand, by providing the reciprocal Galois linear feedback shift register, the phase register value can be adjusted by the Doppler shift amount that changes in the negative direction. This makes it possible to more accurately distinguish Doppler shift amounts that change in both the positive and negative directions and adjust the phase register value more appropriately with a small calculation load.

  According to the third aspect of the present invention, both the forward type and the reciprocal type Fibonacci linear feedback shift registers are provided. In particular, by providing the forward type Fibonacci linear feedback shift register, the phase register value can be adjusted by the Doppler shift amount changing in the positive direction. On the other hand, by providing the reciprocal type Fibonacci linear feedback shift register, the phase register value can be adjusted by the Doppler shift amount that changes in the negative direction. This makes it possible to more accurately distinguish Doppler shift amounts that change in both the positive and negative directions and adjust the phase register value more appropriately with a small calculation load.

  According to the fourth aspect of the present invention, the phase register value generated and output by such a code generation device is applied to the code generation unit of the spread spectrum signal reception system and output from this code generation unit. By multiplying the spread spectrum code generated from the code by the spread spectrum signal from the satellite, it is possible to efficiently capture and track the spread spectrum signal.

It is a block diagram which shows typically the structure of the spread spectrum signal receiving system 1 which concerns on this embodiment. 6 is a timing chart showing an operation of calculating a phase register value by a combination of the phase register calculation circuit unit according to the present embodiment and the phase register adjustment processing unit. Blocks of four types (forward Galois, reciprocal (reverse) Galois, forward Fibonacci, and reciprocal (reverse) Fibonacci) linear feedback shift registers having r-stage (r-bit) shift registers according to the present embodiment It is a figure (Drawing 3 (a), Drawing 3 (b), Drawing 3 (c), and Drawing 3 (d)). Block diagrams (FIGS. 4A and 4B) of forward Galois and reciprocal Galois linear feedback shift registers having four-stage (4-bit) shift registers according to the present embodiment, and 5 is a table (FIGS. 4C and 4D) showing shifts (cycles) of states of respective registers in the forward Galois and reciprocal (reverse) Galois linear feedback shift registers. Block diagrams (FIGS. 5A and 5B) of a forward Fibonacci and a reciprocal (reverse) Fibonacci linear feedback shift register having a 4-stage (4-bit) shift register according to the present embodiment, and FIG. 6 is a table (FIG. 5 (c) and FIG. 5 (d)) showing shifts (cycles) of states of the forward type Fibonacci and reciprocal (reverse type) Fibonacci linear feedback shift registers.

<< Embodiment >>
<Structure of spread spectrum signal receiving system>
A spread spectrum signal receiving system 1 according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram schematically showing the configuration of the spread spectrum signal reception system 1 according to this embodiment.

  As shown in FIG. 1, the spread spectrum signal reception system 1 according to the present embodiment includes an antenna 2, a frequency conversion unit 3, an A / D conversion unit 4, a reception circuit unit 10, and a CPU unit 50. And is mounted in a vehicle (not shown) as a vehicle-mounted GPS receiving module.

  The CPU section 50 includes a reception processing section 60 and a phase register adjustment processing section 70. The CPU section 50 can be configured by software. Further, the code generation device 80 is configured to include a phase register calculation circuit unit 40 and a phase register adjustment processing unit 70. Specifically, the phase register calculation circuit unit 40 and the phase register adjustment processing unit 70 include a forward Galois, a reciprocal (reverse) Galois, a forward Fibonacci, and a reciprocal (reverse) Fibonacci linear feedback shift, which will be described later. Each is equipped with a register.

  Here, when the spread spectrum signal transmitted by radio from a satellite (not shown) is received by the antenna 2 of the spread spectrum signal receiving system 1, the frequency conversion unit 3 converts the spread spectrum signal into a signal of an intermediate frequency. The signal is down-converted and output to the A / D conversion unit 4, and the A / D conversion unit 4 converts the spread spectrum signal from an analog signal to a digital signal and outputs the digital signal to the reception circuit unit 10. Although the spread spectrum signal receiving system 1 includes the receiving circuit units 10 for a predetermined number of channels (usually 8 to 16 channels), only the receiving circuit unit 10 for one channel is shown in FIG. There is.

  When the spread spectrum signal is an L2C signal, the L2C signal superimposes a carrier of a predetermined frequency on a navigation message in the satellite, and further, a CM code (repeating cycle: 10230 bits / cycle) as a spreading code and It is a signal that has been spectrum-spread by a CL code (repeating cycle: 767250 bits / cycle). The CM code and CL code are code strings unique to each satellite and different from each other among the satellites, and a predetermined start position and end position are included in the M-sequence code string generated by each satellite. It is a code with the specified range between and. Therefore, when the spread spectrum signals are received by the antenna 2 from a plurality of satellites, the CM code and CL code of each satellite are generated by the 27-bit Galois linear feedback shift register, and the power of 2 27-1. In the M-sequence code string, different designated ranges are occupied.

  The reception circuit unit 10 includes a code generation unit 20 including a code generator 21 and a code generation NCO 22, a correlator 30, a carrier NCO 31, a carrier wave correlation unit 32, and a phase register calculation circuit unit 40. Has been done.

  The carrier NCO 31 generates a local carrier having the same frequency as the down-converted carrier and outputs this local carrier to the carrier correlation unit 32. The carrier wave correlation unit 32 multiplies the digital signal from the A / D conversion unit 4 by the local carrier from the carrier NCO 31 and outputs the baseband signal from which the down-converted carrier wave has been removed, to the correlator 30. The code generating NCO 22 outputs a clock signal of a predetermined frequency to the code generator 21.

  The code generator 21 generates a spreading code (hereinafter, also referred to as a spreading code) in phase with the CM code and the CL code in the baseband signal based on the clock signal from the code generating NCO 22, and causes the correlator 30 to generate the spreading code. Output. The correlator 30 multiplies the baseband signal from the carrier wave correlator 32 by the spread code from the code generator 21, and outputs the multiplication result to the CPU 50 as a correlation value.

  The CPU unit 50 functions as a positioning calculation control unit and outputs a local carrier control value (frequency and phase) for adjusting the local carrier to the carrier NCO 31 in order to capture and track a spread spectrum signal based on the correlation value. (Carrier phase tracking loop: PLL (Phase Locked Loop) control), and outputs a code control value (frequency and phase) for adjusting the spreading code generation timing to the code generating NCO 22 (code phase tracking loop: DLL (Delay). Locked Loop) control).

  The carrier NCO 31 outputs the local carrier to the carrier wave correlation unit 32 based on the local carrier control value so that the carrier wave and the local carrier are in phase synchronization. Further, the code generation NCO 22 outputs a clock signal to the code generator 21 based on the code control value so that the CM code and the CL code are in phase synchronization with the spread code.

  As a result, in the receiving circuit unit 10, the phase synchronization of the spread code with the CM code and the CL code and the phase synchronization of the local carrier with the carrier wave are respectively achieved, so that the spread spectrum signal can be captured and tracked. It will be possible. Further, the CPU unit 50 reads navigation data from the correlation value, and further, based on the carrier phase of each spread spectrum signal from a plurality of satellites, the Doppler frequency, and the pseudo distance from each satellite to the spread spectrum signal receiving system 1, the system. 1, the current position of the vehicle 1, the speed of a vehicle equipped with the system 1 as a vehicle-mounted GPS receiving module, and the current time can be obtained.

  Further, when the spread spectrum signal is captured and tracked, the CPU unit 50 has information relating to the CM code and CL code included in the spread spectrum signal (start and end positions of the CM code and CL code in the M sequence). An initial setting value including information related to the designated range and information indicating that the CM code or the CL code is located at a predetermined position within the designated range is generated by the code generation device 80 and output to the code generator 21. To do. Therefore, the code generator 21 generates a spread code synchronized with a predetermined position (phase) of the CM code and CL code included in the spread spectrum signal from the initial setting value and the clock signal, and outputs the spread code to the correlator 30.

  In the present embodiment, as the first feature, the target phase register value is calculated by combining the phase register calculation circuit unit 40 and the phase register adjustment processing unit 70. The change factors of the M-sequence code of the received signal are divided into (i) linear change factors due to passage of unit time and (ii) non-linear change factors due to acceleration or irregular movement of satellites (transmitters) and users (receivers). To be

  The phase register calculation circuit unit 40 is provided to deal with a linear change factor of the M-sequence code. On the other hand, the phase register adjustment processing unit 70 is provided to deal with the non-linear change factor of the M-sequence code.

  By selectively using the phase register calculation circuit unit 40 and the phase register adjustment processing unit 70 depending on the change factor, a small-scale circuit configuration and low-performance CPU for the long-period M series used for the L2C signal and the L6 signal However, it is possible to optimally calculate the phase register value.

In the present embodiment, as a second feature, in addition to (i) the phase register calculation circuit unit 40 that calculates the phase register value set in the code generator 21, (ii) the phase for finely adjusting the phase register value The register adjustment processing unit 70 is provided.
The phase register adjustment processing unit 70 is intended to adjust the phase register value by the Doppler shift amount (Doppler change amount) within a short time.

  Further, when the type of the M sequence is a GPS L2C signal, both forward type and reciprocal type Galois linear feedback shift registers (LFSRs) are used. On the other hand, when the M-sequence type is a QZSS L6 signal, both forward and reciprocal Fibonacci linear feedback shift registers are used.

By having both forward and reciprocal Galois and Fibonacci linear feedback shift registers, it is possible to adjust the phase register value by the amount of Doppler shift (the amount of Doppler change) that changes in both positive and negative directions. .
Specifically, when the type of the M-sequence is a GPS L2C signal, a forward Galois linear feedback shift register is provided, which makes it possible to adjust the phase register value by a Doppler shift amount that changes in the positive direction. On the other hand, by providing the reciprocal (reverse) Galois linear feedback shift register, it is possible to adjust the phase register value by the Doppler shift amount that changes in the negative direction.

  When the type of the M-sequence is an L6 signal of QZSS, by providing a forward type Fibonacci linear feedback shift register, it is possible to adjust the phase register value by the Doppler shift amount that changes in the positive direction. On the other hand, by providing the reciprocal (inverse) Fibonacci linear feedback shift register, it is possible to adjust the phase register value by the Doppler shift amount that changes in the negative direction.

  Supposing that the Doppler shift amounts in the positive and negative directions are not distinguished and the phase register values are obtained by the forward Galois and forward Fibonacci linear feedback shift registers, the Doppler shift amount corresponding to the nonlinear change factor is negative. At this time, the phase register value is obtained based on the forward Galois and forward Fibonacci linear feedback shift registers. Since the Doppler shift amount is negative, a predetermined number of cycles in which the cycles are advanced in the reverse direction are determined. However, in practice, the linear feedback shift register cannot advance in the backward cycle (because the backward shift of the shift direction from right shift to left shift does not give the correct result), so it falls into the predetermined number of cycles. The phase register value is obtained by advancing the cycle in the forward direction (plus direction) up to the position. For example, when the predetermined number of cycles determined based on the negative Doppler shift amount is a negative X (X is a natural number) cycle, the forward Galois linear feedback shift register advances in the reverse direction (negative direction) by X cycles. In order to obtain the desired phase register value, the forward Galois linear feedback shift register actually uses "-X modulo Z (Z is the maximum period of the M sequence, a natural number. Modulo is the minimum non-negative remainder. Defined modulo operation.) ”The desired phase register value can be obtained by advancing by a cycle. Here, assuming that X is 1, the maximum period Z of the 27-bit M sequence of the L2C signal is 134217727 (2 ^ 27-1), so in order to obtain the phase register value advanced by -1 cycle, actually 13421726 cycles are required. The calculation of the phase register value is required, and a large amount of the phase register values need to be calculated until the desired phase register value is obtained.

  On the other hand, in the present embodiment, when the Doppler shift amount is negative, the reciprocal Galois and reciprocal Fibonacci linear feedback shift registers are used instead of the forward Galois and forward Fibonacci linear feedback shift registers. As a result, when the predetermined number of cycles determined based on the negative Doppler shift amount is a negative X cycle, in the reciprocal Galois and reciprocal Fibonacci linear feedback shift registers, it is desired to advance X cycles forward. The phase register value of is obtained. In the case where X in the above example is set to 1, it is only necessary to obtain the phase register value advanced by one cycle. That is, it is possible to obtain a desired phase register value with a small amount of calculation in a small number of cycle steps of X cycles without storing all the phase register values in the ROM.

  As a result, it is possible to reduce the ROM capacity and the CPU processing capacity.

<Operating principle>
Next, with reference to FIG. 2, the operation principle of calculating the target phase register value by combining the phase register calculation circuit unit according to the present embodiment and the phase register adjustment processing unit will be described. FIG. 2 is a timing chart showing the operation of calculating the phase register value by the combination of the phase register calculation circuit unit according to the present embodiment and the phase register adjustment processing unit.

  As shown in FIG. 2, the processing that operates in the CPU unit 50 occurs at time UT (User Timing) 0, time UT1, time UT2, time UT3, and time UT4 at intervals of 4 ms (millisecond) along the flow of time. It is necessary to start the process triggered by an interrupt and finish the given process within the 4 ms interval until the next interrupt occurs.

  First, in the CPU unit 50, a calculation circuit setting process is performed from time UT0 to UT1 4 ms later. The calculation circuit setting process calculates and sets information necessary for operating the phase register calculation circuit unit 40. Specifically, the calculation circuit setting process sets a predetermined chip value in order for the phase register calculation circuit unit 40 to calculate a desired phase register value. In the example of FIG. 2, the predetermined chip value is the chip value at the UT3 timing. Since it is necessary to set the phase register value in the code generator 21 at the UT3 timing, the calculation circuit setting process is operated at the UT0 timing in advance to allow the phase register calculation circuit section 40 to calculate a desired phase register value. Issue instructions.

  In the specific example of FIG. 2, the predetermined chip value set in the phase register calculation circuit unit 40 by the calculation circuit setting process is the code chip value of the L2C signal at the UT3 timing of 6138 chips (6138 cycles from the predetermined start position of the M sequence). ). The chip value at the UT3 timing is 6138 chips because the chip rate of the L2C signal is 511.5K (chip per second), and 2046 chips (= 511.5K (chip per second) × 4 ms each time the time advances by 4 ms. ), It is calculated as 6138 chips (chip) (= 0 chip (chip of UT0 timing) + 511.5K (chip per second) × 12 ms (elapsed time of UT0 to UT3)).

  Here, the chip value is a cycle value starting from the start position (starting phase) in each code of the M series, and for example, 6138 chips of the L2C signal is a predetermined start of the CM code and CL code in the M series. In other words, the linear feedback shift register is advanced by 6138 cycles from the position.

  Next, the chip value corresponding to the linear change factor of the M-sequence code is input to the phase register calculation circuit unit 40 from the CPU unit 50 along the data flow S10. The linear change factor is a chip value calculated as “initial value + chip rate × elapsed time”. The phase register calculation circuit unit starts the calculation of the phase register value according to the chip value set by the interrupt at time UT1 and finishes the calculation by UT2. After the phase calculation is completed, the phase register calculation circuit section 40 outputs the phase register value corresponding to the chip value corresponding to the linear change factor of the M-sequence code to the CPU section 50.

  In the specific example of FIG. 2, data of 6138 chips (chip) (= 0 + 511.5K (chip per second) × 12 ms) at the time UT3 timing is sent from the CPU unit 50 to the data flow S10 in the phase register calculation circuit unit 40. Along the line (6138 chip setting (set, 6138 chips)). Subsequently, in the phase register calculation circuit unit 40, the phase calculation is performed from time UT1 to time UT2, and the phase register value corresponding to 6138 chips corresponding to the linear change factor of the M-sequence code is sent to the CPU unit 50 as the data flow S20. Is output along with.

  Next, the phase register adjustment processing unit 70 is input with the phase register value corresponding to the linear change factor of the M-sequence code from the phase register calculation circuit unit 40 along the data flow S20. In addition to this, the adjustment chip value corresponding to the Doppler shift amount corresponding to the non-linear change factor of the M-sequence code, that is, the α chip is input.

  Subsequently, in the phase register adjustment processing unit 70, a phase register adjustment process, which will be described later, is performed, and in consideration of the linear change factor of the M-sequence code, the phase register value corresponding to the nonlinear change factor is generated by the code generator 21 and the code generator. Is output to the NCO 22 for use.

  In the specific example of FIG. 2, in the phase register adjustment processing unit 70, the phase register value corresponding to 6138 chips corresponding to the linear change factor of the M-sequence code calculated by the phase register calculation circuit unit 40 at the time UT2 is set to the phase register value. The data is input from the calculation circuit unit 40 along the data flow S20 (reading of a phase register value corresponding to 6138 chips (read "phase register value corresponding to 6138 chips")). In addition to this, the adjustment chip value calculated based on the Doppler shift amount corresponding to the non-linear change factor of the M-sequence code, that is, the α chip is input. The Doppler shift amount is obtained from the reception processing unit 60 that receives satellite signals.

  Subsequently, in the phase register adjustment processing unit 70, a phase register adjustment process, which will be described later, is performed, and in consideration of a linear change factor of the M-sequence code, a phase register value corresponding to 6138 + α chips corresponding to the nonlinear change factor is code-generated. The data is output to the device 21 and the code generation NCO 22 along the data flow S30 (setting of the phase register value corresponding to “6138 + α” chips (set “phase register value corresponding to“ 6138 + α ”chips”)).

  Next, in the code generator 21 and the code generating NCO 22, the despreading code is set based on the setting of the phase register value corresponding to 6138 + α chips corresponding to the nonlinear change factor in consideration of the linear change factor of the input M sequence code. Is output.

<Linear feedback shift register>
Next, the linear feedback shift register (LFSR) according to the present embodiment will be described with reference to FIG. FIG. 3A is a block diagram of a forward Galois linear feedback shift register having an r-stage (r-bit) shift register according to this embodiment. FIG. 3B is a block diagram of a reciprocal (reverse) Galois linear feedback shift register having an r-stage (r-bit) shift register according to this embodiment. FIG. 3C is a block diagram of a forward-type Fibonacci linear feedback shift register having an r-stage (r-bit) shift register according to this embodiment. FIG. 3B is a block diagram of the reciprocal (reverse) Fibonacci linear feedback shift register having the r-stage (r-bit) shift register according to the present embodiment.

In the present embodiment, two types of linear feedback shift registers (LFSRs) are selectively used according to the two types of M series.
That is, when the M-sequence type is the GPS L2C signal, the Galois linear feedback shift register is used, and when the M-sequence type is the QZSS L6 signal, the Fibonacci linear feedback shift register is used.
Furthermore, in the phase register adjustment processing in each linear feedback shift register, two M-sequence processings of a forward type and a reciprocal type (reverse type) are respectively provided in order to correspond to the Doppler shift amount in the plus direction or the minus direction. Characterize.

<Forward Galois linear feedback shift register>
As shown in FIG. 3A, the forward Galois linear feedback shift register includes r registers 100, 101, 102, ..., 10r−1 and XOR elements (exclusive OR elements) 1111, 112, 113. , ..., 11r-1 and connection elements 121, 122, 123 ,. In this forward Galois linear feedback shift register, the first register 100, the XOR element 111, the second register 101, the XOR element 112, the third register 102, the XOR element 113, ... The data (1 or 0) of each bit in the first to rth registers is a bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ). 100 to 10r-1 are input respectively. The XOR element 111 outputs the exclusive OR of the output of the first connection element 121 and the output of the second register 101 to the first register 100. The XOR element 112 outputs the exclusive OR of the output of the second connection element 122 and the output of the third register 102 to the second register 101. The XOR element 11r-1 outputs the exclusive OR of the output of the connection element 12r-1 and the output of the register 10r-1 to the register 10r-2 in a similar manner. In this case, every time a clock signal is input from a clock generation unit (not shown) in the reception circuit unit 10, the states (bits S ₀ , S ₁ , S ₂ ,) in the _first to r-th registers 100 to 10r-1 are input. .., the state of S _r−1 ) is sequentially shifted toward the next register. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) changed by operating for a predetermined cycle according to the clock signal is It is output to a storage unit (not shown).

<Reciprocal (reverse) Galois linear feedback shift register>
As shown in FIG. 3B, the reciprocal (reverse) Galois linear feedback shift register includes r registers 200, 201, 202, ..., 20r−1 and an XOR element (exclusive OR element) 211. , 212, 213, ..., 21r-1 and connection elements 22r, 22r-1, 22r-2, ..., 223, 222, 221. In this reciprocal (reverse) Galois linear feedback shift register, the first register 200, the XOR element 211, the second register 201, the XOR element 212, ..., The register 20r-2, the XOR element 21r-1, and the register 20r-. The data (1 or 0) of each bit of the start code is serially connected in the order of 1 and the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _{r−). 1} ) is input to the first to r-th registers 200 to 20r-1. The output of the register 20r-1 of the first r is connected devices 221, 222, 223, ..., 22r, _{i.e., b 1, b 2, b} 3, ..., b r-3, b r-2, b r _-1 , _br are input. The XOR element 211 outputs the exclusive OR of the output of the first register 200 and the output of the connection element 22r-1 to the second register 201. The XOR element 212 outputs the exclusive OR of the output of the connection element 22r-2 and the output of the second register 201 to the third register 202. The XOR element 21r-1 outputs the exclusive OR of the output of the connection element 221 and the output of the register 20r-2 to the register 20r-1 in substantially the same manner. In this case, every time a clock signal is input from a clock generation unit (not shown) in the reception circuit unit 10, the states (bits S ₀ , S ₁ , S ₂₎ in the _first to r-th registers 200 to 20r-1 are input. .., the state of S _r−1 ) is sequentially shifted toward the next register. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) changed by operating for a predetermined cycle according to the clock signal is It is output to a storage unit (not shown).

<Forward Fibonacci linear feedback shift register>
As shown in FIG. 3C, the forward type Fibonacci linear feedback shift register includes r registers 300, 301, 302, ..., 30r−1 and XOR elements (exclusive OR elements) 311, 312, 313. , 31r-1 and connection elements 321, 322, 323, ..., 32r-3, 32r-2, 32r-1, 32r. In this forward type Fibonacci linear feedback shift register, registers 300, 301, 302, ..., 30r-4, 30r-3, 30r-2, 30r-1 are serially connected in this order, and data (1 Or 0) as a bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) in the first to rth registers 300 to 30r-1, respectively. Is entered. Further, the output of the first register 300 becomes the input of the second register 301 and the input of the connection element 321. The XOR element 311 outputs the exclusive OR of the output of the connection element 321 and the output of the XOR element 312 to the first register 300. The XOR element 312 outputs the exclusive OR of the output of the connection element 322 and the output of the XOR element 313 to the XOR element 311. The XOR element 31r-1 outputs the exclusive OR of the output of the connection element 32r-1 and the output of the connection element 32r to the XOR element 31r-2 in substantially the same manner. In this case, every time the clock signal from the clock generator (not shown) in the reception circuit unit 10 is inputted, the first through r register 300~30r-1 in the state (bit _S 0 _{to S r-1} state ) Shifts to the next register in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) changed by operating for a predetermined cycle according to the clock signal is It is output to a storage unit (not shown).

<Reciprocal (inverse) Fibonacci linear feedback shift register>
As shown in FIG. 3D, the reciprocal (inverse) Fibonacci linear feedback shift register includes r registers 400, 401, 402, ..., 40r−1 and an XOR element (exclusive OR element) 411. , 41r-1 and connection elements 421, 422, 423, ..., 42r-3, 42r-2, 42r-1, 42r. In this reciprocal (inverse) Fibonacci linear feedback shift register, registers 400, 401, 402, ..., 40r-1 are connected in series in this order, and each bit data (1 or 0) of the start code is converted into a bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) are respectively input to the first to r-th registers 400 to 40r-1. The output of the r-th register 40r-1 becomes the input of the connection element 421 and the input of the r-1-th register 40r-2. The XOR element 411 outputs the exclusive OR of the output of the connection element 421 and the output of the XOR element 412 to the rth register 40r-1. The XOR element 412 outputs the exclusive OR of the output of the connection element 422 and the output of the XOR element 413 to the XOR element 411. The XOR element 41r-1 outputs the exclusive OR of the output of the connection element 42r-1 and the output of the connection element 42r to the XOR element 41r-2 in substantially the same manner. In this case, every time the clock signal from the clock generator (not shown) in the reception circuit unit 10 is inputted, the first through r register 400~40r-1 in the state (bit _S 0 _{to S r-1} state ) Shifts to the next register in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) changed by operating for a predetermined cycle according to the clock signal is It is output to a storage unit (not shown).

In particular, connecting elements _a 1 to be used in the order form Galois or forward type Fibonacci linear feedback shift _register, a _{2, a 3, ...,} and _{a r-3, a r-} 2, a r-1, a r, reciprocity type Galois or reciprocal type Fibonacci connecting element _b 1 used by the linear feedback shift _{register, b 2, b 3, ...} , b r-3, b r-2, b r-1, b r satisfies the following formula .

ここで、Ｄは遅延オペレータ、ｒはレジスタ個数（段数）、ｂ(・)は相反型ガロア又は相反型フィボナッチ線形フィードバックシフトレジスタの結線素子系列（状態）、ａ(・)は順型ガロア又は順型フィボナッチ線形フィードバックシフトレジスタの結線素子系列（状態）である。また結線素子系列ａ（Ｄ），ｂ（Ｄ）は各結線素子による多項式表現で次の式になる。

遅延オペレータＤは以下の文献などで説明されている。
参考文献１ Ｒｏｇｅｒ Ｌ． Ｐｅｔｅｒｓｏｎ，Ｒｏｄｇｅｒ Ｅ．Ｚｉｅｍｅｒ，Ｄａｖｉｄ Ｅ．Ｂｏｒｔｈ著,丸林元 [ほか] 訳
スペクトル拡散通信入門,科学技術出版,ｐｐ．１０８−１８１，Ｓｅｐｔ．２００２．

Where D is a delay operator, r is the number of registers (number of stages), b (•) is a reciprocal Galois or reciprocal Fibonacci linear feedback shift register connection element sequence (state), and a (•) is a forward Galois or forward. 2 is a connection element series (state) of a type Fibonacci linear feedback shift register. The connection element series a (D) and b (D) are represented by the following equations in polynomial expression by each connection element.

The delay operator D is described in the following documents and the like.
Reference 1 Roger L. et al. Peterson, Rodger E. Ziemer, David E. Borth, Translated by Marubayashi Gen [Other] Introduction to spread spectrum communication, Science and Technology Publishing, pp. 108-181, Sept. 2002.

<4-bit M series by Galois linear feedback shift register>
Next, referring to FIG. 4, a simple specific example of the relationship between the forward Galois linear feedback shift register and the reciprocal (reverse) Galois linear feedback shift register in the phase register adjustment processing according to the present embodiment will be described. 4-bit M sequence ”. FIG. 4A is a block diagram of a forward Galois linear feedback shift register having a 4-stage (4-bit) shift register according to this embodiment.
FIG. 4B is a block diagram of a reciprocal (reverse) Galois linear feedback shift register having a 4-stage (4-bit) shift register according to this embodiment.

  4A and 4B show, as an example, a linear feedback shift register having a four-stage (4-bit) shift register, but FIG. It is also possible to configure as a linear feedback shift register of a predetermined bit (r bit) other than 4 bits as shown in FIG. 3B.

<Forward Galois linear feedback shift register>
As shown in FIG. 4A, the forward Galois linear feedback shift register has four registers 141 to 144, an XOR element (exclusive OR element) 140, and coupling elements a ₁ and a _4. . In this forward Galois linear feedback shift register, the first register 141, the XOR element 140, and the second to fourth registers 142 to 144 are serially connected in this order, and the data (1 or 0) of each bit of the start code is Bit strings (S ₀ , S ₁ , S ₂ , S ₃ ) are input to the first to fourth registers 141 to 144, respectively. The output of the first register 141 becomes the input of the XOR element 140 and the input of the fourth register 144. The XOR element 140 outputs the exclusive OR of the output of the first register 141 and the output of the second register 142 to the first register 141. In this case, every time a clock signal is input from a clock generation unit (not shown) in the reception circuit unit 10, the state (state of bits S _{0 to} S ₃ ) in the first to fourth registers 141 to 144 is as follows. Shift towards the register in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ ) changed by operating for a predetermined cycle according to the clock signal is output to a storage unit (not shown).
When the connection element sequence of this forward Galois linear feedback shift register is expressed by the polynomial expression by the delay operator D, the following formula (2) is obtained.

<Reciprocal (reverse) Galois linear feedback shift register>
As shown in FIG. 4B, the reciprocal (reverse) Galois linear feedback shift register includes four registers 241-244, an XOR element (exclusive OR element) 240, and coupling elements b ₃ and b _4. And. In this reciprocal type (reverse type) Galois linear feedback shift register, the first register 241, the XOR element 240, and the second to fourth registers 242 to 244 are connected in series in this order, and the data (1 Or 0) is input to the first to fourth registers 241 to 244 as a bit string (S ₀ , S ₁ , S ₂ , S ₃ ), respectively. The output of the first register 241 becomes the input of the XOR element 240. The XOR element 240 outputs the exclusive OR of the output of the first register 241 and the output of the fourth register 244 to the second register 242. In this case, every time a clock signal is input from a clock generation unit (not shown) in the reception circuit unit 10, the states (states of bits S _{0 to} S ₃ ) in the first to fourth registers 241 to 244 are as follows. Shift towards the register in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ , ..., S _r-3 , S _r-2 , S _r-1 ) changed by operating for a predetermined cycle according to the clock signal is It is output to a storage unit (not shown).
When the connection element series of this reciprocal (reverse) Galois linear feedback shift register is expressed by the polynomial expression by the delay operator D, the following expressions are obtained from (Equation 1) and (Equation 3).

<Phase register adjustment processing: Galois linear feedback shift register>
Next, with reference to FIG. 4C and FIG. 4D, the shift of the state (cycle) of each register in the Galois linear feedback shift register in the phase register adjustment processing will be described. Here, FIG. 4C is a table showing the shift (cycle) of the state of each register in the forward Galois linear feedback shift register, and FIG. 4D is the reciprocal (reverse) Galois linear feedback shift. 8 is a table showing shifts (cycles) of states of each register in the register.

  Specifically, the phase register value corresponding to the linear change factor is input to the phase register adjustment processing unit 70 from the phase register calculation circuit unit 40 along the data flow S20, and in addition, the Doppler shift corresponding to the nonlinear change factor is added. The adjustment chip value corresponding to the amount, that is, the α chip is input.

In the phase register adjustment processing unit 70, when the adjustment chip value corresponding to the Doppler shift amount corresponding to the nonlinear change factor, that is, α chip is positive, the phase register value is obtained based on the forward Galois linear feedback shift register. . More specifically, based on the adjustment chip value corresponding to the positive Doppler shift amount, that is, α chips, in the forward Galois linear feedback shift register, a predetermined number of cycles along the time axis, in other words, cycles. A predetermined number of cycles that proceed in the forward direction are determined. For example, if the predetermined number of cycles determined based on the positive Doppler shift amount is plus 5 cycles, the phase states (S ₃ , S ₂ , S ₁ , S ₁ of the phase register values of the forward Galois linear feedback shift register, S ₀ ) = ( _{0, 0, 0, 1} ) (see cycle 0 in FIG. 4C), and the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₀ , ₀ , ₁ ) (see cycle 1 in FIG. 4C), the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₁ , ₀ 1) (see cycle 2 in FIG. 4C), the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₁ , ₁ , ₁ ) (FIG. 4 ( Referring to cycle 3 in c)), and the phase state of the phase register value _{(S 3, S 2, S} 1, S ) = (1,1,1,0) (see FIG. 4 (c) through a reference to the cycle 4 in), the phase state of the phase register value _{(S 3, S 2, S} 1, S 0) = (0, 1, 1, 1) (see cycle 5 in FIG. 4 (c)) is obtained. Here, the “phase state” according to the present embodiment means a sequence of phase register values of 0 or 1.

In particular, in the present embodiment, on the other hand, when the adjustment chip value corresponding to the Doppler shift amount corresponding to the nonlinear change factor, that is, the α chip is negative, the reciprocal Galois linear feedback is used instead of the forward Galois linear feedback shift register. The phase register value is determined based on the shift register. More specifically, the reciprocal Galois linear feedback shift register determines a predetermined number of cycles in the reciprocal type based on the adjustment chip value corresponding to the negative Doppler shift amount, that is, the α chip. It For example, when the predetermined number of cycles determined based on the negative Doppler shift amount is minus 2 cycles, the forward Galois linear feedback shift register does not move backward by 2 cycles, but reciprocal Galois linear feedback. The shift register moves forward for only two cycles. That is, the phase states (S ₃ , S ₂ , S ₁ , S ₀ ) of the phase register values of the reciprocal Galois linear feedback shift register = ( ₀ , ₀ , ₀ , ₁ ) (cycle 0 in FIG. As shown in FIG. 4D, the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₀ , ₀ , ₁ , ₀ ) (see cycle 1 in FIG. 4D). After that, the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₀ , ₁ , ₀ , ₀ ) (see cycle 2 in FIG. 4D) is obtained. The phase states (S ₃ , S ₂ , S ₁ , S ₀ ) of the phase register values obtained in this way are output to the code generator 21 and the code generating NCO 22 along the data flow S30.

As described above, in the present embodiment, the cycle of the forward Galois linear feedback shift register is advanced in the reverse direction, that is, the phase state in which the cycle is advanced in the reverse direction of cycles 0, 14, 13 ,. It is characterized in that the point that the cycle of the Galois linear feedback shift register is advanced in the forward direction and the phase states of the cycles 0, 1, 2, ... Specifically, in the forward Galois linear feedback shift register, the phase states (S ₃ , S ₂ , S ₁ , S ₀ ) of the phase register values advanced in the opposite direction by 2 cycles = ( ₀ , ₁ , ₀ , ₀ ) (Refer to cycle 13 shown by P1 in FIG. 4C) and the phase states (S ₃ , S ₂ , S of the phase register value advanced by 2 cycles in the reciprocal Galois linear feedback shift register). ₁ , S ₀ ) = ( ₀ , ₁ , ₀ , ₀ ) (refer to cycle 2 shown by P2 in FIG. 4D) is used.

  That is, the present embodiment is characterized in that the reciprocal (reverse) Galois linear feedback shift register uses the two M sequences of the forward type and the reciprocal (reverse type) in addition to the above-described features. is there. By using the reciprocal type (reverse type) M series, it is possible to obtain an effect equivalent to advancing the cycle in the reverse direction (negative direction) of the phase state of the forward type M series. The reciprocal (reverse) M sequence with respect to the forward M sequence is uniquely determined by a predetermined relational expression, and the desired action and effect cannot be obtained even if any other M sequence is used. By using two M series, a forward M series and a reciprocal (reverse) M series, it is possible to calculate a desired action and effect with a small number of cycle steps.

If the adjustment chip value corresponding to the Doppler shift amount corresponding to the non-linear change factor, that is, the α chip is negative, when the phase register value is obtained based on the forward Galois linear feedback shift register, the cycle is reversed. The predetermined number of cycles that have been advanced to the previous step are determined, and in fact, the phase register value that has advanced the cycles in the forward direction to the position corresponding to the predetermined number of cycles that have advanced in the reverse direction is obtained. For example, if the predetermined number of cycles determined based on the amount of negative Doppler shift is minus two cycles, the forward type Galois linear feedback shift register advances by two cycles in the reverse direction, that is, the forward type The Galois linear feedback shift register advances in the forward direction by 13 (= -2 modulo 15) cycles. That is, the phase state of the phase register value of the forward Galois linear feedback shift register (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₀ , ₀ , ₀ , ₁ ) (cycle 0 in FIG. As shown in FIG. 4C, the phase state of the phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₀ , ₀ , ₁ ) (see cycle 1 in FIG. 4C), Phase state of phase register value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₁ , ₀ , ₁ ) (see cycle 2 in FIG. 4C), phase state of phase register value ( S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₁ , ₁ , ₁ , ₁ ) (see cycle 3 in FIG. 4C), the phase state of the phase register value (S ₃ , S ₂ , S ₀ ). ₁ , S ₀ ) = ( ₁ , ₁ , ₁ , ₀ ) (refer to cycle 4 in FIG. 4C), and thereafter, through cycles 5 to 12, the desired phase shift A large amount of 13 cycle steps is required until the phase value (S ₃ , S ₂ , S ₁ , S ₀ ) = ( ₀ , ₁ , ₀ , ₀ ) (see cycle 13 in FIG. 4C) of the transistor value is obtained. The phase register value needs to be calculated.

On the other hand, in the present embodiment, when the Doppler shift amount is negative, the reciprocal Galois linear feedback shift register is used instead of the forward Galois linear feedback shift register. Thereby, for example, when the predetermined number of cycles determined based on the minus Doppler shift amount is minus two cycles, the reciprocal Galois linear feedback shift register advances by two cycles in the forward direction. That is, the phase state (S ₃ , S ₂ , S ₁ , S ₀ ) of the desired phase register value = (0, 1, 0, 0) (see cycle 2 in FIG. 4 (d)).
Given the phase states (S ₀ , S ₁ , S ₂ , S ₃ ) of the start code, calculate the phase states (S ₀ , S ₁ , S ₂ , S ₃ ) of the desired phase register value in few cycle steps. Not all phase register values need to be stored in ROM.

  As a result, it is possible to reduce the ROM capacity and the CPU processing capacity.

<4-bit M series by Fibonacci linear feedback shift register>
Next, with reference to FIG. 5, a simple specific example of the relationship between the forward type Fibonacci linear feedback shift register and the reciprocal (reverse type) Fibonacci linear feedback shift register in the phase register adjustment processing according to the present embodiment will be described. 4-bit M sequence ”. FIG. 5A is a block diagram of a forward-type Fibonacci linear feedback shift register having a 4-stage (4-bit) shift register according to this embodiment.
FIG. 5B is a block diagram of a reciprocal (reverse) Fibonacci linear feedback shift register having a 4-stage (4-bit) shift register according to this embodiment.

  5A and 5B show, as an example, a linear feedback shift register (code generation device) having a 4-stage (4-bit) shift register, but FIG. It is also possible to configure as a linear feedback shift register of a predetermined bit (r bit) other than 4 bits as shown in 3 (c) and FIG. 3 (d).

<Forward Fibonacci linear feedback shift register>
The forward type Fibonacci linear feedback shift register has four registers 341 to 344, an XOR element (exclusive OR element) 340, and coupling elements a ₁ and a ₄ as shown in FIG. 5A. . In this forward type Fibonacci linear feedback shift register, the first register 341, the XOR element 340, and the second to fourth registers 342 to 344 are serially connected in this order, and the data (1 or 0) of each bit of the start code is Bit strings (S ₀ , S ₁ , S ₂ , S ₃ ) are input to the first to fourth registers 341 to 344, respectively. The output of the first register 341 becomes the input of the XOR element 340 and the input of the second register 342. The XOR element 340 outputs the exclusive OR of the output of the first register 341 and the output of the fourth register 344 to the first register 341. In this case, each time a clock signal is input from a clock generator (not shown) in the receiving circuit unit 10, the state (state of bits S _{0 to} S ₃ ) in the first to fourth registers 341 to 344 is changed to the next state. Shift to registers in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ ) changed by operating for a predetermined cycle according to the clock signal is output to a storage unit (not shown).
When the connection element series of this forward type Fibonacci linear feedback shift register is expressed in polynomial expression by the delay operator D, the following is obtained from (Equation 2).

<Reciprocal (inverse) Fibonacci linear feedback shift register>
As shown in FIG. 5B, the reciprocal (inverse) Fibonacci linear feedback shift register includes four registers 441 to 444, an XOR element (exclusive OR element) 440, and coupling elements b ₃ and b _4. And. In this reciprocal (reverse) Fibonacci linear feedback shift register, the first register 441, the second to third registers 442 to 443, the XOR element 440, and the fourth register 444 are connected in series in this order, and the start code The data (1 or 0) of each bit is input to the first to fourth registers 441 to 444 as a bit string (S ₀ , S ₁ , S ₂ , S ₃ ), respectively. Further, the output of the second register 442 becomes the input of the XOR element 440 and the input of the first register 441. The XOR element 440 outputs the exclusive OR of the output of the second register 442 and the output of the first register 441 to the fourth register 444. In this case, every time a clock signal is input from a clock generation unit (not shown) in the reception circuit unit 10, the states (states of bits S _{0 to} S ₃ ) in the first to fourth registers 441 to 444 are as follows. Shift to registers in order. The data (1 or 0) of the bit string (S ₀ , S ₁ , S ₂ , S ₃ ) changed by operating for a predetermined cycle according to the clock signal is output to a storage unit (not shown).
When the connection element series of this reciprocal (inverse) Fibonacci linear feedback shift register is expressed by the polynomial expression by the delay operator D, the following expressions are obtained from (Equation 1) and (Equation 5).

<Phase register adjustment processing: Fibonacci linear feedback shift register>
Next, with reference to FIG. 5C and FIG. 5D, the shift (cycle) of the state of each register in the Fibonacci linear feedback shift register in the phase register adjustment processing will be described. Here, FIG. 5C is a table showing shifts (cycles) of states of each register in the forward-type Fibonacci linear feedback shift register, and FIG. 5D is a reciprocal (reverse) Fibonacci linear feedback shift register. 8 is a table showing shifts (cycles) of states of each register in the register.

  Specifically, the phase register value corresponding to the linear change factor is input to the phase register adjustment processing unit 70 from the phase register calculation circuit unit 40 along the data flow S20, and in addition, the Doppler shift corresponding to the nonlinear change factor is added. The adjustment chip value corresponding to the amount, that is, the α chip is input.

In the phase register adjustment processing unit 70, when the adjustment chip value corresponding to the Doppler shift amount corresponding to the non-linear change factor, that is, α chip is positive, the phase register value is obtained based on the forward Fibonacci linear feedback shift register. . More specifically, based on the adjustment chip value corresponding to the positive Doppler shift amount, that is, α chips, in the forward type Fibonacci linear feedback shift register, a predetermined number of cycles along the time axis, in other words, cycles. A predetermined number of cycles that proceed in the forward direction are determined. For example, if the determined predetermined number of cycles is plus 5 cycles based on the positive Doppler shift amount, the phase states (S ₀ , S ₁ , S ₂ , S ₂ of the phase register values of the forward-type Fibonacci linear feedback shift register, S ₃ ) = ( ₁ , ₀ , ₀ , ₀ ) (see cycle 0 in FIG. 5C), and the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ). = (1,1,0,0) (see cycle 1 in FIG. 5C), the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = (1, 1, 1 , 0) (see cycle 2 in FIG. 5C), the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₁ , ₁ , ₁ , ₁ ) (FIG. 5 ( cycle 3 in c)) and the phase states of the phase register values (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₀ , ₁ , ₁ , ₁ ) (see cycle 4 in FIG. 5 (c)), the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = (1, 0, 1, 1) (see cycle 5 in FIG. 5C) is obtained.

Particularly, in the present embodiment, on the other hand, when the adjustment chip value corresponding to the Doppler shift amount corresponding to the non-linear change factor, that is, α chip is negative, the reciprocal Fibonacci linear feedback is used instead of the forward Fibonacci linear feedback shift register. The phase register value is determined based on the shift register. More specifically, the reciprocal Fibonacci linear feedback shift register determines a predetermined number of cycles in the reciprocal type based on the adjustment chip value corresponding to the negative Doppler shift amount, that is, the α chip. It For example, if the predetermined number of cycles determined based on the amount of negative Doppler shift is minus 2 cycles, the forward Fibonacci linear feedback shift register does not move backward by 2 cycles, but reciprocal Fibonacci linear feedback. The shift register moves forward for only two cycles. That is, the phase states (S ₀ , S ₁ , S ₂ , S ₃ ) of the phase register values of the reciprocal Fibonacci linear feedback shift register = ( ₁ , ₀ , ₀ , ₀ ) (cycle 0 in FIG. Phase) of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₀ , ₀ , ₀ , ₁ ) (see cycle 1 in FIG. 5D) The phase state of the register value (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₀ , ₀ , ₁ , ₀ ) (see cycle 2 in FIG. 5D) is obtained. The phase states (S ₃ , S ₂ , S ₁ , S ₀ ) of the phase register values obtained in this way are output to the code generator 21 and the code generating NCO 22 along the data flow S30.

As described above, in the present embodiment, the cycle of the forward-type Fibonacci linear feedback shift register is advanced in the reverse direction, that is, the phase state in which the cycle is advanced in the reverse direction of cycles 0, 14, 13, ... It is characterized in that the point that the cycle state of the Fibonacci linear feedback shift register in the forward direction, that is, the cycle 0, 1, 2, ... Specifically, in the forward Fibonacci linear feedback shift register, the phase state of the phase register value advanced in the opposite direction by two cycles (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₀ , ₀ , ₁ , ₀ ) (Refer to cycle 13 shown by P3 in FIG. 5C) and the phase states (S ₀ , S ₁ , S of the phase register value advanced by two cycles in the reciprocal Fibonacci linear feedback shift register). ₂ , S ₃ ) = (0, 0, 1, 0) (see cycle 2 indicated by P4 in FIG. 5D) is used.

  That is, the present embodiment is characterized in that the reciprocal (inverse) Fibonacci linear feedback shift register uses the two M sequences of the forward type and the reciprocal (inverse) type in addition to the above-described features. is there. By using the reciprocal type (reverse type) M series, it is possible to obtain an effect equivalent to advancing the cycle in the reverse direction (negative direction) of the phase state of the forward type M series. The reciprocal (reverse) M sequence with respect to the forward M sequence is uniquely determined by a predetermined relational expression, and the desired action and effect cannot be obtained even if any other M sequence is used. By using two M series, a forward M series and a reciprocal (reverse) M series, it is possible to calculate a desired action and effect with a small number of cycle steps.

If the adjustment chip value corresponding to the Doppler shift amount corresponding to the nonlinear change factor, that is, the α chip is negative, when the phase register value is obtained based on the forward Fibonacci linear feedback shift register, the cycle is reversed. The predetermined number of cycles that have been advanced to the previous step are determined, and in fact, the phase register value that has advanced the cycles in the forward direction to the position corresponding to the predetermined number of cycles that have advanced in the reverse direction is obtained. For example, if the predetermined number of cycles determined based on the negative Doppler shift amount is minus two cycles, the forward type Fibonacci linear feedback shift register proceeds in the opposite direction by two cycles, that is, The Fibonacci linear feedback shift register advances by 13 (= -2 modulo 15) cycles in the forward direction. That is, the phase state of the phase register value of the forward type Fibonacci linear feedback shift register (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₁ , ₀ , ₀ , ₀ ) (cycle 0 in FIG. (See), the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = (1, ₁ , ₀ , 0) (see cycle 1 in FIG. 5C), Phase state of phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₁ , ₁ , ₁ , ₀ ) (see cycle 2 in FIG. 5C), phase state of phase register value ( S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₁ , ₁ , ₁ , ₁ ) (see cycle 3 in FIG. 5 (c)), the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = (0, 1, 1, 1) (refer to cycle 4 in FIG. 5C), and thereafter, through cycles 5 to 12, the desired A large amount of 13 cycle steps until the phase state of the phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = ( ₀ , ₀ , ₁ , ₀ ) (see cycle 13 in FIG. 5C) is obtained. It is necessary to calculate the phase register value of

On the other hand, in the present embodiment, when the Doppler shift amount is negative, the reciprocal Fibonacci linear feedback shift register is used instead of the forward Fibonacci linear feedback shift register. Thus, for example, when the predetermined number of cycles determined based on the minus Doppler shift amount is minus two cycles, the reciprocal type Fibonacci linear feedback shift register advances by two cycles in the forward direction. That is, the phase state of the desired phase register value (S ₀ , S ₁ , S ₂ , S ₃ ) = (0, 0, 1, 0) (see cycle 2 in FIG. 5D) can be obtained.
Given the phase states (S ₀ , S ₁ , S ₂ , S ₃ ) of the start code, calculate the phase states (S ₀ , S ₁ , S ₂ , S ₃ ) of the desired phase register value in few cycle steps. Not all phase register values need to be stored in ROM.

  As a result, it is possible to reduce the ROM capacity and the CPU processing capacity.

  Although the embodiments of the present invention have been described above, the specific configuration is not limited to the above-mentioned embodiments, and even if there is a design change or the like within a range not departing from the gist of the present invention, Included in the invention.

  The present invention can also be applied to a spread spectrum signal receiving system for receiving the same type of spread spectrum signal using an M sequence other than the GPS L2C signal and the QZSS L6 signal.

Description of Codes in FIG. 1 1 Spread spectrum signal reception system 2 Antenna 3 Frequency conversion unit 4 A / D conversion unit 10 Reception circuit unit 20 Code generation unit 21 Code generator 22 Code generation NCO
30 Correlator 31 Carrier NCO
32 carrier wave correlation unit 40 phase register calculation circuit unit 50 CPU unit 60 reception processing unit 70 phase register adjustment processing unit 80 code generation device

Claims (4)

A code generation device for generating a phase register value which is a code of a desired phase state by setting the phase of the M-sequence code of the received signal as a phase state and changing the phase state by a predetermined cycle,
Phase register calculating means for calculating a phase register value corresponding to the linear change factor of the M-sequence code;
Phase register adjusting means for adjusting the phase register value in response to the non-linear change factor of the M-sequence code;
A code generation device comprising: The phase register adjusting means,
When the M-sequence code is generated by a Galois linear feedback shift register and the Doppler shift amount according to the nonlinear change factor is positive, the forward Galois linear feedback shift register adjusts the phase register value,
The code generation device according to claim 1, wherein when the Doppler shift amount is negative, the phase register value is adjusted by a reciprocal Galois linear feedback shift register. The phase register adjusting means,
When the M-sequence code is generated by the Fibonacci linear feedback shift register and the Doppler shift amount according to the non-linear change factor is positive, the forward-type Fibonacci linear feedback shift register adjusts the phase register value,
The code generation device according to claim 1, wherein when the Doppler shift amount is negative, the phase register value is adjusted by a reciprocal Fibonacci linear feedback shift register.   A code for capturing and tracking a spread spectrum signal from a satellite, comprising the code generation device according to any one of claims 1 to 3, and the phase register value generated and output by the code generation device. A spread spectrum signal reception system characterized by being set in a generator.

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