JP4806341B2 - Code generating apparatus and spread spectrum signal receiving system - Google Patents

Description

  The present invention relates to a code generation device that generates a code in a desired phase state, and a spread spectrum signal reception system to which the code generation device is applied.

  Recently, as a code generator in a spread spectrum signal reception system of GNSS (Global Navigation Satellite System), a Galois type code generator or a Fibonacci type code generator has been adopted, and these code generators are predetermined. It is composed of a linear feedback shift register having a shift register composed of registers of the number of stages and an XOR (exclusive OR) element. In this case, in the shift register, the state of each register is sequentially shifted every time a clock signal is input from the outside, and the state of each register changes periodically. As a result, the code generator It is possible to generate and output a desired M-sequence spreading code.

  The code generator disclosed in Patent Document 1 includes a Galois-type linear feedback shift register, and a desired code phase (hereinafter also referred to as a start code) is set as a start phase state, and a desired phase is generated from the start phase state. When generating an M-sequence spreading code as a result code in a phase state (result phase state), it is determined whether the start phase state that is Fibonacci type is a unit phase state. After setting the number of bits corresponding to the difference (offset amount) between the start phase state and the result phase state in the counter, and further setting the unit phase state as a temporary state, the count value (number of bits) of the counter Until the value of 0 becomes 0, the square calculation for the sign of the temporary state is repeated, and the phase state when the count value reaches 0 is changed to the Galois type temporary To re-set as a state.

  In the code generator, when the count value reaches 0, a Fibonacci type multiplication is performed by performing Galois field multiplication of the code in the temporary state and the Fibonacci type code in the start phase state. It is possible to obtain a result code.

  Note that the Galois type or Fibonacci type code means a code input to a Galois type or Fibonacci type code generator or a code output from the code generator.

JP 2000-332728 A (FIG. 8)

  However, since the code generator disclosed in Patent Document 1 generates a result code using square calculation, when the code generator is configured with a multistage linear feedback shift register, the result code Calculation load related to generation increases.

  In the code generator, before calculating the offset amount, first, a condition determination process is performed to determine whether the start phase state is a unit phase state, and then, according to the result of the condition determination process, Which of the two types of processing contents prepared in advance is used to generate the result code is determined. Further, the code generator also performs a condition determination process as to whether or not the count value has reached zero during the square calculation. For this reason, the code generator also increases the load related to each condition determination process.

  The present invention has been made to solve the above-described problems, and a code generation apparatus capable of reducing various loads related to generation of a result code, and a spread spectrum signal receiving system to which the code generation apparatus is applied. The purpose is to provide.

  The code generation device according to the present invention is a code generation device that generates a result code of a desired result phase state by changing the phase by a predetermined cycle with the phase of the start code as a start phase state. A starting phase state generating means having a 1 code generator and a reciprocal Fibonacci type second code generator, a reciprocal Galois type or reciprocal Fibonacci type third code generator, a Galois type or Fibonacci type fourth code generator, and A differential phase state creation means having a fifth code generator; and a result phase state creation means, wherein the first code generator changes the phase of the start code by a predetermined cycle to change the start code. The Galois type start code is converted into a reciprocal Fibonacci type start code, and the second code generator further converts the phase of the reciprocal Fibonacci type start code. The start code with the phase changed by a predetermined cycle is output to the resultant phase state creation means, and the third code generator sets the phase of the unit code as the unit phase state and changes the phase by a predetermined cycle. The fourth code generator changes the phase of the unit code that has changed the phase based on the maximum cycle amount that can change the phase of the unit code, while changing the phase of the unit code by a predetermined cycle. The data of each address is sequentially output to the fifth code generator, and the fifth code generator includes the start phase state and the result phase state among the new codes composed of the sequentially input data. And outputs the data at a predetermined address determined based on the cycle amount according to the phase difference to the result phase state creating means as the difference code corresponding to the phase difference, and the result Phase state generation means, and generating the result code by the multiplication difference code and the Galois field from the start code and the fifth code generator from said second code generator.

  According to this configuration, each of the Galois type, reciprocal Galois type, Fibonacci type and reciprocal Fibonacci type code generators in the start phase state creation unit and the differential phase state creation unit has the start code phase (start phase state) and unit code. The result phase state creation means generates a Galois-type result code by multiplying the start code and the difference code by a Galois field, and thus is disclosed in Patent Document 1. Compared with the process using the square calculation in the code generator, the calculation load related to the generation of the result code is reduced, and the result code can be generated efficiently. Further, unlike the code generator disclosed in Patent Document 1, it is not necessary to prepare two types of code generation processes in advance, so that various condition determination processes are not required, and the load related to the generation of the result code is further reduced. Can do.

  Note that changing the phase of the start code, the phase of the unit code, and the phase of the new code by a predetermined cycle means that the phase of these codes is changed every time a clock signal is input in each code generator. Is sequentially shifted from the initial phase to a desired phase at a predetermined interval. Further, the maximum cycle amount that can change the phase of the unit code means the phase range when the phase of the unit code is periodically changed within a predetermined phase range, and an M-sequence spread code is used. In the case of an L2C signal transmitted by a GPS satellite, it refers to a specified range between the start position and end position of a specified spread code, that is, the maximum length of the spread code. Furthermore, the data at each address in the unit code refers to the value (0 or 1) of each bit constituting the unit code. Furthermore, the Galois field multiplication means the multiplication process of the start code and the difference code and the exclusive OR calculation process for the multiplication result as described above.

  Here, the start phase state creation unit further includes a start phase state storage unit that stores a start code whose phase is changed by a predetermined cycle in the second code generator, and the differential phase state creation unit includes It is preferable to further include a differential phase state storage unit that stores the differential code generated by the fifth code generator.

  As a result, when a plurality of result codes or a plurality of desired codes corresponding to the result codes are known, that is, the start phase state and the maximum cycle amount are defined, and accordingly, the start code and the difference code are created in advance. If it is possible to store the start code in the start phase state storage unit in advance, and store the difference code in the difference phase state storage unit in advance, when the result code is repeatedly created Since the start code generation processing in the start phase state creation means and the difference code generation processing in the difference phase state creation means are not required, the code generation apparatus as a whole can generate the result code with less calculation load. it can.

  In this case, the code generation device further includes at least one of a start phase state update unit arranged in the start phase state creation unit and a differential phase state update unit arranged in the differential phase state creation unit. The start phase state update unit updates the start code phase stored in the start phase state storage unit by one cycle at a time, and updates the start code that has advanced the phase in the result phase state. The differential phase state update unit sequentially outputs to the creating means, and the differential phase state update unit advances the differential code stored in the differential phase state storage unit by one cycle at a time while updating the differential code with the phase advanced. It is preferable to output to the result phase state creating means.

  Accordingly, it is possible to repeatedly generate a result code in a desired result phase state without performing a start code generation process in the start phase state creation unit and a difference code generation process in the difference phase state creation unit.

  The result phase state creation means includes a code operation unit that performs the Galois field multiplication and a result phase state creation unit that includes a Galois type code generator, and the code operation unit includes the start code. And each time the difference code is input, the respective codes are multiplied, an exclusive OR of the multiplication results is calculated and sequentially output to the result phase state creation unit, and the result phase state creation unit is sequentially input It is preferable that the result code is generated by changing the data composed of each of the exclusive ORs, which is performed, by a cycle amount corresponding to a difference between the start phase state and the result phase state.

  Thereby, also in the result phase state creating means, the calculation load related to the generation of the result code is reduced, so that the result code can be generated more efficiently.

  Furthermore, when generating a Fibonacci-type result code having a desired result phase state by changing the phase of the Fibonacci-type start code by a predetermined cycle, the start phase state creating means includes the Fibonacci-type start code. Is converted into the Galois type start code and output to the first code generator, and the third code generator is configured as a reciprocal Fibonacci type code generator, The fourth code generator and the fifth code generator are configured as Fibonacci type code generators, and in the result phase state creation means, the generated Galois type result code is converted into the Fibonacci type result code. It is preferable that a Fibonacci type code generator for conversion is arranged.

  Accordingly, it is possible to generate a Galois type result code from a Galois type start code and a Fibonacci type result code from a Fibonacci type start code in one code generation device.

  If the first to sixth code generators are configured with linear feedback shift registers, the above-described processes can be performed efficiently.

  Such a code generator is applied to a code generator of a spread spectrum signal receiving system, and a spread code generated based on a result code output from the code generator is multiplied with a spread spectrum signal from a satellite. Thus, it is possible to efficiently capture and track the spread spectrum signal.

  According to the present invention, the Galois type, reciprocal Galois type, Fibonacci type, and reciprocal Fibonacci type code generators in the starting phase state creating unit and the differential phase state creating unit are configured to use the start code phase (start phase state) and unit code. The result phase state creation means generates a Galois type result code by multiplying the start code and the difference code by a Galois field, and thus is disclosed in Patent Document 1. Compared with the process using square calculation in the code generator, the calculation load related to the generation of the result code is reduced, and the result code can be generated efficiently. Further, unlike the code generator disclosed in Patent Document 1, it is not necessary to prepare two types of code generation processes in advance, so that various condition determination processes are not required, and the load related to the generation of the result code is further reduced. Can do.

  A preferred embodiment in which a code generation apparatus according to the present invention is applied to a code generation unit of a spread spectrum signal reception system will be described and described below with reference to the accompanying drawings.

  As shown in FIG. 1, the code generation unit (code generation device) 8 according to the present embodiment is disposed in the positioning calculation control unit 22 of the spread spectrum signal reception system 12. The spread spectrum signal reception system 12 includes a frequency conversion unit 16, an A / D conversion unit 18, a reception signal processing unit 20, and a positioning calculation control unit 22, for example, a vehicle not shown as an in-vehicle GPS reception module. It is mounted on.

  Here, when a spread spectrum signal transmitted from a satellite (not shown) via radio is received by the antenna 14 of the spread spectrum signal receiving system 12, the frequency converter 16 converts the spread spectrum signal into a signal of an intermediate frequency. The A / D converter 18 down-converts and outputs the signal to the A / D converter 18. The A / D converter 18 converts the spread spectrum signal from an analog signal to a digital signal and outputs the signal to the received signal processor 20. Note that the spread spectrum signal receiving system 12 includes the received signal processing units 20 for a predetermined number of channels (usually 8 to 16 channels), but in FIG. 1, only the received signal processing units 20 for one channel are shown. Show.

When the spread spectrum signal is an L2C signal, the L2C signal superimposes a carrier wave of a predetermined frequency on the navigation message in the satellite, and further, a CM code as a spread code (repetition cycle: 10230 bits / cycle) And a signal spread spectrum by CL code (repetition cycle: 767250 bits / cycle). Further, the CM code and the CL code are code sequences that are unique to each satellite and are different from each other among the satellites, and among the M-sequence code sequences generated by the satellites, a predetermined start position and This code has a specified range between the end position. Therefore, when the spectrum spread signal is received from each of the plurality of satellites by the antenna 14, the CM code and the CL code of each satellite are designated differently in (2 ²⁷ -1) M-sequence code strings. Will be occupied.

  The received signal processing unit 20 includes a carrier correlation unit 24, a code correlation unit 26, a code generation unit 10, a carrier NCO (numerically controlled oscillator) 28, and a code generation NCO 30.

  The carrier NCO 28 generates a local carrier having the same frequency as the down-converted carrier wave, and outputs the local carrier to the carrier wave correlation unit 24. The carrier correlation unit 24 multiplies the digital signal from the A / D conversion unit 18 by the local carrier from the carrier NCO 28 and outputs the baseband signal from which the down-converted carrier is removed to the code correlation unit 26. . The code generating NCO 30 outputs a clock signal having a predetermined frequency to the code generating unit 10.

  Based on the clock signal from the code generating NCO 30, the code generator 10 generates a spread code (hereinafter also referred to as a spread code) in phase with the CM code and the CL code in the baseband signal, and performs code correlation. To the unit 26. The code correlator 26 multiplies the baseband signal from the carrier correlator 24 and the spreading code from the code generator 10 and outputs the multiplication result to the positioning calculation controller 22 as a correlation value.

  The positioning calculation control unit 22 outputs a local carrier control value (frequency and phase) for adjusting the local carrier to the carrier NCO 28 in order to capture and track the spread spectrum signal based on the correlation value (carrier wave). (Phase tracking loop), a code control value (frequency and phase) for adjusting the generation timing of the spreading code is output to the code generating NCO 30 (code phase tracking loop).

  The carrier NCO 28 outputs the local carrier to the carrier correlation unit 24 so that the carrier wave and the local carrier are phase-synchronized based on the local carrier control value. Further, the code generating NCO 30 outputs the clock signal to the code generating unit 10 based on the code control value so that the CM code, the CL code, and the spreading code are phase-synchronized.

  As a result, in the received signal processing unit 20, the phase synchronization between the spread code and the CM code and the CL code and the phase synchronization between the local carrier and the carrier are respectively performed, and the spread spectrum signal Capturing and tracking can be performed. In addition, the positioning calculation control unit 22 reproduces navigation data from the correlation value, and further, the carrier phase of each spread spectrum signal from a plurality of satellites, the Doppler frequency, and the simulation from each satellite to the spread spectrum signal receiving system 12. From the distance, the current position of the system 12, the speed of the vehicle on which the system 12 is mounted as an in-vehicle GPS receiving module, and the current time can be obtained. Note that correction data for correcting the current position, the speed, and the current time are also input to the positioning calculation control unit 22 from the outside.

  Further, when the positioning calculation control unit 22 captures and tracks the spread spectrum signal, the information related to the CM code and CL code included in the spread spectrum signal (the start position and end position of the CM code and CL code in the M series). The code generator 8 generates an initial setting value including information related to the position and the specified range, and information indicating that the CM code or CL code is located at a predetermined position in the specified range. Output to. Accordingly, the code generator 10 generates a spread code synchronized with the predetermined position (phase) of the CM code and the CL code included in the spread spectrum signal from the initial setting value and the clock signal, and generates a code correlation. To the unit 26.

  Next, the configuration of the code generation unit 8 according to the present embodiment that calculates the initial setting value (result code in the result phase state) will be described with reference to the block diagrams of FIGS.

  3 and 4, as an example, a start sequence creation unit (first code generator) 52, a start phase state creation unit (second code generator) 56, a start phase state update unit 60, and a differential phase state update Although the case where the unit 74 and the result series development unit 80 are configured as a linear feedback shift register (code generator) having a four-stage (4-bit) shift register is illustrated, a linear feedback shift of a predetermined bit other than 4 bits is illustrated. It can also be configured as a register.

  The code generation unit 8 includes a start phase state creation unit 40, a differential phase state creation unit 42, and a result phase state creation unit 44.

  The start phase state creation means 40 includes a start phase state setting unit (sixth code generator) 50, a start sequence creation unit (first code generator) 52, a start sequence temporary storage unit 54, and a start phase state creation unit. (Second code generator) 56, a start phase state storage unit 58, and a start phase state update unit 60.

  The start phase state setting unit 50 outputs a Galois type start code (start code) (4-bit binary code) having the phase at the start position of the spread spectrum signal as the start phase state to the start sequence creation unit 52.

  As shown in FIG. 3, the start sequence creation unit 52 is a reciprocal Galois type linear feedback shift register having four registers 100 to 106 and an XOR element 108. In this linear feedback shift register, the first register 100, the XOR element 108, the second to fourth registers 102 to 106 are connected in this order, and the data (1 or 0) of each bit of the start code is stored in the first to fourth registers. 100 to 106 are input. The output of the fourth register 106 is input to the first register 100 and the XOR element 108, and the XOR element 108 obtains the exclusive OR of the output of the first register 100 and the output of the fourth register 106. Output to. In this case, every time a clock signal is input from a clock generation unit (not shown) in the positioning calculation control unit 22, the state in the first to fourth registers 100 to 106 (the state of bits S0 to S3) becomes the next register. In addition to shifting sequentially (changing by a predetermined cycle), the state (1 or 0) of the bit S0 of the first register 100 is sequentially output to the start sequence temporary storage unit 54.

  The start sequence temporary storage unit 54 temporarily stores a 4-bit code sequentially input from the first register 100 of the start sequence creation unit 52.

  The start phase state creation unit 56 is a reciprocal Fibonacci type linear feedback shift register having four registers 110 to 116 and an XOR element 118. In this linear feedback shift register, the data (1 or 0) of each bit of the start code connected in the order of the first to fourth registers 110 to 116 and stored in the start sequence temporary storage unit 54 is the first to first registers. Input to the fourth registers 110 to 116. In this case, the start code from the start sequence temporary storage unit 54 is the start code converted from the Galois type to the reciprocal Fibonacci type by the start sequence creation unit 52.

  Further, the XOR element 118 outputs the exclusive OR of the output of the third register 114 and the output of the fourth register 116 to the first register 110. In this case, every time the clock signal is input, the state in the first to fourth registers 110 to 116 (the state of bits S0 to S3) is sequentially shifted to the next register (changes by a predetermined cycle), and The state of the bit S0 of the first register 110 is sequentially output to the start phase state storage unit 58.

  The start phase state storage unit 58 stores a reciprocal Fibonacci type 4-bit start code input from the first register 110 of the start phase state creation unit 56.

  The start phase state update unit 60 is a Fibonacci type linear feedback shift register having four registers 120 to 126 and an XOR element 128. In this linear feedback shift register, the first to fourth registers 120 to 126 are connected in this order, and the XOR element 128 outputs the exclusive OR of the output of the first register 120 and the output of the fourth register 126 to the first register 120. Output. In this case, every time the clock signal is input, the states (bits S0 to S3) in the first to fourth registers 120 to 126 are sequentially shifted (changed by a predetermined cycle) and the start phase state is stored. The 4-bit start code stored in advance in the unit 58 is updated to the states of the bits S0 to S3 of the first to fourth registers 120 to 126.

  As shown in FIGS. 2 and 4, the differential phase state creation unit 42 includes a differential phase state creation unit (third code generator) 62, a differential phase state temporary storage unit 64, and a difference sequence creation unit (fourth code). Generator) 66, a difference sequence storage unit 68, a difference sequence expansion unit (fifth code generator) 70, a difference phase state storage unit 72, and a difference phase state update unit 74.

  Similar to the start sequence creation unit 52, the differential phase state creation unit 62 is configured by a reciprocal Galois type linear feedback shift register, and based on an initial setting signal from the positioning calculation control unit 22, a Galois type unit code ( The phase of the unit code) is set as the unit phase state, and this phase is changed by 3 cycles {= 4 (the number of bits of the linear feedback shift register) -1}, and the unit code changed by 3 cycles is stored in the differential phase state temporary storage unit. 64.

  The differential phase state temporary storage unit 64 temporarily stores the Galois type 4-bit unit code input from the differential phase state generation unit 62.

  Similar to the differential phase state update unit 74 and the result sequence expansion unit 80 (see FIG. 4), the differential sequence creation unit 66 includes a Galois type linear feedback shift register (a 4-bit code generator). The phase of the 4-bit unit code temporarily stored in the state temporary storage unit 64 is set to the initial phase state, and each time the clock signal is input, the maximum addition cycle amount (for example, the linear feedback shift register) 6 cycles) (maximum value of cycle amount for changing the state of each register of the linear feedback shift register. In the case of the L2C signal, designation between the start position and the end position in the CM code and CL code Range, ie maximum length of CM code and CL code) and 3 cycles {= 4 (the linear feedback shift Only 9 cycles obtained by adding the register number of bits) -1} is the state sequentially shifts of the respective registers, and sequentially outputs the state of the first register (not shown) to the difference sequence storing section 68.

  The difference series storage unit 68 stores Galois type 10-bit codes that are sequentially input from the difference series creation unit 66. In this case, the difference series storage unit 68 stores each bit in the code in association with 10 addresses (address 0 to address 10).

  Similar to the differential phase state update unit 74 and the result sequence expansion unit 80 (see FIG. 4), the differential sequence expansion unit 70 includes a Galois linear feedback shift register (a 4-bit code generator), and the clock Each time a signal is input, a predetermined addition cycle (for example, 5 cycles) at address 0 among 10-bit codes temporarily stored in the difference series storage unit 68 (in the case of an L2C signal, a CM code) And an address 5 obtained by adding a cycle amount corresponding to the difference between the start position of the CL code and the predetermined position of the CM code and the CL code in the initial setting signal as an initial position. The data for 4 cycles (bits) until is obtained sequentially, and the state of each register in the 4th cycle is changed to 4-bit code, that is, the start position (start phase State) and outputs to the predetermined position (differential phase state storage unit 72 as a result the phase state) and Galois-type 4-bit differential code corresponding to the phase difference (difference code). Thereby, the differential phase state storage unit 72 stores the Galois type 4-bit difference code input from the differential sequence expansion unit 70.

  The differential phase state update unit 74 is a Galois linear feedback shift register having four registers 130 to 136 and an XOR element 138, as shown in FIG. In this linear feedback shift register, the first to fourth registers 130 to 136 are connected in this order, and the XOR element 138 sends the exclusive OR of the output of the first register 130 and the output of the second register 132 to the first register 130. Output. In this case, each time the clock signal is input, the states (bits S0 to S3) in the first to fourth registers 130 to 136 are sequentially shifted (changed by a predetermined cycle), and the differential phase state storage unit The 4-bit code stored in 72 is updated to the states of bits S0 to S3 of the first to fourth registers 130 to 136.

  As shown in FIGS. 2 and 4, the result phase state creation unit 44 includes a bit calculation unit 76, a result series storage unit 78, a result series development unit 80, a result phase state storage unit 82, and an output unit 84.

  Each time the clock signal is input, the bit calculation unit 76 generates a reciprocal Fibonacci type start code stored in the start phase state storage unit 58 and a Galois type difference stored in the differential phase state storage unit 72. A Galois field operation is performed to multiply the code and calculate an exclusive OR for the multiplication result, and the operation result (1 or 0) is sequentially output to the result series storage unit 78.

  The result series storage unit 78 stores a numerical value of 1 or 0 indicating the operation result sequentially input from the bit operation unit 76 as a Galois type 4-bit code.

  The result series expansion unit 80 is a Galois linear feedback shift register having four registers 140 to 146. In this linear feedback shift register, the second to fourth registers 142 to 146 are connected in this order, and the output of the first register 140 is input to the fourth register 146. In this case, every time the clock signal is input, the states (bits S0 to S3) in the first to fourth registers 140 to 146 are sequentially shifted (changed by a predetermined cycle), and the registers 140 to 146 are also changed. (1 or 0) is output to the result phase state storage unit 82.

  The result phase state storage unit 82 stores a numerical value of 1 or 0 input from each of the registers 140 to 146 of the result series development unit 80 as a Galois type 4-bit result code.

  The output unit 84 extracts the result code stored in the result phase state storage unit 82 and outputs the result code to the code generation unit 10 as an initial set value.

  Next, the operation of the code generation unit 8 according to this embodiment (initial setting value generation operation) will be described with reference to FIGS.

  Here, generation of an initial setting value (result code) including a desired phase state (result phase state) when each linear feedback shift register in the code generation unit 8 is the above-described 4-bit shift register will be described. .

  5A to 5D are tables showing the shift (cycle) of the state of each register in the 4-bit linear feedback shift register. That is, FIG. 5A is a table regarding a Galois type linear feedback shift register, FIG. 5B is a table regarding a Fibonacci type linear feedback shift register, and FIG. 5C is a table regarding a reciprocal Galois type linear feedback shift register. FIG. 5D is a table relating to a reciprocal Fibonacci type linear feedback shift register.

  In the following description, a Galois type start code (S3, S2, S1, S0) = (0, 1, 1, 1) in the code generation unit 8 (see cycle 5 indicated by arrow a in FIG. 5A). (S3, S2, S1, S0) = (0, 1, 1, 0) (refer to cycle 10 indicated by arrow b in FIG. 5A). The case where a Galois result code (initial setting value) in the result phase state is generated will be described.

  First, the start phase state setting unit 50 in the code generation unit 8 has a Galois type start code (S3, S2, S1, S0) = (0, 1, 1, 1) (Refer to cycle 10 shown by arrow c in FIG. 5C) is set, and this start code is output to start sequence creation unit 52.

  The reciprocal Galois type start sequence creation unit 52 sets the value of each bit in the start code input from the start phase state setting unit 50 in each register 100 to 106, and the state of each register 100 to 106 at this time Is set to the initial phase state in the start sequence creation unit 52, and each time the clock signal is input, the states in the first to fourth registers 100 to 106 are shifted in order, and the bit S0 of the first register 100 is changed. The state is sequentially output to the start sequence temporary storage unit 54. In this case, when the start sequence creation unit 52 shifts the state of each of the registers 100 to 106 by 3 cycles (= 4-1), the start sequence temporary storage unit 54 stores (0 cycle, 1 cycle, 2 cycles, 3 cycles). (Cycle) = (S3, S2, S1, S0) = (1, 0, 1, 1) code is temporarily stored (see bit S0 of cycles 10 to 13 shown by arrow d in FIG. 5C. The code corresponds to cycle 10 indicated by arrow e in FIG. 5D.)

  The reciprocal Fibonacci-type start phase state creation unit 56 first sets the value of each bit in the codes (1, 0, 1, 1) stored in the start sequence temporary storage unit 54 in the registers 110 to 116. Then, after the states of the registers 110 to 116 at this time are set to the initial phase state in the start phase state creation unit 56, the states in the first to fourth registers 110 to 116 are changed each time the clock signal is input. The state of bit S0 of the first register 110 is sequentially output to the start phase state storage unit 58 by shifting in order. In this case, when the start phase state creation unit 56 shifts the states of the registers 110 to 116 by three cycles (see cycle 10 to cycle 13 indicated by the arrow f in FIG. 5D), the start phase state storage unit 58 stores A reciprocal Fibonacci-type start code of (0 cycle, 1 cycle, 2 cycles, 3 cycles) = (S0, S1, S2, S3) = (1, 1, 1, 0) is stored.

  Based on the initial setting signal, the reciprocal Galois-type differential phase state creation unit 62 generates a unit code of unit phase states (S3, S2, S1, S0) = (0, 0, 0, 1) (arrow in FIG. 5C). (see cycle 0 indicated by g) is set as an initial phase state, and each time the clock signal is input, the state of each register is shifted by 3 cycles (= 4-1) and changed by 3 cycles ( S3, S2, S1, S0) = (1, 0, 0, 0) (see cycle 3 indicated by arrow h in FIG. 5C) is output to the differential phase state temporary storage unit 64.

  First, the Galois type difference series creation unit 66 stores each code in the code (1, 0, 0, 0) (see cycle 12 indicated by arrow i in FIG. 5A) stored in the differential phase state temporary storage unit 64. Each time the clock signal is input after the bit value is set in each register and the state of each register at this time is set to the initial phase state in the difference series creating unit 66, the maximum value in the linear feedback shift register is set. The state of each register is sequentially shifted by 9 cycles obtained by adding the addition cycle amount (6 cycles) and 3 cycles (= 4-1) (see cycle 12 to cycle 6 shown by arrow j in FIG. 5A). The state of the bit S0 of the first register is sequentially output to the difference series storage unit 68. In this case, when the difference series creation unit 66 shifts the state of each register by the above-described nine cycles, the difference series storage unit 68 stores the address (0, 1, 2, 3, 4, 5, 6, 7, 8, 9) = (0, 0, 0, 1, 1, 1, 1, 0, 1, 0) Galois type differential code is stored.

  First, the Galois type difference sequence development unit 70 sets the state in each register to 0, and sets the state of each register at this time to the initial phase state {(S3, S2, S1,. S0) = (0, 0, 0, 0)} and each time the clock signal is input, the Galois-type code stored in the difference series storage unit 68 is sequentially extracted from the smallest number. Are set in the first register, and the state of each register is sequentially shifted, and the state of each register in a predetermined cycle is output to the differential phase state storage unit 72 as a 4-bit Galois type differential code.

  In this case, the cycle amount corresponding to the difference between the above-described start position (start phase state) and a predetermined position (the position of the spread code to be output from the code generator 10 and the result phase state) is 5 cycles. For example, the difference series development unit 70 uses the address 5 in the fifth cycle from the address 0 as the data extraction start address, and for every three cycles from the start address (address 5) to the address 8 every time the clock signal is input. Only the data from the difference series storage unit 68 is taken out and set in the first register, and the state of each register is shifted in order. Accordingly, the differential phase state storage unit 72 stores the 4-bit Galois type difference code {(), which is the state of each register when the state of the shift register is shifted by three cycles in the difference series development unit 70. S3, S2, S1, S0) = (0, 1, 1, 1)} (see cycle 5 indicated by arrow a in FIG. 5A) is stored.

  Each time the clock signal is input, the bit operation unit 76 stores the reciprocal Fibonacci type start code stored in the start phase state storage unit 58 (for example, (S3, S2, S1, S0) = (0 , 1, 1, 1)} and a Galois type difference code stored in the differential phase state storage unit 72 {eg, (S3, S2, S1, S0) described above = (0, 1, 1, 1) }, And performs a Galois field operation to calculate an exclusive OR for the multiplication result, and sequentially outputs the operation result (1 for each of the 4-bit codes described above) to the result series storage unit 78. Each time the clock signal is input, the start phase state update unit 60 or the differential phase state update unit 74 causes the start phase state storage unit 58 or the differential phase state storage unit 72 to set the above-described 4 bits as the initial phase state. Since new codes are sequentially stored, the calculation result of the Galois field calculation is sequentially stored from the bit calculation unit 76 to the result series storage unit 78. For example, if the result of the Galois field operation in the bit operation unit 76 is in the order of 1, 1, 0, 0, a Galois type code of (1, 1, 0, 0) is stored in the result series storage unit 78. The

  The Galois type result series expansion unit 80 first sets the state of each of the registers 140 to 146 to 0 and sets the state of each of the registers 140 to 146 to the initial phase state in the result series expansion unit 80. Each time the clock signal is input, the value of each bit of the Galois type code stored in the result series storage unit 78 is sequentially extracted and set in the first register 140, and the registers 140 to 146 are also stored. The states are sequentially shifted, and the states of the bits S0 to S3 of the registers 140 to 146 are sequentially output to the result phase state storage unit 82. In this case, when the result series development unit 80 shifts the state of each of the registers 140 to 146 by four cycles, the result phase state storage unit 82 stores (S3, S2, S1, S0) = (0, 1, 1, 0) Galois-type result code is stored (see cycle 10 shown by arrow b in FIG. 5A).

  The output unit 84 extracts the result code (0, 1, 1, 0) stored in the result phase state storage unit 82 and outputs it to the code generation unit 10 as an initial set value.

  In the process of generating the result code (initial setting value), the Fibonacci-type start phase state update unit 60 stores the 4-bit code (S3, S2, S1, S0) stored in the start phase state storage unit 58 = After setting (0, 1, 1, 1) in the first to fourth registers 120 to 126, every time the clock signal is input, the state (bit S0) in the first to fourth registers 120 to 126 is set. To S3) are sequentially shifted one cycle at a time, and the code stored in the start phase state storage unit 58 is updated to the state of bits S0 to S3 (cycle 2 to cycle indicated by arrow k in FIG. 5B). 5).

  On the other hand, the Galois-type differential phase state update unit 74 sets the 4-bit code (S3, S2, S1, S0) = (0, 1, 1, 1) stored in the differential phase state storage unit 72 to the first. Each time the clock signal is input after setting to the fourth registers 130 to 136, the states (bits S0 to S3) in the first to fourth registers 130 to 136 are sequentially shifted one cycle at a time. Thus, the code stored in the differential phase state storage unit 72 is updated to the state of the bits S0 to S3.

  The start code update process by the start phase state update unit 60 described above is performed when the start code is stored in advance in the start phase state storage unit 58. In this case, the difference phase state update unit The update process of the difference code by 74 is not performed. On the other hand, the update process of the difference code by the difference phase state update unit 74 is performed when the difference code is stored in the difference phase state storage unit 72 in advance. In this case, the start phase state update unit The start code update process by 60 is not performed. When the start code is stored in advance in the start phase state storage unit 58 and the difference code is stored in advance in the differential phase state storage unit 72, each update process described above can be performed. Of course.

  Thus, according to the present embodiment, the Galois type, reciprocal Galois type, Fibonacci type, and reciprocal Fibonacci type linear feedback shift registers (code generators) in the start phase state creation unit 40 and the differential phase state creation unit 42 are as follows. Only the process of changing the phase of the start code (start phase state) and the phase of the unit code by a predetermined cycle is performed, and the result phase state creation means 44 multiplies the start code and the difference code by Galois field multiplication to obtain a Galois type result. Since the code (initial setting value for generating the spreading code) is generated, the calculation load related to the generation of the result code compared to the process using the square calculation in the code generator disclosed in Patent Document 1 Is reduced, and the resulting code can be generated efficiently. In addition, unlike the code generator of Patent Document 1, it is not necessary to prepare two types of code generation processes in advance, and various condition determination processes are also unnecessary, thereby further reducing the load related to the generation of result codes. Can do.

  Further, since the code generation unit 8 includes the start phase state storage unit 58 and the differential phase state storage unit 72, when a plurality of spread codes, or a plurality of CM codes and CL codes are known, that is, the CM code If the start position of the CL code and the maximum addition cycle amount are defined, and therefore it is possible to create the start code and the difference code in advance, the start code is stored in the start phase state storage unit 58 in advance. If the difference code is stored in the difference phase state storage unit 72 in advance, when the result code is repeatedly created, the start code generation process in the start phase state creation unit 40 and the difference in the difference phase state creation unit 42 Since code generation processing is not required, the result code can be generated with less calculation load as the entire code generation unit 8. Furthermore, in the CM code and CL code from each satellite, if the desired position of each code from the start position is the same within each specified range, a result code can be generated using one type of difference code. As a result, the memory capacity of the differential phase state storage unit 72 can be saved.

  In this case, since the code generation unit 8 includes the start phase state update unit 60 and the differential phase state update unit 74, the start code generation process in the start phase state creation unit 40 and the difference code in the differential phase state generation unit 42 It is possible to repeatedly generate a result code in a desired result phase state without performing a generation process.

  Further, since the result phase state creation unit 44 includes the bit arithmetic unit 76 that performs Galois field multiplication and the Galois type result series expansion unit 80, the result phase state creation unit 44 is also involved in the generation of the result code. The calculation load can be reduced and the resulting code can be generated more efficiently.

  Therefore, if such a code generator 8 is applied to the spread spectrum signal receiving system 12, the code generator 10 can easily generate a spread code phase-synchronized with the CM code or the CL code from the result code (initial setting value). It is possible to generate the spectrum spread signal and multiply the spread spectrum signal from the satellite by the spread code, thereby efficiently capturing and tracking the spread spectrum signal.

  In the above description, the case where the code generation unit 8 generates a Galois type result code (initial setting value) from the Galois type start code has been described.

  Here, when generating a Fibonacci-type result code from a Fibonacci-type start code, first, the start phase state setting unit 50 of the start phase state creating means 40 is used, and the Fibonacci-type start code is changed to a Galois type start code. It is configured as a linear feedback shift register that converts and outputs to the start sequence creation unit 52. Regarding the differential phase state creation means 42, the differential phase state creation unit 62 is configured as a reciprocal Fibonacci type linear feedback shift register, and the differential sequence creation unit 66 and the differential sequence expansion unit 70 are configured as a Fibonacci type linear feedback shift register. Further, in the result phase state creation means 44, the result series expansion unit 80 is configured as a Fibonacci type linear feedback shift register that converts a Galois type result code into a Fibonacci type result code.

  Thus, in one code generation unit 8, it is possible to generate a Galois type result code from the Galois type start code and further generate a Fibonacci type result code from the Fibonacci type start code.

  It goes without saying that the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.

It is a block diagram of the spread spectrum signal receiving system to which the code generation part concerning this embodiment is applied. It is a block diagram of the code generation part of FIG. FIG. 3 is a block diagram of a start phase state creation unit in FIG. 2. FIG. 3 is a partial block diagram of a differential phase state creation unit and a result phase state creation unit in FIG. 2. FIG. 5A is a table showing the cycle of each register state in the Galois linear feedback shift register, and FIG. 5B is a table showing the cycle of each register state in the Fibonacci linear feedback shift register. FIG. 5D is a table showing a cycle of each register state in the reciprocal Galois linear feedback shift register, and FIG. 5D is a table showing a cycle of each register state in the reciprocal Fibonacci linear feedback shift register.

Explanation of symbols

DESCRIPTION OF SYMBOLS 8 ... Code generation part 10 ... Code generation part 12 ... Spread spectrum signal reception system 20 ... Reception signal processing part 40 ... Start phase state creation means 42 ... Difference phase state creation means 44 ... Result phase state creation means 50 ... Start phase state setting Unit 52 ... start sequence creation unit 54 ... start sequence temporary storage unit 56 ... start phase state creation unit 58 ... start phase state storage unit 60 ... start phase state update unit 62 ... differential phase state creation unit 64 ... differential phase state temporary storage unit 66 ... Difference series creation unit 68 ... Difference series storage unit 70 ... Difference series development unit 72 ... Difference phase state storage unit 74 ... Difference phase state update unit 76 ... Bit operation unit 78 ... Result series storage unit 80 ... Result series development unit 82 ... result phase state storage unit 84 ... output units 100-106, 110-116, 120-126, 130-136, 140-146 ... register 108, 18,128,138 ... XOR element

Claims (2)

In a code generation device that generates a result code of a desired result phase state by changing the phase by a predetermined cycle with the phase of the start code as a start phase state,
A starting phase state creating means having a reciprocal Galois type first code generator and a reciprocal Fibonacci type second code generator;
Differential phase state creation means having a reciprocal Galois or reciprocal Fibonacci third code generator, and a Galois or Fibonacci fourth code generator and a fifth code generator;
A result phase state creation means;
With
The first code generator converts the start code from a Galois type start code to a reciprocal Fibonacci type start code by changing the phase of the start code by a predetermined cycle,
The second code generator further changes the phase of the reciprocal Fibonacci-type start code by a predetermined cycle, and outputs the start code having the phase changed to the result phase state creating means,
The third code generator changes the phase by a predetermined cycle with the phase of the unit code as a unit phase state,
The fourth code generator further changes each phase of the unit code in the unit code while changing the phase of the unit code that has changed the phase by a predetermined cycle based on the maximum cycle amount that can change the phase of the unit code. The address data is sequentially output to the fifth code generator,
The fifth code generator is a predetermined address determined based on a cycle amount corresponding to a phase difference between the start phase state and the result phase state among new codes composed of the sequentially input data. Output the data at the result phase state creating means as a differential code corresponding to the phase difference,
The result phase state creating means generates the result code by multiplying the start code from the second code generator and the difference code from the fifth code generator by Galois field multiplication. A code generation device.   A spread spectrum signal receiving system comprising the code generation device according to claim 1, wherein the result code generated and output by the code generation device is a code for capturing and tracking a spread spectrum signal from a satellite.

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