CN114296111A - Ranging code generation method compatible with continuous and pulse navigation signals - Google Patents
Ranging code generation method compatible with continuous and pulse navigation signals Download PDFInfo
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- CN114296111A CN114296111A CN202111651208.6A CN202111651208A CN114296111A CN 114296111 A CN114296111 A CN 114296111A CN 202111651208 A CN202111651208 A CN 202111651208A CN 114296111 A CN114296111 A CN 114296111A
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Abstract
The invention discloses a method for generating a ranging code compatible with continuous and pulse navigation signals, which comprises the steps of generating a G1 sequence and a G2 sequence by shifting a feedback shift register; generating a reset control clock at the time of the whole millisecond, and controlling G1, G2, a chip counter and a time slot counter to reset; setting sequence periods of G1 and G2 respectively; the shift control clock generates a CA sequence and a CB sequence by continuously shifting the two feedback shift registers; the CA sequence and the CB sequence are subjected to XOR to obtain a ranging code low bit with two bit widths; controlling a chip counter to count chips and generating a driving signal when the chip counter reaches a module value; the time slot counter selects a control signal to control and generate a high bit of a ranging code according to the driving signal and by receiving a time sequence; and combining the high bits of the ranging code and the low bits of the ranging code to generate the ranging code compatible with continuous and pulse navigation signals. The invention can compatibly capture and track satellite continuous signals and pseudo satellite pulse signals, and expands the baseband processing capability.
Description
Technical Field
The invention relates to the technical field of satellite navigation, in particular to a ranging code generation method compatible with continuous and pulse navigation signals.
Background
The satellite navigation system is based on navigation signals broadcast by satellites in space and provides positioning, speed measuring and time service functions for a satellite navigation receiver. The current major navigation systems include the Beidou satellite navigation System (BDS) in China, the Global Positioning System (GPS) in the United states, the Russian Global navigation satellite System (GLONASS), and the Galileo System (Galileo) in Europe.
The ranging code generator is an important unit of the satellite navigation receiver, and mainly generates the ranging code of the navigation signal. At present, the satellite navigation system mainly adopts a continuous CDMABPSK signal format, namely, the ranging code signal continuously exists in the whole time period. Basic tasks of a satellite navigation receiver: the method comprises the steps of capturing signals of visible satellites, tracking the operation of the satellites, carrying out a series of processing on the received GNSS signals so as to measure the distance and the change rate of the distance of the GNSS signals from the satellites to a receiver antenna, analyzing navigation messages sent by the satellites, and further calculating the three-dimensional position, the speed and the time of the receiver antenna. Pseudolites are generally arranged on the ground, and independently broadcast a navigation enhancement signal similar to a real satellite navigation signal and differential information, so that a navigation enhancement function can be provided for a pseudolite coverage area. By arranging the pseudolites, the number of visible stars can be increased, and the positioning effectiveness is improved; meanwhile, the space geometric distribution of the satellite is improved, the space position accuracy factor (PDOP) is reduced, and the positioning accuracy is improved.
In order to effectively inhibit the near-far effect, most of the current regional enhanced pseudolite signals adopt a TDMA + CDMA BPSK signal format, namely pulse navigation pulse signals, and the traditional ranging code generator circuit cannot generate pulse ranging codes and cannot be compatible with continuous navigation signals and pulse navigation signals.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a ranging code generation method compatible with continuous and pulse navigation signals, wherein the traditional ranging code generator circuit is optimized and improved, the original ranging code is improved from a 1-bit-width representation mode to a 2-bit-width mode, the improved ranging code can represent a continuous form ranging code and a pulse form ranging code, and a tracking satellite continuous signal and a pseudo satellite pulse signal can be compatibly captured and tracked.
The purpose of the invention is realized by the following technical scheme:
a method for generating a ranging code compatible with continuous and pulsed navigation signals, comprising:
the method comprises the following steps: generating a G1 sequence and a G2 sequence by using a feedback shift register;
step two: generating a reset control clock at the time of the whole millisecond, and controlling the reset of the G1 sequence, the G2 sequence, the chip counter and the time slot counter;
step three: setting sequence periods of the G1 sequence and the G2 sequence respectively;
step four: the shift control clock generates a CA sequence and a CB sequence by continuously shifting the two feedback shift registers;
step five: carrying out XOR on the CA sequence and the CB sequence to obtain a ranging code low-order pn _ l with two bit widths;
step six: controlling a chip counter to count chips through a shift control clock, and generating a time slot counter driving signal when a chip count value reaches a module value;
step seven: the time slot counter controls and generates the high-order pn _ h of the ranging code by receiving a time sequence selection control signal according to a time slot counter driving signal;
step eight: and combining the high-order pn _ h of the ranging code and the low-order pn _ l of the ranging code to generate the ranging code compatible with continuous and pulse navigation signals.
Specifically, the first step specifically comprises: the G1 sequence and the G2 sequence are generated by shifting through a feedback shift register, and the generating polynomials are respectively:
G1(X)＝X13+X4+X3+X+1；
G2(X)＝X13+X12+X10+X9+X7+X5+X5+X+1。
specifically, the third step specifically comprises: the period of a CA sequence generated by a G1 sequence is shortened by 1 bit from 8191 chips, the period is changed into 8190 chips, and the phase of a G1 sequence is set to be in a full '1' state at the time of whole millisecond or the time when the phase of the G1 sequence is '1111111111100';
the CB sequence generated by the G2 sequence has a period of 8191 chips and is set to the initial phase of the G2 sequence at the time of the whole millisecond.
Specifically, the seventh step specifically includes: the time slot counter is controlled by receiving a timing selection control signal and can be applied to continuous signals and pulse signals; when the ranging code generator is applied to a pulse signal, the time slot counter generates pulse time slots required by different pseudolites, the time slot of a certain pseudolite is appointed through time slot selection control, and when the time slot counter counts the appointed time slot, the high-order pn _ h of the ranging code is 1, and other moments are 0; the pseudolite timing may be a fixed time slot or a random time slot by time slot selection control;
when the ranging code generator is applied to the continuous signal, the time slot selection control signal controls the high bit of the ranging code output by the time slot counter to be 1 all the time.
Furthermore, the method also comprises the step of improving a circuit of the ranging code generating circuit, wherein the improved ranging code generating circuit comprises a reset control clock, a shift control clock, a feedback shift register A, a feedback shift register B, a chip counter, a time slot counter and a low-order signal output circuit; the reset control clock is respectively connected with the feedback shift register A, the feedback shift register B, the chip counter and the time slot counter; the shift control clock is respectively connected with the feedback shift register A, the feedback shift register B and the chip counter; the output end of the chip counter is connected with the time slot counter; and the input end of the low-order signal output circuit is respectively connected with the output ends of the feedback shift register A and the feedback shift register B.
Further, the method also comprises the step of improving the acquisition and tracking circuit, wherein the improved acquisition and tracking circuit comprises an exclusive-or gate circuit and a selector; the input end of the exclusive-OR gate circuit is connected with the output end of the low-order signal output circuit; and the output end of the selector is respectively connected with the output end of the exclusive-OR gate circuit and the output end of the time slot counter.
The invention has the beneficial effects that:
the invention solves the problem that the traditional code generator can not generate the ranging code compatible with continuous and pulse navigation signals, and the receiver adopts the circuit, and the acquisition and tracking circuit can compatibly acquire and track the satellite continuous signal and the pseudo-satellite pulse signal only by slightly changing the correlator circuit without changing other circuits, thereby expanding the baseband processing capability.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a circuit diagram of a conventional typical ranging code generator generation method;
FIG. 3 is a circuit diagram related to a conventional continuous navigation signal;
FIG. 4 is a block diagram of a ranging code generation circuit of the present invention that is improved to be compatible with continuous and pulsed pilot signals;
fig. 5 is a circuit diagram of a correlator compatible with continuous and pulsed pilot signals after improvement in accordance with the present invention.
Detailed Description
The following detailed description will be selected to more clearly understand the technical features, objects and advantages of the present invention. It should be understood that the embodiments described are illustrative of some, but not all embodiments of the invention, and are not to be construed as limiting the scope of the invention. All other embodiments that can be obtained by a person skilled in the art based on the embodiments of the present invention without any inventive step are within the scope of the present invention.
The first embodiment is as follows:
as shown in fig. 2, a typical ranging code generator is composed of two feedback shift registers, a reset control clock, a shift control clock, and a feedback shift register initial phase. The feedback shift register is a 13-stage register; the reset control clock generates a reset signal at a specific moment, and the initial phase of the feedback shift register is placed into the feedback shift register; the shift control clock is an operation clock for driving the shift register, and is generally a code rate clock. The ranging code pn is a 1-bit wide pseudo code generated by the circuit for ranging.
The ranging code generation method realized by the ranging code generator circuit is as follows:
(1) the ranging code is generated by truncating two linear sequences G1 and G2, modulo two adding, and then truncating. The G1 sequence and the G2 sequence are generated by shifting through a feedback shift register, and the generating polynomials are respectively:
G1(X)＝X13+X4+X3+X+1；
G2(X)＝X13+X12+X10+X9+X7+X5+X5+X+1。
(2) the reset control clock is generated at the time of the whole millisecond, and controls the reset of the G1 sequence and the G2 sequence. The shift control clock drives the shift operation of the feedback shift register.
(3) The CA sequence generated by G1 is truncated by 8191 by 1 bit, and becomes 8190 chips in period. G1 places the phase into the all "1" state at the full millisecond time or G1 phase of "1111111111100".
(4) The CB sequence generated by G2 has a period of 8191 chips. G2 sets the initial phase of G2 at the full millisecond, with the initial phases of different satellites differing.
(5) The shift control clock generates a CA sequence and a CB sequence by successively shifting the two feedback shift registers.
(6) And carrying out XOR on the CA sequence and the CB sequence to obtain a ranging code pn with 1-bit width.
Meanwhile, as shown in fig. 3, in the conventional correlation circuit, data in fig. 3 is intermediate frequency data, pn is 1 bit width ranging code, and data _ xor is a result of performing an exclusive or operation on the intermediate frequency data and the 1 bit width ranging code.
The corresponding correlation calculation table is shown in the following table 1:
table 1: continuous navigation signal correlation value table
For regional augmentation pseudolite signals, in order to effectively inhibit near-far effect, pulse navigation signals, namely TDMA + CDMA signals, are mostly adopted, and the traditional ranging code generator circuit cannot generate pulse-form ranging codes.
In order to effectively inhibit the near-far effect, most of the current regional enhanced pseudo satellite signals adopt a TDMA + CDMA BPSK signal format, namely pulse navigation pulse signals, and in order to realize that a capturing and tracking circuit of a receiver can compatibly receive satellite continuous signals and pseudo satellite pulse signals, the invention optimizes and improves the traditional distance measuring code generator circuit, and the distance measuring code generator circuit can generate and represent continuous form distance measuring codes and pulse form distance measuring codes; meanwhile, the receiver can be compatible with the continuous signals of the acquisition tracking satellite and the pseudo-satellite pulse signals only by slightly changing correlators of the acquisition and tracking circuit and under the condition that other circuits in the acquisition tracking circuit are not changed. The improved method for generating the ranging code comprises the following steps:
as shown in fig. 1, a method for generating a ranging code compatible with continuous and pulsed navigation signals includes:
the method comprises the following steps: generating a G1 sequence and a G2 sequence by using a feedback shift register;
step two: generating a reset control clock at the time of the whole millisecond, and controlling the reset of the G1 sequence, the G2 sequence, the chip counter and the time slot counter;
step three: setting sequence periods of the G1 sequence and the G2 sequence respectively;
step four: the shift control clock generates a CA sequence and a CB sequence by continuously shifting the two feedback shift registers;
step five: carrying out XOR on the CA sequence and the CB sequence to obtain a ranging code low-order pn _ l with two bit widths;
step six: controlling a chip counter to count chips through a shift control clock, and generating a time slot counter driving signal when a chip count value reaches a module value;
step seven: the time slot counter controls and generates the high-order pn _ h of the ranging code by receiving a time sequence selection control signal according to a time slot counter driving signal;
step eight: and combining the high-order pn _ h of the ranging code and the low-order pn _ l of the ranging code to generate the ranging code compatible with continuous and pulse navigation signals.
Specifically, the first step specifically comprises: the G1 sequence and the G2 sequence are generated by shifting through a feedback shift register, and the generating polynomials are respectively:
G1(X)＝X13+X4+X3+X+1；
G2(X)＝X13+X12+X10+X9+X7+X5+X5+X+1。
in this embodiment, the third step specifically includes: the period of a CA sequence generated by a G1 sequence is shortened by 1 bit from 8191 chips, the period is changed into 8190 chips, and the phase of a G1 sequence is set to be in a full '1' state at the time of whole millisecond or the time when the phase of the G1 sequence is '1111111111100';
the CB sequence generated by the G2 sequence has a period of 8191 chips and is set to the initial phase of the G2 sequence at the time of the whole millisecond.
In this embodiment, the seventh step specifically includes: the time slot counter is controlled by receiving a timing selection control signal and can be applied to continuous signals and pulse signals; when the ranging code generator is applied to a pulse signal, the time slot counter generates pulse time slots required by different pseudolites, the time slot of a certain pseudolite is appointed through time slot selection control, and when the time slot counter counts the appointed time slot, the high-order pn _ h of the ranging code is 1, and other moments are 0; the pseudolite timing may be a fixed time slot or a random time slot by time slot selection control;
when the ranging code generator is applied to the continuous signal, the time slot selection control signal controls the high bit of the ranging code output by the time slot counter to be 1 all the time.
Example two:
in this embodiment, as shown in fig. 4, the method further includes performing circuit improvement on the ranging code generating circuit, where the improved ranging code generating circuit includes a reset control clock, a shift control clock, a feedback shift register a, a feedback shift register B, a chip counter, a slot counter, and a low-order signal output circuit; the reset control clock is respectively connected with the feedback shift register A, the feedback shift register B, the chip counter and the time slot counter; the shift control clock is respectively connected with the feedback shift register A, the feedback shift register B and the chip counter; the output end of the chip counter is connected with the time slot counter; and the input end of the low-order signal output circuit is respectively connected with the output ends of the feedback shift register A and the feedback shift register B.
The present embodiment is optimized and improved on the above-mentioned traditional ranging code generator circuit, and adds chip counter, time slot counter and time slot selection control signal. The chip counter is pushed by a shift control clock to count the chips and generate a time slot counter driving signal at the same time; the time slot counter counts the time slots of the pulse navigation signals, and outputs a ranging code high-order pn _ h signal of a designated satellite through the driving signal drive of the time slot counter and the control of a time slot selection control signal.
The method comprises the steps that the original ranging code is improved from a 1-bit-width representation mode to a 2-bit-width mode, wherein the low bit is a continuous chip and is the same as the traditional 1-bit-width ranging code pn, and the low bit is represented as ranging code low bit pn _ l; the high bit is pulse enable, here denoted as ranging code high bit pn _ h; the ranging code with the bit width of 2 is represented in a { pn _ h, pn _ l }, and the improved ranging code can represent a continuous ranging code and a pulse ranging code.
In this embodiment, as shown in fig. 5, the method further includes modifying the capturing and tracking circuit, where the modified capturing and tracking circuit includes an exclusive-or gate and a selector; the input end of the exclusive-OR gate circuit is connected with the output end of the low-order signal output circuit; and the output end of the selector is respectively connected with the output end of the exclusive-OR gate circuit and the output end of the time slot counter.
The improved correlator of the capturing and tracking circuit is shown as follows, in fig. 5, data is intermediate frequency data, { pn _ h, pn _ l } is the improved ranging code, and data _ xor is the result of the correlation operation between the intermediate frequency data and the 2-bit wide ranging code. When pn _ h of the selector in the figure is 0, the output value of the selector is 0, namely the result data _ xor after the correlation operation is 0; when pn _ h is 1, the selector outputs the result of the exclusive OR operation of data _ and pn _ l.
The corresponding correlator calculation table is shown in table 2:
TABLE 2 correlator computation table compatible with continuous and pulsed pilot signals
The main improvements of this embodiment include:
(1) the representation mode of the ranging code is improved from 1 bit to 2 bits, a pulse enabling pn _ h signal circuit is added on a ranging code generator, the pulse enabling signal pn _ h is used as the high bit of the ranging code, the traditional continuous ranging chip pn is used as the low bit pn _ l of the ranging code, and the ranging code { pn _ h, pn _ l } compatible with continuous and pulse navigation signals is generated by combining the high bit pn _ h and the low bit pn _ l of the ranging code.
(2) The correlator circuit of the acquisition and tracking circuit is modified to adapt to the correlation operation of the 2-bit wide ranging code.
The invention optimizes and improves the traditional distance measuring code generator circuit, and the distance measuring code generator circuit can generate the distance measuring code representing the continuous form and the pulse form; meanwhile, the receiver can be compatible with the continuous signals of the acquisition tracking satellite and the pseudo-satellite pulse signals only by slightly changing correlators of the acquisition and tracking circuit and under the condition that other circuits in the acquisition tracking circuit are not changed.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. A method for generating a ranging code compatible with continuous and pulsed navigation signals, comprising:
the method comprises the following steps: generating a G1 sequence and a G2 sequence by using a feedback shift register;
step two: generating a reset control clock at the time of the whole millisecond, and controlling the reset of the G1 sequence, the G2 sequence, the chip counter and the time slot counter;
step three: setting sequence periods of the G1 sequence and the G2 sequence respectively;
step four: the shift control clock generates a CA sequence and a CB sequence by continuously shifting the two feedback shift registers;
step five: carrying out XOR on the CA sequence and the CB sequence to obtain a ranging code low-order pn _ l with two bit widths;
step six: controlling a chip counter to count chips through a shift control clock, and generating a time slot counter driving signal when a chip count value reaches a module value;
step seven: the time slot counter controls and generates the high-order pn _ h of the ranging code by receiving a time sequence selection control signal according to a time slot counter driving signal;
step eight: and combining the high-order pn _ h of the ranging code and the low-order pn _ l of the ranging code to generate the ranging code compatible with continuous and pulse navigation signals.
2. The method as claimed in claim 1, wherein the step one comprises: the G1 sequence and the G2 sequence are generated by shifting through a feedback shift register, and the generating polynomials are respectively:
G1(X)＝X13+X4+X3+X+1；
G2(X)＝X13+X12+X10+X9+X7+X5+X5+X+1。
3. the method as claimed in claim 1, wherein the step three specifically comprises: the period of a CA sequence generated by a G1 sequence is shortened by 1 bit from 8191 chips, the period is changed into 8190 chips, and the phase of a G1 sequence is set to be in a full '1' state at the time of whole millisecond or the time when the phase of the G1 sequence is '1111111111100';
the CB sequence generated by the G2 sequence has a period of 8191 chips and is set to the initial phase of the G2 sequence at the time of the whole millisecond.
4. The method as claimed in claim 1, wherein the seventh step specifically comprises: the time slot counter is controlled by receiving a timing selection control signal and can be applied to continuous signals and pulse signals; when the ranging code generator is applied to a pulse signal, the time slot counter generates pulse time slots required by different pseudolites, the time slot of a certain pseudolite is appointed through time slot selection control, and when the time slot counter counts the appointed time slot, the high-order pn _ h of the ranging code is 1, and other moments are 0; the pseudolite timing may be a fixed time slot or a random time slot by time slot selection control;
when the ranging code generator is applied to the continuous signal, the time slot selection control signal controls the high bit of the ranging code output by the time slot counter to be 1 all the time.
5. The method as claimed in claim 1, further comprising improving the circuit of the ranging code generating circuit, wherein the improved ranging code generating circuit comprises a reset control clock, a shift control clock, a feedback shift register a, a feedback shift register B, a chip counter, a slot counter and a low-order signal output circuit; the reset control clock is respectively connected with the feedback shift register A, the feedback shift register B, the chip counter and the time slot counter; the shift control clock is respectively connected with the feedback shift register A, the feedback shift register B and the chip counter; the output end of the chip counter is connected with the time slot counter; and the input end of the low-order signal output circuit is respectively connected with the output ends of the feedback shift register A and the feedback shift register B.
6. The method of claim 1, further comprising modifying the acquisition and tracking circuit, wherein the modified acquisition and tracking circuit comprises an exclusive-or gate and a selector; the input end of the exclusive-OR gate circuit is connected with the output end of the low-order signal output circuit; and the output end of the selector is respectively connected with the output end of the exclusive-OR gate circuit and the output end of the time slot counter.
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