JP2020053595A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide a semiconductor device and a method of manufacturing the same, capable of suppressing an occurrence of dew condensation on a semiconductor element, applicable also to a case where a leak path is generated in a package and water vapor enters the inside.SOLUTION: The semiconductor device includes: a semiconductor substrate 15A; a semiconductor element 15B formed on the semiconductor substrate 15A; a porous portion 15F fixed to the semiconductor substrate 15A, having a plurality of holes having a diameter of 10 nm or less; and a package covering the semiconductor substrate 15A.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

  Patent Literature 1 discloses a technique for preventing moisture from entering the package by preventing moisture from entering from outside by absorbing moisture from the outside by providing a moisture absorbing means in an internal region of a package for sealing an electronic element. ing.

JP-A-7-322251

In conventional semiconductor devices, sealing a semiconductor element inside the package, which was N ₂ substitution or vacuum, had a structure to protect the semiconductor element from moisture. In this case, when an external force such as an external force or temperature is applied to the package, a crack or the like may be generated in the package and a leak path may be generated. When water vapor enters the inside of the package and the temperature of the package is reduced, the inside of the package is dewed and the semiconductor elements are adversely affected by ion migration.

  The present invention has been made in order to solve the above-described problems, and has a semiconductor device and a semiconductor device capable of suppressing the occurrence of dew condensation on a semiconductor element even when a leak path occurs in a package and water vapor enters the inside. It is an object of the present invention to provide a method for producing the same.

  A semiconductor device according to the invention of the present application includes a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a porous portion fixed to the semiconductor substrate and having a plurality of holes having a diameter of 10 nm or less, and a semiconductor substrate. And a covering package.

  Another semiconductor device according to the invention of the present application includes a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a concavo-convex structure having a plurality of convex portions provided on the semiconductor substrate at intervals of 10 nm or less, and And a package for covering the substrate.

  The method of manufacturing a semiconductor device according to the present invention includes forming two metal patterns surrounding a predetermined portion of a semiconductor substrate on a semiconductor substrate in which a semiconductor element is partially formed; By providing water to a region surrounded by the pattern and applying a voltage to the two metal patterns, a metal is precipitated from a side of the two metal patterns to which a negative voltage is applied, and a pore having a pore diameter of 10 nm or less is formed. Forming a porous portion having a plurality of holes.

  Other features of the present invention will be clarified below.

  According to the present invention, by providing a portion where dew condensation is more likely to occur than a semiconductor element on the same substrate as the semiconductor element, dew condensation occurs on the semiconductor element even when a leak path occurs in the package and water vapor invades inside. Can be suppressed.

FIG. 2 is a sectional view of the semiconductor device according to the first embodiment; It is sectional drawing of a semiconductor chip. It is a top view of a semiconductor chip. It is a top view of the semiconductor chip in which the metal pattern was formed. It is sectional drawing of FIG. FIG. 4 is a diagram showing that a voltage is applied to a metal pattern. It is sectional drawing of FIG. It is a figure which shows metal precipitation. It is sectional drawing of FIG. FIG. 9 is a plan view of a semiconductor device according to a second preferred embodiment; It is a figure showing another example of composition of a porous part. FIG. 14 is a sectional view of a semiconductor device according to a third embodiment; FIG. 14 is a sectional view of a semiconductor device according to a fourth embodiment. It is sectional drawing of the semiconductor device concerning another example.

  A semiconductor device according to an embodiment and a method for manufacturing the semiconductor device will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and description thereof may not be repeated.

Embodiment 1 FIG.
FIG. 1 is a sectional view of the semiconductor device according to the first embodiment. The package of the semiconductor device is, for example, a package in which a frame 10 and a cap 12 are bonded with a sealing material 13. For example, solder can be used as the sealing material 13. In such a package, a leak path 14 may occur due to a crack or the like. The semiconductor chip 15 is stored in the package.

  FIG. 2 is a sectional view of the semiconductor chip 15. The semiconductor chip 15 has a semiconductor substrate 15A. The material of the semiconductor substrate 15A is, for example, GaAs or SiC. A semiconductor element 15B is formed on a part of the semiconductor substrate 15A. The semiconductor element 15B can be, for example, a switching element such as an FET. The semiconductor element 15B includes a source electrode 15C, a gate electrode 15D, and a drain electrode 15E on a semiconductor substrate 15A. Another electrode may be provided.

  The distance x2 between the gate electrode 15D and the drain electrode 15E is, for example, 50 nm or more. The distance x3 between the gate electrode 15D and the source electrode 15C is, for example, 50 nm or more. Thus, the plurality of electrodes are provided at a distance of 50 nm or more. In other words, the electrodes can be arranged such that one electrode of the plurality of electrodes is at least 50 nm away from the remaining electrodes.

  On the semiconductor substrate 15A, a porous portion 15F is fixed beside a region where the semiconductor element 15B is formed. The porous portion 15F has a plurality of pores having a pore diameter of 10 nm or less. FIG. 2 shows a pore diameter x1 of the porous portion 15F. This pore diameter x1 is 10 nm or less. The material of the porous portion 15F is, for example, Au.

  FIG. 3 is a plan view of the semiconductor chip 15. The porous portion 15F surrounds the semiconductor element 15B in a plan view. In this example, the porous portion 15F is provided in an annular shape along the outer edge of the semiconductor substrate 15A. A plurality of pores having pore diameters x1 and y1 of 10 nm or less are formed in the porous portion 15F. Such a semiconductor chip 15 is ideally hermetically sealed by the above-described package that covers the semiconductor substrate 15A.

  Next, a method for manufacturing the above-described semiconductor device will be described. First, a metal pattern is formed around the semiconductor element 15B by vapor deposition, sputtering or plating. FIG. 4 is a plan view of a semiconductor chip on which metal patterns 20A and 20B are formed. As shown in FIG. 4, two metal patterns 20A and 20B surrounding a predetermined portion of the semiconductor substrate 15A are formed on a semiconductor substrate 15A where a semiconductor element 15B is partially formed.

  In the example of FIG. 4, a portion along the outer edge of the semiconductor substrate 15A is surrounded by two metal patterns 20A and 20B. Each of the two metal patterns 20A and 20B is, for example, a rectangular frame. The material of the metal patterns 20A and 20B is, for example, Au, but any metal material can be used. FIG. 5 is a sectional view of FIG. The metal patterns 20A and 20B have a certain thickness, so that a groove is formed in a region sandwiched between them.

  Next, water is provided to a region surrounded by the two metal patterns 20A and 20B, and a water film is provided on this portion. In this state, a voltage is applied to the two metal patterns 20A and 20B. FIG. 6 is a diagram showing that a voltage is applied to the metal patterns 20A and 20B. FIG. 6 illustrates that the power supply 30 applies a positive voltage to the metal pattern 20A and applies a negative voltage to the metal pattern 20B. In this example, the power supply 30 provides a voltage between 1.23 and 100V and a current between 0.1 pA and 1A.

  FIG. 7 is a sectional view of FIG. Water 32 is provided in a region sandwiched between the metal patterns 20A and 20B. Due to the presence of the water 32 and the voltage application by the power supply 30, an electrochemical reaction occurs, the metal is dissolved from the metal pattern 20A to which the positive voltage is applied, and the metal is precipitated on the metal pattern 20B to which the negative voltage is applied, It grows porous. FIG. 8 is a diagram showing metal deposition. The melted metal proceeds from the metal pattern 20A in the direction of the arrow and precipitates on the metal pattern 20B side to which the negative voltage is applied. FIG. 8 shows the deposited metal 42.

  FIG. 9 is a sectional view of FIG. As the deposition of the metal 42 proceeds, a porous portion 15F having a plurality of holes having a diameter of 10 nm or less is formed. Next, the water 32 is dried to leave the porous portion 15F surrounding the semiconductor element 15B. Thus, the semiconductor device shown in FIGS. 1-3 is completed.

  Condensation is more likely to occur on a porous or uneven material surface than on a flat material surface. This phenomenon is called capillary condensation. The smaller the pore diameter of the porous material or the distance between the irregularities, the more easily dew condensation occurs. For example, "Reliability Test of Electronic Components", edited by Hisashi Mine and Kiyoshige Koshikawa, p. 109, describes that dew condensation occurs at a relative humidity of 90% on the surface of a 10-nm-diameter hole.

  In consideration of such technical background, the semiconductor device according to the first embodiment includes a porous portion 15F having a plurality of holes having a diameter of 10 nm or less. For example, when the humidity around the semiconductor element 15B increases due to the intrusion of moisture via the leak path 14, water vapor condenses on the porous portion 15F before the relative humidity becomes 100%. Since the water vapor is condensed and adsorbed on the porous portion 15F before the semiconductor element 15B, the dew condensation on the semiconductor element 15B can be suppressed. Further, by providing the plurality of electrodes separated by 50 nm or more, it is possible to suppress the occurrence of dew condensation due to capillary condensation in the semiconductor element 15B.

  Further, in the present embodiment, since the semiconductor element 15B and the porous portion 15F are formed collectively on the semiconductor substrate 15A, the height can be reduced as compared with the case where the moisture absorbing means is provided at a position away from the semiconductor substrate. . Therefore, the semiconductor device of the present embodiment is suitable for a small package having a small internal capacitance. In addition, since the semiconductor element 15B and the porous portion 15F are collectively formed on the semiconductor substrate 15A, the semiconductor element 15B and the porous portion 15F can be brought close to each other. Can be efficiently absorbed by the quality portion 15F. Since the porous portion 15F is provided around the semiconductor element 15B, the porous portion 15F does not affect the electrical characteristics or high-frequency electrical characteristics of the semiconductor device 15B.

  Various modifications can be made to the semiconductor device and the method of manufacturing the semiconductor device according to the first embodiment without departing from the characteristics thereof. For example, the material of the porous portion 15F may be Al or another metal material instead of Au. The modification described in the first embodiment can be applied to a semiconductor device and a method of manufacturing a semiconductor device according to the following embodiments. The semiconductor device and the method of manufacturing the semiconductor device according to the second embodiment have many points in common with the first embodiment, and therefore, the description will focus on the differences from the first embodiment.

Embodiment 2 FIG.
FIG. 10 is a plan view of the semiconductor device according to the second embodiment. The plurality of porous portions 15F are formed around the semiconductor element 15B in plan view. In this example, four porous portions 15F are provided around the semiconductor element 15B. FIG. 11 is a diagram illustrating another configuration example of the porous portion 15F. In this example, one porous portion 15F is formed beside the semiconductor element 15B in plan view. As described above, the porous portion 15F can be provided at an arbitrary position on the semiconductor substrate 15A. Providing a plurality of porous portions or forming a single island-shaped porous portion improves design flexibility.

  When an island-shaped and non-cyclic porous portion is formed, a circular pattern that can hold water when forming the porous portion and that can apply a voltage is required. Two metal patterns and an insulator that insulates them can provide such an annular pattern. A porous portion can be formed by surrounding a predetermined portion of the semiconductor substrate 15A with an annular pattern and depositing a metal as described above.

Embodiment 3 FIG.
FIG. 12 is a sectional view of the semiconductor device according to the third embodiment. The thermal conductivity of the porous portion 50 is higher than the thermal conductivity of the source electrode 15C, the gate electrode 15D, and the drain electrode 15E. For example, if the material of the electrode is Au or Al, the material of the porous portion 50 can be Ag or Cu.

  According to the semiconductor device of the third embodiment, when the temperature of the package decreases, the temperature of the porous portion 50 having a high thermal conductivity decreases faster than that of the electrode of the semiconductor element 15B. Therefore, dew condensation is likely to occur on the porous portion 50 before the semiconductor element 15B. By combining the effect of dew condensation and adsorption of moisture due to capillary condensation in the porous portion 50 with the effect of adjusting the thermal conductivity, dew condensation can be further concentrated on the porous portion 50. As a result, the amount of water vapor around the semiconductor element 15B decreases, so that dew condensation on the semiconductor element 15B can be suppressed.

  The porous portion 50 may be provided in a ring shape as in the porous portion 15F in FIG. 3, or one or more porous portions 50 may be provided in an island shape as described in the second embodiment.

Embodiment 4 FIG.
FIG. 13 is a cross-sectional view of the semiconductor device according to the fourth embodiment. There are a plurality of protrusions 60 provided at an interval of 10 nm or less on the semiconductor substrate 15A. The plurality of protrusions 60 can be an oxide film or a nitride film formed on the semiconductor substrate 15A. An example of the oxide film is SiO, and an example of the nitride film is SiN. An uneven structure 62 is provided by the plurality of protrusions 60 and the upper surface 15a of the semiconductor substrate 15A. By setting the distance x4 between the plurality of convex portions 60 to 10 nm or less, water vapor easily forms on the concave-convex structure 62. The concavo-convex structure 62 in FIG. 13 can be obtained, for example, by forming an oxide film or a nitride film and then patterning this by dry etching of a fluorine-based gas.

  FIG. 14 is a cross-sectional view of a semiconductor device according to another example. The uneven structure 72 is provided by forming a plurality of grooves 72b in the semiconductor substrate 15A. The groove 72b forms a convex portion 72a, and the convex portion 72a and the groove 72b constitute the uneven structure 72. The distance x4 between the plurality of protrusions 72a is 10 nm or less. The concavo-convex structure 72 in FIG. 14 can be obtained by, for example, wet-etching the GaAs semiconductor substrate 15A with citric acid or hydrofluoric-nitric acid.

  In the concavo-convex structure 62 of FIG. 13 and the concavo-convex structure 72 of FIG. 14, condensation occurs easily because capillary condensation occurs similarly to the porous portion described above. When the humidity around the semiconductor element 15B increases, water vapor condenses on the concave and convex structures 62 and 72 before the semiconductor element 15B, so that dew condensation on the semiconductor element 15B can be suppressed.

  In addition, the uneven structures 62 and 72 may be provided in a ring shape as in the porous portion 15F in FIG. 3, or may be provided in one or a plurality in an island shape as described in the second embodiment.

  Reference Signs List 10 frame, 12 cap, 13 sealing material, 14 leak path, 15 semiconductor chip, 15A semiconductor substrate, 15B semiconductor element, 15C source electrode, 15D gate electrode, 15E drain electrode, 15F porous portion, 20A, 20B metal pattern, 50 Porous part, 62,72 Uneven structure

Claims (14)

A semiconductor substrate;
A semiconductor element formed on the semiconductor substrate;
A porous portion fixed to the semiconductor substrate and having a plurality of pores having a pore size of 10 nm or less,
A package covering the semiconductor substrate.   The semiconductor device according to claim 1, wherein the porous portion surrounds the semiconductor element in a plan view.   The semiconductor device according to claim 1, wherein a plurality of the porous portions are formed around the semiconductor element in a plan view.   The semiconductor device according to claim 1, wherein the porous portion is formed beside the semiconductor element in a plan view.   The semiconductor device according to claim 1, wherein a material of the porous portion is Au or Al. The semiconductor element has an electrode on the semiconductor substrate,
The semiconductor device according to claim 1, wherein a thermal conductivity of the porous portion is larger than a thermal conductivity of the electrode.   7. The semiconductor device according to claim 6, wherein the material of the electrode is Au or Al, and the material of the porous portion is Ag or Cu. A semiconductor substrate;
A semiconductor element formed on the semiconductor substrate;
A concavo-convex structure having a plurality of convex portions provided on the semiconductor substrate at intervals of 10 nm or less;
A package covering the semiconductor substrate.   9. The semiconductor device according to claim 8, wherein the plurality of protrusions are an oxide film or a nitride film formed on the semiconductor substrate.   9. The semiconductor device according to claim 8, wherein the uneven structure is provided by forming a plurality of grooves in the semiconductor substrate. The semiconductor element has a plurality of electrodes on the semiconductor substrate,
11. The semiconductor device according to claim 1, wherein the plurality of electrodes are provided at a distance of 50 nm or more. 12. Forming two metal patterns surrounding a predetermined portion of the semiconductor substrate on a semiconductor substrate on which a semiconductor element is partially formed;
By providing water to a region surrounded by the two metal patterns and applying a voltage to the two metal patterns, a metal is deposited from a side of the two metal patterns to which a negative voltage is applied, and 10 nm is deposited. Forming a porous portion having a plurality of holes having the following hole diameters.   13. The method according to claim 12, wherein the two metal patterns are formed in a rectangular shape.   The method according to claim 12, wherein the predetermined portion is surrounded by the two metal patterns and an insulator.

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